SOC cache system and electronic equipment

Abstract

The invention relates to the technical field of computers, in particular to an SOC cache system and electronic equipment. To-be-processed data is stored in each master device of the SOC cache system; the data splitting module is in signal connection with each main device through each access bus module, and the data splitting module is used for splitting the to-be-processed data into a plurality of data units; the data behavior recognition module is in signal connection with the data splitting module, and the data behavior recognition module is used for performing behavior recognition on the data in each data unit to determine a corresponding data behavior; the cache control module is in signal connection with the data behavior identification module, the main memory and the cache memory, and prefetches corresponding data into the cache memory when the data behavior is read data; and writing the corresponding data into the main memory under the condition that the data behavior is write data. The invention provides the SOC cache system with higher efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a SOC caching system and electronic device. Background Technology

[0002] In recent years, with the rapid development of various enterprises' businesses, the amount of data carried, processed, and interacted between the systems and subsystems used by these enterprises has also grown rapidly. Although the systems used by these enterprises are developed using top-tier enterprise-level architectures and have many advantages, the ultra-rapid growth in business volume has brought new challenges of big data and high concurrency to enterprise systems, putting significant pressure on the performance and stability of the entire core system.

[0003] Computer systems consist of a wide variety of hardware, and their I / O access performance varies greatly. To address data transfer between hardware devices with different I / O performance, caching technology was invented, and a series of caching strategies were subsequently developed. Caching improves the hit rate of cached content through well-designed algorithms such as data block partitioning, prefetching, sequential prefetching, and cache replacement. If data is read directly from main memory (RAM), which is relatively large, it typically takes hundreds or even thousands of cycles to retrieve a single piece of data, resulting in a significant time consumption.

[0004] Therefore, there is an urgent need for a more efficient data caching system. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a SOC caching system and an electronic device.

[0006] A first aspect of the embodiments of this application provides a SOC caching system, comprising at least:

[0007] Multiple master devices, each storing data to be processed;

[0008] The data splitting module is connected to each of the main devices via a signal from each access bus module. The data splitting module is used to split the data to be processed into multiple data units.

[0009] A data behavior recognition module is signal-connected to the data splitting module. The data behavior recognition module is used to perform behavior recognition on the data in each data unit and determine the corresponding data behavior.

[0010] The cache control module is connected to the data behavior recognition module, the main memory, and the cache memory respectively. The cache control module is used to prefetch the corresponding data into the cache memory when the data behavior is read data, so that the target device can read it; and to write the corresponding data into the main memory when the data behavior is write data.

[0011] In one optional embodiment of this application, the cache memory includes a plurality of reserved storage spaces, which serve as reserve storage spaces for the main memory.

[0012] In one optional embodiment of this application, the cache unit address ranges of the data units after the data to be processed is split by the data splitting module do not overlap.

[0013] In one optional embodiment of this application, the arbitration mechanism of each access bus module connected to the master device signal is polling arbitration. The data splitting module is used to arbitrate each access bus module connected to the master device signal according to the polling arbitration mechanism, and send the target data unit corresponding to the target access bus module obtained by arbitration to the cache memory for processing.

[0014] In one optional embodiment of this application, the data processing mechanism of each access bus module connected to the master device signal is either sequential processing or out-of-order processing.

[0015] In an optional embodiment of this application, the data behavior recognition module includes at least: a read behavior recognition module and a write behavior recognition module that are independent of each other; wherein,

[0016] The read behavior identification module is connected to the data splitting module, the cache control module and the high-speed cache memory respectively. The read behavior identification module is used to identify and determine the read data behavior of data in each data unit.

[0017] The write behavior identification module is connected to the data splitting module, the cache control module and the main memory respectively. The write behavior identification module is used to identify and determine the write data behavior of data in each data unit.

[0018] In one optional embodiment of this application, the cache control module includes at least: a control unit and multiple temporary storage units, wherein,

[0019] The control unit is connected to the data behavior recognition module, the main memory and the high-speed cache memory respectively. The control unit is used to prefetch the data corresponding to the write data behavior to multiple temporary storage units.

[0020] If the data corresponding to the write operation can fill the data unit in the cache memory, then the control unit controls the data corresponding to the write operation in the temporary storage unit to be written into the cache memory.

[0021] In an optional embodiment of this application, in the above-described SOC caching system, if new data written to the cache memory replaces old data in the cache memory, the control unit controls the cache memory to store the old data to the main memory through the temporary storage unit.

[0022] In an optional embodiment of this application, if the data corresponding to the write data action cannot fill the data unit in the cache memory, the control unit controls the temporary storage unit to merge and package the data read from the cache memory or the main memory with the data corresponding to the write data action and then write it into the cache memory.

[0023] A second aspect of this application provides an electronic device that includes at least the SOC caching system described in any of the preceding claims.

[0024] This application provides a SOC caching system, comprising at least: multiple master devices, each storing data to be processed; a data splitting module connected to each of the master devices via access bus modules, capable of splitting the data to be processed into multiple data units; and a data behavior recognition module connected to the data splitting module, capable of identifying the data behavior of the data in each data unit. When the data behavior is read, the caching control module prefetches the corresponding data into a high-speed cache for the target device to read; when the data behavior is write, the corresponding data is written to the main memory. Main memory is relatively large, typically requiring hundreds or even thousands of cycles to read a single piece of data, resulting in a long processing time. The SOC caching system provided in this application prefetches data into a high-speed cache during data caching, allowing direct data retrieval from the main memory, significantly reducing the lookup time and providing a more efficient data caching system. Furthermore, the high-speed cache has an extremely fast data transfer speed, approaching that of the CPU, further improving the data caching efficiency of the SOC caching system provided in this application. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0026] Figure 1 This is a schematic diagram of the structure of the SOC caching system provided in the embodiments of this application. Detailed Implementation

[0027] In the process of developing this application, the applicant discovered that there is an urgent need for a more efficient data caching system.

[0028] To address the aforementioned problems, this application provides a SOC caching system and an electronic device. To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, through embodiments and in conjunction with the accompanying drawings, further illustrates a SOC caching system and electronic device. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0030] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0031] Please see Figure 1 This application provides a SOC caching system, which includes at least: a master device, a data splitting module, a data behavior recognition module, and a cache control module, wherein:

[0032] There are multiple master devices, each storing data to be processed. A master device is a component capable of initiating and controlling data transmission operations, corresponding to a slave device. Each master device can be a CPU, direct memory access controller, graphics processor, network controller, or storage controller, etc., and is not exhaustively listed here; any electronic device that requires internal data processing is acceptable.

[0033] The data splitting module is connected to each of the aforementioned master devices via signal signals from their respective access bus modules. The data splitting module is used to split the data to be processed into multiple data units; each data unit refers to a single, indivisible execution unit that bundles a series of operations into a single, indivisible unit that either succeeds entirely or fails entirely. The data splitting module can be a general-purpose processor, a smart network interface card (NIC), a multi-core processor, a storage controller, etc. For example, a programmable or multi-core processor, such as an FPGA or a multi-core ARM SoC, can be integrated on the NIC. This application does not impose specific limitations on the embodiments and can be flexibly configured according to actual conditions. An access bus module is a connection medium in a network topology where all network devices (nodes) are directly connected to a shared communication medium (i.e., a "bus"). This shared medium can be a coaxial cable, an optical fiber, or a printed circuit on a circuit board. The data splitting module, as shown... Figure 1 In the bus2line, where, Figure 1 In the term "bus2line," "bus" refers to a bus, a set of physical channels used to transmit data, addresses, or control signals. It also refers to a circuit or logic module that converts information on the bus into single-line signals. "2" stands for "to," indicating a conversion or connection. "line" refers to a cache line. "bus2line" means breaking down a long burst operation (which combines multiple fragmented, contiguous memory address operations into a single, continuous batch data transfer operation) that crosses cache line boundaries into multiple shorter burst operation lines that do not cross cache lines.

[0034] The data behavior recognition module is signal-connected to the data splitting module. The data behavior recognition module is used to identify the behavior of data in each data unit and determine the corresponding data behavior; this data behavior is at least one of reading data behavior and writing data behavior. Reading data behavior and writing data behavior can be determined by signal recognition, hardware circuitry, or software, as shown in Table 1 below:

[0035] Table 1

[0036]

[0037] The cache control module is signal-connected to the data behavior recognition module, the main memory, and the cache memory. The cache control module is used to prefetch the corresponding data into the cache memory when the data behavior is read, for the target device to read; and to write the corresponding data into the main memory when the data behavior is write. After identifying a series of consecutive read data behaviors, the module reads the data from the main memory in advance according to the read data address in the read data behavior and places it into the cache memory for future reading. In this embodiment, both the main memory and the cache memory are used as memory, and their characteristics differ as shown in Table 2 below:

[0038] Table 2

[0039]

[0040] This application provides a SOC caching system, comprising at least: multiple master devices, each storing data to be processed; a data splitting module connected to each of the master devices via access bus modules, capable of splitting the data to be processed into multiple data units; and a data behavior recognition module connected to the data splitting module, capable of identifying the data behavior of the data in each data unit. When the data behavior is read, the caching control module prefetches the corresponding data into a high-speed cache for the target device to read; when the data behavior is write, the corresponding data is written to the main memory. Main memory is relatively large, typically requiring hundreds or even thousands of cycles to read a single piece of data, resulting in a long processing time. The SOC caching system provided in this application prefetches data into a high-speed cache during data caching, allowing direct data retrieval from the main memory, significantly reducing the lookup time and providing a more efficient data caching system. Furthermore, the high-speed cache has an extremely fast data transfer speed, approaching that of the CPU, further improving the data caching efficiency of the SOC caching system provided in this application.

[0041] In one optional embodiment of this application, the cache memory includes multiple reserved storage spaces. Each reserved storage space refers to a small block of high-speed, low-latency memory dedicated to a specific processor or computing unit. Specifically, multiple ways (a subset or "column" of the cache containing multiple cache lines and operating in parallel with other "ways") are reserved in the cache for use as main memory, and can be referred to as local memory. These reserved storage spaces serve as backup storage for the main memory, temporarily storing the most critical data to facilitate backup when main memory space is insufficient, thereby improving the stability and reliability of the SOC caching system in this embodiment.

[0042] In an optional embodiment of this application, the data splitting module ensures that the cache unit address ranges of the data units split from the data to be processed do not overlap. The cache can be connected to multiple master devices, which access the cache through their respective access bus modules. To facilitate processing, the data splitting module splits data unit transactions that span the cache line (the smallest unit of data managed by the CPU cache, typically a contiguous block of 64 bytes) address range into multiple data unit transactions. After splitting, each data unit transaction will not cross the cache line address range, facilitating data processing and thereby improving the cache efficiency of the SOC cache system in this embodiment.

[0043] In an optional embodiment of this application, the arbitration mechanism for each access bus module connected to the master device is round-robin. The data splitting module is used to arbitrate each access bus module connected to the master device according to the round-robin arbitration mechanism, and send the target data unit corresponding to the target access bus module obtained by arbitration to the cache memory for further processing. Round-robin arbitration allows for sequential querying of each access bus module, preventing low-priority master devices from being "starved." Under high load, even if there is a very high-priority device, it must wait for its turn before accessing the device again, thus ensuring that other devices can also receive service. Round-robin arbitration typically only requires a counter or a state machine, switching to the next master device in each clock cycle. This means low hardware resource consumption (fewer gate circuits), low power consumption, and easy verification of its correctness.

[0044] In one optional embodiment of this application, the data processing mechanism of each access bus module connected to the master device signal is either sequential processing or out-of-order processing. That is, each master device bus supports out-of-order processing, multiple buses are independent of each other and do not affect each other, support different data processing mechanisms, have high compatibility, and can also improve the efficiency of data caching.

[0045] In one optional embodiment of this application, the bus access module of each master device supports writestream / readstream functionality. The data behavior recognition module includes at least two independent modules: a read behavior recognition module and a write behavior recognition module.

[0046] The read behavior identification module is connected to the data splitting module, the cache control module and the high-speed cache memory respectively. The read behavior identification module is used to identify and determine the read data behavior of data in each data unit.

[0047] The write behavior identification module is connected to the data splitting module, the cache control module and the main memory respectively. The write behavior identification module is used to identify and determine the write data behavior of data in each data unit.

[0048] The readstream module can identify continuous large-scale data read operations and take corresponding actions, such as predicting the data needed by the master device and prefetching the data into the cache to improve data reading efficiency. The writestream module can identify continuous large-scale data write operations and take corresponding actions, such as writing downstream in cache lines and not allocating the data to the cache, thereby improving data transfer efficiency.

[0049] In an optional embodiment of this application, the cache control module includes at least a control unit and multiple temporary storage units (line buffers). The control unit is signal-connected to the data behavior recognition module, the main memory, and the cache memory, respectively. The control unit is used to prefetch data corresponding to the write data behavior into the multiple temporary storage units. The temporary storage units (line buffers) are used for data caching. The data read / write process may include the following three scenarios:

[0050] In the first scenario: if the data corresponding to the write operation can fill the data unit in the cache memory, then the control unit controls the data corresponding to the write operation in the temporary storage unit to be written into the cache memory.

[0051] In the second scenario: if new data written to the cache memory replaces the old data in the cache memory, the control unit controls the cache memory to store the old data to the main memory through the temporary storage unit.

[0052] The third scenario: If the data corresponding to the write data action cannot fill the data unit in the cache memory, the control unit controls the temporary storage unit to merge and package the data read from the cache memory or the main memory with the data corresponding to the write data action and then write it into the cache memory.

[0053] For example, a write burst operation (which merges multiple scattered, contiguous memory address write operations into a single, continuous data transfer operation) typically follows this process: First, the data splitting module bus2line splits the cross-cacheline data unit transaction into multiple data unit transactions. The split data unit transactions are then arbitrated and sequentially entered into the temporary storage area line buffer. For data unit transactions that can fill the entire cacheline, the temporary storage area line buffer directly writes the data to the cache. If this causes other cachelines to be replaced (e.g., the space in the same way of the cache is filled), dirty data (i.e., old data) may be replaced. The buffer writes the replaced dirty data to main memory to prevent data loss. For data transactions that cannot fill the entire cache line, since both the temporary storage area line buffer and the cache process data in units of cache lines, the data needs to be read back from the cache and merged with the data written in the data transaction. Of course, if the cache line does not exist in the cache, it needs to be read back from main memory and then written to the cache.

[0054] One embodiment of this application provides an electronic device that includes at least the SOC caching system described in any of the preceding claims.

[0055] The beneficial effects of this SOC caching system have been described in detail in the above embodiments and will not be repeated here.

[0056] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A SOC caching system, characterized in that, At least including: Multiple master devices, each storing data to be processed; The data splitting module is connected to each of the main devices via a signal from each access bus module. The data splitting module is used to split the data to be processed into multiple data units. A data behavior recognition module is signal-connected to the data splitting module. The data behavior recognition module is used to perform behavior recognition on the data in each data unit and determine the corresponding data behavior. The cache control module is connected to the data behavior recognition module, the main memory, and the cache memory respectively. The cache control module is used to prefetch the corresponding data into the cache memory when the data behavior is read data, so that the target device can read it; and to write the corresponding data into the main memory when the data behavior is write data.

2. The SOC caching system according to claim 1, characterized in that, The cache memory includes multiple reserved storage spaces, which serve as backup storage spaces for the main memory.

3. The SOC caching system according to claim 1, characterized in that, The data splitting module ensures that the cache unit address ranges of the data units after splitting the data to be processed do not overlap.

4. The SOC caching system according to claim 1, characterized in that, The arbitration mechanism of each access bus module connected to the master device signal is polling arbitration. The data splitting module is used to arbitrate each access bus module connected to the master device signal according to the polling arbitration mechanism, and send the target data unit corresponding to the target access bus module obtained by arbitration to the cache memory for processing.

5. The SOC caching system according to claim 1, characterized in that, The data processing mechanism of each access bus module connected to the master device signal is either sequential processing or out-of-order processing.

6. The SOC caching system according to claim 1, characterized in that, The data behavior recognition module includes at least two independent modules: a read behavior recognition module and a write behavior recognition module; wherein... The read behavior identification module is connected to the data splitting module, the cache control module and the high-speed cache memory respectively. The read behavior identification module is used to identify and determine the read data behavior of data in each data unit. The write behavior identification module is connected to the data splitting module, the cache control module and the main memory respectively. The write behavior identification module is used to identify and determine the write data behavior of data in each data unit.

7. The SOC caching system according to claim 6, characterized in that, The cache control module includes at least: a control unit and multiple temporary storage units, wherein, The control unit is connected to the data behavior recognition module, the main memory and the high-speed cache memory respectively. The control unit is used to prefetch the data corresponding to the write data behavior to multiple temporary storage units. If the data corresponding to the write operation can fill the data unit in the cache memory, then the control unit controls the data corresponding to the write operation in the temporary storage unit to be written into the cache memory.

8. The SOC caching system according to claim 7, characterized in that, If new data written to the cache memory replaces the old data in the cache memory, the control unit controls the cache memory to store the old data to the main memory through the temporary storage unit.

9. The SOC caching system according to claim 7, characterized in that, If the data corresponding to the write data action cannot fill the data unit in the cache memory, the control unit controls the temporary storage unit to merge and package the data read from the cache memory or the main memory with the data corresponding to the write data action and then write it into the cache memory.

10. An electronic device, characterized in that, It includes at least the SOC caching system as described in any one of claims 1-9.

Images