An extensible programmable memory bank self-test system and method

Abstract

The application discloses a storage body self-test system and method with extensible programming, which comprises the following steps: a CPU is connected to a configurable storage body test controller through a CPU configuration interface and a configuration bus for bidirectional transmission of configuration instructions and parameters; the configurable storage body test controller is connected to each group of SRAM and ROM through a storage body access bus; test results of the measured storage body are written into a state register through an internal bus, and the state register is connected to a CPU data reading port for output; a fault signal output end of the configurable storage body test controller is connected to an interrupt module, and the interrupt module sends an interrupt request to the CPU; and an ATE test multiplexing interface reserved in the configurable storage body test controller is directly connected to MBIST logic of chip factory test for multiplexing. The method is implemented based on the system. The application has the advantages of simple principle, lower cost, better responsiveness, stronger compatibility, wider application range and the like.

Description

Technical Field

[0001] This invention mainly relates to the field of storage security testing technology, specifically a scalable programmable storage self-testing system and method. Background Technology

[0002] With the widespread application of semiconductors in the automotive and industrial markets, functional safety has become a key dimension in semiconductor design, in addition to traditional aspects such as power consumption, performance, and area. Functional safety standards (such as ISO 26262 for the automotive industry, IEC 61508 for the industrial industry, and IEC 60730 for the consumer electronics industry) list the requirements that must be followed when designing and deploying such systems.

[0003] Functional safety requires the elimination of unreasonable residual risks caused by safety-related electronic and electrical system failures. These failures can be systematic or random hardware failures. Regarding random hardware failures, memory (especially SRAM) is a critical component for functional safety when executing software in electronic and programmable electronic devices. This is because SRAM typically has the largest area and transistor count in the overall device. Furthermore, due to its high density, SRAM is susceptible to minute defects. Moreover, SRAM operates at voltages lower than normal circuit logic, making it more prone to interference. Customers building functional safety systems using chips require specific memory diagnostic coverage to meet various functional safety standards or requirements. Specific diagnostic coverage needs to address both single points of failure and potential failures. Electronic devices and programmable electronic devices used in functional safety applications need the ability to perform memory tests periodically during startup or maintenance cycles.

[0004] Memory modules (SRAM, ROM) constitute the largest portion of the chip area and transistor ratio. They are high-density, operate at low voltage, and are prone to random hardware failures. Therefore, self-tests must be performed during power-on and operation / maintenance phases to meet the requirements for single-point-of-failure and potential-fault diagnosis coverage. Currently, there are two main types of mainstream memory module self-test technologies: 1. ROM-based programmable self-test method: The test algorithm and grouping information are embedded in the ROM and executed through microinstructions; 2. Pure software testing method: Write test programs using the CPU instruction set to perform read and write verification on memory cells one by one.

[0005] The aforementioned traditional methods still have the following technical shortcomings: 1. ROM solution drawbacks: It requires additional large-capacity ROM storage algorithms and grouping configurations, increasing chip area and cost; it requires defining dedicated microinstructions and complex control logic, making hardware implementation cumbersome and scalable; the algorithms and groups are fixed, making it impossible to flexibly adapt to different specifications and quantities of memory.

[0006] 2. Software shortcomings: The test program is large and consumes system resources; the test speed is slow and cannot meet the requirements of rapid self-testing of automotive / industrial chips upon power-on; the diagnostic coverage is low and it is difficult to achieve the fault coverage required by functional safety standards.

[0007] 3. Common defects: The test logic cannot be reused with the ATE (chip factory test) logic, resulting in high hardware redundancy; the error location capability is weak, there is no interrupt mechanism, and the fault handling is not timely; it does not support flexible testing by group and cannot configure differentiated algorithms for different memory banks. Summary of the Invention

[0008] The technical problem to be solved by this invention is to provide a scalable programmable memory self-testing system and method that is simple in principle, lower in cost, more responsive, more compatible, and more widely applicable, in response to the technical problems existing in the prior art.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A scalable memory self-test system, comprising: The CPU connects to the configurable memory test controller via the CPU configuration interface and configuration bus, and transmits configuration commands and parameters bidirectionally. The configurable memory test controller connects to each group of SRAM and ROM via the memory access bus; The test results of the memory under test are written to the status register via the internal bus, and the output of the status register is connected to the CPU data read port. The fault signal output terminal of the configurable memory test controller is connected to the interrupt module, and the interrupt module sends an interrupt request to the CPU; The configurable memory test controller has a reserved ATE test multiplexing interface, which can be directly connected and multiplexed with the chip's factory test MBIST logic.

[0010] As a further improvement to the system of the present invention: the configurable memory test controller includes: the output terminals of a group configuration module and an algorithm configuration module, which are connected to a common logic unit; the common logic unit is respectively connected to a RAM test submodule and a ROM test submodule; the output of the address generation unit is connected to the address port of the memory under test; the data generation and comparison unit is bidirectionally connected to the data port of the memory under test; the ROM test submodule is connected to the MISR signature verification unit, and the verification result is sent to the status register; the group configuration module receives the CPU grouping instruction, divides the memory into multiple groups, and selects the current test group; the algorithm configuration module receives the CPU algorithm selection instruction and switches algorithms; the RAM test control submodule executes the March13n algorithm; the ROM test control submodule executes the ROM1 algorithm, reads data and sends it to the MISR for signature verification; the address generation unit automatically increments according to the address depth and traverses the entire address space of the memory; the data generation and comparison unit generates test vectors, writes them to the memory, reads back the data and compares them in real time, and marks errors; the MISR signature verification unit performs polynomial compression on the data read from the ROM, compares it with the expected signature, and judges the ROM. Whether it is intact; common logic unit, providing shared logic for different algorithms in RAM / ROM.

[0011] As a further improvement to the system of the present invention: the input of the group selection state machine comes from the group configuration module, and the output strobe signal is sent to the corresponding memory group; the input of the algorithm selection state machine comes from the algorithm configuration module, and the output algorithm enable signal is sent to the RAM / ROM submodule; the two state machines are interconnected through a synchronization signal; the output of the state machine directly controls the start and stop of the address generation unit and the data generation unit.

[0012] As a further improvement to the system of the present invention: the group selection state machine traverses the test groups in the configuration order, supporting single group, multiple groups, and full group testing; the algorithm selection state machine loads the corresponding algorithm independently for each group, supporting different algorithms between groups; the state latching logic is used to save the current test state.

[0013] As a further improvement to the system of the present invention: the group selection state machine selects one or more groups of memory in sequence according to the CPU configuration order; it supports skipping, single group, and full group testing, and can be rewritten by the CPU at any time.

[0014] As a further improvement to the system of the present invention: the algorithm selects the state machine to load the corresponding algorithm for the currently selected memory group; different algorithms share the address generation, data generation, and comparison logic, and only switch the differences.

[0015] The present invention further provides a memory self-testing method based on any one of the above-mentioned systems with scalable programming capabilities, comprising: Step S1: Register configuration: The CPU directly reads and writes the configuration register to complete the parameter settings; Step S2: Dual-state machine control: Algorithm selection state machine and group selection state machine are used to schedule the test process; that is: the group selection state machine selects the target memory group in sequence according to the configuration; the controller executes the core operations of address increment, write, read, and comparison; the test results are written to the status register in real time; Step S3: Fault handling; Fault detected: Immediately stop the current test and issue a hardware interrupt; Interrupt service routine execution: Terminate test / skip fault group / restart subsequent group test; CPU reads status register and accurately locates faulty memory.

[0016] As a further improvement to the method of the present invention: in step S2, the state machine switches between the March13n algorithm and the ROM1 algorithm according to the register configuration, sharing the address / data / comparison logic.

[0017] As a further improvement to the method of the present invention, it also includes an MPOST power-on self-test process, which includes: BOOT self-test: Perform the BOOT self-test. Only after the test is successful can the subsequent MPOST test be performed. Before executing the MPOST test, a test case that always fails is executed first. If the test fails, the entire test sequence is bypassed and the test status is returned to the application code. If the above tests pass, the MPOST test will be started, and all memory banks will be tested according to the configuration. If an error is detected in a memory bank, the MPOST test will stop and an interrupt signal will be issued to call the interrupt reset procedure for handling: either terminating the test or restarting the test of subsequent memory banks by setting registers.

[0018] As a further improvement to the method of the present invention: step S3 includes fault detection and response processing, the process of which includes: If the data comparison fails or the MISR check fails, the test is immediately paused, while maintaining the current address and group number; the hardware sends an interrupt signal to the CPU; the error information is stored in the status register, and the CPU reads and locates it directly. The interrupt service procedure can be interrupted by choosing to terminate the test, skip the current group and continue, or restart the test.

[0019] Compared with the prior art, the advantages of the present invention are as follows: 1. The scalable programmable memory self-testing system and method of the present invention addresses the shortcomings of existing technologies, such as large area, slow speed, and poor scalability, by proposing an unconventional hardware architecture. It abandons ROM and microinstructions and adopts a technical route of register configuration + dual state machine + logic multiplexing. The present invention can be directly implemented in automotive, industrial, and home appliance chips, with a clear process, hardware implementation, and quantifiable results.

[0020] 2. The scalable programmable memory self-testing system and method of the present invention involves the CPU sending test parameters through a configuration interface, the controller driving the memory to execute the test, and the results being stored in a status register. A fault triggers an interrupt. The system supports expansion and ATE logic reuse without requiring additional ROM. Specifically, the CPU writes parameters to the system through the configuration bus, and the configuration values ​​are directly latched in the controller's internal registers, eliminating the need for ROM storage. The system automatically adapts to the maximum memory width, and ultra-wide memory cells are compatible through a splicing method. In other words, its principle lies in using registers instead of ROM to achieve programmability, resulting in extremely simple control logic and immediate response.

[0021] 3. The scalable programmable memory self-test system and method of the present invention is a hardware implementation method for programmable memory self-testing that is not based on ROM and microinstructions. It uses kernel configuration registers and a state machine to achieve flexible group control and algorithm selection. The algorithm implementation is integrated into an optimized memory controller, which can perform different algorithm tests on ROM and SRAM. By analyzing the implementation logic of different algorithms, it was confirmed that most of the control logic is the same. This optimization can effectively reduce the area of ​​the memory controller. Furthermore, this logic can be reused with the MBIST control logic of ATE testing, without significantly increasing resources overall. The group control and algorithm selection state machine can be flexibly expanded according to the number and type of memory. The test results are written to a status register, and the CPU reads the register value to quickly locate the specific faulty memory. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the topological structure principle of the system of the present invention in a specific embodiment.

[0023] Figure 2 This is a schematic diagram of the principle of the configurable storage test controller in a specific embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the algorithm and group selection state machine in a specific embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the MPOST power-on self-test process in a specific implementation of the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The key innovation of this invention lies in abandoning the ROM-based solid-state and pure software modes and adopting a hardware architecture of "CPU register configuration + dual-state machine control + configurable test controller" to achieve self-testing of the memory bank with programmable algorithms, configurable grouping, reusable logic, and optimizable area.

[0028] like Figure 1 As shown, the present invention provides a scalable programmable memory self-test system, comprising: a CPU configuration interface, a configurable memory test controller, a memory under test (SRAM / ROM), a status register, an interrupt module, and an ATE test multiplexing interface; wherein: The CPU is connected to the configurable memory test controller via a configuration bus, enabling bidirectional transmission of configuration commands and parameters. The configurable memory test controller connects to each group of SRAM and ROM via the memory access bus; The test results of the memory under test are written to the status register via the internal bus, and the output of the status register is connected to the CPU data read port. The fault signal output terminal of the configurable memory test controller is connected to the interrupt module, and the interrupt module sends an interrupt request to the CPU; The configurable memory test controller has a reserved ATE test multiplexing interface, which can be directly connected and multiplexed with the chip's factory test MBIST logic.

[0029] By adopting the above structure, the CPU sends test parameters through the configuration interface, the controller drives the memory to execute the test, the results are stored in the status register, and a fault triggers an interrupt. The system supports expansion and ATE logic multiplexing without requiring additional ROM. Specifically, the CPU writes parameters (memory type, group number, address depth, data width, test algorithm, ROM MISR signature) to the system via the configuration bus. The configuration values ​​are directly latched in the controller's internal registers, eliminating the need for ROM storage. The system automatically adapts to the maximum memory width, and ultra-wide memory is compatible through a splicing method. In other words, the principle lies in using registers instead of ROM to achieve programmability, resulting in extremely simple control logic and instant response.

[0030] See Figure 2This invention provides a configurable memory test controller in a specific application example. The configurable memory test controller includes: a group configuration module, an algorithm configuration module, a RAM test control submodule (including the March13n algorithm), a ROM test control submodule (including the ROM1 algorithm), an address generation unit, a data generation and comparison unit, a MISR signature verification unit (ROM-specific), and a common logic unit (address auto-increment, data path, timing control); wherein: The outputs of the group configuration module and the algorithm configuration module are both connected to a common logic unit. The common logic unit is connected to the RAM test submodule and the ROM test submodule respectively; The output of the address generation unit is connected to the address port of the memory under test; The data generation and comparison unit is bidirectionally connected to the data port of the memory under test; The ROM test submodule is connected to the MISR signature verification unit, and the verification result is sent to the status register; The grouping configuration module receives CPU grouping instructions, divides the storage into multiple groups, and selects the current test group; The algorithm configuration module receives CPU algorithm selection instructions and switches between March13n, ROM1, or supplementary algorithms. The RAM test control submodule executes the March13n algorithm to complete the March series of operations, such as write 0 → read 0 → write 1 → read 1. The ROM test control submodule executes the ROM1 algorithm, reads data, and sends it to MISR for signature verification. The address generation unit automatically increments according to the address depth, traversing the entire address space of the memory. The data generation and comparison unit generates test vectors, writes them to storage, reads back the data and compares them in real time, and marks errors. The MISR signature verification unit performs polynomial compression on the data read from the ROM and compares it with the expected signature to determine whether the ROM is intact. The common logic unit provides shared logic for different algorithms in RAM / ROM, only switching the different parts, thus reducing the area.

[0031] As can be seen from the above, the test controller uniformly drives the memory to perform the following hardware operations: Address auto-increment: Traverse address by address from 0 to the maximum address.

[0032] Data generation: Generate test patterns such as 0x00, 0xFF, 0x55, and 0xAA according to the algorithm.

[0033] Write → Read Back → Compare: SRAM: Write data → Read data → Compare data to detect fixed faults, flip faults, and coupling faults.

[0034] ROM: Read the data → send it to MISR for compression → compare it with the expected signature to determine if the data is corrupted.

[0035] The results are written to the status register: the test results for each group and each address are recorded in real time.

[0036] By adopting the above scheme, March13n + ROM1 provides high fault coverage; the reuse of common logic allows multiple algorithm support to increase the area by only about 10%.

[0037] In this invention, the data width of the controller is determined by the maximum data width of the storage. Since the data width has a significant impact on the controller area, it is necessary to set an appropriate storage width through comprehensive evaluation. If the storage width is too large, it can be achieved by splicing storage units together.

[0038] In this invention, RAM testing is primarily implemented using March13n, the main algorithm for memory testing, which provides the highest overall coverage. Other algorithms can also be used for supplementary testing, and the selection needs to be made through algorithm settings. The required algorithms are implemented in the RAM controller.

[0039] In this invention, ROM testing is primarily implemented using the ROM1 algorithm. The required algorithm is implemented in the ROM controller, and then switching is performed through algorithm settings.

[0040] In this invention, when implementing the ROM and RAM controllers, the same logic is shared for different algorithm implementations, and only different parts are selected for control, which effectively reduces the area. Analysis confirms that compared to a controller implementing a single algorithm, a controller implementing multiple algorithms only increases the area by about 10%. This is mainly because the core logic of different algorithm implementations is the same: address increment, write data generation, and data comparison.

[0041] Algorithm selection and group selection are implemented using state machines. These two state machines allow for flexible implementation of algorithm control and group control. See also Figure 3This diagram illustrates the algorithm and group selection state machine in a specific application example of the present invention. The group selection state machine receives input from the group configuration module and outputs a strobe signal to the corresponding memory group; the algorithm selection state machine receives input from the algorithm configuration module and outputs an algorithm enable signal to the RAM / ROM submodule; the two state machines are interconnected via a synchronization signal to ensure the execution order of "selecting the group first, then the algorithm"; the state machine outputs directly control the start and stop of the address generation unit and the data generation unit. Specifically, the group selection state machine traverses the test groups according to the configuration order, supporting single-group, multi-group, and full-group testing; the algorithm selection state machine loads the corresponding algorithm independently for each group, supporting different algorithms between groups; the state latch logic is used to save the current test state, preserving the context in case of errors for easy CPU location.

[0042] In other words, the system has two independent state machines working together: The group selection state machine selects one or more memory groups sequentially according to the CPU configuration order; it supports skipping, single group, and full group testing, and can be rewritten by the CPU at any time. The algorithm selection state machine loads the corresponding algorithm for the currently selected memory bank group: SRAM → March13n (main test); ROM → ROM1 + MISR verification; different algorithms share address generation, data generation, and comparison logic, only switching the differences.

[0043] Through the above design, the state machine hardware parallel scheduling is faster than software, more flexible than microinstructions, and has a very small logic plane.

[0044] The system described above in this invention can specify different test algorithms for each group of memory banks through CPU configuration algorithms; it can also specify the group for each test as needed through CPU configuration groups; test results are written to registers and can be accessed by the CPU to quickly locate faulty memory banks; an interrupt response mechanism is introduced, which issues an interrupt after an error is detected, and the subsequent operation is determined by the interrupt service routine; this structure can be quickly expanded, and the registers and related logic can be expanded according to the type and number of memory banks, and the logic can be automatically generated by scripts; it can be merged with ATE test logic to share test logic, and the overall hardware will not be increased too much; compared with ROM-based self-test methods, no additional ROM memory banks are required, and the control logic is also simplified.

[0045] Furthermore, this invention enables expansion and reuse. When the number / type of memory cells changes, only the registers and state machine need to be automatically expanded using a script, without requiring architecture reconstruction. The test controller and the ATE factory-installed MBIST logic share address, data, and control paths, without adding a large amount of additional hardware. The entire design is modular and parametric, enabling design once and reuse across all platforms.

[0046] This invention further provides a scalable programmable memory self-testing method based on the above system. The CPU configures test parameters through registers, a dual-state machine implements grouping and algorithm scheduling, and a configurable controller can perform high-coverage tests on SRAM / ROM using shared hardware logic. Faults are reported via real-time interrupts. The entire system requires no ROM, is scalable, and can be reused with ATE (Automatic Test Equipment), meeting the requirements for rapid power-on self-testing of functional safety chips. The method includes: Step S1: Register Configuration: The CPU directly reads and writes the configuration registers to complete the parameter settings such as test algorithm, memory grouping, address depth, data width, and MISR signature; specifically, in this example, it may include memory type (RAM / ROM), group number, address depth, data width, test algorithm (March13n / ROM1 / supplementary algorithm), and MISR signature of ROM; Step S2: Dual-state machine control: Algorithm selection state machine and group selection state machine to achieve flexible scheduling of the test process; that is: the group selection state machine selects the target memory group in sequence according to the configuration; the controller executes the core operations of address auto-increment, write, read, and comparison; the test results are written to the status register in real time; Step S3: Fault Handling: Fault Detection: Immediately stop the current test and issue a hardware interrupt; Interrupt Service Routine Execution: Terminate the test / skip the fault group / restart the subsequent group test; CPU reads the status register and accurately locates the faulty memory.

[0047] In specific application examples, the present invention also includes a test completion and system startup process, namely: if all tests pass, RAM initialization is performed; test resources are released and the chip enters normal working mode.

[0048] In a specific application example, in step S2, the state machine switches between March13n, ROM1 and the supplementary algorithm according to the register configuration, sharing the address / data / comparison logic.

[0049] In step S2, the algorithm selects a state machine to load the corresponding test algorithm for each group: SRAM: main test March13n algorithm (high coverage), optional supplementary algorithm; ROM: main test ROM1 algorithm, in conjunction with MISR signature verification.

[0050] In specific application examples, in the above steps, the registers and control logic are automatically expanded by script according to the number / type of memory cells, supporting width splicing to adapt to ultra-large bit-width memory cells.

[0051] The method of this invention achieves logic reuse optimization: RAM / ROM testing uses the core logic of address auto-increment, data generation, and comparison, and only the differentiated parts are subject to selection control.

[0052] The method of this invention realizes ATE logic multiplexing: the self-test hardware and the chip factory test MBIST logic are merged without adding a large amount of additional hardware resources.

[0053] Furthermore, step S3 includes fault detection and response processing, the process of which includes: If the data comparison fails or the MISR check fails, the test is immediately paused, while maintaining the current address and group number; the hardware sends an interrupt signal to the CPU; the error information is stored in the status register, which the CPU can directly read and locate. The interrupt service procedure can be interrupted by choosing to terminate the test, skip the current group and continue, or restart the test.

[0054] Hardware can implement real-time interrupts, which have lower latency and higher security levels than software polling.

[0055] The present invention may further include the MPOST power-on self-test process: MPOST power-on self-test: in conjunction with OTP configuration, the entire process of BOOT self-test → controller verification → group test → fault interrupt → RAM initialization is automatically executed upon power-on.

[0056] like Figure 4 The diagram shown illustrates the MPOST self-test process in a specific application example of the present invention. After configuring OTP, the user executes the MPOST test BOOT process upon each power-on reset. The specific process is as follows: BOOT self-test: Since the MPOST program is stored in BOOT, it cannot be tested through the MPOST storage self-test program. The BOOT self-test must be performed before the subsequent MPOST test can proceed. Before executing the MPOST test, a test case that always fails is executed first. This is to verify the normal functioning of the MPOST controller and its ability to indicate faults. If the test fails, the entire test sequence is bypassed and the test status is returned to the application code.

[0057] If the above tests pass, the MPOST test will be started, and all memory banks will be tested according to the configuration. If an error is detected in a memory bank, the MPOST test will stop and an interrupt signal will be issued to call the interrupt reset procedure for handling: the test can be terminated, or the test of subsequent memory banks can be restarted by setting the registers.

[0058] Initialize RAM after the test is complete.

[0059] Specific application scenarios: Application Scenario 1: Automotive-grade MCU chip (compliant with ISO 26262 ASIL-D) Chip configuration: Built-in 6 SRAM groups (32KB / group) and 2 ROM groups (64KB / group) for automotive power control; Implementation of this invention: Configuration grouping: SRAM is divided into 3 groups, ROM is divided into 2 groups, and 1 group of extension bits is reserved; Algorithm configuration: Use March13n for the entire SRAM group, and ROM1 for the ROM, and configure the corresponding MISR signature; Enable OTP power-on automatic test; Execution process: Power on → BOOT self-test passes → Force failure test case verification controller → Test sequentially by group; During the test, the second group of SRAMs failed → an interrupt was immediately triggered → the CPU read the status register to locate the faulty group → the interrupt service routine selected to skip this group and continued testing the remaining groups; Effect: The power-on self-test time is less than 10ms, which meets the requirements for rapid vehicle start-up. Fault coverage ≥99%, achieving ASIL-D level; Compared to ROM solutions, it saves approximately 12% of chip area.

[0060] Application Scenario 2: Industrial Control SOC Chip (compliant with IEC 61508 SIL-3) Chip configuration: a hybrid of multiple memory modules, including 128-bit high-bandwidth SRAM and small-capacity configuration ROM; Implementation of this invention: Width adaptation: The 128-bit SRAM uses a splicing method to adapt to the maximum width of the controller; Group testing: Grouped by functional modules, only the storage of the current working module is tested; Logic reuse: Shares MBIST control logic with ATE factory testing; Effect: Supports online group testing without interrupting the operation of industrial equipment; The hardware area increases by only 8%, far less than traditional solutions; It can be quickly extended via scripts to adapt to different models of industrial chips.

[0061] Application Scenario 3: Home appliance main control chip (compliant with IEC 60730) Chip configuration: Low-cost, small-area MCU with 2 sets of SRAM and 1 set of ROM; Implementation of this invention: Minimalist configuration: One-click configuration of default CPU algorithm and full group testing; No additional ROM: Programmable control is implemented entirely using registers; Effect: BOM costs are reduced to meet the low-cost demand for home appliances; The power-on self-test is reliable, avoiding safety risks caused by storage failures during appliance operation.

[0062] In summary, the advantages of the present invention compared with the prior art are shown in the table below: Table 1. Comparison of Results

[0063] As can be seen from the above, by adopting the above-described solution of this invention, a ROM-free and microinstruction-free design is used, with pure register configuration, dual-state machine grouping, and flexible algorithm control. The overall structure is simpler, the implementation cost is lower, common logic is reused, the area of ​​multiple algorithms increases by only about 10%, and the ATE interface is reused without significantly increasing hardware. By using interrupts plus status registers, faulty memory can be quickly located. Because the script is scalable, it can adapt to any number / specification of memory, making it more widely applicable.

[0064] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A self-testing system for scalable programmable memory, characterized in that, include: The CPU connects to the configurable memory test controller via the CPU configuration interface and configuration bus, and transmits configuration commands and parameters bidirectionally. The configurable memory test controller connects to each group of SRAM and ROM via the memory access bus; The test results of the memory under test are written to the status register via the internal bus, and the output of the status register is connected to the CPU data read port. The fault signal output terminal of the configurable memory test controller is connected to the interrupt module, and the interrupt module sends an interrupt request to the CPU; The configurable memory test controller has a reserved ATE test multiplexing interface, which can be directly connected and multiplexed with the chip's factory test MBIST logic.

2. The scalable programmable memory self-test system according to claim 1, characterized in that, The configurable memory test controller includes: outputs of a group configuration module and an algorithm configuration module, both connected to a common logic unit; the common logic unit is connected to a RAM test submodule and a ROM test submodule; the address generation unit output is connected to the address port of the memory under test; the data generation and comparison unit is bidirectionally connected to the data port of the memory under test; the ROM test submodule is connected to the MISR signature verification unit, and the verification result is sent to the status register; the group configuration module receives CPU grouping instructions, divides the memory into multiple groups, and selects the current test group; the algorithm configuration module receives CPU algorithm selection instructions and switches algorithms; the RAM test control submodule executes the March13n algorithm; the ROM test control submodule executes the ROM1 algorithm, reads data and sends it to the MISR for signature verification; the address generation unit automatically increments according to the address depth, traversing the entire address space of the memory; the data generation and comparison unit generates test vectors, writes them to the memory, reads back data and compares them in real time, and marks errors; the MISR signature verification unit performs polynomial compression on the data read from the ROM, compares it with the expected signature, and determines whether the ROM is intact; the common logic unit is for RAM / ROM. Different algorithms provide common logic.

3. The scalable programmable memory self-test system according to claim 2, characterized in that, The group selection state machine receives input from the group configuration module and outputs a strobe signal to the corresponding memory group; the algorithm selection state machine receives input from the algorithm configuration module and outputs an algorithm enable signal to the RAM / ROM submodule; the two state machines are interconnected via a synchronization signal; the state machine outputs directly control the start and stop of the address generation unit and the data generation unit.

4. The scalable programmable memory self-test system according to claim 3, characterized in that, in, The group selection state machine traverses the test groups in the configured order, supporting single-group, multi-group, and full-group testing; the algorithm selection state machine loads the corresponding algorithm independently for each group, supporting different algorithms between groups; the state latching logic is used to save the current test state.

5. The scalable programmable memory self-test system according to claim 4, characterized in that, The group selection state machine selects one or more memory groups sequentially according to the CPU configuration order; it supports skipping, single group testing, and full group testing, and can be rewritten by the CPU at any time.

6. The scalable programmable memory self-test system according to claim 4, characterized in that, The algorithm selects a state machine to load the corresponding algorithm for the currently selected memory group; different algorithms share address generation, data generation, and comparison logic, only switching the differences.

7. A method for self-testing memory based on the scalable programming of the system according to any one of claims 1-6, characterized in that: include: Step S1: Register configuration: The CPU directly reads and writes the configuration register to complete the parameter settings; Step S2: Dual-state machine control: Algorithm selection state machine and group selection state machine are used to schedule the test process; that is: the group selection state machine selects the target memory group in sequence according to the configuration; the controller executes the core operations of address increment, write, read, and comparison; the test results are written to the status register in real time; Step S3: Fault handling; Fault detected: Immediately stop the current test and issue a hardware interrupt; Interrupt service routine execution: Terminate test / skip fault group / restart subsequent group test; The CPU reads the status register to pinpoint the faulty memory.

8. The self-testing method for extensible programmable memory according to claim 7, characterized in that: In step S2, the state machine switches between the March13n algorithm and the ROM1 algorithm according to the register configuration, sharing the address / data / comparison logic.

9. The self-testing method for extensible programmable memory according to claim 7 or 8, characterized in that: It also includes the MPOST power-on self-test process, which includes: BOOT self-test: Perform the BOOT self-test. Only after the test is successful can the subsequent MPOST test be performed. Before executing the MPOST test, a test case that always fails is executed first. If the test fails, the entire test sequence is bypassed and the test status is returned to the application code. If the above tests pass, the MPOST test will be started, and all memory banks will be tested according to the configuration. If an error is detected in a memory bank, the MPOST test will stop and an interrupt signal will be issued to call the interrupt reset procedure for handling: either terminating the test or restarting the test of subsequent memory banks by setting registers.

10. The self-testing method for extensible programmable memory according to claim 7 or 8, characterized in that: Step S3 includes fault detection and response processing, the process of which includes: If the data comparison fails or the MISR check fails, the test is immediately paused, while maintaining the current address and group number; the hardware sends an interrupt signal to the CPU; the error information is stored in the status register, and the CPU reads and locates it directly. The interrupt service procedure can be interrupted by choosing to terminate the test, skip the current group and continue, or restart the test.

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