BMC health management module based on Tenglong E2000S

Abstract

The invention relates to a BMC (Baseboard Management Controller) health management module based on Tenglong E2000S, and belongs to the technical field of computers. The BMC health management module provided by the invention comprises an E2000S processor, an LPDDR4 storage chip, a 50MHZ active crystal oscillator, a FLASH storage chip, a USB (Universal Serial Bus) change-over switch, a power supply and a CTOLC180PIN connector. The system is nationwide, rich in interface and small in size, can be flexibly configured and reused in different application scenes, realizes efficient application, shortens the research and development cycle of products, and reduces research and development investment.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to a BMC health management module based on the Tenglong E2000S. Background Technology

[0002] With the continuous development of domestically produced computers and servers, the Phytium Tenlong E2000 series embedded system management processor has filled the gap in the control and management capabilities of domestically produced computers and servers. As a crucial force driving the self-sufficiency of domestic servers, the Tenlong E2000 series processor is continuously contributing to the independent research and development and innovation capabilities of my country's server industry. The Tenlong E2000 series processor features high efficiency, low power consumption, high scalability, comprehensive management capabilities, and supports multiple open-source standards, enhancing the self-sufficiency of domestic servers through innovation. If a universal BMC health management module based on the Tenlong E2000S can be implemented, which can be flexibly configured and reused in different application scenarios, efficiency can be greatly improved. Summary of the Invention

[0003] (a) Technical problems to be solved The technical problem to be solved by this invention is how to provide a BMC health management module based on Tenglong E2000S, so as to solve the design problem of a general BMC health management module.

[0004] (II) Technical Solution To solve the above-mentioned technical problems, this invention proposes a BMC health management module based on Tenlong E2000S. The BMC health management module includes: E2000S processor, LPDDR4 memory chip, 50MHz active crystal oscillator, FLASH memory chip, USB switch, power supply and CTOLC_180PIN connector. The LPDDR4 memory chip and the Tenglong E2000S processor are connected by signal according to the relevant LPDDR4 protocol to realize the full chip main memory space; The 50MHz active crystal oscillator is powered by 3.3V_AUX through a 120ohm / 3A ferrite bead. The STDBY pin is pulled up to the power supply with a resistor. The clock output pin CLK is connected to the E2000S processor with a resistor as the E2000S reference clock. A QSPI Flash chip is connected to the Tenglong E2000S processor according to the relevant QSPI protocol design to store the BIOS firmware; One SPI Flash chip is connected to the SPI3 signal of the Tenglong E2000S processor according to the relevant SPI protocol design, and is used to store the operation log; The KVM switching USB 2.0 signal KVM0_USB2_P2_DP / N of the Tenlong E2000S processor and the USB 2.0 signal BMC_USB2_P2_DP / N transmitted from the host processor on CTOLC_180PIN are connected to the USB switching switch. The USB enable signal E2000_USB2_EN of the Tenlong E2000S processor controls the enable, realizing KVM switching. The Tenlong E2000S processor's signal debugging USB 2.0 port is connected to a two-pin header via a common-mode inductor and ESD protection design for debugging purposes. The CTOLC_180PIN connector is a 180PIN dual-row high-speed connector used to bring out the external interface signals of the Tenglong E2000S processor.

[0005] (III) Beneficial Effects This invention proposes a BMC health management module based on the Tenlong E2000S. The technical solution proposed in this invention realizes a BMC health management module based on the Tenlong E2000S, which is fully domestically produced, has rich interfaces, is compact in size, can be flexibly configured and reused in different application scenarios, achieves efficient application, shortens product development cycle and reduces R&D investment. Attached Figure Description

[0006] Figure 1 The structural dimensions of the BMC health management module designed for this invention are shown in the diagram. Figure 2 This is a stacked design diagram for the present invention; Figure 3 This is a schematic diagram of the design of the present invention; Figure 4 A schematic diagram of the pin layout of the CTOLC_180PIN connector designed for this invention. Figure 5 shows the pin signal definitions of the CTOLC_180PIN connector designed in this invention; (a) is X1-1; (b) is X1-2. Detailed Implementation

[0007] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0008] This invention belongs to the field of computer technology, specifically relating to a BMC health management module based on the Phytium E2000S, which is suitable for BMC health management of computers and servers based on the Phytium processor platform.

[0009] The BMC health management module of the Tenglong E2000S of this invention is specifically designed to meet the health management needs of domestically produced computers and servers, and features small size, compact structure, comprehensive functions, and excellent performance. For example... Figure 3 As shown, this module integrates a rich set of peripheral interfaces and high-speed buses, including PCIE, DP, USB, ADC, UART, NCSI, I2C, and other interfaces. It also integrates onboard LPDDR4 memory chips and Flash chips. It is currently the smallest domestically produced BMC health management module that can meet the needs of various types of interfaces.

[0010] Users can flexibly and quickly build systems based on domestically developed wire-controlled platforms, applicable not only to the computer and server sectors but also to a wide range of industries and scenarios, including industrial automation, rail transportation, power energy, instrumentation, and medical equipment. The Phytium Tenglong E2000S system management module achieves standardized hardware design, enabling BMC code adaptation and standardization on a certain basis. This significantly shortens product development cycles, reduces R&D investment, and makes it an ideal form of system control for various fields, promoting industry development. This invention provides a fully domestically produced BMC health management module based on the Tenglong E2000S processor. The following sections will detail the structural dimensions, impedance design, and operational principle.

[0011] 1. Structural Dimension Design like Figure 1 The BMC health management module's structural dimensions are shown in the diagram. The module measures 50mm x 70mm. The front (TOP) side houses the main components, including the Tenglong E2000S processor, LPDDR4 memory chips, and power supply chips. The back (BOT) side is the connector mating side. The connectors are AVIC Optoelectronics high-speed connectors, model CTOLC-145-22-LQA. After mating with the motherboard, the height is 10mm, with a 3mm height limit on the module side and a 5mm height limit on the motherboard side. The small size and large height margin meet the miniaturization requirements of various applications for high-efficiency processors, satisfying users' multi-level and multi-scenario selection needs.

[0012] The BMC health management module is designed with four mounting holes, each with a diameter of 2.7mm and a pad size of 6mm. The mounting holes on both sides of the connector not only further increase the mating reliability of the CTOLC_180PIN connector, but also, together with the other two mounting holes, strengthen the bond between the module and the motherboard, thereby improving the reliability of the connector mating and its shock resistance.

[0013] The BMC health management module features two concave arcs on both sides, ensuring ease of insertion and removal. The four corners of the board are chamfered to prevent accidental injury from sharp edges during insertion and removal.

[0014] 2. Impedance design of multilayer stack like Figure 2As shown in the layer stack design diagram, the BMC health management module adopts military-grade TU-752 PCB material with a 12-layer stack design, meeting the military-grade printed circuit board acceptance standard GJB362C-2021. The 12-layer stack includes two top layers and ten inner layers. The first layer (TOP) and the twelfth layer (BOTTOM) are component layers. The ten inner layers include four routing layers (L3, L5, L8, L10), four GND layers (L2, L4, L9, L11), and two power layers (L6, L7). Routing layers L3 and L10 are both ground planes on both sides, with complete signal references, serving as primary routing layers for important and high-speed signals. Signal layers L5 and L8 are both ground planes on one side and power planes on the other, serving as secondary routing layers, containing a mix of LPDDR4 address signals, some power supplies, and a small number of low-speed single-ended traces. The LPDDR4 address signal reference to the LPDDR4 power supply design ensures reference integrity and provides a path for LPDDR4 power, saving stack-up and reducing printing costs. L6 and L7 are power layers, recessed 3H relative to the ground plane (H is the distance from the power plane to the ground plane). Due to the low power consumption of the Tenglong E2000S processor, the power supply design meets the power supply requirements of each chip in the circuit while ensuring the integrity and impedance continuity of adjacent traces. The routing impedance requirements are designed and simulated according to the Tenglong E2000S processor requirements to ensure signal quality.

[0015] 3. Principle Design like Figure 3 The principle block diagram is shown. The main circuits of this BMC health management module include: E2000S processor, LPDDR4 memory chip, 50MHz active crystal oscillator, FLASH memory chip, USB switch, power supply, and CTOLC_180PIN connector.

[0016] The Tenglong E2000S processor features an excellent architecture, small size, low power consumption, rich peripheral interfaces, and good scalability. The following is a detailed introduction to the interfaces of the Tenglong E2000S processor BMC health management module.

[0017] The LPDDR4 memory chip uses Changxin's onboard X32 2GB memory chip, model CXDB4ABAM-MK, and is connected to the Tenglong E2000S processor according to the relevant LPDDR4 protocol design to realize the full chip main memory space.

[0018] The 50MHz active crystal oscillator uses Yangxing Technology OT322550MJBA4SL, powered by a 3.3V_AUX through a 120ohm / 3A ferrite bead. The STDBY pin is pulled up to the power supply using a 10K / 1% 0402 resistor. The clock output pin CLK is connected to the E2000S processor via a 33R / 1% 0402 resistor as the E2000S reference clock.

[0019] A QSPI Flash chip, specifically a Fudan Microelectronics 512Mb Flash chip, model EFM25QL512, is used to connect with the Tenglong E2000S processor according to the relevant QSPI protocol and stores the BIOS firmware.

[0020] One SPI Flash chip, using Fudan Microelectronics 128Mb Flash, model FM25Q128A-SOB-UG, is connected to the Tenglong E2000S processor's SPI3 signal according to the relevant SPI protocol design, and is used to store operation logs.

[0021] The KVM switching USB 2.0 signal name of the Tenlong E2000S processor is KVM0_USB2_P2_DP / N. The USB 2.0 signal BMC_USB2_P2_DP / N transmitted from the host processor on CTOLC_180PIN is connected to the Zhenxin Technology USB switch, model GMH3USB31. The USB enable signal E2000_USB2_EN of the Tenlong E2000S processor controls the enable, realizing KVM switching.

[0022] The Tenlong E2000S processor's signal debugging USB 2.0 is connected to a two-pin header via a common-mode inductor and ESD design for debugging purposes.

[0023] The CTOLC_180PIN connector uses a dual-row high-speed connector with 180PIN from AVIC Optoelectronics, model: CTOLC-145-22-LQA, to bring out the external interface signals of the Tenglong E2000S processor. For example... Figure 4 The pinout diagram of the CTOLC_180PIN connector is shown. This connector is a surface-mount 180-pin connector with a locating pin positioning method. It has a rated current of 2.5A, a transmission rate of 10Gbps, a pin pitch of 1.27mm, and uses a "fork tone" type double contact socket with gold-plated contacts. The four rows of pins are arranged in two sets of surface-mount pins, with long and short pins distributed. Pin signals can be defined according to requirements. In the Cadence PCB design software, the routing starting point is the center of the pad. If a differential line is defined as two adjacent long and short pins, the corresponding short pin routing needs to be compensated by 0.63mm to ensure equal length for differential pairs. The four rows of pins are grouped: one group includes short pins A1~A45 and long pins B1~B45, and another group includes long pins C1~C45 and short pins D1~D45, with long and short pins arranged alternately. Signal design follows the rule of adjacent signals within the same group and grounded signals between different groups. As shown in Figure 5, the CTOLC_180PIN connector pin signal definition is divided into two parts, Part 1 and Part 2.

[0024] Part 1 (i.e., X1-1), pins A1~A20, B1~B20, C1~C20, D1~D20. Signals include: PCIe X1 signals CPU_BMC_PCIex1_RX / TXP / N for communication with the main processor on pins C4 / D4 and C6 / D6; 100MHz PCIe differential clock signal BMC_PCIE_100M_REFCLKP / N on pins C2 / D2; DP display signal E2000_DP0_L0_P / N, 100MHz, on pins A5 / B5 / A3 / B3 / A7 / B7. DP clock signals BMC_DP0_100M_REFCLKP / N and E2000_DP0_AUX_P / N, E2000_DP0_HPD on pin A9; USB3 signal USB20_BMC_P / N5 on pins C9 / D9 of the Tenglong E200S processor; USB signal USB20_BMC_P / N4 for KVM switching on pins C8 / D8; reset signals E2000_RSTn, E2000_PCIE_RSTn, and E2000_CORE_RSTn on pins B9 / A10 / B10 of the Tenglong E2000S; A11 / A12 / A14 / A15 / Pins B11 / B12 / B14 / B15 / C15 / D15: Fan control signals P6_FAN_TACH[0:3], P6_FAN_PWM[0:3], and FAN_SCL / SDA; Pins A17 / B17: Main processor over-temperature indication signal CPU0_D[0:1]_TEMP_OVER_TO_BMC; Pins C11 / D11: Temperature sensor I2C signal BMC_TEMP_SCL / SDA; Pins C12 / D12 / C13 / D13 / C14 / D14: Connected to VPX board P0 slot address signals CAP and CA[0:4]; Pins C16 / D16: E2000S UART1 debug serial port signal CPU_DEBUG_UART1_RX / TX_TO_BMC; A16 pin main processor firmware switching switch enable pin signal BIOS_QSPI_SEL#; A18 / B18 / A19 / B19 pins connected to the Kunlun firmware configuration signals PowerON_CPLD_to_BMC, PowerOFF_CPLD_to_BMC, RESTART_CPLD_to_BMC, PowerGD_CPLD_to_BMC of the CPLD; A17 / B17 pins UART0 debug serial port signal E2000_Debug_R / TXD of the Tenglong E2000S; C18 / D18 pin reserved CRU I2C interface signal BMC_CPU_I2C0_CRU_SCL / SDA; C19 / D19 / C19 / D19 pins connected to the VPX board P0 slot management control IPMB signal IPMB_IIC[0:1]_SCL / SDA.

[0025] Part 2 (i.e. X1-2), pins A21~A45, B21~B45, C21~C45, D21~D45. The signals include: C21 / D21 pin voltage detection I2C bus BMC_Voltage_I2C_SCL / SDA, which can be externally connected to SM2990 to expand ADC voltage monitoring signals; A22 / B22 / A23 / B23 / A24 / B24 pins connect to the RACK_ID[0:5] signals for data transmission between devices on the VPX board P6; C23 / D23 / C24 / D24 pins are reserved and can be configured as SPI or GPIO signals BMC_SPI2SCLK / GPIO3_3, BMC_SPI2RXD / GPIO3_4, BMC_SPI2TXD / GPIO3_5, BMC_SPI2CSN0 / GPIO3_6; A25 / B25 / A26 / B26 pins are system firmware upgrade SPI signals BMC_SPIM0_SCLK, BMC_SPIM0_TXD, BMC_SPIM0_RXD, BMC_SPIM0_CSN0; A27 / B27 / A28 / B28 / A29 pins E2000S JTAG signals E2000_JTAG_TCK, E2000_JTAG_TDI, E2000_JTAG_TDO, E2000_JTAG_TMS, E2000_JTAG_NTRST; C26 pin connected to the CPLD's BMC system reset response signal RSTn_CPLD_to_BMC; D26 / C27 / D27 / The C28 / D28 / C29 / D29 / C30 / D30 pins communicate with the main processor via LPC data processing signals E2000_LPC_LDRQn, E2000_LPC_SIRQn, E2000_LPC_CLK_33M, E2000_LPC_AD0, E2000_LPC_AD1, E2000_LPC_AD2, E2000_LPC_AD3, E2000_LPC_LFRAMEn, and E2000_LPC_RSTn; the A30 / B30 / A31 / B31 / A32 / B32 / A33 / B33 pins provide the 8-channel ADC power supply detection signal BMC_ADC[0:7].C32 / D32 / C33 / D33 / C34 / D34 / C35 / D35 / C33 / D33 / C34 / D34 / C35 / D35 / C36 / D36 / C37 / D37 / C39 / D39 / C40 / D40 / C41 / D41 / C42 / D42 / C43 / D43 / C44 / D44 Pin 2 NCSI signal NCSI[0:1]_TXD0, NCSI[0:1]_TXD1, NCSI[0:1]_RXD0, NCSI[0:1]_RXD1, NCSI[0:1]_TXEN, NCSI[0:1]_CRSDV, NCSI[0:1]_REFCLK, NCSI[0:1]_MDC, NCSI[0:1]_ MDIO; A35 / B35 / A35 / B35 pins: 4-channel CPIO signal BMC_CPU_GPIO[0:3]; A37 / B37 pins: serial port signal for communication with the main processor BMC_UART2_RX / TX; A38 / B38 pins: BMC status indicator control signals BMC_STATUS_Error#, BMC_STATUS_RDY#; A39 pins: power-off enable signal for abnormal conditions such as power supply and temperature BMC_PWR_ON; A41 / B41 pins: RTC chip communication signal BMC_RTC_SCL / SDA; A42 / B42 pins: configurable as serial port or I2C signals BMC_MIO9_A, BMC_MIO9_B; A45 / B45 pins: power supply VDD3V3_AUX input, supplying power to the module. Other unmentioned pins are GND pins.

[0026] The BMC health management module is powered by an external 3.3V supply (VDD3V3_AUX) from pins A45 / B45 / B44 of the CTOLC_180PIN connector, which is then converted to VDD3V3 via a fuse. The E2000S core power supply (0.8V) is converted from VDD3V3 to 0.8V by the Huawei power chip NAE12S17-B; the LPDDR4 interface (1.1V) is converted from VDD3V3 to 1.1V by the Huawei power chip NAE03S03-B; the LPDDR4 interface (0.6V) is converted from VDD3V3 to 1.2V by the Huawei power chip NAE03S03-B, which then supplies power to the SGM2054XTD10G / TR DDR power chip, which converts it to 0.6V; and the E2000S processor (1.8V) is converted from VDD3V3 to 1.8V by the Huawei power chip NAE03S03-B. The 1.65V ADC reference voltage of the E2000S processor ADC_VREF is powered by a voltage divider (VDD3V3) consisting of two 1K / 1% 0402 resistors, filtered by a 100Nf / 50V capacitor.

[0027] The above-described embodiments are merely one implementation of the present invention. The design method of the present invention is also applicable to other processors with BMC health management and can be used in industries such as computers and servers. The technical solution proposed in this invention realizes a BMC health management module based on Tenglong E2000S. It is fully domestically produced, has rich interfaces, is compact in size, and can be flexibly configured and reused in different application scenarios to achieve efficient application, shorten product development cycle and reduce R&D investment. The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A BMC health management module based on Tenlong E2000S, characterized in that, The BMC health management module includes: an E2000S processor, an LPDDR4 memory chip, a 50MHz active crystal oscillator, a FLASH memory chip, a USB switch, a power supply, and a CTOLC_180PIN connector. The LPDDR4 memory chip and the Tenglong E2000S processor are connected by signal according to the relevant LPDDR4 protocol to realize the full chip main memory space; The 50MHz active crystal oscillator is powered by 3.3V_AUX through a 120ohm / 3A ferrite bead. The STDBY pin is pulled up to the power supply with a resistor. The clock output pin CLK is connected to the E2000S processor with a resistor as the E2000S reference clock. A QSPI Flash chip is connected to the Tenglong E2000S processor according to the relevant QSPI protocol design to store the BIOS firmware; One SPI Flash chip is connected to the SPI3 signal of the Tenglong E2000S processor according to the relevant SPI protocol design, and is used to store the operation log; The KVM switching USB 2.0 signal KVM0_USB2_P2_DP / N of the Tenlong E2000S processor and the USB 2.0 signal BMC_USB2_P2_DP / N transmitted from the host processor on CTOLC_180PIN are connected to the USB switching switch. The USB enable signal E2000_USB2_EN of the Tenlong E2000S processor controls the enable, realizing KVM switching. The Tenlong E2000S processor's signal debugging USB 2.0 port is connected to a two-pin header via a common-mode inductor and ESD protection design for debugging purposes. The CTOLC_180PIN connector is a 180PIN dual-row high-speed connector used to bring out the external interface signals of the Tenglong E2000S processor.

2. The BMC health management module based on Tenlong E2000S as described in claim 1, characterized in that, The LPDDR4 memory chip uses an onboard X32 2GB memory chip, model CXDB4ABAM-MK; the 50MHz active crystal oscillator is OT322550MJBA4SL.

3. The BMC health management module based on Tenlong E2000S as described in claim 1, characterized in that, The QSPI Flash uses Fudan Microelectronics' 512Mb Flash, model EFM25QL512.

4. The BMC health management module based on Tenlong E2000S as described in claim 1, characterized in that, The model number of the USB switch is GMH3USB31.

5. The BMC health management module based on Tenlong E2000S as described in any one of claims 1-4, characterized in that, The CTOLC_180PIN connector is a surface-mount 180-pin connector with a positioning pin. It has a rated current of 2.5A, a transmission rate of 10Gbps, a pin pitch of 1.27mm, and uses a "fork-tone" dual-contact design with gold-plated contacts. The four-row pin arrangement uses two sets of surface-mount pins with varying lengths. Pin signals are defined according to requirements. The routing starting point in the Cadence PCB design software is the center of the pad. If differential lines are defined as two adjacent pins of varying lengths, the corresponding short pin routing needs to be compensated by 0.63mm to ensure equal length differential pairs. The four rows of pins are grouped: one group includes short pins A1-A45 and long pins B1-B45, and the other group includes long pins C1-C45 and short pins D1-D45, with the pins arranged in a crisscross pattern. Signal design follows the rule of adjacent signals within the same group and grounded signals for different groups. The CTOLC_180PIN connector consists of two parts: Part 1 and Part 2.

6. The BMC health management module based on Tenlong E2000S as described in claim 5, characterized in that, Part 1, or X1-1, has pins A1~A20, B1~B20, C1~C20, and D1~D20; the signals include: The C4 / D4 and C6 / D6 pins communicate with the main processor via the PCIe X1 signal CPU_BMC_PCIex1_RX / TXP / N; The C2 / D2 pins are for the 100MHz PCIe differential clock signal BMC_PCIE_100M_REFCLKP / N; the A5 / B5 / A3 / B3 / A7 / B7 pins are for the DP display signal E2000_DP0_L0_P / N, the 100MHz DP clock signal BMC_DP0_100M_REFCLKP / N, and E2000_DP0_AUX_P / N. Pin A9 is E2000_DP0_HPD; The C9 / D9 pin is the USB3 signal USB20_BMC_P / N5 of the Tenglong E200S processor; Pins C8 / D8 are the USB signal USB20_BMC_P / N4 for KVM switching; Pins B9 / A10 / B10 are the reset signals E2000_RSTn, E2000_PCIE_RSTn, and E2000_CORE_RSTn for the Tenglong E2000S. Pins A11 / A12 / A14 / A15 / B11 / B12 / B14 / B15 / C15 / D15 are the fan control signals P6_FAN_TACH[0:3], P6_FAN_PWM[0:3], and FAN_SCL / SDA; Pins A17 / B17 are the main processor over-temperature indication signals CPU0_D[0:1]_TEMP_OVER_TO_BMC; Pins C11 / D11 are the temperature sensor I2C signal BMC_TEMP_SCL / SDA; pins C12 / D12 / C13 / D13 / C14 / D14 are the CAP and CA[0:4] address signals connected to the P0 slot of the VPX board. Pins C16 / D16 are the E2000S UART1 debug serial port signals CPU_DEBUG_UART1_RX / TX_TO_BMC; Pin A16 is the master processor firmware switching enable pin signal BIOS_QSPI_SEL#; pins A18 / B18 / A19 / B19 are the Kunlun firmware configuration signals connected to the CPLD: PowerON_CPLD_to_BMC, PowerOFF_CPLD_to_BMC, RESTART_CPLD_to_BMC, and PowerGD_CPLD_to_BMC. Pins A17 / B17 are the Uart0 debug serial port signal E2000_Debug_R / TXD for the Tenlong E2000S; pins C18 / D18 are the reserved CRU I2C interface signal BMC_CPU_I2C0_CRU_SCL / SDA; pins C19 / D19 / C19 / D19 are the IPMB signal IPMB_IIC[0:1]_SCL / SDA connected to the P0 slot management control of the VPX board.

7. The BMC health management module based on Tenlong E2000S as described in claim 5, characterized in that, Part 2, or X1-2, pins A21~A45, B21~B45, C21~C45, D21~D45; signals include: The C21 / D21 pin is the voltage detection I2C bus BMC_Voltage_I2C_SCL / SDA, which is connected to the SM2990 to extend the ADC voltage monitoring signal. Pins A22 / B22 / A23 / B23 / A24 / B24 are the RACK_ID[0:5] signals connected to the data transmission of each device on the VPX board P6; Pins C23 / D23 / C24 / D24 are reserved for configurable SPI or GPIO signals BMC_SPI2SCLK / GPIO3_3, BMC_SPI2RXD / GPIO3_4, BMC_SPI2TXD / GPIO3_5, and BMC_SPI2CSN0 / GPIO3_6. Pins A25 / B25 / A26 / B26 are the system firmware upgrade SPI signals BMC_SPIM0_SCLK, BMC_SPIM0_TXD, BMC_SPIM0_RXD, and BMC_SPIM0_CSN0; pins A27 / B27 / A28 / B28 / A29 are the E2000S JTAG signals E2000_JTAG_TCK, E2000_JTAG_TDI, E2000_JTAG_TDO, E2000_JTAG_TMS, and E2000_JTAG_NTRST. Pin C26 is the BMC system reset response signal RSTn_CPLD_to_BMC connected to the CPLD; pins D26 / C27 / D27 / C28 / D28 / C29 / D29 / C30 / D30 are the LPC data processing signals E2000_LPC_LDRQn, E2000_LPC_SIRQn, E2000_LPC_CLK_33M, E2000_LPC_AD0, E2000_LPC_AD1, E2000_LPC_AD2, E2000_LPC_AD3, E2000_LPC_LFRAMEn, and E2000_LPC_RSTn for data communication with the main processor. Pins A30 / B30 / A31 / B31 / A32 / B32 / A33 / B33 are for 8-channel ADC power detection signals BMC_ADC[0:7]; The C32 / D32 / C33 / D33 / C34 / D34 / C35 / D35 / C33 / D33 / C34 / D34 / C35 / D35 / C36 / D36 / C37 / D37 / C39 / D39 / C40 / D40 / C41 / D41 / C42 / D42 / C43 / D43 / C44 / D44 pins are 2 NCSI signals: NCSI[0:1]_TXD0, NCSI[0:1]_TXD1, NCSI[0:1]_RXD0, NCSI[0:1]_RXD1, NCSI[0:1]_TXEN, NCSI[0:1]_CRSDV, NCSI[0:1]_REFCLK, NCSI[0:1]_MDC, NCSI[0:1]_MDIO; The A35 / B35 / A35 / B35 pins are 4-channel CPIO signals BMC_CPU_GPIO[0:3]; The A37 / B37 pins are the serial port signals BMC_UART2_RX / TX for communication with the main processor. The A38 / B38 pins are the BMC status indicator control signals BMC_STATUS_Error# and BMC_STATUS_RDY#. Pin A39 is the power-off enable signal BMC_PWR_ON for abnormal power, temperature, and other conditions. Pins A41 / B41 are the RTC chip communication signals BMC_RTC_SCL / SDA; Pins A42 / B42 are configurable as serial port or I2C signals BMC_MIO9_A and BMC_MIO9_B; pins A45 / B45 are power inputs VDD3V3_AUX, supplying power to the module. Other unmentioned pins are GND pins.

8. The BMC health management module based on Tenlong E2000S as described in claim 7, characterized in that, The BMC health management module is powered externally at 3.3V (VDD3V3_AUX) via the A45 / B45 / B44 pins of the CTOLC_180PIN connector, converted to VDD3V3 after passing through a fuse. The E2000S core power supply is 0.8V, which is converted from VDD3V3 to 0.8V by the NAE12S17-B power chip. The LPDDR4 interface's 1.1V power supply is converted from VDD3V3 to 1.1V by the NAE03S03-B power chip. The LPDDR4 interface's 0.6V power supply is converted from VDD3V3 to 1.2V by the NAE03S03-B power chip, which then supplies power to the DDR power chip SGM2054XTD10G / TR, converting it to 0.6V. The E2000S processor's 1.8V power supply is also converted from VDD3V3 to 1.8V by the NAE03S03-B power chip. The E2000S processor's ADC_VREF power supply is 1.65V. The ADC reference voltage is supplied by a voltage divider consisting of two resistors, VDD3V3, which is then filtered by a 100Nf / 50V capacitor.

9. The BMC health management module based on Tenlong E2000S as described in claim 1, characterized in that, The front (TOP) side of the BMC health management module is the main component side, containing a Tenlong E2000S processor, LPDDR4 memory chip, and power chip; the back (BOT) side is the connector mating side, and the mating connector is a high-speed connector from AVIC Optoelectronics, model: CTOLC-145-22-LQA. After mating with the motherboard, the mating height is 10mm, the module side height limit is 3mm, and the motherboard side height limit is 5mm. The BMC health management module is designed with four mounting holes with a diameter of 2.7mm and a pad size of 6mm. The mounting holes on both sides of the connector increase the mating reliability of the CTOLC_180PIN connector and, together with the other two mounting holes, strengthen the robustness between the module and the motherboard. The BMC health management module features two concave arcs on both sides for easy insertion; the four corners of the board are chamfered to prevent accidental damage from sharp corners during insertion and removal.

10. The BMC health management module based on Tenlong E2000S as described in claim 1, characterized in that, The BMC health management module uses military-grade TU-752 board material with a 12-layer stacked design, meeting the acceptance standards of military-grade printed circuit boards GJB362C-2021. The 12-layer stack-up includes two top layers and ten inner layers. The first layer (TOP) and the twelfth layer (BOTTOM) are component layers. The ten inner layers include four routing layers (L3, L5, L8, L10), four GND layers (L2, L4, L9, L11), and two power layers (L6, L7). Both routing layers L3 and L10 have ground planes on both sides, ensuring complete signal reference. They are the main routing layers used for routing important and high-speed signals. Both L5 and L8 signal layers are ground layers on one side and power layers on the other. They are secondary routing layers, containing a mix of LPDDR4 address signals, some power supplies, and a small number of low-speed single-ended traces. The LPDDR4 address signals ensure the integrity of the reference and also provide a path for the LPDDR4 power supply. L6 and L7 are power planes, which are recessed 3H relative to the ground plane, where H is the distance from the power plane to the ground plane. The power supply design ensures the continuity of the reference impedance of adjacent traces while meeting the power supply requirements of each chip in the circuit; the wiring impedance requirements are designed and simulated according to the requirements of the Tenglong E2000S processor to ensure signal quality.

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