Wind power converter reliability evaluation method considering chip thermal coupling effect

Abstract

The invention belongs to the technical field of reliability evaluation of wind power converters, and particularly relates to a reliability evaluation method of a wind power converter considering a chip thermal coupling effect, which comprises the following steps: S1, generating a time sequence wind speed sequence with statistical representativeness; s2, solving to obtain a time sequence operation power sequence of the wind power converter; s3, solving to obtain a time sequence power loss sequence of each chip; s4, based on the geometric layout of each chip and the thermal characteristics of the packaging material, establishing a multi-chip thermal coupling model containing a transverse thermal diffusion effect; based on the multi-chip thermal coupling model, constructing an equivalent thermal network model considering mutual thermal influence between the chips; solving to obtain junction temperature time sequence response and junction temperature fluctuation characteristics of each chip; s5, evaluating the service life of each chip based on the junction temperature time sequence response of each chip obtained in S4; and S6, calculating the overall time-varying reliability of the IGBT module and the wind power converter. According to the method, more accurate and real time-varying reliability prediction of the wind power converter can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of reliability evaluation of wind power converters, and particularly relates to a wind power converter reliability evaluation method considering chip thermal coupling effect. BACKGROUND

[0002] In a wind turbine, a power electronic converter is a core component for realizing efficient conversion of wind energy and electric energy, and its operation reliability is directly related to the stability and availability of the entire wind turbine. Statistical data shows that wind turbine shutdown events caused by converter failures account for more than 40%, which has become one of the main bottlenecks affecting the operation and maintenance cost and power generation efficiency of the wind power system. Inside the converter, power semiconductor devices are the key elements for realizing electric energy conversion, among which insulated gate bipolar transistor (IGBT) modules are widely used in the main circuit topology of wind power converters due to their fast switching speed, small driving power, strong voltage withstand capability, and high current carrying capacity. However, a large number of field failure data shows that IGBT modules are one of the components most prone to failure in the converter, and their reliability level largely determines the service life of the wind power converter and even the entire machine.

[0003] Current research generally believes that the main mechanism of IGBT module failure is thermal mechanical fatigue caused by junction temperature fluctuations during long-term operation, leading to packaging level failures such as bond wire shedding and solder layer cracking. Therefore, for the reliability evaluation of wind power converters, the academic and industrial communities generally take the junction temperature evolution characteristics of IGBT modules as the core basis. Existing research has improved the accuracy of reliability evaluation from multiple angles: on the one hand, some scholars combined the random characteristics of wind speed, built a wind speed model based on the two-parameter Weibull distribution, and further established the mapping relationship between wind turbine power output and converter operating conditions, thus more truly reflecting the power stress in actual operation; on the other hand, researchers have also considered the influence of changes in converter control parameters (such as modulation strategy, switching frequency) on IGBT power loss and junction temperature fluctuations, and fitted a life model suitable for specific operating conditions through accelerated aging test data, significantly improving the accuracy of life prediction. In addition, the influence of environmental factors (such as ambient temperature, humidity) on heat dissipation performance and device aging rate has also been included in the reliability analysis framework, and some research even distinguishes the differences in operating characteristics between the machine-side and grid-side converters, establishes a separate aging model, and reveals the reliability differences between the two sides of IGBT modules due to different junction temperature fluctuations.

[0004] However, in the aforementioned existing technologies, the calculation of IGBT module junction temperature mostly relies on traditional one-dimensional thermal impedance models, such as the Foster or Cauer equivalent thermal network model. These models typically assume that heat is conducted unidirectionally only in the vertical direction (i.e., from the chip through solder, substrate, and thermal interface material to the heat sink), neglecting the lateral thermal diffusion effect existing within the same package or between adjacent modules. In actual wind power converters, multiple IGBT chips are usually integrated on the same substrate or closely arranged in adjacent areas. Under high power density operating conditions, each chip, as an independent heat source, will influence each other, forming a complex multi-chip thermal coupling phenomenon. This thermal coupling effect means that the heating of one chip not only affects its own junction temperature but also raises the temperature base of adjacent chips through the lateral thermal conduction of the substrate material, leading to local hot spot accumulation and uneven thermal stress distribution, thereby exacerbating temperature fluctuation amplitude and thermal cycling stress. Studies have shown that neglecting this effect will lead to an underestimation of junction temperature, especially under dynamic loads or conditions of severe wind speed fluctuations, resulting in an overly optimistic estimate of device lifespan.

[0005] While some preliminary research has begun to focus on the thermal coupling problem in multi-chip systems and has attempted to establish two-dimensional or three-dimensional thermal models incorporating lateral heat transfer to improve the accuracy of junction temperature calculations, these studies have largely concentrated on static thermal field analysis or simulation verification under specific operating conditions. They have not yet been systematically integrated into a comprehensive analytical framework encompassing wind speed modeling and reliability assessment. Particularly in time-varying conditions for wind power applications, organically combining stochastic wind speed excitation, dynamic power output, nonlinear thermal coupling responses between multiple chips, and fatigue accumulation effects still faces challenges such as high modeling complexity, large computational load, and strong coupling of physical mechanisms. Furthermore, due to the spatial dependence and temporal cumulative nature of thermal coupling effects, traditional single-chip independent analysis methods struggle to accurately capture the mutual thermal stress effects between chips within a module, leading to reliability assessment results deviating from reality.

[0006] Therefore, how to achieve more accurate and realistic time-varying reliability prediction for wind power converters has become an urgent problem to be solved. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, this invention provides a method for assessing the reliability of wind power converters that considers the thermal coupling effect of chips, enabling more accurate and realistic time-varying reliability predictions for wind power converters.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] A reliability assessment method for wind power converters considering chip thermal coupling effects includes the following steps:

[0010] S1. Based on the two-parameter Weibull distribution model, the wind speed during the wind farm's operating cycle is stochastically modeled to generate a statistically representative time-series wind speed sequence.

[0011] S2. Establish an output power model based on the power output characteristics of the wind turbine; use the time-series wind speed sequence obtained in S1 as the input of the output power model, and solve to obtain the time-series operating power sequence of the wind power converter;

[0012] S3. Based on the physical characteristics of the IGBT module, establish the power loss model of each chip inside the IGBT module; use the timing power sequence obtained in S2 and the preset converter control parameters as inputs to the power loss model, and solve to obtain the timing power loss sequence of each chip.

[0013] S4. Based on the geometric layout of each chip and the thermal properties of the packaging material, a multi-chip thermal coupling model including the lateral thermal diffusion effect is established; and based on the multi-chip thermal coupling model, an equivalent thermal network model considering the mutual thermal influence between chips is constructed; the timing power loss sequence of each chip obtained in S3 and the preset ambient temperature are used as inputs to solve for the junction temperature timing response and junction temperature fluctuation characteristics of each chip.

[0014] S5. Based on the junction temperature timing response of each chip obtained in S4, the temperature amplitude and average temperature of the thermal cycle are extracted using the rainflow counting method; combined with the segmented fatigue cumulative life model obtained by fitting the accelerated aging test data of the IGBT module, the service life of each chip is evaluated.

[0015] S6. Based on the lifetime assessment results of each chip obtained in S5, a two-parameter Weibull distribution function S(t) characterizing the reliability of each chip is obtained by fitting using statistical methods; and based on S(t) of each chip, the time-varying reliability of the IGBT module and the wind power converter as a whole is calculated according to the reliability calculation principle of the series system.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. Improved physical realism of junction temperature calculations. Compared to traditional methods that only consider longitudinal heat conduction within the chip using one-dimensional Foster or Cauer thermal network models, this approach establishes a multi-chip thermal coupling model in S4 that incorporates lateral heat diffusion effects, and constructs an equivalent thermal network accordingly. This model fully considers the spatial geometric layout of multiple chips within the IGBT module and the thermal conductivity of the packaging materials, accurately reflecting the mutual thermal influence between chips. Therefore, it avoids the junction temperature underestimation problem caused by neglecting lateral heat transfer in traditional methods, significantly improving the accuracy of junction temperature timing response calculations, especially under high power density or dynamic load conditions.

[0018] 2. Enhanced dynamic correlation between power loss and thermal behavior. This scheme starts with stochastic wind speed modeling (S1) and gradually derives power sequences (S2) and chip-level loss sequences (S3), achieving a refined mapping from external meteorological conditions to internal device power loss. Compared to existing technologies that often use typical operating conditions or steady-state assumptions for simplified analysis, this method fully preserves the time-varying and stochastic nature of wind power operating conditions, making the input for subsequent thermo-mechanical-lifetime analysis closer to actual operating conditions and improving the engineering applicability of the entire evaluation chain.

[0019] 3. This solution enables differentiated lifetime assessment at the multi-chip system level. Due to the thermal coupling effect between chips, the junction temperature fluctuation characteristics experienced by chips at different locations vary. Based on accurate junction temperature response in S5, this solution combines rainflow counting and a segmented fatigue lifetime model to independently assess the lifetime loss of each chip. Compared to the traditional method of treating the IGBT module as a single heat source and uniformly calculating its lifetime, this approach more realistically reflects the inconsistency in aging among the chips within the module, providing a more granular basis for module-level reliability assessment.

[0020] 4. A complete quantitative path from device failure to system reliability is constructed. In S6, by fitting the lifetime assessment results of each chip to a two-parameter Weibull distribution function and calculating the overall time-varying reliability based on the reliability theory of series systems, a seamless connection from microscopic failure mechanisms to macroscopic system performance is achieved. Compared with existing methods that only provide the mean time between failures (MTBF) or qualitatively judge reliability, this scheme outputs a reliability curve that evolves over time, which can support risk warning and operation and maintenance decisions for wind power converters throughout their entire life cycle.

[0021] In summary, this method can achieve more accurate and realistic time-varying reliability prediction for wind power converters.

[0022] Preferably, in S5, the process of evaluating the lifespan of each chip using the segmented fatigue cumulative life model includes:

[0023] In the first stage, when the normalized thermal resistance increment is less than 0.5%, the normalized thermal resistance value is calculated using a linear stage model.

[0024] In the second stage, when the normalized thermal resistance increment is greater than or equal to 0.5%, the normalized thermal resistance value is iteratively updated using a nonlinear iterative growth model.

[0025] When the normalized thermal resistance reaches 1.5, the chip is considered to have failed, and its failure time is used as the life assessment result.

[0026] Preferably, in the first stage, the linear stage model is as follows:

[0027]

[0028] In the formula, R th The normalized thermal resistance is initially set to 1; N(i) represents the number of thermal cycles of type i, obtained through rainflow counting; N c (i) represents the number of cycles that increase the thermal resistance by 0.5% for the i-th type of thermal cycle; a1, a2, and a3 are parameters of the linear stage obtained through accelerated aging tests; ΔT j (i) represents the temperature amplitude of the i-th type of thermal cycle, i.e., the difference between the maximum and minimum chip junction temperatures in this thermal cycle: T jm (i) represents the average temperature of the i-th type of thermal cycle.

[0029] Preferably, in the second stage, the nonlinear iterative growth model is:

[0030] R th (t+1)=R th (t)+N(i)·R(t);

[0031]

[0032] In the formula, t is time; R th (t) represents the normalized thermal resistance value at time t; b1, b2, b3, b4, b5, and b6 are parameters of the nonlinear stage obtained through accelerated aging tests; R(t) is the thermal resistance growth rate at time t, i.e., the relative increase in thermal resistance per unit time; ΔT j (t) represents the current thermal cycle temperature amplitude at time t; R th (i) represents the normalized thermal resistance value corresponding to the i-th type of thermal cycle, indicating the thermal resistance growth state of the device under this type of cycle.

[0033] This approach offers several advantages: 1. It enhances the sensitivity of the lifespan prediction model to early aging behavior. Traditional fatigue life models often employ a single empirical formula (such as the Coffin-Manson model) for thermal cycling accumulation, which struggles to accurately characterize the aging characteristics of devices in the initial low-stress phase. This approach, by introducing a linear stage model, can more precisely reflect the accumulation process of thermal resistance within a small increment, making it particularly suitable for describing the slow degradation of devices caused by slight thermomechanical fatigue during the initial operation phase, thus avoiding underestimation of the early aging process.

[0034] 2. Enhanced ability to describe the accelerated aging process in later stages. In the later stages of device service, the aging rate accelerates significantly due to the exacerbation of nonlinear damage mechanisms such as bonding layer fatigue and solder creep. Existing models often assume a linear or power-law relationship in the aging process, making it difficult to capture this accelerating trend. This scheme introduces a nonlinear iterative growth model in the second stage, correlating the thermal resistance growth rate R(t) with the current thermal cycling temperature amplitude and historical thermal resistance state. This achieves dynamic feedback on aging dynamics and more realistically reflects the nonlinear evolution characteristics of the actual failure mechanism.

[0035] 3. The model achieves phased modeling and continuous transition of the aging process. By setting a 0.5% thermal resistance increment threshold to divide the linear and nonlinear stages, the model retains the stability of the early aging stages while also possessing the ability to respond to rapid degradation in later stages. This segmented structure not only improves the model's adaptability but also ensures a smooth transition in aging assessment from low-stress to high-stress conditions, avoiding the problem of insufficient applicability of a single model throughout the entire life cycle.

[0036] 4. Enhanced interpretability and engineering applicability of lifetime assessment. Normalized thermal resistance, as an aging indicator, has clear physical meaning and measurability, facilitating comparison and verification with actual test data. Furthermore, all model parameters are derived from accelerated aging tests, ensuring the experimental basis and engineering credibility of the model. Compared to traditional methods relying on pure statistical fitting or black-box models, this approach provides a more physically supported lifetime evolution path, contributing to improved interpretability and application value of the assessment results.

[0037] Preferably, in S1, the shape parameter k and scale parameter c of the two-parameter Weibull distribution model are obtained by fitting the historical wind speed data of the target wind farm.

[0038] Preferably, in S2, the output power model is established in which the output power of the wind turbine is calculated in segments according to the wind speed range, and it is assumed that the operating power of the wind power converter is consistent with the output power of the wind turbine; wherein, the wind speed range includes four ranges: below the cut-in wind speed, below the rated wind speed, below the cut-out wind speed, and above the cut-out wind speed.

[0039] Preferably, in S2, the wind turbine output power P out The formula for calculation is:

[0040]

[0041] In the formula, V wind V represents the operating wind speed. ci V co V r These are the cut-in wind speed, cut-out wind speed, and rated wind speed, respectively; A, B, and C are constants.

[0042] The calculations for A, B, and C are as follows:

[0043]

[0044] This approach offers several advantages: 1. Compared to traditional methods that use idealized linear or simple parabolic models to describe wind power curves, this scheme, by introducing a cubic coefficient C and combining it with precise analytical calculations of A and B, can more accurately characterize the nonlinear power growth process of wind turbines as they enter the rated wind speed range. Especially in low-wind-speed sections and near-rated-wind-speed areas, this model better matches the aerodynamic response of real turbines, avoiding power prediction deviations caused by simplification assumptions. Furthermore, this piecewise model ensures the continuity of the output power function at the boundary points of each wind speed range, effectively avoiding power jumps caused by abrupt changes. Compared to some methods that only model specific ranges while ignoring overall smoothness, this scheme helps improve the physical plausibility of subsequent time-series power sequence generation and reduces the interference of numerical fluctuations on downstream thermal-electrical-lifetime analysis.

[0045] 2. The coefficients in the model depend only on the basic design parameters of the wind turbine (such as rated power, cut-in / rated / cut-out wind speed), and can be directly calculated using analytical formulas without relying on a large amount of measured data for fitting. This makes the model highly versatile and portable, suitable for rapid modeling and simulation analysis of different types of wind turbines.

[0046] Preferably, in S3, the power loss of the IGBT module includes the conduction loss and switching loss of the IGBT chip and the anti-parallel diode chip.

[0047] In S4, the equivalent thermal network model adopts a Cauer-type RC network structure. The longitudinal thermal resistance of a single chip is calculated based on the thermal conductivity and thickness of each layer of material and the effective thermal conduction area determined by the thermal diffusion angle. The inter-chip coupling thermal resistance is calculated by analyzing the overlapping area of ​​the thermal diffusion paths of adjacent chips in each layer of material and integrating the transverse thermal resistance.

[0048] The multi-chip thermal coupling model covers IGBT and diode chips in each arm of the wind power converter on both the machine side and the grid side. The equivalent thermal network model includes multiple mutually coupled heat sources and heat paths.

[0049] This approach, compared to traditional methods that rely solely on simplified empirical formulas or ignore switching losses, fully utilizes key electrical parameters (such as on-state voltage drop and switching energy) provided in the device datasheet and performs separate calculations based on actual operating conditions (such as current, voltage, modulation ratio, and switching frequency). This allows for a more realistic reflection of the energy loss distribution of the IGBT module under dynamic loads. This physics-based modeling method avoids error accumulation caused by parameter extrapolation or approximate assumptions, significantly improving the accuracy of power loss prediction.

[0050] 2. Traditional one-dimensional thermal resistance models typically neglect lateral thermal interaction between chips. This approach, however, introduces lateral thermal coupling resistance and performs integral calculations based on the overlapping regions of thermal diffusion paths, achieving a quantitative description of heat transfer between adjacent chips. This allows the model to not only capture the longitudinal heat dissipation characteristics of a single chip but also reflect the localized temperature rise caused by thermal crosstalk when multiple chips share a substrate, thus more realistically simulating the non-uniform temperature field in actual packaging.

[0051] 3. This solution not only establishes a thermal network for a single IGBT or diode chip, but also extends it to the multi-chip combination system of the entire converter bridge arm, covering all key power devices on both the generator and grid sides. By constructing multiple mutually coupled heat sources and thermal paths, a complete thermodynamic system model is formed, supporting the collaborative solution of the junction temperature response of each chip within the entire IGBT module, thus overcoming the systematic bias problem caused by traditional independent modeling.

[0052] Preferably, in S4, during the process of establishing the multi-chip thermal coupling model, the thermal resistance and convective heat transfer resistance of the single-layer structure are calculated based on the following formula, taking into account lateral thermal diffusion:

[0053]

[0054] In the formula, R thj R th_conv A j These represent the thermal resistance of the j-th layer, the convective heat transfer thermal resistance, and the equivalent heat conduction area, respectively; N is the maximum number of layers.

[0055] k j ρ j t j θ j , respectively, represent the thermal conductivity, density, thickness, and thermal diffusion angle of the j-th structural material; h is the convective heat transfer coefficient; l j-1 w j-1 The initial equivalent heat conduction surface A of the j-th layer is respectively j-1 Length and width; l j w j Equivalent heat conduction surface A jThe length and width of the chip; l0 and w0 are the length and width of the initial heat source chip, respectively; z is the vertical coordinate in the direction of heat conduction, representing the distance the heat is conducted upwards along the thickness direction from the top surface of the chip; L c W c These represent the length and width of the initial heat source chip, respectively.

[0056] This approach offers several advantages over traditional methods that treat each material layer as a uniform thin plate and calculate thermal resistance using a constant cross-sectional area. By introducing the thermal diffusion angle and the equivalent heat transfer area that varies with depth, this scheme accurately describes the phenomenon of gradually increasing cross-sectional area as heat diffuses upwards from the chip surface. This modeling method better reflects the three-dimensional characteristics of heat flow propagation between multiple heterogeneous materials in real-world packaging, avoiding the underestimation of thermal resistance caused by neglecting lateral thermal diffusion.

[0057] 2. Enhanced accuracy in characterizing non-uniform thermal fields in complex packaging structures. In IGBT modules, different material layers (such as silicon chips, solder, substrates, and heat sinks) have different thermal conductivity and thermal diffusivity, leading to uneven heat flow distribution. This solution calculates thermal resistance through layer-by-layer integration and dynamically adjusts the heat transfer area based on the thermal diffusivity angle. This effectively captures the changing trends of heat flux density within each layer, making it particularly suitable for thermal behavior analysis under high power density or asymmetric layouts, significantly improving the model's accuracy in predicting local hot spots.

[0058] 3. This approach achieves a description of the thermal resistance model from static assumptions to dynamic evolution. Traditional models typically treat thermal resistance as a constant or solely dependent on material properties. However, this scheme expresses thermal resistance as an integral function along the thickness direction, making it a function of spatial coordinates and reflecting the spatial evolution of the heat conduction process. This allows the model to not only reflect steady-state thermal resistance values ​​but also support transient thermal response analysis, providing a higher-order physical foundation for subsequent junction temperature dynamic simulations.

[0059] Preferably, in S4, during the process of establishing the multi-chip thermal coupling model, the coupling thermal resistance between each chip is also calculated based on the same calculation method; wherein, in the j-th layer, the calculation formula for the coupling thermal resistance of chip 2 to chip 1 is:

[0060]

[0061] In the formula, R thj_2 Let A be the thermal resistance of chip 2 in layer j; j2 (z) represents the effective thermal conductivity area of ​​chip 2 at the z-coordinate of the j-th layer; z cj A represents the z-axis coordinate where the thermal paths of the two chips intersect; 12 (z) Effective thermal conductivity area of ​​chip 2 at z coordinate of layer 1.

[0062] This approach offers several advantages: 1. Compared to traditional methods that ignore inter-chip thermal effects or rely solely on empirical coefficients to estimate coupling effects, this scheme directly calculates the thermal resistance corresponding to the shared thermal path between two chips using an integral method. This accurately reflects the physical process of heat transfer from one chip to another. This calculation method, based on geometric and thermal diffusion characteristics, avoids errors caused by human assumptions and significantly improves the scientific rigor of thermal coupling modeling.

[0063] 2. In actual IGBT modules, chips may have different sizes, locations, or heat source intensities, resulting in complex overlaps in their heat diffusion paths across different material layers. This solution analyzes the effective heat transfer area layer by layer and limits the integration interval to the thermal overlap region, allowing for flexible handling of arbitrary chip arrangements. It is applicable to various layouts of IGBT and diode chips in both machine-side and grid-side bridge arms, exhibiting good versatility and scalability. Attached Figure Description

[0064] To make the objectives, technical solutions, and advantages of the invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0065] Figure 1 This is a flowchart of the method;

[0066] Figure 2 This is a schematic diagram of the IGBT module layering based on thermal diffusion angle in the embodiment;

[0067] Figure 3 This is the equivalent model of the Cauer-type RC thermal network of the IGBT module in the embodiment;

[0068] Figure 4 This is a schematic diagram of the heat diffusion path formed by the two chips in the embodiment;

[0069] Figure 5 This is a schematic diagram of the intersecting thermal paths of the two chips in the embodiment;

[0070] Figure 6 This is a schematic diagram of a two-chip thermal network model considering thermal coupling effects in the embodiment;

[0071] Figure 7 This is a simplified schematic diagram of the wind power converter chip in the embodiment;

[0072] Figure 8 This is a schematic diagram of the multi-chip thermal coupling circuit model in the embodiment;

[0073] Figure 9 This is a schematic diagram of the multi-chip thermal coupling equivalent thermal network model in the embodiment. Detailed Implementation

[0074] The following detailed explanation illustrates the specific implementation methods:

[0075] Example:

[0076] like Figure 1 As shown, this embodiment discloses a method for reliability assessment of wind power converters considering chip thermal coupling effects, including the following steps:

[0077] S1. Based on the two-parameter Weibull distribution model, the wind speed during the wind farm's operating cycle is stochastically modeled to generate a statistically representative time-series wind speed sequence.

[0078] In practice, the shape parameter k and scale parameter c of the two-parameter Weibull distribution model are obtained by fitting the historical wind speed data of the target wind farm.

[0079] S2. Establish an output power model based on the power output characteristics of the wind turbine; use the time-series wind speed sequence obtained in S1 as the input of the output power model, and solve to obtain the time-series operating power sequence of the wind power converter.

[0080] In specific implementation, in the established output power model, the output power of the wind turbine is calculated in segments according to the wind speed range, and it is assumed that the operating power of the wind power converter is consistent with the output power of the wind turbine; wherein, the wind speed range includes four ranges: below the cut-in wind speed, below the rated wind speed, below the cut-out wind speed, and above the cut-out wind speed.

[0081] Wind turbine output power P out The formula for calculation is:

[0082]

[0083] In the formula, V wind V represents the operating wind speed. ci V co V r These are the cut-in wind speed, cut-out wind speed, and rated wind speed, respectively; A, B, and C are constants.

[0084] The calculations for A, B, and C are as follows:

[0085]

[0086] Compared to traditional methods that use idealized linear or simple parabolic models to describe wind power curves, this approach, by introducing a cubic coefficient C and combining it with precise analytical calculations of A and B, can more accurately characterize the nonlinear power growth process of wind turbines from cut-in to rated wind speed. Especially in the low-wind-speed range and near-rated-wind-speed region, this model better matches the aerodynamic response of real turbines, avoiding power prediction biases caused by simplification assumptions. Furthermore, this piecewise model ensures the continuity of the output power function at the boundary points of each wind speed range, effectively avoiding power jumps caused by abrupt changes. Compared to some methods that only model specific ranges while ignoring overall smoothness, this approach helps improve the physical rationality of subsequent time-series power sequence generation and reduces the interference of numerical fluctuations on downstream thermal-electrical-lifetime analysis. In addition, the coefficients in the model only depend on the basic design parameters of the wind turbine (such as rated power, cut-in / rated / cut-out wind speeds), which can be directly calculated using analytical formulas, without relying on a large amount of measured data for fitting. This makes the model highly versatile and portable, suitable for rapid modeling and simulation analysis of different types of wind turbines.

[0087] S3. Based on the physical characteristics of the IGBT module, establish the power loss model of each chip inside the IGBT module; use the timing power sequence obtained in S2 and the preset converter control parameters as inputs to the power loss model, and solve to obtain the timing power loss sequence of each chip.

[0088] The power loss of the IGBT module includes the conduction loss and switching loss of the IGBT chip and the anti-parallel diode chip. In practice, conduction loss is calculated based on the on-state voltage drop and operating current parameters provided in the device datasheet, while switching loss is calculated based on the switching energy parameters, operating current, DC bus voltage, modulation ratio, and switching frequency provided in the device datasheet. Compared to traditional methods that only use simplified empirical formulas or ignore the proportion of switching losses, this approach fully utilizes the key electrical parameters (such as on-state voltage drop and switching energy) provided in the device datasheet and performs separate calculations based on actual operating conditions (such as current, voltage, modulation ratio, and switching frequency), thus more realistically reflecting the energy loss distribution of the IGBT module under dynamic loads. This physical mechanism-based modeling method avoids error accumulation caused by parameter extrapolation or approximate assumptions, significantly improving the accuracy of power loss prediction.

[0089] S4. Based on the geometric layout of each chip and the thermal properties of the packaging material, a multi-chip thermal coupling model including the lateral thermal diffusion effect is established; and based on the multi-chip thermal coupling model, an equivalent thermal network model considering the mutual thermal influence between chips is constructed; the timing power loss sequence of each chip obtained in S3 and the preset ambient temperature are used as inputs to solve for the junction temperature timing response and junction temperature fluctuation characteristics of each chip.

[0090] The equivalent thermal network model adopts a Cauer-type RC network structure. The longitudinal thermal resistance of a single chip is calculated based on the thermal conductivity and thickness of each layer of material and the effective thermal conduction area determined by the thermal diffusion angle. The inter-chip coupling thermal resistance is calculated by integrating the cross-sectional thermal impedance by analyzing the overlapping area of ​​the thermal diffusion paths of adjacent chips in each layer of material.

[0091] The multi-chip thermal coupling model covers IGBT and diode chips in each arm of the wind power converter on both the machine side and the grid side. The equivalent thermal network model includes multiple mutually coupled heat sources and heat paths.

[0092] Traditional one-dimensional thermal resistance models typically neglect lateral thermal interaction between chips. This approach, however, introduces lateral thermal coupling resistance and performs integral calculations based on the overlapping regions of thermal diffusion paths, achieving a quantitative description of heat transfer between adjacent chips. This allows the model to capture not only the longitudinal heat dissipation characteristics of a single chip but also reflect the localized temperature rise caused by thermal crosstalk when multiple chips share a substrate, thus more realistically simulating the non-uniform temperature field in actual packaging. Furthermore, this approach not only establishes thermal networks for individual IGBT or diode chips but also extends them to the entire multi-chip combination system of the converter bridge arm, covering all key power devices on both the machine and grid sides. By constructing multiple mutually coupled heat sources and thermal paths, a complete thermodynamic system model is formed, supporting the collaborative solution of the junction temperature response of each chip within the entire IGBT module, overcoming the systematic bias problem caused by traditional independent modeling.

[0093] For ease of understanding, the following illustration is provided; see [link / reference]. Figure 2 , Figure 3 This diagram illustrates the layered structure of the IGBT module based on the thermal diffusion angle and its equivalent model in a Cauer-type RC thermal network. In the diagram, A1, A2, ..., A7 represent the effective heat conduction area of ​​each layer, and θ... j T represents the thermal diffusion angle of the j-th layer structure. j T1, ..., T6 represent the surface temperatures of the chip's bonding layer, the direct bonding copper (DBC) substrate, and the substrate bonding layer, respectively. c This indicates the case temperature, specifically the temperature of the lower surface of the copper base plate, in T. a Indicates ambient temperature R th_conv This represents the convective heat transfer thermal resistance. The thickness of the j-th layer is t. j Its initial equivalent heat conduction surface A j-1 The length and width are l j-1 w j-1 Cut-off equivalent heat conduction surface A j The length and width are l j w jThe heat diffusion region of the j-th layer is determined by the diffusion angle θ. j Define.

[0094] In practical implementation, during the establishment of the multi-chip thermal coupling model, the thermal resistance and convective heat transfer resistance of the single-layer structure are calculated based on the following formula, taking into account lateral thermal diffusion:

[0095]

[0096] In the formula, R thj R th_conv A j These represent the thermal resistance of the j-th layer, the convective heat transfer thermal resistance, and the equivalent heat conduction area, respectively; N is the maximum number of layers.

[0097] k j ρ j t j θ j , respectively, represent the thermal conductivity, density, thickness, and thermal diffusion angle of the j-th structural material; h is the convective heat transfer coefficient; l j-1 w j-1 The initial equivalent heat conduction surface A of the j-th layer is respectively j-1 Length and width; l j w j Equivalent heat conduction surface A j The length and width of the chip; l0 and w0 are the length and width of the initial heat source chip, respectively; z is the vertical coordinate in the direction of heat conduction, representing the distance the heat is conducted upwards along the thickness direction from the top surface of the chip; L c W c These represent the length and width of the initial heat source chip, respectively.

[0098] Compared to traditional methods that treat each material layer as a uniform thin plate and calculate thermal resistance using a constant cross-sectional area, this approach introduces the thermal diffusion angle and the equivalent heat transfer area that varies with depth. This allows for an accurate description of the phenomenon where the cross-sectional area gradually increases as heat diffuses upwards from the chip surface. This modeling method better reflects the three-dimensional characteristics of heat flow propagation between multiple heterogeneous materials in real-world packaging, avoiding the underestimation of thermal resistance caused by neglecting lateral thermal diffusion. Furthermore, in IGBT modules, different material layers (such as silicon chips, solder, substrates, and heat sinks) have different thermal conductivity and thermal diffusion characteristics, leading to uneven heat flow distribution. This approach calculates thermal resistance through layer-by-layer integration and dynamically adjusts the heat transfer area using the thermal diffusion angle. This effectively captures the changing trends of heat flux density within each layer, making it particularly suitable for thermal behavior analysis under high power density or asymmetric layouts, significantly improving the model's accuracy in predicting local hotspots. Moreover, traditional models typically treat thermal resistance as a constant or solely dependent on material properties, while this approach expresses thermal resistance as an integral function along the thickness direction, making it a function of spatial coordinates and reflecting the spatial evolution characteristics of the heat conduction process. This allows the model to not only reflect steady-state thermal resistance but also support transient thermal response analysis, providing a higher-order physical basis for subsequent junction temperature dynamic simulation.

[0099] See Figure 4 and Figure 5 In practical implementation, during the establishment of the multi-chip thermal coupling model, the coupling thermal resistance between each chip is also calculated using the same calculation method; among them, in the j-th layer, the calculation formula for the coupling thermal resistance of chip 2 to chip 1 is:

[0100]

[0101] In the formula, R thj_2 Let A be the thermal resistance of chip 2 in layer j; j2 (z) represents the effective thermal conductivity area of ​​chip 2 at the z-coordinate of the j-th layer; z cj A represents the z-axis coordinate where the thermal paths of the two chips intersect; 12 (z) Effective thermal conductivity area of ​​chip 2 at z coordinate of layer 1.

[0102] Compared to traditional methods that ignore the thermal effects between chips or rely solely on empirical coefficients to estimate coupling effects, this approach directly calculates the thermal resistance corresponding to the shared thermal path between two chips using an integral method. This accurately reflects the physical process of heat transfer from one chip to another. This calculation method, based on geometric and thermal diffusion characteristics, avoids errors caused by human assumptions and significantly improves the scientific rigor of thermal coupling modeling. Furthermore, in actual IGBT modules, chips may have different sizes, locations, or heat source intensities, leading to complex overlaps in their thermal diffusion paths across different material layers. This approach, by analyzing the effective heat transfer area layer by layer and limiting the integration interval to the thermal path overlap region, can flexibly handle arbitrary chip arrangements. It is applicable to various layouts of IGBT and diode chips in machine-side and grid-side bridge arms, exhibiting good versatility and scalability.

[0103] See Figure 6 In the diagram, P loss_T and P loss_D Power losses of the IGBT and diode are respectively; R thc_1 To R thc_n These are the corresponding IGBT equivalent layer thermal resistances; R thc(1,2) To R thc(1,n-1) These represent the equivalent layer thermal resistances of adjacent diodes corresponding to the IGBT; T a The ambient temperature.

[0104] See Figure 7 This is a simplified schematic diagram of the internal chip structure of an IGBT module.

[0105] See Figure 8 and Figure 9 An equivalent thermal coupling circuit and thermal network model corresponding to the IGBT module is constructed. Both figures show the thermal coupling of four chips T1, T4, D1, and D4 in a single bridge arm of the generator-side converter. The thermal coupling of other bridge arms and even the grid-side converter is similar. Figure 8 and Figure 9 The multi-chip junction temperature calculation model for IGBT modules is as follows:

[0106]

[0107] T c =P total R th_conv +T a ;

[0108]

[0109] P total =6(P loss_T +P loss_D ).

[0110] S5. Based on the junction temperature timing response of each chip obtained in S4, the temperature amplitude and average temperature of the thermal cycle are extracted using the rainflow counting method; combined with the segmented fatigue cumulative life model obtained by fitting the accelerated aging test data of the IGBT module, the service life of each chip is evaluated.

[0111] Regarding the lifespan assessment model for IGBT modules, the lifespan of IGBT modules is generally estimated through accelerated aging tests. These tests use weighted conditions of specific factors to accelerate the normal aging process before evaluating the IGBT module's lifespan. This invention is based on a segmented fatigue cumulative model, which divides the physical process of IGBT module failure into linear and nonlinear stages. The fatigue damage of the IGBT module mainly targets the equivalent thermal resistance of the solder layer. The thermal resistance changes mentioned below in both stages refer to the changes in the thermal resistance of the solder layer.

[0112] The process of evaluating the lifespan of each chip using a segmented fatigue cumulative life model includes:

[0113] In the first stage, when the normalized thermal resistance increment is less than 0.5%, the normalized thermal resistance value is calculated using a linear stage model.

[0114] In the second stage, when the normalized thermal resistance increment is greater than or equal to 0.5%, the normalized thermal resistance value is iteratively updated using a nonlinear iterative growth model.

[0115] When the normalized thermal resistance reaches 1.5, the chip is considered to have failed, and its failure time is used as the life assessment result.

[0116] In practical implementation, the linear phase model in the first stage is as follows:

[0117]

[0118] In the formula, R th The normalized thermal resistance is initially set to 1; N(i) represents the number of thermal cycles of type i, obtained through rainflow counting; N c (i) represents the number of cycles that increase the thermal resistance by 0.5% for the i-th type of thermal cycle; a1, a2, and a3 are parameters of the linear stage obtained through accelerated aging tests; ΔT j (i) represents the temperature amplitude of the i-th type of thermal cycle, i.e., the difference between the maximum and minimum chip junction temperatures in this thermal cycle: T jm (i) represents the average temperature of the i-th type of thermal cycle.

[0119] In the second stage, the nonlinear iterative growth model is as follows:

[0120] R th (t+1)=R th (t)+N(i)·R(t);

[0121]

[0122] In the formula, t is time; R th (t) represents the normalized thermal resistance value at time t; b1, b2, b3, b4, b5, and b6 are parameters of the nonlinear stage obtained through accelerated aging tests; R(t) is the thermal resistance growth rate at time t, i.e., the relative increase in thermal resistance per unit time; ΔT j (t) represents the current thermal cycle temperature amplitude at time t; R th (i) represents the normalized thermal resistance value corresponding to the i-th type of thermal cycle, indicating the thermal resistance growth state of the device under this type of cycle.

[0123] Traditional fatigue life models often employ single empirical formulas (such as the Coffin-Manson model) for thermal cycling accumulation, which struggles to accurately characterize the aging characteristics of devices in the initial low-stress stage. This approach, by introducing a linear stage model, can more precisely reflect the accumulation process of thermal resistance within a small increment, making it particularly suitable for describing the slow degradation caused by slight thermomechanical fatigue in the initial operating phase of a device, thus avoiding underestimation of the early aging process. Furthermore, in the later stages of device service, the aging rate accelerates significantly due to the exacerbation of nonlinear damage mechanisms such as bond layer fatigue and solder creep. Existing models often assume a linear or power-law relationship in the aging process, making it difficult to capture this accelerating trend. This approach, however, introduces a nonlinear iterative growth model in the second stage, correlating the thermal resistance growth rate R(t) with the current thermal cycling temperature amplitude and historical thermal resistance state, achieving dynamic feedback on aging dynamics and more realistically reflecting the nonlinear evolution characteristics of actual failure mechanisms.

[0124] By setting a 0.5% thermal resistance increment threshold to delineate the linear and nonlinear stages, the model retains stability in the early aging stages while also possessing the ability to respond to rapid degradation in later stages. This segmented structure not only improves the model's adaptability but also ensures a smooth transition in aging assessment from low-stress to high-stress conditions, avoiding the problem of insufficient applicability of a single model throughout the entire life cycle. Furthermore, the normalized thermal resistance value, as an aging index, has clear physical meaning and measurability, facilitating comparison and verification with actual test data. Simultaneously, all model parameters are derived from accelerated aging tests, ensuring the experimental basis and engineering credibility of the model. Compared to traditional methods relying on purely statistical fitting or black-box models, this approach provides a more physically supported life evolution path, contributing to improved interpretability and application value of the assessment results.

[0125] S6. Based on the lifetime assessment results of each chip obtained in S5, a two-parameter Weibull distribution function S(t) characterizing the reliability of each chip is obtained by fitting using statistical methods; and based on S(t) of each chip, the time-varying reliability of the IGBT module and the wind power converter as a whole is calculated according to the reliability calculation principle of the series system.

[0126] Compared to traditional methods that only consider longitudinal heat conduction within the chip using one-dimensional Foster or Cauer thermal network models, this approach establishes a multi-chip thermal coupling model in S4 that incorporates lateral heat diffusion effects, and constructs an equivalent thermal network accordingly. This model fully considers the spatial geometric layout of multiple chips within the IGBT module and the thermal conductivity of the packaging materials, accurately reflecting the mutual thermal influence between chips. Therefore, it avoids the junction temperature underestimation problem caused by neglecting lateral heat transfer in traditional methods, significantly improving the calculation accuracy of the junction temperature time-series response, especially under high power density or dynamic load conditions. Furthermore, this approach starts with stochastic wind speed modeling (S1) and progressively derives power sequences (S2) and chip-level loss sequences (S3), achieving a refined mapping from external meteorological conditions to internal device power losses. Compared to existing technologies that often use typical operating conditions or steady-state assumptions for simplified analysis, this method fully preserves the time-varying and stochastic nature of wind power operating conditions, making the input for subsequent thermo-mechanical-lifetime analysis closer to actual operating conditions and improving the engineering applicability of the entire evaluation chain.

[0127] Due to the thermal coupling effect between chips, the junction temperature fluctuation characteristics experienced by chips at different locations vary. In S5, this solution, based on accurate junction temperature response and combining rainflow counting with a segmented fatigue life model, can independently assess the lifespan loss of each chip. Compared to the traditional method of treating the IGBT module as a single heat source and uniformly calculating its lifespan, this approach more realistically reflects the inconsistency in aging among the chips within the module, providing a more granular basis for module-level reliability assessment. Furthermore, in S6, by fitting the lifespan assessment results of each chip to a two-parameter Weibull distribution function and calculating the overall time-varying reliability based on series system reliability theory, a seamless connection is achieved from microscopic failure mechanisms to macroscopic system performance. Compared to existing methods that only provide mean time between failures (MTBF) or qualitatively assess reliability, this solution outputs a reliability curve that evolves over time, supporting risk warning and operation and maintenance decisions for wind power converters throughout their entire lifecycle.

[0128] This method can achieve more accurate and realistic time-varying reliability prediction for wind power converters.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A reliability assessment method for wind power converters considering chip thermal coupling effects, characterized in that, Includes the following steps: S1. Based on the two-parameter Weibull distribution model, the wind speed during the wind farm's operating cycle is stochastically modeled to generate a statistically representative time-series wind speed sequence. S2. Establish an output power model based on the power output characteristics of the wind turbine; use the time-series wind speed sequence obtained in S1 as the input of the output power model, and solve to obtain the time-series operating power sequence of the wind power converter; S3. Based on the physical characteristics of the IGBT module, establish the power loss model of each chip inside the IGBT module; use the timing power sequence obtained in S2 and the preset converter control parameters as inputs to the power loss model, and solve to obtain the timing power loss sequence of each chip. S4. Based on the geometric layout of each chip and the thermal properties of the packaging material, a multi-chip thermal coupling model including the lateral thermal diffusion effect is established; and based on the multi-chip thermal coupling model, an equivalent thermal network model considering the mutual thermal influence between chips is constructed; the timing power loss sequence of each chip obtained in S3 and the preset ambient temperature are used as inputs to solve for the junction temperature timing response and junction temperature fluctuation characteristics of each chip. S5. Based on the junction temperature timing response of each chip obtained in S4, the temperature amplitude and average temperature of the thermal cycle are extracted using the rainflow counting method; combined with the segmented fatigue cumulative life model obtained by fitting the accelerated aging test data of the IGBT module, the service life of each chip is evaluated. S6. Based on the lifetime assessment results of each chip obtained in S5, a two-parameter Weibull distribution function S(t) characterizing the reliability of each chip is obtained by fitting using statistical methods; and based on S(t) of each chip, the time-varying reliability of the IGBT module and the wind power converter as a whole is calculated according to the reliability calculation principle of the series system.

2. The reliability assessment method for wind power converters considering chip thermal coupling effects as described in claim 1, characterized in that: In S5, the process of evaluating the lifespan of each chip using the segmented fatigue cumulative life model includes: In the first stage, when the normalized thermal resistance increment is less than 0.5%, the normalized thermal resistance value is calculated using a linear stage model. In the second stage, when the normalized thermal resistance increment is greater than or equal to 0.5%, a nonlinear iterative growth model is used to iteratively update the normalized thermal resistance value. When the normalized thermal resistance reaches 1.5, the chip is considered to have failed, and its failure time is used as the life assessment result.

3. The wind power converter reliability assessment method considering chip thermal coupling effect as described in claim 2, characterized in that: In the first stage, the linear stage model is as follows: In the formula, R th The normalized thermal resistance is initially set to 1; N(i) represents the number of thermal cycles of type i, obtained through rainflow counting; N c (i) represents the number of cycles that increase the thermal resistance by 0.5% for the i-th type of thermal cycle; a1, a2, and a3 are parameters of the linear stage obtained through accelerated aging tests; ΔT j (i) represents the temperature amplitude of the i-th type of thermal cycle, i.e., the difference between the maximum and minimum values ​​of the chip junction temperature in this thermal cycle: T jm (i) represents the average temperature of the i-th type of thermal cycle.

4. The wind power converter reliability assessment method considering chip thermal coupling effect as described in claim 3, characterized in that: In the second stage, the nonlinear iterative growth model is as follows: R th (t+1)=R th (t)+N(i)·R(t); In the formula, t is time; R th (t) represents the normalized thermal resistance value at time t; b1, b2, b3, b4, b5, and b6 are parameters of the nonlinear stage obtained through accelerated aging tests; R(t) is the thermal resistance growth rate at time t, i.e., the relative increase in thermal resistance per unit time; ΔT j (t) represents the current thermal cycle temperature amplitude at time t; R th (i) represents the normalized thermal resistance value corresponding to the i-th type of thermal cycle, indicating the thermal resistance growth state of the device under this type of cycle.

5. The wind power converter reliability assessment method considering chip thermal coupling effect as described in claim 1, characterized in that: In S1, the shape parameter k and scale parameter c of the two-parameter Weibull distribution model are obtained by fitting the historical wind speed data of the target wind farm.

6. The reliability assessment method for wind power converters considering chip thermal coupling effects as described in claim 1, characterized in that: In S2, the output power model is established in which the output power of the wind turbine is calculated in segments according to the wind speed range, and it is assumed that the operating power of the wind power converter is the same as the output power of the wind turbine; wherein, the wind speed range includes four ranges: below the cut-in wind speed, below the rated wind speed, below the cut-out wind speed, and above the cut-out wind speed.

7. The wind power converter reliability assessment method considering chip thermal coupling effect as described in claim 6, characterized in that: In S2, the wind turbine output power P out The formula for calculation is: In the formula, V wind V represents the operating wind speed. ci V co V r These are the cut-in wind speed, cut-out wind speed, and rated wind speed, respectively; A, B, and C are constants. The calculations for A, B, and C are as follows:

8. The reliability assessment method for wind power converters considering chip thermal coupling effects as described in claim 1, characterized in that: In S3, the power loss of the IGBT module includes the conduction loss and switching loss of the IGBT chip and the anti-parallel diode chip. In S4, the equivalent thermal network model adopts a Cauer-type RC network structure. The longitudinal thermal resistance of a single chip is calculated based on the thermal conductivity and thickness of each layer of material and the effective thermal conduction area determined by the thermal diffusion angle. The inter-chip coupling thermal resistance is calculated by analyzing the overlapping area of ​​the thermal diffusion paths of adjacent chips in each layer of material and integrating the transverse thermal resistance. The multi-chip thermal coupling model covers IGBT and diode chips in each arm of the wind power converter on both the machine side and the grid side. The equivalent thermal network model includes multiple mutually coupled heat sources and heat paths.

9. The reliability assessment method for wind power converters considering chip thermal coupling effects as described in claim 1, characterized in that: In S4, during the establishment of the multi-chip thermal coupling model, the thermal resistance and convective heat transfer resistance of the single-layer structure are calculated based on the following formula, taking into account lateral thermal diffusion: In the formula, R thj R th_conv A j These represent the thermal resistance of the j-th layer, the convective heat transfer thermal resistance, and the equivalent heat conduction area, respectively; N is the maximum number of layers. k j ρ j t j θ j , respectively, represent the thermal conductivity, density, thickness, and thermal diffusion angle of the j-th structural material; h is the convective heat transfer coefficient; l j-1 w j-1 The initial equivalent heat conduction surface A of the j-th layer is respectively j-1 Length and width; l j w j Equivalent heat conduction surface A j The length and width of the chip; l0 and w0 are the length and width of the initial heat source chip, respectively; z is the vertical coordinate in the direction of heat conduction, representing the distance the heat is conducted upwards along the thickness direction from the top surface of the chip; L c W c These represent the length and width of the initial heat source chip, respectively.

10. The wind power converter reliability assessment method considering chip thermal coupling effect as described in claim 9, characterized in that: In S4, during the process of establishing the multi-chip thermal coupling model, the coupling thermal resistance between each chip is also calculated based on the same calculation method; among them, in the j-th layer, the calculation formula for the coupling thermal resistance of chip 2 to chip 1 is: In the formula, R thj_2 Let A be the thermal resistance of chip 2 in layer j; j2 (z) represents the effective thermal conductivity area of ​​chip 2 at coordinate z in the j-th layer; z cj A represents the z-axis coordinate where the thermal paths of the two chips intersect; 12 (z) Effective thermal conductivity area of ​​chip 2 at z coordinate of layer 1.

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