Threshold voltage diagram generation method, memory and electronic equipment

Abstract

The invention discloses a threshold voltage map generation method, a memory and electronic equipment. The threshold voltage diagram generation method is applied to the Nand flash memory and comprises the steps that feature data of a plurality of storage units in the Nand flash memory are obtained, and the feature data comprise operation parameters and threshold voltages; according to the threshold voltage in the feature data of the plurality of storage units, constructing an initial threshold voltage VT diagram; and according to operation parameters in the feature data of the plurality of storage units, utilizing a trained aging prediction model to predict the variation of distribution parameters of the VT diagram, and based on the variation, adjusting the VT diagram. By adopting the scheme provided by the invention, the matched VT diagram is dynamically generated by means of the intelligent model, and the dynamic evaluation requirement of the threshold voltage required by the Nand flash memory due to use aging and use environment change is fully met.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of storage technology, and in particular to a method for generating threshold voltage maps, memory, and electronic devices. Background Technology

[0002] Each cell in a NAND flash memory is essentially a floating-gate transistor. By injecting or removing electrons into or from the floating gate, the threshold voltage of a single transistor can be permanently changed; this is the physical basis of NAND flash memory's data storage. Correspondingly, data "0" and "1" are defined by detecting this altered threshold voltage. Data reading involves determining the storage state of the cell using one or more reference voltages. The threshold voltage (VT) graph serves as a "health electrocardiogram" and "navigation map" throughout the entire lifecycle of NAND flash memory, from design and manufacturing to testing, use, and end-of-life. Constructing an accurate VT graph is crucial for the read / write performance, reliability, and lifespan of NAND flash memory. Summary of the Invention

[0003] This application provides a threshold voltage diagram (VT) generation method, a memory, and an electronic device. By using an intelligent model, a matching VT diagram is dynamically generated according to the usage status of the NAND flash memory, fully meeting the dynamic threshold voltage evaluation requirements of NAND flash memory due to aging and changes in the usage environment. This facilitates dynamic adjustment of the reference voltage based on the VT diagram, ensuring the read / write performance and reliability of the NAND flash memory.

[0004] This disclosure provides a threshold voltage map generation method applied to Nand flash memory, including: Acquire feature data of multiple storage cells in the Nand flash memory, the feature data including: operating parameters and threshold voltage; An initial threshold voltage VT map is constructed based on the threshold voltage in the feature data of the plurality of storage cells; Based on the operation parameters in the feature data of the multiple storage units, the aging prediction model that has been trained is used to predict the change in the distribution parameters of the VT graph, and the VT graph is adjusted based on the change. The distribution parameters of the VT diagram include: a threshold voltage range for at least one storage state and a boundary threshold between storage states.

[0005] This disclosure also provides a memory, including: a memory controller and a Nand flash memory comprising a plurality of memory cells; The storage controller is configured to perform the method described in any embodiment of this disclosure to generate a threshold voltage map of the Nand flash memory.

[0006] This disclosure also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the threshold voltage map generation method as described in any embodiment of this disclosure.

[0007] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0009] Figure 1 A flowchart of a VT diagram generation method provided in this embodiment of the disclosure; Figure 2 A flowchart of another VT diagram generation method provided in this disclosure embodiment; Figure 3 A flowchart of another VT diagram generation method provided in this disclosure embodiment; Figure 4 A flowchart of another VT diagram generation method provided in this embodiment of the disclosure. Detailed Implementation

[0010] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0011] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0012] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0013] In the field of NAND flash memory technology, the threshold voltage (VT) map serves as a crucial basis for describing the distribution of threshold voltages in memory cells, and its accuracy directly impacts the read / write performance and reliability of the flash memory. An initial VT map is generated by a preset voltage scan before the NAND flash memory leaves the factory and remains fixed during use. However, NAND flash memory exhibits significant aging effects (such as increased erase / write cycle counts and extended data retention time) and environmental sensitivity (such as temperature), causing the VT distribution to drift during use. A static VT map cannot track these dynamic changes, easily leading to problems such as increased read / write error rates and storage capacity degradation.

[0014] The threshold voltage (VT) diagram determined at the factory can deviate from the factory-set threshold voltage due to various factors such as the frequency of use, usage method, aging, and operating environment of the NAND flash memory. This deviation can cause errors when reading data based on the initially set reference voltage. Therefore, continuously monitoring the threshold voltage changes of the storage cells and adjusting the reference voltage in a timely manner during the use of NAND flash memory is of great importance to ensuring read / write performance and device reliability.

[0015] This disclosure provides a threshold voltage map generation method, applied to NAND flash memory, such as... Figure 1 As shown, it includes: Step 110: Obtain feature data of multiple storage cells in the Nand flash memory, the feature data including: operating parameters and threshold voltage; Step 120: Construct an initial threshold voltage VT map based on the threshold voltage in the feature data of the plurality of storage cells; Step 130: Based on the operation parameters in the feature data of the multiple storage units, use the trained aging prediction model to predict the change in the distribution parameters of the VT graph, and adjust the VT graph based on the change. The distribution parameters of the VT diagram include: a threshold voltage range for at least one storage state and a boundary threshold between storage states.

[0016] The operating parameters include at least one of the following: number of erase / write cycles, data retention time, and operating temperature. Data retention time represents the elapsed time since the last data write to the storage cell. As can be seen, the operating parameters reflect the operational usage of the Nand flash memory and are factors that directly or indirectly affect the actual threshold voltage of the storage cell. Optionally, other operating parameters may also be included, not limited to those described in this disclosure.

[0017] It should be noted that the initial VT diagram constructed in step 120 of this embodiment does not refer to the VT diagram corresponding to the Nand flash memory in its pre-shipment state, but rather to the VT diagram before adjustments compared to other steps in this application. This initial VT diagram is constructed based on the current device state of the Nand flash memory. In step 130, a trained aging prediction model is used to predict trends based on changes in collected feature data, obtaining the (predicted) changes in relevant distribution parameters, and then adjusting the VT diagram. Related control adjustments are made based on the adjusted VT diagram, such as adjusting the reference voltage. Compared to a VT diagram that only reflects the current device state, a VT diagram that incorporates predictions of changing trends and corresponding adjustments better matches the changing trends of the Nand flash memory device state. The corresponding control adjustments will also better meet the needs of device state changes, enabling the Nand flash memory to stably maintain good read / write performance and reliability.

[0018] In some exemplary embodiments, the threshold voltage in the characteristic data of each memory cell is determined according to the following method: The threshold voltage is obtained by acquiring the threshold voltage sample data of the storage unit through a voltage scanning circuit.

[0019] In some exemplary embodiments, a portion of all memory cells in the Nand flash memory is randomly selected according to a set ratio for the aforementioned voltage scan to determine the corresponding threshold voltage. Optionally, the aforementioned voltage scan is performed on all memory cells in all physical pages and blocks to determine the corresponding threshold voltage.

[0020] In some exemplary embodiments, the threshold voltages of multiple memory cells obtained by scanning are filtered to remove noise interference, retain valid samples, and construct an initial VT map.

[0021] In some exemplary embodiments, step 120 includes: fitting the VT distribution curve of each memory state using a Gaussian mixture model (GMM) based on the threshold voltage in the feature data of the plurality of memory cells; Extract the characteristic parameters of each VT distribution curve to construct the initial VT map; The characteristic parameters of the VT distribution curve include at least one of the following: mean, standard deviation, and peak value.

[0022] Depending on the mode of the storage cells in Nand flash memory, the storage states included in a single storage cell also vary. For example, SLC (Single-Level Cell) mode includes storage states 0 and 1; MLC (Multi-Level Cell) mode includes storage states 00, 01, 10, and 11; TLC (Triple-Level Cell) mode includes 8 storage states; and QLC (Quadruple-Level Cell) mode includes 16 storage states.

[0023] The VT distribution curve for each storage state is obtained by fitting the GMM model, and the corresponding feature parameters are extracted: mean, standard deviation and peak value. Then, an initial VT map is constructed, which includes the threshold voltage range and boundary threshold of each storage state.

[0024] In some exemplary embodiments, the aging prediction model is pre-trained according to the following method: A training sample set is constructed based on the feature data of multiple storage cells collected multiple times from the Nand flash memory and / or other Nand flash memory of the same type. The aging prediction model is obtained by training a long short-term memory network model based on the training sample set.

[0025] As we know, Long Short-Term Memory (LSTM) networks are primarily used to process time-series data, capturing long-term dependencies. After training, they are used to predict changes in the distribution parameters of the VT graph. Alternatively, other models can be used, trained with pre-built training sample sets, to obtain aging prediction models. Examples include: Recurrent Neural Network (RNN) models, Gated Recurrent Unit (GRU) models, Bidirectional RNN models; and Convolutional Neural Network (CNN) models, such as Temporal Convolutional Network (TCN) models; and Transformer models based on attention mechanisms. The base model can be selected as needed, and a corresponding training sample set can be built for training.

[0026] Training samples in the training sample set can be generated based on historical feature data collected from this Nand flash memory, or from historical feature data collected from other devices of the same type / model, or from historical feature data collected from this device and other devices of the same type / model. Model training and updates can be performed in the memory (controller) containing the Nand flash memory, by an external host, or by a cloud server. After training or model updates are completed, the data is downloaded to the local memory. The approach is not limited to any specific aspect; the choice can be made flexibly based on the memory configuration and application scenario.

[0027] In some exemplary embodiments, such as Figure 2 As shown, the method further includes: Step 210: Obtain read / write error monitoring data of the Nand flash memory; Step 220: If the read / write error monitoring data meets the fine calibration triggering conditions, iteratively execute the following steps until the set calibration stop conditions are met: Step 221: For the memory cell where the error occurred, obtain incremental feature data; Step 222: Based on the incremental feature data, the distribution parameters of the VT graph are optimized using an incremental learning algorithm to update the VT graph.

[0028] According to this scheme, the read / write status of the Nand flash memory is monitored in real time. When a large number of read / write errors occur, it indicates that the read / write control determined based on the current VT (Vibration Detection) is inaccurate, requiring timely adjustments to reduce errors and ensure read / write accuracy. The incremental learning process is iteratively executed to update the VT graph until the set calibration stop condition is met. The system focuses on memory cells experiencing errors, collecting the latest corresponding feature data as the basis for incremental learning, optimizing the distribution parameters of the VT graph, and obtaining an updated VT graph. It can be seen that adjusting the read / write control based on the latest VT graph can gradually reduce the occurrence of errors until the set stop condition is reached.

[0029] The memory, including Nand flash memory, also includes an error recording module for recording errors occurring during Nand flash memory read / write operations and generating read / write error detection data. The incremental learning algorithm can include various methods, and the appropriate algorithm can be selected based on the fitting model.

[0030] In some exemplary embodiments, the incremental learning algorithm includes: an online gradient descent algorithm; correspondingly, based on the incremental feature data, the incremental learning algorithm is used to optimize the distribution parameters to update the VT graph, including: Based on the incremental feature parameters, the fitting parameters of the Gaussian mixture model are updated using an online gradient descent algorithm to update the VT distribution curves of each storage state; Based on the updated VT distribution curves of each storage state, the boundary thresholds between each storage state are optimized to update the VT graph.

[0031] In some exemplary embodiments, the read / write error monitoring data includes: bit error rate (BER); including: page BER, block BER, plane BER, or die BER.

[0032] If the bit error rate is greater than or equal to a set first error rate threshold, the fine calibration trigger condition is determined to be reached; if the bit error rate is less than or equal to a set second error rate threshold, the calibration stop condition is determined to be reached; wherein, the first error rate threshold is greater than the second error rate threshold.

[0033] Therefore, during Nand flash memory read / write operations, errors are monitored and the error rate (BER) is recorded. If the BER is greater than or equal to a first error rate threshold, a fine calibration step is initiated: based on the memory cell at the error location, supplementary feature data is collected, the VT (Vibration Transformation) graph is updated using an incremental learning algorithm, and the distribution parameters of the VT graph—the boundary thresholds between memory states—are optimized until the BER drops to less than or equal to a second error rate threshold. Once the BER falls below the second error rate threshold, it indicates that the current Nand flash memory's BER meets the usage requirements, and the fine calibration process stops.

[0034] In some exemplary embodiments, such as Figure 3 As shown, the method further includes: Step 140: Obtain the operating environment parameters of the Nand flash memory; Step 150: Based on the working environment parameters, find the preset mapping relationship between the environment parameter and the VT distribution parameter correction value, and determine the correction value corresponding to the distribution parameter; Step 160: Modify the distribution parameters of the VT plot according to the correction value.

[0035] In some exemplary embodiments, the working environment parameters include at least one of the following: temperature and humidity. Optionally, other parameters may also be included.

[0036] The modification of the VT diagram's distribution parameters involves adjusting the correction values ​​based on the current distribution parameters. A pre-defined mapping relationship between environmental parameters and VT distribution parameter correction values ​​is used to find the corresponding VT diagram distribution parameter correction values ​​based on the current operating environment parameters. The distribution parameters include one or more items, and the corresponding correction values ​​also include one or more items. For example, if the operating parameters include a threshold voltage range for at least one storage state, then the distribution parameter correction value corresponds to the correction value for that threshold voltage range. The original threshold voltage range (value) for the at least one storage state is modified based on this correction value to obtain the corrected threshold voltage range (value) for the at least one storage state, thus completing the modification of the VT diagram.

[0037] The preset mapping relationship between environmental parameters and VT distribution parameter correction values ​​is obtained by fitting historical data or set based on experience, reflecting the influence of working environment conditions on the VT distribution parameters. This mapping relationship can be a mapping table or a mapping model (function), also known as an environmental parameter compensation model, and is not limited to a specific method.

[0038] It should be noted that the correction of the VT diagram distribution parameters in steps 140-160 and the modification of the VT diagram in step 130 are not limited to a specific execution order. Modifications can be performed before or after step 130. In some exemplary embodiments, steps 140-160 and step 130 can be optimized for different distribution parameters. In the absence of conflict, the same distribution parameters can also be modified twice. The choice can be flexible and based on the needs. Therefore, by using an aging prediction model for trend prediction and using operating environment parameters for dynamic correction to compensate for environmental interference, the accuracy of the VT diagram is effectively improved, laying an accurate data foundation for subsequent adjustment and control of the memory based on the VT diagram.

[0039] This disclosure also provides a VT graph generation method, applied to SLC Nand flash memory, such as... Figure 4 As shown, it includes: Step 410, Data Acquisition and Preprocessing: An integrated temperature sensor (accuracy ±0.5℃) is used to monitor the temperature of the Nand flash memory chip in real time, with a sampling frequency of 1Hz; the number of erase / write cycles for each chip is recorded by the flash memory controller, with a resolution of 1 cycle; a voltage scan is performed on each flash memory chip: the gate voltage is applied in 10mV steps within the range of 0-5V, the on-current of the memory cell is recorded, and the VT value is determined; a median filtering algorithm is used to remove impulse noise, and VT samples within the 95% confidence interval are retained.

[0040] Step 420: Generate the initial VT plot: Select 1000 VT samples for both state 0 and state 1; use a Gaussian mixture model (GMM) for distribution fitting, where the VT distribution for state 0 is set to N(1.2V, 0.1V). 2 ), 1 state is set to N (2.5V, 0.15V) 2 In the initial VT diagram, the threshold boundary between the 0 state and the 1 state is set as the intersection of the two distributions (1.8V).

[0041] Step 430, Aging Model Prediction Adjustment of VT Map: Using the trained aging prediction model, the mean change in cycles 101-200, and the mean change in subsequent cycles, can be predicted. For example, when the erase / write cycle reaches 1000, the model predicts that the mean change in state 0 will drift to 1.3V, and the mean change in state 1 will drift to 2.7V, adjusting the threshold boundary to 2.0V. This aging prediction model is pre-trained based on feature data collected during the first 100 erase / write cycles. Optionally, it can also be trained based on feature data collected during more historical erase / write cycles, or the model can be updated with feature data collected during more erase / write cycles, without being limited to any specific aspect.

[0042] Step 440, Real-time Feedback Calibration: During read / write operations, if the Page BER of a physical page exceeds 1e-4, fine calibration is triggered; the memory cell corresponding to the erroneous bit is located, and 50 additional VT samples are collected; the GMM parameters are updated using an online gradient descent algorithm, the threshold boundary is finely adjusted to 1.95V, and continuous monitoring continues until the BER drops below 5e-5.

[0043] Step 450, adaptive adjustment of working environment: According to the established environmental temperature compensation model: for every 5°C increase in temperature, the mean value of VT in state 0 decreases by 0.05V and the mean value of VT in state 1 decreases by 0.08V; when the temperature is detected to rise from 25°C to 45°C, the threshold boundary is automatically lowered by 0.13V, and the distribution parameters of the VT graph are further adjusted.

[0044] In particular, step 440, real-time feedback accuracy, means that after the VT diagram is determined, during the normal operation of the Nand flash memory, the read and write status is continuously monitored, read and write error monitoring data is obtained, and when the fine calibration trigger conditions are met, the corresponding fine calibration steps are started and executed until the calibration stop conditions are met.

[0045] This disclosure also provides a Nand flash memory control method, including: generating a VT diagram according to the VT diagram generation method described in any embodiment of this disclosure; Adjust the read data reference voltage of the Nand flash memory according to the VT diagram.

[0046] In some exemplary embodiments, other Nand flash memory control parameters can also be adjusted based on the VT diagram, not limited to the read data reference voltage described above. Further examples are not discussed in detail here.

[0047] This disclosure also provides a memory, including: a memory controller and a Nand flash memory comprising a plurality of memory cells; The storage controller is configured to perform the method described in any embodiment of this disclosure to generate a threshold voltage map of the Nand flash memory.

[0048] In some exemplary embodiments, the storage controller is further configured to adjust the read data reference voltage corresponding to each storage state based on the latest threshold voltage map.

[0049] The Nand flash memory includes: 2D Nand flash memory, 3D Nand flash memory, or other architectures of Nand flash memory. It is not limited to specific capacities and types.

[0050] This disclosure also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the threshold voltage map generation method as described in any embodiment of this disclosure.

[0051] The VT graph generation scheme provided in this disclosure achieves dynamic updates of the VT graph through real-time data acquisition and machine learning prediction, effectively tracking VT drift caused by flash memory aging and environmental changes, and significantly improving the dynamic adaptability of Nand flash memory. In some exemplary embodiments, model fitting and incremental learning optimization are used to improve the accuracy of VT distribution characterization, which is particularly suitable for multi-mode storage scenarios such as MLC / TLC / QLC. In some exemplary embodiments, a feedback calibration mechanism is used to control the BER at a low level, reducing the read / write error rate and improving device reliability; adaptive adjustment based on the feature data of individual flash memory reduces wear caused by excessive erasure and writing, and extends the service life.

[0052] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0053] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for generating a threshold voltage map, characterized in that, Applications in Nand flash memory include: Acquire feature data of multiple storage cells in the Nand flash memory, the feature data including: operating parameters and threshold voltage; An initial threshold voltage VT map is constructed based on the threshold voltage in the feature data of the plurality of storage cells; Based on the operation parameters in the feature data of the multiple storage units, the aging prediction model that has been trained is used to predict the change in the distribution parameters of the VT graph, and the VT graph is adjusted based on the change. The distribution parameters of the VT diagram include: a threshold voltage range for at least one storage state and a boundary threshold between storage states.

2. The method according to claim 1, characterized in that, The step of constructing an initial threshold voltage VT map based on the threshold voltages in the feature data of the plurality of storage cells includes: Based on the threshold voltage in the characteristic data of the multiple memory cells, a Gaussian mixture model is used to fit the VT distribution curve of each memory state; Extract the characteristic parameters of each VT distribution curve to construct the initial VT map; The characteristic parameters of the VT distribution curve include at least one of the following: mean, standard deviation, and peak value.

3. The method according to claim 1, characterized in that, The method further includes: acquiring read / write error monitoring data of the Nand flash memory; If the read / write error monitoring data is determined to meet the fine calibration triggering conditions, the following steps are iteratively executed until the set calibration stop condition is met: For the memory cell where the error occurred, obtain incremental feature data; Based on the incremental feature data, an incremental learning algorithm is used to optimize the distribution parameters of the VT graph in order to update the VT graph.

4. The method according to claim 3, characterized in that, The incremental learning algorithm includes: an online gradient descent algorithm; The step of optimizing the distribution parameters using an incremental learning algorithm based on the incremental feature data to update the VT graph includes: Based on the incremental feature parameters, the fitting parameters of the Gaussian mixture model are updated using an online gradient descent algorithm to update the VT distribution curves of each storage state; Based on the updated VT distribution curves of each storage state, the boundary thresholds between each storage state are optimized to update the VT graph.

5. The method according to claim 3, characterized in that, The read / write error monitoring data includes: bit error rate; If the bit error rate is greater than or equal to a set first error rate threshold, it is determined that the fine calibration trigger condition is met; If the bit error rate is less than or equal to a set second error rate threshold, it is determined that the calibration stop condition is met; Wherein, the first error rate threshold is greater than the second error rate threshold.

6. The method according to any one of claims 1-5, characterized in that, The operating parameters include at least one of the following: number of erase / write cycles, data retention time, and operating temperature; The aging prediction model was pre-trained using the following method: A training sample set is constructed based on the feature data of multiple storage cells collected multiple times from the Nand flash memory and / or other Nand flash memory of the same type. The aging prediction model is obtained by training a long short-term memory network model based on the training sample set.

7. The method according to any one of claims 1-5, characterized in that, The method further includes: Obtain the operating environment parameters of the Nand flash memory; Based on the working environment parameters, find the preset mapping relationship between the environment parameter and the VT distribution parameter correction value, and determine the correction value corresponding to the distribution parameter; The distribution parameters of the VT plot are modified based on the correction value.

8. A memory, characterized in that, include: Storage controller and Nand flash memory comprising multiple storage cells; The storage controller is configured to perform the method described in any one of claims 1-7 to generate a threshold voltage map of the Nand flash memory.

9. The memory according to claim 8, characterized in that, The storage controller is also configured to adjust the read data reference voltage corresponding to each storage state according to the latest threshold voltage map.

10. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the threshold voltage map generation method as described in any one of claims 1-7.

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