Quantum voltage driving device and method

Abstract

The application provides a quantum voltage driving device and method. A control module of the quantum voltage driving device is configured to obtain a driving parameter, output a first control signal and a second control signal according to the driving parameter, and output a waveform signal; a clock module is configured to output a reference clock signal; a frequency adjustment module is configured to obtain the first control signal, adjust the frequency of the reference clock signal to a preset frequency range based on the first control signal, and output an adjusted frequency signal; a digital-to-analog conversion module is configured to obtain the adjusted frequency signal and the waveform signal, adjust the waveform signal to a current pulse signal based on the adjusted frequency signal, and make the amplitude of the current pulse signal fall within a preset amplitude range; and obtain the second control signal and selectively output a current pulse signal with a target amplitude based on the second control signal, and make the target amplitude fall within the preset amplitude range; and limit the waveform signal to a target frequency through the adjusted frequency signal to meet the requirements of a Josephson arbitrary waveform synthesizer.

Description

Technical Field

[0001] This application belongs to the field of power metering technology, and in particular relates to a quantum voltage driving device and method. Background Technology

[0002] The Josephson Arbitrary Waveform Synthesizer (JAWS) is a broadband AC quantum voltage synthesizer based on the Josephson effect. Its core working principle is to drive the Josephson array chip with a high-speed pulse sequence to achieve precise quantum voltage output.

[0003] Among related technologies, JAWS has high requirements for drive current, mainly due to the high frequency requirements of the drive current. Current quantum voltage drive devices are difficult to output drive current that meets the frequency requirements. Summary of the Invention

[0004] The purpose of this application is to provide a quantum voltage driving device and method, which aims to solve the problem that quantum voltage driving devices in traditional technologies are difficult to output driving current that meets frequency requirements.

[0005] A first aspect of this application provides a quantum voltage driving device, the quantum voltage driving device comprising:

[0006] The control module is used to acquire drive parameters, output a first control signal and a second control signal according to the drive parameters, and output waveform signals.

[0007] The clock module is used to output a reference clock signal;

[0008] A frequency adjustment module is used to acquire the first control signal and adjust the frequency of the reference clock signal to a preset frequency band based on the first control signal, so as to output a frequency-modulated signal;

[0009] A digital-to-analog converter module is used to acquire the frequency modulation signal and the waveform signal, and adjust the waveform signal into a current pulse signal based on the frequency modulation signal, wherein the amplitude of the current pulse signal falls within a preset amplitude range; and to acquire the second control signal, and selectively output a current pulse signal with a target amplitude based on the second control signal, wherein the target amplitude falls within the preset amplitude range.

[0010] In some embodiments of this application, the frequency adjustment module includes a first frequency modulation unit and a second frequency modulation unit. The first frequency modulation unit is used to acquire the reference clock signal and to output a multiplied clock signal after multiplying the reference clock signal. The second frequency modulation unit is used to acquire the first control signal and to modulate the multiplied clock signal to a preset frequency band based on the first control signal, so as to output the frequency modulation signal.

[0011] In some embodiments of this application, the digital-to-analog conversion module includes:

[0012] The third frequency modulation unit is used to acquire the frequency modulation signal and perform frequency multiplication on the frequency modulation signal to obtain a refresh clock signal.

[0013] The digital-to-analog converter is used to acquire the refresh clock signal, the waveform signal, and the second control signal to output a current pulse signal with a target amplitude.

[0014] In some embodiments of this application, the frequency of the refresh clock signal and the frequency of the reference clock signal satisfy the following conditions:

[0015] ;in, The frequency of the refresh clock signal, N1 is the frequency of the reference clock signal, N2 is the frequency multiplier of the first frequency modulation unit, N2 is the frequency multiplier of the third frequency modulation unit, and K is the frequency modulation ratio value of the second frequency modulation unit that adjusts the frequency multiplier clock signal based on the first control signal.

[0016] In some embodiments of this application, the quantum voltage driving device is used to output to a Josephson arbitrary waveform synthesizer, and the frequency of the refresh clock signal is the same as the characteristic frequency of the Josephson junction.

[0017] In some embodiments of this application, the second control signal is related to the critical current of the Josephson junction.

[0018] In some embodiments of this application, the actual current of the current pulse signal satisfies the following condition: ;in, The actual current of the current pulse signal. is the maximum full-scale current of the current pulse signal, D is the control value of the digital-to-analog converter module, and D is -32768 to +32767.

[0019] In some embodiments of this application, the control value of the digital-to-analog converter is set to automatically pad the lower 4 bits with 0, and the control value of the digital-to-analog converter is 16-bit two's complement from -32768 to +32752.

[0020] In some embodiments of this application, the quantum voltage driving device satisfies at least one of the following:

[0021] The driving parameters include the critical current of the Josephson junction and the characteristic frequency of the Josephson junction;

[0022] The clock module includes a miniature atomic clock;

[0023] The second frequency modulation unit includes a direct digital frequency synthesizer.

[0024] In some embodiments of this application, the control module is connected to a storage unit, the storage unit is used to store waveform data, and the control module is used to output the waveform signal based on the waveform data.

[0025] In some embodiments of this application, the control module includes multiple memories for storing different waveform data.

[0026] In some embodiments of this application, the digital-to-analog converter module is used to output at least two current pulse signals, and the waveforms of the at least two current pulse signals are different.

[0027] A second aspect of this application also provides a quantum voltage driving method, which is applied to the quantum voltage driving device described above; the quantum voltage driving method includes:

[0028] Obtain the driving parameters, and obtain the first control signal and the second control signal based on the driving parameters;

[0029] A reference clock signal is acquired, and the reference clock signal is tuned to a preset frequency band based on the first control signal to output a frequency-modulated signal;

[0030] The frequency modulation signal and the waveform signal are acquired, and the waveform signal is adjusted into a current pulse signal based on the frequency modulation signal, wherein the amplitude of the current pulse signal falls within a preset amplitude range;

[0031] Based on the second control signal, a current pulse signal with a target amplitude is selectively output, wherein the target amplitude falls within the preset amplitude range.

[0032] The beneficial effects of this application are as follows: This application provides a quantum voltage driving device and method. The quantum voltage driving device includes a control module, a clock module, a frequency adjustment module, and a digital-to-analog converter module. The control module is used to acquire driving parameters and output a first control signal and a second control signal according to the driving parameters, and to output a waveform signal. The clock module is used to output a reference clock signal. The frequency adjustment module is used to acquire the first control signal and, based on the first control signal, modulate the reference clock signal to a preset frequency band to output a frequency-modulated signal. The digital-to-analog converter module is used to acquire the frequency-modulated signal and the waveform signal, and, based on the frequency-modulated signal, adjust the waveform signal into a current pulse signal, the amplitude of which falls within a preset amplitude range. It is also used to acquire a second control signal and, based on the second control signal, selectively output a current pulse signal with a target amplitude, the target amplitude falling within a preset amplitude range. In this application, the frequency-modulated signal is output through the clock module and the frequency adjustment module, and the waveform signal is limited to a target frequency by the frequency-modulated signal to meet the requirements of the Josephson arbitrary waveform synthesizer. Attached Figure Description

[0033] Figure 1 A schematic diagram of the frame structure of a quantum voltage driving device provided in an embodiment of this application;

[0034] Figure 2 A schematic diagram of the frame structure of a quantum voltage driving device provided in another embodiment of this application;

[0035] Figure 3 A schematic diagram of the frame structure of a quantum voltage driving device provided in yet another embodiment of this application;

[0036] Figure 4 A schematic diagram of the circuit structure of a quantum voltage driving device provided in an embodiment of this application;

[0037] Figure 5 A schematic diagram of a current pulse drive waveform with logic 1 provided in an embodiment of this application;

[0038] Figure 6 A schematic diagram of a current pulse drive waveform with logic value of -1 provided in an embodiment of this application;

[0039] Figure 7 A schematic diagram of a current pulse drive waveform with logic 0 provided in an embodiment of this application;

[0040] Figure 8 This is a schematic diagram of the steps of a quantum voltage driving method provided in an embodiment of this application.

[0041] Specific element symbol explanations: 100-Control module, 200-Clock module, 300-Frequency adjustment module, 310-First frequency modulation unit, 320-Second frequency modulation unit, 400-Digital-to-analog conversion module, 410-Third frequency modulation unit, 420-Digital-to-analog conversion unit. Detailed Implementation

[0042] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0043] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0045] It's important to know that the Josephson Arbitrary Waveform Synthesizer (JAWS) is a broadband AC quantum voltage synthesizer based on the Josephson effect. Its core working principle is to drive a Josephson array chip with a high-speed pulse sequence to achieve precise quantum voltage output. Compared to the traditional Programmable Josephson Voltage Standard (PJVS), JAWS has significant technological advantages: it eliminates the need for step-switching operations, produces a cleaner output signal spectrum, and has a wider operating bandwidth, making it irreplaceable in high-precision quantum measurement and quantum metrology.

[0046] JAWS's core operating mechanism relies on the precise driving of Josephson junction array chips, a process that must be achieved through high-speed programmable current pulses. Due to the extremely high characteristic frequency of Josephson junctions (typically reaching 14.4 GHz), stringent requirements are placed on the performance of the driving current pulses: Firstly, the current pulses must have picosecond (ps) level time accuracy, ensuring that the duration of the pulse exceeding the critical current (Ic) or -Ic does not exceed the period of the Josephson junction's characteristic frequency, and the driving current amplitude at logic 0 must be strictly limited between (-Ic, +Ic). Secondly, the current pulse amplitude must have a wide range of adjustment capabilities to adapt to the critical current requirements of different types of Josephson junctions (such as SNS structures) (typically in the range of 0.3 mA to 10 mA). Simultaneously, the pulse signal must support continuous output and high-speed refresh to meet the driving requirements of different repetition frequencies, and strict synchronous control must be achieved in multi-channel driving scenarios. Furthermore, the frequency of the driving current pulses must be precisely adjustable, and their accuracy must match the high-precision requirements of quantum measurements to ensure the stability and reliability of the JAWS output quantum voltage.

[0047] Based on this, this application improves upon traditional quantum voltage driving devices and methods.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of the framework structure of the quantum voltage driving device provided in this embodiment. The quantum voltage driving device of this application embodiment includes a control module 100, a clock module 200, a frequency adjustment module 300, and a digital-to-analog converter module 400. The control module 100 is used to acquire driving parameters and output a first control signal and a second control signal according to the driving parameters, and is also used to output a waveform signal. The clock module 200 is used to output a reference clock signal. The frequency adjustment module 300 is used to acquire the first control signal and adjust the reference clock signal to a preset frequency band based on the first control signal to output a frequency-modulated signal. The digital-to-analog converter module 400 is used to acquire the frequency-modulated signal and the waveform signal, and adjust the waveform signal into a current pulse signal based on the frequency-modulated signal, wherein the amplitude of the current pulse signal falls within a preset amplitude range. It is also used to acquire the second control signal and selectively output a current pulse signal with a target amplitude based on the second control signal, wherein the target amplitude falls within a preset amplitude range.

[0049] It should be explained that the quantum voltage driving device is an electronic device that provides adapted driving signals for quantum voltage synthesis equipment. It precisely controls the signal frequency and amplitude to meet the specific operating requirements of quantum devices. The frequency adjustment module 300 is a functional module that receives control signals and adjusts the frequency of the input clock signal. It can calibrate the reference clock signal to a preset frequency band, achieving precise frequency control. The digital-to-analog converter module 400 is an electronic module that converts digital waveform signals into analog current signals, possessing signal format conversion and amplitude adjustment capabilities. Driving parameters are key information characterizing the driving signal requirements, including core indicators such as frequency and amplitude. The first control signal is the instruction signal output from the control module 100 to the frequency adjustment module 300, used to specify the target parameters for frequency adjustment and guide the precise execution of the frequency modulation process. The second control signal is the instruction signal output from the control module 100 to the digital-to-analog converter module 400, used to select a current pulse signal with a target amplitude, achieving precise amplitude control of the driving signal.

[0050] The waveform signal is a digital signal generated by the control module 100, containing preset waveform characteristics, and serves as the basis for subsequent conversion into drive current pulses. The reference clock signal is a stable frequency signal output by the clock module 200, possessing fixed period and frequency characteristics, and serves as the original reference signal for frequency adjustment. The frequency modulation signal is a clock signal output by the frequency adjustment module 300 after processing, with a frequency falling within a preset frequency band. The current pulse signal is an analog drive signal output by the digital-to-analog converter module 400, transmitting energy in pulse form, possessing specific amplitude and frequency, and directly driving the quantum device. The preset amplitude range is a current amplitude interval set according to the operating requirements of the quantum device, ensuring that the output drive signal can adapt to the device's operating threshold and avoiding device malfunctions caused by excessively strong or weak signals. The target amplitude is a specific current amplitude value selected from the preset amplitude range. The Josephson arbitrary waveform synthesizer is a device that achieves wideband AC quantum voltage synthesis based on the Josephson effect, possessing advantages such as spectral purity and stepless switching, and requires dedicated high-precision drive signal support.

[0051] It is understood that the clock module 200 in this embodiment provides a stable reference clock, and the frequency adjustment module 300 adjusts it to a preset frequency band based on a first control signal to ensure that the drive signal frequency meets the timing requirements of the Josephson arbitrary waveform synthesizer and guarantees the stability of the synthesizer's operation. The digital-to-analog conversion module 400 converts the waveform signal into a current pulse based on the frequency-modulated signal and selects a target amplitude through a second control signal to ensure that the signal amplitude falls within a preset range and is suitable for the synthesizer's drive threshold. Furthermore, the control module 100 can flexibly adjust the drive parameters, changing the frequency-modulated signal frequency and the target amplitude of the current pulse. This allows for adaptation to Josephson arbitrary waveform synthesizers of different specifications without reconstructing the device structure, improving the device's versatility. Under the coordination of the control module 100, each module works collaboratively, forming a complete closed loop from parameter reception and frequency adjustment to signal conversion, reducing signal distortion and deviation, and providing stable and reliable drive support for the synthesizer.

[0052] In some embodiments of this application, please refer to Figure 2 , Figure 2 A schematic diagram of the framework structure of the quantum voltage driving device provided in this embodiment is shown. The frequency adjustment module 300 of this embodiment includes a first frequency modulation unit 310 and a second frequency modulation unit 320. The first frequency modulation unit 310 is used to acquire a reference clock signal and to output a frequency-multiplied clock signal after frequency multiplication of the reference clock signal. The second frequency modulation unit 320 is used to acquire a first control signal and to modulate the frequency-multiplied clock signal to a preset frequency band based on the first control signal, so as to output a frequency-modulated signal.

[0053] It should be explained that the first frequency modulation unit 310 is a functional unit in the electronic system that amplifies the frequency of the input clock signal. It increases the frequency of the clock signal through specific circuit logic, providing a suitable base frequency for subsequent precise frequency modulation. The second frequency modulation unit 320 is a functional module that receives control signals and performs precise frequency calibration on the multiplied clock signal. It can adjust the signal frequency to a preset frequency band according to instructions. The multiplied clock signal is a high-frequency clock signal obtained after being multiplied by the first frequency modulation unit 310. Its frequency is higher than the reference clock signal, thus widening the frequency coverage range of subsequent frequency modulation.

[0054] It is understood that in this embodiment, the frequency multiplication of the first frequency modulation unit 310 increases the fundamental frequency of the clock signal. Combined with the precise calibration of the second frequency modulation unit 320, this allows the frequency-modulated signal to cover a wider frequency range, fully meeting the synthesizer's requirements for clocks in different frequency bands. Furthermore, frequency control is completed in two steps: first, the frequency multiplication reduces the adjustment range of subsequent frequency modulation; then, the second frequency modulation unit 320 performs fine calibration based on the control signal, reducing frequency deviation and ensuring the accuracy of the frequency-modulated signal. Simultaneously, the frequency multiplication can boost the reference clock signal to a high-frequency level, and after precise frequency modulation, output a high-frequency signal that meets the requirements, satisfying the Josephson arbitrary waveform synthesizer's need for a high-speed clock.

[0055] In some embodiments of this application, please refer to Figure 3 , Figure 3 A schematic diagram of the frame structure of the quantum voltage driving device provided in this embodiment is shown. The digital-to-analog conversion module 400 of this embodiment includes a third frequency modulation unit 410 and a digital-to-analog conversion unit 420. The third frequency modulation unit 410 is used to acquire the frequency modulation signal and perform frequency multiplication processing on the frequency modulation signal to obtain a refresh clock signal. The digital-to-analog conversion unit 420 is used to acquire the refresh clock signal, the waveform signal and the second control signal to output a current pulse signal of the target amplitude.

[0056] It should be explained that the third frequency modulation unit 410 is a functional unit in the electronic circuit that performs secondary frequency amplification on the input clock signal. It increases the signal frequency by a certain magnitude through an internal frequency multiplication mechanism, providing high-speed timing support for subsequent signal conversion. The digital-to-analog converter unit 420 is the core functional component that converts digital waveform signals into analog current signals. It has the ability to receive timing signals, control signals, and waveform data, and can output analog signals of specific amplitudes according to instructions. The refresh clock signal is a high-speed clock signal obtained after frequency multiplication by the third frequency modulation unit 410. It has fixed high-frequency characteristics and provides a timing reference for the rapid conversion and output of waveform signals.

[0057] It can be explained that in this embodiment, the third frequency modulation unit 410 increases the clock signal frequency through frequency multiplication, providing a high-frequency refresh timing for the digital-to-analog converter 420, ensuring rapid and continuous output of the current pulse signal, and meeting the synthesizer's driving requirements for ultra-short period pulses. Under the synchronization of the refresh clock signal, the digital-to-analog converter 420 works in conjunction with the waveform signal and the second control signal to accurately output current pulses of the target amplitude according to instructions, adapting to the synthesizer's critical current adaptation requirements.

[0058] In some embodiments of this application, please refer to Figure 4 , Figure 4 A schematic diagram of the circuit structure of the quantum voltage driving device provided in this embodiment is shown; as follows: Figure 4As shown, clock module 200 is a 10MHz miniature atomic clock, outputting a 10MHz reference clock signal; the first frequency modulation unit 310 is a clock multiplier, with a multiplier N1 of 30; the second frequency modulation unit 320 is a DDS (Direct Digital Synthesizer) frequency modulator; in this embodiment, the frequency of the refresh clock signal and the frequency of the reference clock signal satisfy the following conditions: ;in, To refresh the frequency of the clock signal, N1 is the frequency of the reference clock signal, N2 is the frequency multiplier of the first frequency modulation unit 310, K is the frequency multiplier of the third frequency modulation unit 410, and K is the frequency modulation ratio value of the second frequency modulation unit 320 based on the first control signal to adjust the frequency multiplier clock signal.

[0059] Understandably, this embodiment, through the coordinated calculation of the reference clock signal, two-stage frequency multipliers, and frequency modulation ratio, can accurately set the refresh clock signal frequency, avoid frequency deviation, ensure precise matching with the synthesizer's characteristic frequency, and improve the timing accuracy of the drive signal. The reference clock signal is amplified by two stages of frequency multiplication (N1 and N2), and with the fine adjustment of the K value, the refresh clock signal can cover a wide frequency band from low to high frequencies, fully meeting the diverse high-speed timing requirements of synthesizers of different specifications.

[0060] In some embodiments of this application, the quantum voltage driving device is used to output to a Josephson arbitrary waveform synthesizer, and the frequency of the refresh clock signal is the same as the characteristic frequency of the Josephson junction.

[0061] In some embodiments of this application, the second control signal is related to the critical current of the Josephson junction.

[0062] Specifically, the full-scale resolution of K is approximately 48 bits. The quantum voltage drive device is set during operation. The frequency is the characteristic frequency fc of the JAWS junction. Since the resolution of the K value is approximately 48 bits, and the typical characteristic frequency of a JAWS junction is around 14.4 GHz, close to full-scale resolution, the error in setting K is approximately 1 / 248 = 3.5527 × 10⁻⁶. -15 Therefore, it can be ignored. Furthermore, this application does not require specific current rise and fall within 1 / fc, but it requires high accuracy in the repetition of 1 / fc. Therefore, this embodiment generates the current amplitude after setting the full-scale IF value. Then, the accuracy of time control is achieved through the internal frequency multiplier circuit of a 10MHz miniature atomic clock (corresponding to clock module 200) + clock multiplier (corresponding to the first frequency modulation unit 310) + DDS frequency modulation (corresponding to the second frequency modulation unit 320) + DAC (digital-to-analog converter module 400) (corresponding to the third frequency modulation unit 410).

[0063] In some embodiments of this application, the actual current of the current pulse signal satisfies the following condition: ;in, The actual current of the current pulse signal. D is the maximum full-scale current of the current pulse signal, and D is the control value of the digital-to-analog converter module 400, ranging from -32768 to +32767.

[0064] It is understood that the control value D in this embodiment covers both positive and negative ranges. Combined with the maximum full-scale current IF as a reference, it allows for precise calculation and output of actual currents of different magnitudes and directions via formulas, reducing current output deviation and ensuring the accuracy of the drive signal. By adjusting the control value D and the maximum full-scale current IF, the actual current Io can be flexibly adapted to the critical current requirements of Josephson junctions of different specifications. This allows for diverse drive scenarios to be met without hardware refactoring, improving the device's versatility.

[0065] In some embodiments of this application, the control value of the digital-to-analog converter module 400 is set to automatically pad the lower 4 bits with 0, and the control value of the digital-to-analog converter module 400 is 16-bit two's complement from -32768 to +32752.

[0066] In some embodiments of this application, the driving parameters include the critical current of the Josephson junction and the characteristic frequency of the Josephson junction.

[0067] Specifically, IF can be 1.2mA~40mA, and Io is -IF to 0.9999694×IF. Since the digital-to-analog converter module 400 has a high resolution, to improve the data refresh rate of the serial interface clock of the data converter, the transmission ratio of this invention is set to 12 bits. The lower 4 bits of the setting value D of the digital-to-analog converter module 400 are automatically padded with 0. Therefore, after fixing the lower 4 bits of the setting value D of the digital-to-analog converter module 400 to 0, the actual value range of D is 16-bit two's complement -32768 to +32752; the output range of Io is the output current pulse amplitude -IF to 0.999512×IF. Since D has a 12-bit resolution, the required drive current can be accurately output. This application has relatively low requirements for the absolute accuracy of Io; the key is to output an effective current pulse within each 1 / fc time interval. The integral of the voltage output and time of a current pulse driving a Josephson junction is exactly one magnetic flux quantum. Since the DDS has a frequency resolution of 48 bits... Therefore, a highly stable atomic clock can output a current pulse precisely at a time interval of 1 / fc, and the accuracy of its time reference can be traced back to the 10MHz miniature atomic clock U5.

[0068] In some embodiments, the clock module 200 includes a miniature atomic clock.

[0069] In some embodiments, the second frequency modulation unit 320 includes a direct digital frequency synthesizer.

[0070] In some embodiments of this application, the control module 100 is connected to a storage unit, which is used to store waveform data, and the control module 100 is used to output waveform signals based on the waveform data.

[0071] In some embodiments of this application, the control module includes multiple memories for storing different waveform data.

[0072] In some embodiments of this application, the digital-to-analog converter module 400 is used to output at least two current pulse signals, and the waveforms of the at least two current pulse signals are different.

[0073] Specifically, such as Figure 4 middle, 1+ and 1- represents a current pulse signal. 2+ and 2- represents another current pulse signal.

[0074] Please see Figures 5 to 7 , Figures 5 to 7 This embodiment illustrates pulse drive waveforms for different JAWS logics. When the logic is 1: the time the drive current pulse exceeds Ic is ≤ the period of the characteristic frequency of the Josephson junction, such as... Figure 5 As shown. When the logic is -1: the time the drive current pulse exceeds -Ic is ≤ the period of the characteristic frequency of the Josephson junction, as shown. Figure 6 As shown. When the logic value is 0: the magnitude of the drive current must be between (-Ic, +Ic).

[0075] Because the characteristic frequency of the Josephson junction is very high, typically 14.4 GHz, the DAC's drive frequency must be ≥14.4 GHz. This application uses a reference clock + clock multiplier + DDS frequency modulation + high-performance RF DAC internal multiplier to achieve a maximum clock frequency of 17 GHz. This requires an extremely short pulse current output capability of 1 / 17 GHz. Furthermore, it requires the ability to continuously output pulse currents with different repetition frequencies, meaning it needs the ability to quickly refresh waveform data. This application achieves high-speed waveform data refresh through a large-scale FPGA + four DDR4 interleaved memory modules + a 16-channel JESD204C interface.

[0076] In some embodiments of this application, the 10MHz atomic clock signal (corresponding to the reference clock signal) output by U5 (corresponding to clock module 200) is first multiplied by 30 times to 300MHz by U6 (corresponding to the first frequency modulation unit 310). Then, a 48-bit DDS (corresponding to the second frequency modulation unit 320) can precisely modulate the 300MHz clock to any frequency between 10MHz and 300MHz. Finally, a high-performance RF DAC (corresponding to digital-to-analog converter module 400) multiplies the frequency by 90 times to a DA conversion clock DACLK (corresponding to the refresh clock signal) between 0.9GHz and 22.5GHz. Driven by DACLK, the high-performance RF DAC outputs a 16-bit adjustable current (corresponding to the current pulse signal). IF can be set by software to 1.2mA to 40mA, which can meet the drive current requirements of most JAWS (Jack-on-Width) converters. The critical current of JAWS is generally between 0.3mA and 10mA. For example, the critical current of a 150mV SNS Josephson junction is approximately 0.3mA. The critical current of a 1V SNS Josephson junction is approximately 7.5mA. By selecting an appropriate full-scale current IF, the range and accuracy of the output current can be improved. The peak value of the absolute value of the output current (positive and negative pulses) is set to 1.5 times the critical current Ic of the Josephson junction.

[0077] In some embodiments, the control module 100 is U2, i.e. Figure 4 The control and data processing FPGA in the system includes at least four DDR4 interfaces (for connecting memory), sixteen JESD204C interfaces (for outputting waveform signals), two SPI interfaces (for outputting the first and second control signals respectively), and a network port (for connecting to the host computer PC1).

[0078] In some embodiments, the number of memories is four. As shown in Table 1, the data of the four waveform files are interleaved and stored in the four memories. Waveform files 1 and 2 are used to store the waveform data of current output channel 1, and waveform files 3 and 4 are used to store the waveform data of current output channel 2. Data is stored in 64-bit increments, or 8 bytes per second, interleaved. The purpose is to allow 64 bits of DDR4 data to be read at once. Each cycle is stored sequentially. N in Table 1 is one-eighth of the number of sampling points.

[0079] Table 1

[0080]

[0081] Since the DAC supports speeds up to 17GHz, it requires a bandwidth of 17GHz. 12 = 204 Gbit / s. This invention can output two DAC channels simultaneously, so the maximum bandwidth is 204 Gbit / s. 2 = 408 Gbit / s. The high-performance RF DAC U1 supports up to 16 channels of the JESD204C transmission interface; the maximum transmission rate is 32 Gbit / s, with an overhead of approximately 3% when using 64B / 66B encoding, resulting in an effective data rate of approximately 31 Gbit / s. Therefore, the total transmission rate for 16 channels is 31 Gbit / s. 16 = 496 Gbit / s. This meets the 408 Gbit / s dual-channel output speed requirement at a maximum frequency of 17 GHz. However, to further increase the bandwidth, four DDR4 memory chips are needed. One DDR4 chip has a 64-bit bus width and a data rate of 2.4 Gbit / s, resulting in a bandwidth of 2.4 GHz / s × 64 = 153.6 Gbit / s. This is insufficient to meet the 408 Gbit / s bandwidth requirement, therefore four DDR4 memory chips are needed for simultaneous reading, achieving a speed of 153.6 Gbit / s. 4 = 614.4 Gbit / s, which meets the requirement of 408 Gbit / s.

[0082] Furthermore, for better implementation of the quantum voltage driving device in any of the above embodiments, please refer to [link to relevant documentation]. Figure 8 , Figure 8 A schematic diagram illustrating the steps of the quantum voltage driving method provided in this embodiment is shown. This application also provides a quantum voltage driving method applied to the quantum voltage driving device described above; the quantum voltage driving method includes:

[0083] S100: Obtain the drive parameters, and obtain the first control signal and the second control signal based on the drive parameters;

[0084] S200: Acquire a reference clock signal and, based on the first control signal, modulate the reference clock signal to a preset frequency band to output a frequency-modulated signal;

[0085] S300: Acquires frequency modulation signal and waveform signal, and adjusts the waveform signal into current pulse signal based on the frequency modulation signal, with the amplitude of the current pulse signal falling within a preset amplitude range;

[0086] S400: Based on the second control signal, a current pulse signal with a target amplitude is selectively output, and the target amplitude falls within the preset amplitude range.

[0087] Specifically, computer PC1 imports four waveform files into memory 1 to 4 via the network port and the control and data processing FPGA U2, and inputs the critical current Ic and characteristic frequency fc of the Josephson junction via the keyboard.

[0088] The control and data processing FPGA U2, based on the Josephson junction characteristic frequency fc sent by the computer PC1, sets the K value of the DDS frequency modulation U3 via the SPI1 interface to satisfy fc. DACLK =fc. The control and data processing FPGAU2, based on the Josephson junction's critical current Ic sent by computer PC1, sets it to a reasonable full-scale value IF via the SPI2 interface. The full-scale value of IF is ≥ 1.5 times the current Ic. The control and data processing FPGAU2 also sets the drive currents Io1 and Io2 to be output through two channels via SPI2.

[0089] The control and data processing FPGAU2 configures JESD204C channels 1-8 of the high-performance RF DAC as the data transmission channels for DAC1's current channel Io1 via SPI2. It also configures JESD204C channels 9-16 as the data transmission channels for DAC2's current channel Io2. The control and data processing FPGAU2 controls DDR4 interface 1 and DDR4 interface 2 to interleave the sampled data from the two channels through channels 1-8 to output to DAC Io1, and through channels 9-16 to output to DAC Io2, as shown in Table 1.

[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0091] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0092] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0093] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0094] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A quantum voltage driving device, characterized in that, The quantum voltage driving device includes: The control module is used to acquire drive parameters, output a first control signal and a second control signal according to the drive parameters, and output waveform signals. The clock module is used to output a reference clock signal; A frequency adjustment module is used to acquire the first control signal and adjust the frequency of the reference clock signal to a preset frequency band based on the first control signal, so as to output a frequency-modulated signal; A digital-to-analog converter module is used to acquire the frequency modulation signal and the waveform signal, and adjust the waveform signal into a current pulse signal based on the frequency modulation signal, wherein the amplitude of the current pulse signal falls within a preset amplitude range; and to acquire the second control signal, and selectively output a current pulse signal with a target amplitude based on the second control signal, wherein the target amplitude falls within the preset amplitude range; The frequency adjustment module includes a first frequency modulation unit and a second frequency modulation unit. The first frequency modulation unit is used to acquire the reference clock signal and to multiply the reference clock signal by frequency to output a multiplied clock signal. The second frequency modulation unit is used to acquire the first control signal and to modulate the multiplied clock signal to a preset frequency band based on the first control signal to output the frequency modulation signal. The digital-to-analog conversion module includes: The third frequency modulation unit is used to acquire the frequency modulation signal and perform frequency multiplication on the frequency modulation signal to obtain a refresh clock signal. The digital-to-analog converter is used to acquire the refresh clock signal, the waveform signal, and the second control signal to output a current pulse signal with a target amplitude.

2. The quantum voltage driving device according to claim 1, characterized in that, The frequency of the refresh clock signal and the frequency of the reference clock signal satisfy the following condition: ;in, The frequency of the refresh clock signal, N1 is the frequency of the reference clock signal, N2 is the frequency multiplier of the first frequency modulation unit, K is the frequency multiplier of the third frequency modulation unit, and K is the frequency modulation ratio value of the second frequency modulation unit that adjusts the frequency multiplier clock signal based on the first control signal.

3. The quantum voltage driving device according to claim 2, characterized in that, The quantum voltage driving device is used to output to the Josephson arbitrary waveform synthesizer, and the frequency of the refresh clock signal is the same as the characteristic frequency of the Josephson junction. And / or, the second control signal is related to the critical current of the Josephson junction.

4. The quantum voltage driving device according to claim 3, characterized in that, The actual current of the current pulse signal satisfies the following condition: ;in, The actual current of the current pulse signal. is the maximum full-scale current of the current pulse signal, D is the control value of the digital-to-analog converter module, and D is -32768 to +32767.

5. The quantum voltage driving device according to claim 4, characterized in that, The control value of the digital-to-analog converter module is set to automatically pad the lower 4 bits with 0, and the control value of the digital-to-analog converter module is 16-bit two's complement from -32768 to +32752.

6. The quantum voltage driving device according to claim 3, characterized in that, The quantum voltage driving device satisfies at least one of the following: The driving parameters include the critical current of the Josephson junction and the characteristic frequency of the Josephson junction; The clock module includes a miniature atomic clock; The second frequency modulation unit includes a direct digital frequency synthesizer.

7. The quantum voltage driving device according to claim 1, characterized in that, The control module is connected to a storage unit, which is used to store waveform data, and the control module is used to output the waveform signal based on the waveform data.

8. The quantum voltage driving device according to claim 7, characterized in that, The control module includes multiple memories, which are used to store different waveform data.

9. The quantum voltage driving device according to claim 7, characterized in that, The digital-to-analog converter module is used to output at least two current pulse signals, and the waveforms of the at least two current pulse signals are different.

10. A quantum voltage driving method, characterized in that, The quantum voltage driving method is applied to the quantum voltage driving device as described in any one of claims 1 to 9; The quantum voltage driving method includes: Obtain the driving parameters, and obtain the first control signal and the second control signal based on the driving parameters; A reference clock signal is acquired, and the reference clock signal is tuned to a preset frequency band based on the first control signal to output a frequency-modulated signal; The frequency modulation signal and the waveform signal are acquired, and the waveform signal is adjusted into a current pulse signal based on the frequency modulation signal, wherein the amplitude of the current pulse signal falls within a preset amplitude range; Based on the second control signal, a current pulse signal with a target amplitude is selectively output, wherein the target amplitude falls within the preset amplitude range.

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