Analog-to-digital conversion circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides an analog-to-digital conversion circuit, a chip and electronic equipment, the analog-to-digital conversion circuit comprises a logic control module, a multiplexer, a first voltage generation module, a buffer and an analog-to-digital converter, the analog-to-digital converter generates quantization results of a first type of test signals and a second type of test signals, whether the function of the analog-to-digital converter is abnormal is determined according to the quantification result, so that the analog-to-digital conversion circuit can perform self-inspection on whether the function of the analog-to-digital converter is abnormal, and the working reliability of the analog-to-digital conversion circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to an analog-to-digital converter circuit. Background Technology

[0002] In addition to the core analog-to-digital converter, some analog-to-digital conversion circuits also include other functional modules, such as multiplexers and buffers.

[0003] However, at least one of the multiplexers, buffers, and analog-to-digital converters in the analog-to-digital conversion circuit may be at risk of malfunction. Therefore, it is especially important for the analog-to-digital conversion circuit to have the ability to self-test for whether each function is malfunctioning. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide an analog-to-digital conversion circuit, a chip, and an electronic device to alleviate at least one of the above technical problems.

[0005] In a first aspect, embodiments of this application provide an analog-to-digital conversion circuit, which includes a logic control module, a multiplexer, a first voltage generation module, a buffer, and an analog-to-digital converter. The logic control module is used to generate a first type of control signal, a second type of control signal, and a fourth type of control signal. The multiplexer is used to control the switching state of the corresponding channel according to the first type of control signal. The first voltage generation module is used to generate a first type of test signal according to the second type of control signal. The buffer is used to directly output the first type of test signal and the second type of test signal according to the fourth type of control signal. The analog-to-digital converter is used to generate the quantization result of the first type of test signal, so as to determine whether the function of the analog-to-digital converter is abnormal based on the quantization result.

[0006] Secondly, embodiments of this application also provide a chip that includes the analog-to-digital conversion circuit described above.

[0007] Thirdly, embodiments of this application also provide an electronic device, which includes the analog-to-digital conversion circuit or chip described above.

[0008] The analog-to-digital converter circuit, chip, and electronic device provided in this application generate a first type of control signal, a second type of control signal, and a fourth type of control signal through a logic control module. A multiplexer controls the switching state of the corresponding channel according to the first type of control signal. A first voltage generation module generates a first type of test signal according to the second type of control signal. A buffer directly outputs the first type of test signal according to the fourth type of control signal. The analog-to-digital converter generates the quantization result of the first type of test signal. Based on the quantization result, it is determined whether the function of the analog-to-digital converter is abnormal. This allows the analog-to-digital converter circuit to perform self-checks on whether the function of the analog-to-digital converter is abnormal, thereby improving the working reliability of the analog-to-digital converter circuit.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A first schematic block diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown.

[0012] Figure 2 A second schematic diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown.

[0013] Figure 3 The schematic diagram of the logic control module is shown.

[0014] Figure 4 The circuit schematic of the first logic submodule is shown.

[0015] Figure 5 The schematic diagram of the first logic unit is shown.

[0016] Figure 6 The circuit schematic of the first logic subunit is shown.

[0017] Figure 7 The circuit schematic of the second logic subunit is shown.

[0018] Figure 8 The schematic diagram of the second logic unit is shown.

[0019] Figure 9 The circuit schematic of the third logic subunit is shown.

[0020] Figure 10 The circuit schematic of the fourth logic subunit is shown.

[0021] Figure 11 The circuit schematic of the fifth logic subunit is shown.

[0022] Figure 12 The circuit schematic of the sixth logic subunit is shown.

[0023] Figure 13 The circuit schematic of the seventh logic subunit is shown.

[0024] Figure 14 A block diagram of the first voltage generation module is shown.

[0025] Figure 15 The schematic diagram of the voltage generation submodule is shown.

[0026] Figure 16 The circuit diagram of the first voltage generating unit is shown.

[0027] Figure 17 The circuit schematic of the second voltage generating unit is shown.

[0028] Figure 18 The circuit schematic of the first selection transmission submodule is shown.

[0029] Figure 19 The principle block diagram of the first anti-interference submodule is shown.

[0030] Figure 20 The circuit diagram of the first anti-interference unit is shown.

[0031] Figure 21 The circuit diagram of the second anti-interference unit is shown.

[0032] Figure 22 The schematic diagram of the second logic submodule is shown.

[0033] Figure 23 The circuit schematic of the third logic unit is shown.

[0034] Figure 24 The circuit schematic of the fourth logic unit is shown.

[0035] Figure 25 The circuit diagram of the buffer is shown.

[0036] Figure 26 The circuit schematic of the third logic submodule is shown.

[0037] Figure 27 The block diagram of a multiplexer is shown.

[0038] Figure 28 The circuit schematic of the channel unit is shown.

[0039] Figure 29 The circuit schematic of the bias voltage generation unit is shown.

[0040] Figure 30 The circuit schematic of the peripheral device is shown.

[0041] Figure 31 The schematic diagram of the fourth logic submodule is shown.

[0042] Figure 32 The circuit schematic of the fifth logic unit is shown.

[0043] Figure 33 The circuit schematic of the sixth logic unit is shown.

[0044] Figure 34 The circuit schematic of the seventh logic unit is shown.

[0045] Figure 35 The circuit schematic of the eighth logic unit is shown.

[0046] Figure 36 A block diagram of the second voltage generation module is shown.

[0047] Figure 37 The circuit schematic of the second selective transmission submodule is shown.

[0048] Figure 38 The principle block diagram of the second anti-interference submodule is shown.

[0049] Figure 39 The circuit diagram of the third anti-interference unit is shown.

[0050] Figure 40 The circuit schematic of the fourth anti-interference unit is shown.

[0051] Figure 41 The timing diagram of the first logic submodule is shown.

[0052] Figure 42 The timing diagram of the second logic submodule is shown.

[0053] Figure 43 The timing diagram of the third logic submodule is shown.

[0054] Figure 44 A schematic diagram of the chip structure provided in an embodiment of this application is shown.

[0055] Figure 45 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0056] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0057] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0058] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0059] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0061] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0062] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0063] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0064] like Figure 1 As shown in the figure, this application embodiment provides an analog-to-digital converter (ADC) circuit 100, which includes a logic control module 10, a multiplexer 20, a first voltage generation module 30, a buffer 50, and an ADC 60. The logic control module 10 is used to generate a first type of control signal, a second type of control signal, and a fourth type of control signal. The multiplexer 20 is used to control the switching state of the corresponding channel according to the first type of control signal. The first voltage generation module 30 is used to generate a first type of test signal V2 according to the second type of control signal. The buffer 50 is used to directly output the first type of test signal V2 according to the fourth type of control signal. The ADC 60 is used to generate the quantization result of the first type of test signal V2, so as to determine whether the ADC 60 is malfunctioning based on the quantization result.

[0065] It is understood that the analog-to-digital converter circuit 100 provided in this embodiment generates a first type of control signal, a second type of control signal, and a fourth type of control signal through the logic control module 10. The multiplexer 20 controls the switching state of the corresponding channel according to the first type of control signal. The first voltage generation module 30 generates a first type of test signal V2 according to the second type of control signal. The buffer 50 quantizes the first type of test signal V2 according to the fourth type of control signal. The analog-to-digital converter 60 generates the quantization result of the first type of test signal V2. Based on the quantization result, it is determined whether the function of the analog-to-digital converter 60 is abnormal. This allows the analog-to-digital converter circuit 100 to perform self-checks on whether the function of the analog-to-digital converter 60 is abnormal, thereby improving the working reliability of the analog-to-digital converter circuit 100.

[0066] In some embodiments, such as Figure 2As shown, the analog-to-digital converter circuit 100 also includes a second voltage generation module 40, and the logic control module 10 is further used to generate a third type of control signal. The second voltage generation module 40 is used to generate a second type of test signal V3 based on the third type of control signal. The buffer 50 is used to directly output the second type of test signal V3 based on the fourth type of control signal. The analog-to-digital converter 60 is used to generate the quantization result of the second type of test signal V3, so as to determine whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken based on the quantization result.

[0067] It is understood that the analog-to-digital converter circuit 100 provided in this embodiment generates a third type of control signal through the logic control module 10, the second voltage generation module 40 generates a second type of test signal V3 according to the third type of control signal, the buffer 50 directly outputs the second type of test signal V3 according to the fourth type of control signal, and the analog-to-digital converter 60 generates the quantization result of the second type of test signal V3. Based on the quantization result, it is determined whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken. This allows the analog-to-digital converter circuit 100 to perform a self-test on whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken, thereby improving the working reliability of the analog-to-digital converter circuit 100.

[0068] It should be noted that, in some embodiments, the multiplexer 20 is also used to generate a third type of test signal V1 when the switch state is on. The buffer 50 is also used to control the buffering of at least one of the third type of test signal V1, the first type of test signal V2, and the second type of test signal V3 according to the fourth type of control signal, so as to generate a fourth type of test signal V4 after buffering. The analog-to-digital converter 60 is also used to generate the quantization results of the third type of test signal V1 and the fourth type of test signal V4, so as to determine whether the functions of the multiplexer 20 and the buffer 50 are abnormal based on the quantization results.

[0069] In some embodiments, the logic control module 10 controls all channels of the multiplexer 20 to be in an off state, and controls the buffer 50 to directly output the first type of test signal V2 to the analog-to-digital converter 60, so as to determine whether the analog-to-digital converter 60 is functioning normally based on the quantization result of the first type of test signal V2.

[0070] In some embodiments, the logic control module 10 controls all channels of the multiplexer 20 to be in an off state, and controls the buffer 50 to generate a fourth type of test signal V4 to be output to the analog-to-digital converter 60 based on the first type of test signal V2, so as to determine whether the function of the buffer 50 is normal based on the quantization result of the fourth type of test signal V4.

[0071] In some embodiments, the logic control module 10 selects different channels of the multiplexer 20 to generate a third type of test signal V1, and controls the first voltage generation module 30, the second voltage generation module 40 and the buffer 50 to directly output the third type of test signal V1 to the analog-to-digital converter 60, so as to determine whether the function of the multiplexer 20 is normal based on the quantization result of the third type of test signal V1.

[0072] In some embodiments, the logic control module 10 controls the buffer 50 to directly output the second type test signal V3 or the third type test signal V1 to the analog-to-digital converter 60, so as to determine whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken based on the quantization result of the second type test signal V3 or the third type test signal V1.

[0073] The analog-to-digital converter 60 may be, but is not limited to, a SAR ADC including a sample / hold circuit, a comparator, SAR logic, and a DAC circuit, or other ADCs applicable to this application. <n:1>To quantify the results.

[0074] In some embodiments, such as Figure 3 As shown, the logic control module 10 includes a first logic submodule 11, a second logic submodule 12, a third logic submodule 13, and a fourth logic submodule 14. The first logic submodule 11 generates a second type of control signal based on a first sampled signal Sample, a first enable signal CD_EN, a first selection control signal SEL<2:0>, and a second selection control signal CD_SEL<1:0>. The second logic submodule 12 generates a fourth type of control signal based on the first sampled signal Sample, the second enable signal BUF_EN, the second sampled signal BUF_SAMP, and the input signal of the buffer 50. The third logic submodule 13 generates a first type of control signal based on the first sampled signal Sample, the first selection control signal SEL<2:0>, and the input signal of the multiplexer 20. The fourth logic submodule 14 generates a third type of control signal based on the first sampled signal Sample, the first selection control signal SEL<2:0>, the third enable signal BWD_EN, and the third selection control signal BWD_SEL.

[0075] It should be noted that the first type of control signal is used to control the multiplexer 20, the second type of control signal is used to control the first voltage generation module 30, the third type of control signal is used to control the second voltage generation module 40, and the fourth type of control signal is used to control the buffer 50, so as to detect in turn whether the analog-to-digital converter 60 is malfunctioning, whether the buffer 50 is malfunctioning, whether the multiplexer 20 is malfunctioning, and whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken.

[0076] In some embodiments, such as Figure 4 As shown, the second type of control signals includes a first selection sub-signal CD_SELB, a second selection sub-signal CD_SELA, a first drive signal SW1P, a second drive signal SW2P, a third drive signal SW3N, and a fourth drive signal SW4N. The first logic submodule 11 includes a first logic unit 111 and a second logic unit 112. The first logic unit 111 is used to generate a first intermediate signal, the first selection sub-signal CD_SELB, and the second selection sub-signal CD_SELA based on the first sample signal Sample, the first enable signal CD_EN, and the first selection control signal SEL<2:0>. The second logic unit 112 is used to generate the first drive signal SW1P, the second drive signal SW2P, the third drive signal SW3N, and the fourth drive signal SW4N based on the second selection control signal CD_SEL<1:0> and the first intermediate signal.

[0077] It should be noted that, based on the first sampling signal Sample, the first enable signal CD_EN, the first selection control signal SEL<2:0>, and the second selection control signal CD_SEL<1:0>, this embodiment can generate the first selection sub-signal CD_SELB, the second selection sub-signal CD_SELA, the first drive signal SW1P, the second drive signal SW2P, the third drive signal SW3N, and the fourth drive signal SW4N to control the first voltage generation module 30 to generate the first type of test signal V2, and determine whether the analog-to-digital converter 60 is malfunctioning based on the quantization result of the first type of test signal V2.

[0078] In some embodiments, such as Figure 5 As shown, the first logic unit 111 includes a first logic subunit 1111 and a second logic subunit 1112. The first logic subunit 1111 is used to generate a first intermediate signal based on the first sampled signal Sample, the first enable signal CD_EN, and the first selection control signal SEL<2:0>. The second logic subunit 1112 is used to generate a first selection sub-signal CD_SELB and a second selection sub-signal CD_SELA based on the first intermediate signal.

[0079] It should be noted that, in this embodiment, the first selection sub-signal CD_SELB and the second selection sub-signal CD_SELA can be generated by sequentially connecting the first logic sub-unit 1111 and the second logic sub-unit 1112 to control the first voltage generation module 30.

[0080] In some embodiments, such as Figure 6 As shown, the first logic subunit 1111 includes a first NAND gate AN1, a second NAND gate AN2, a third NAND gate AN3, and a first NOT gate N1. The three inputs of the first NAND gate AN1 are respectively connected to one bit of the first selection control signal SEL<2:0>. The two inputs of the second NAND gate AN2 are respectively connected to the first sampling signal Sample and the first enable signal CD_EN. The two inputs of the third NAND gate AN3 are respectively connected to the outputs of the first NAND gate AN1 and the second NAND gate AN2. The input of the first NOT gate N1 is connected to the output of the third NAND gate AN3, and the output of the first NOT gate N1 generates a first intermediate signal.

[0081] It should be noted that the first NAND gate AN1 performs NAND operation on the three bits of the first selection control signal SEL<2:0>, the second NAND gate AN2 performs NAND operation on the first sampling signal Sample and the first enable signal CD_EN, and the third NAND gate AN3 performs NAND operation on the result of the operation of the first NAND gate AN1 and the result of the operation of the second NAND gate AN2. After being inverted by the first NOT gate N1, the first intermediate signal is generated.

[0082] In some embodiments, such as Figure 7 As shown, the second logic sub-unit 1112 includes a second NOT gate N2, a third NOT gate N3, and a fourth NOT gate N4. The input of the second NOT gate N2 is connected to the output of the first NOT gate N1; the input of the third NOT gate N3 is connected to the output of the second NOT gate N2, and the output of the third NOT gate N3 generates a first selection sub-signal CD_SELB; the input of the fourth NOT gate N4 is connected to the output of the third NOT gate N3, and the output of the fourth NOT gate N4 generates a second selection sub-signal CD_SELA.

[0083] It should be noted that after the second NOT gate N2 and the third NOT gate N3 delay the first intermediate signal, the first selection sub-signal CD_SELB is generated, and then after being inverted by the fourth NOT gate N4, the second selection sub-signal CD_SELA is generated.

[0084] In some embodiments, such as Figure 8 As shown, the second logic unit 112 includes a third logic subunit 1121, a fourth logic subunit 1122, a fifth logic subunit 1123, a sixth logic subunit 1124, and a seventh logic subunit 1125. The third logic subunit 1121 is used to generate a second intermediate signal and a third intermediate signal according to the second selection control signal CD_SEL<1:0>. The fourth logic subunit 1122 is used to generate a first drive signal SW1P according to the first intermediate signal and the second intermediate signal. The fifth logic subunit 1123 is used to generate a second drive signal SW2P according to the first intermediate signal and the third intermediate signal. The sixth logic subunit 1124 is used to generate a third drive signal SW3N according to the first intermediate signal and the second intermediate signal. The seventh logic subunit 1125 is used to generate a fourth drive signal SW4N according to the first intermediate signal, the second intermediate signal, and the third intermediate signal.

[0085] It should be noted that in this embodiment, the second intermediate signal and the third intermediate signal are generated by the third logic subunit 1121. Each of the fourth logic subunit 1122, the fifth logic subunit 1123, the sixth logic subunit 1124 and the seventh logic subunit 1125 can generate the first driving signal SW1P, the second driving signal SW2P, the third driving signal SW3N and the fourth driving signal SW4N respectively based on two of the first intermediate signal, the second intermediate signal and the third intermediate signal.

[0086] In some embodiments, such as Figure 9 As shown, the third logic subunit 1121 includes a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, and an eighth NOT gate N8. The input of the fifth NOT gate N5 is connected to the highest bit of the second selection control signal CD_SEL<1:0>, i.e., CD_SEL. <1> The input of the sixth NOT gate N6 is connected to the output of the fifth NOT gate N5, and the output of the sixth NOT gate N6 generates the second intermediate signal; the input of the seventh NOT gate N7 is connected to the least significant bit of the second selection control signal CD_SEL<1:0>, i.e., CD_SEL. <0> The input of the eighth NOT gate N8 is connected to the output of the seventh NOT gate N7, and the output of the eighth NOT gate N8 generates the third intermediate signal.

[0087] It should be noted that the fifth NOT gate N5 and the sixth NOT gate N6 delay the most significant bit of the second selection control signal CD_SEL<1:0> to generate the second intermediate signal. The seventh NOT gate N7 and the eighth NOT gate N8 delay the least significant bit of the second selection control signal CD_SEL<1:0> to generate the third intermediate signal.

[0088] In some embodiments, such as Figure 10 As shown, the fourth logic sub-unit 1122 includes a ninth NOT gate N9, a fourth NAND gate AN4, a tenth NOT gate N10, and an eleventh NOT gate N11. The input of the ninth NOT gate N9 is connected to the output of the sixth NOT gate N6. The two inputs of the fourth NAND gate AN4 are respectively connected to the first intermediate signal and the inverted second intermediate signal. The input of the tenth NOT gate N10 is connected to the output of the fourth NAND gate AN4. The input of the eleventh NOT gate N11 is connected to the output of the tenth NOT gate N10. The output of the eleventh NOT gate N11 generates the first driving signal SW1P.

[0089] It should be noted that after the fourth NAND gate AN4 performs NAND operation on the first intermediate signal and the inverted second intermediate signal, the signal is delayed by the tenth NOT gate N10 and the eleventh NOT gate N11 to generate the first driving signal SW1P. Here, SW1N is the output signal of the tenth NOT gate N10.

[0090] In some embodiments, such as Figure 11 As shown, the fifth logic subunit 1123 includes a twelfth NOT gate N12, a fifth NAND gate AN5, a thirteenth NOT gate N13, and a fourteenth NOT gate N14. The input of the twelfth NOT gate N12 is connected to a third intermediate signal; the two inputs of the fifth NAND gate AN5 are respectively connected to a first intermediate signal and an inverted third intermediate signal; the input of the thirteenth NOT gate N13 is connected to the output of the fifth NAND gate AN5; the input of the fourteenth NOT gate N14 is connected to the output of the thirteenth NOT gate N13, and the output of the fourteenth NOT gate N14 generates a second driving signal SW2P.

[0091] It should be noted that after the fifth NAND gate AN5 performs a NAND operation on the first intermediate signal and the inverted third intermediate signal, the signal is then delayed by the thirteenth NOT gate N13 and the fourteenth NOT gate N14 to generate the second driving signal SW2P. Here, SW2N is the output signal of the thirteenth NOT gate N13.

[0092] In some embodiments, such as Figure 12 As shown, the sixth logic sub-unit 1124 includes a sixth NAND gate AN6 and a fifteenth NOT gate N15. The two input terminals of the sixth NAND gate AN6 are respectively connected to the first intermediate signal and the second intermediate signal. The input terminal of the fifteenth NOT gate N15 is connected to the output terminal of the sixth NAND gate AN6, and the output terminal of the fifteenth NOT gate N15 generates a third driving signal SW3N.

[0093] It should be noted that after the sixth NAND gate AN6 performs NAND operations on the first and second intermediate signals, the signals are inverted by the fifteenth NOT gate N15 to generate the third driving signal SW3N. Here, SW3P is the signal that is inverted by the third driving signal SW3N.

[0094] In some embodiments, such as Figure 13 As shown, the seventh logic sub-unit 1125 includes a first NOR gate RN1, a sixteenth NOT gate N16, a seventh NAND gate AN7, and a seventeenth NOT gate N17. The two inputs of the first NOR gate RN1 are respectively connected to the second intermediate signal and the third intermediate signal; the input of the sixteenth NOT gate N16 is connected to the output of the first NOR gate RN1; the first input of the seventh NAND gate AN7 is connected to the output of the sixteenth NOT gate N16, and the second input of the seventh NAND gate AN7 is connected to the first intermediate signal; the input of the seventeenth NOT gate N17 is connected to the output of the seventh NAND gate AN7, and the output of the seventeenth NOT gate N17 generates a fourth driving signal SW4N.

[0095] It should be noted that after the first NOR gate RN1 performs a NOR operation on the second and third intermediate signals, it is inverted by the sixteenth NOT gate N16. The seventh NAND gate AN7 performs a NAND operation on the output signal of the sixteenth NOT gate N16 and the first intermediate signal, and then inverts it by the seventeenth NOT gate N17 to generate the fourth driving signal SW4N. Here, SW4P is the signal inverted from the fourth driving signal SW4N.

[0096] In some embodiments, such as Figure 14 As shown, the first voltage generation module 30 includes a voltage generation submodule 31, a first selection and transmission submodule 32, and a first anti-interference submodule 33. The voltage generation submodule 31 is used to generate a corresponding first input voltage VIN1 according to the first driving signal SW1P, the second driving signal SW2P, the third driving signal SW3N, and the fourth driving signal SW4N. The first selection and transmission submodule 32 is used to select and transmit the first input voltage VIN1 according to the first selection sub-signal CD_SELB and the second selection sub-signal CD_SELA to generate a first type of test signal V2. The first anti-interference submodule 33 is used to transmit a first bias voltage VB1 or a second bias voltage VB2 to the first selection and transmission submodule 32 according to the first selection sub-signal CD_SELB and the second selection sub-signal CD_SELA to improve the anti-interference capability of the first selection and transmission submodule 32.

[0097] It should be noted that the first input voltage VIN1 generated by the voltage generation submodule 31 has four different voltage values. The first selection transmission submodule 32 selectively transmits these four different voltage values ​​as the first type of test signal V2. Since the first anti-interference submodule 33 can improve the anti-interference capability of the first selection transmission submodule 32, the first type of test signal V2 can be protected from interference, thereby improving the accuracy of whether the corresponding function is abnormal.

[0098] In some embodiments, such as Figure 15 As shown, the voltage generation submodule 31 includes a first voltage generation unit 311 and a second voltage generation unit 312. The first voltage generation unit 311 is used to generate a first initial input voltage corresponding to the first power supply voltage VDD according to the first driving signal SW1P and the second driving signal SW2P. The second voltage generation unit 312 is used to generate a second initial input voltage corresponding to the second power supply voltage VSS according to the third driving signal SW3N and the fourth driving signal SW4N. The combination of the first initial input voltage and the second initial input voltage results in the first input voltage VIN1.

[0099] It should be noted that the first voltage generating unit 311 and the second voltage generating unit 312 generate the first initial input voltage and the second initial input voltage respectively based on the first power supply voltage VDD and the second power supply voltage VSS. Since the output terminal of the first voltage generating unit 311 is connected to the output terminal of the second voltage generating unit 312, the first initial input voltage and the second initial input voltage can be combined, and the combination result is the first input voltage VIN1.

[0100] In some embodiments, such as Figure 16 As shown, the first voltage generating unit 311 includes a first resistor R1, a first transistor MP1, a second resistor R2, a second transistor MP2, and a third resistor R3. The first terminal of the first resistor R1 is connected to the first power supply voltage VDD; the first terminal of the first transistor MP1 is connected to the second terminal of the first resistor R1, and the control terminal of the first transistor MP1 is connected to the first drive signal SW1P; the first terminal of the second resistor R2 is connected to the second terminal of the first transistor MP1; the first terminal of the second transistor MP2 is connected to the first terminal of the first transistor MP1 and the second terminal of the first resistor R1, and the control terminal of the second transistor MP2 is connected to the second drive signal SW2P; the first terminal of the third resistor R3 is connected to the second terminal of the second transistor MP2, and the second terminal of the third resistor R3 is connected to the second terminal of the second resistor R2 to generate the first initial input voltage.

[0101] It should be noted that in this embodiment, various voltage values ​​of the first initial input voltage can be generated by combining the switching states of the first transistor MP1 and the second transistor MP2. Each transistor can be a field-effect transistor or a bipolar junction transistor (BJT), and the control electrode can be the gate or the base.

[0102] In some embodiments, such as Figure 17 As shown, the second voltage generating unit 312 includes a fourth resistor R4, a third transistor MN1, a fifth resistor R5, a fourth transistor MN2, and a sixth resistor R6. The first terminal of the fourth resistor R4 is connected to the second power supply voltage VSS, and the resistance value of the fourth resistor R4 is equal to the resistance value of the first resistor R1. The first terminal of the third transistor MN1 is connected to the second terminal of the fourth resistor R4, and the control terminal of the third transistor MN1 is connected to the third drive signal SW3N. The first terminal of the fifth resistor R5 is connected to the second terminal of the third transistor MN1. The first terminal of the fourth transistor MN2 is connected to the first terminal of the third transistor MN1 and the sixth resistor R6. The second terminal of resistor R4 is connected to the control terminal of the fourth transistor MN2, which is connected to the fourth drive signal SW4N. The first terminal of the sixth resistor R6 is connected to the second terminal of the fourth transistor MN2, and the second terminal of the sixth resistor R6 is connected to the second terminal of the fifth resistor R5 to generate a second initial input voltage. The second terminal of the sixth resistor R6 is connected to the second terminal of the fifth resistor R5, the second terminal of the third resistor R3, and the second terminal of the second resistor R2 to generate a first input voltage VIN1. The resistance value of the sixth resistor R6 is the same as the resistance values ​​of the fifth resistor R5, the third resistor R3, and the second resistor R2.

[0103] It should be noted that in this embodiment, multiple different voltage values ​​of the second initial input voltage can be generated by combining the switching states of the third transistor MN1 and the fourth transistor MN2, and then combined with the first initial input voltage having multiple different voltage values ​​to generate the first input voltage VIN1.

[0104] The voltage value of the first input voltage VIN1 is shown in Table 1 below:

[0105] When the second selection control signal CD_SEL<1:0> is 00, the first drive signal SW1P and the second drive signal SW2P are both low, and the first transistor MP1 and the second transistor MP2 are both turned on; the third drive signal SW3N and the fourth drive signal SW4N are both low, and the third transistor MN1 and the fourth transistor MN2 are both turned off. At this time, the first input voltage VIN1 is equal to the first power supply voltage VDD.

[0106] When the second selection control signal CD_SEL<1:0> is 01, the first drive signal SW1P is low, the second drive signal SW2P is high, the first transistor MP1 is turned on, and the second transistor MP2 is turned off; the third drive signal SW3N is low, the fourth drive signal SW4N is high, the third transistor MN1 is turned off, and the fourth transistor MN2 is turned on. At this time, the first input voltage VIN1 is equal to half of the first power supply voltage VDD.

[0107] When the second selection control signal CD_SEL<1:0> is 10, the first drive signal SW1P is high, the second drive signal SW2P is low, the first transistor MP1 is off, and the second transistor MP2 is on; the third drive signal SW3N and the fourth drive signal SW4N are both high, and the third transistor MN1 and the fourth transistor MN2 are both on. At this time, the first input voltage VIN1 is equal to one-third of the first power supply voltage VDD.

[0108] When the second selection control signal CD_SEL<1:0> is 11, both the first drive signal SW1P and the second drive signal SW2P are high, and both the first transistor MP1 and the second transistor MP2 are off; both the third drive signal SW3N and the fourth drive signal SW4N are high, and both the third transistor MN1 and the fourth transistor MN2 are on. At this time, the first input voltage VIN1 is equal to the second power supply voltage VSS. The first power supply voltage VDD is higher than the second power supply voltage VSS.

[0109] In some embodiments, such as Figure 18 As shown, the first selection transmission submodule 32 includes a fifth transistor MN3, a sixth transistor MN4, a seventh transistor MP3, and an eighth transistor MP4. The first terminal of the fifth transistor MN3 is connected to the first anti-interference submodule 33, the second terminal of the fifth transistor MN3 is connected to the first input voltage VIN1, and the control terminal of the fifth transistor MN3 is connected to the second selection sub-signal CD_SELA. The second terminal of the sixth transistor MN4 is connected to the first terminal of the fifth transistor MN3, and the control terminal of the sixth transistor MN4 is connected to the second selection sub-signal CD_SELA. The first terminal of the seventh transistor MP3 is connected to the second terminal of the fifth transistor MN3, the second terminal of the seventh transistor MP3 is connected to the first anti-interference submodule 33, and the control terminal of the seventh transistor MP3 is connected to the first selection sub-signal CD_SELB. The first terminal of the eighth transistor MP4 is connected to the second terminal of the seventh transistor MP3, and the second terminal of the eighth transistor MP4 is connected to the first terminal of the sixth transistor MN4 to generate a first type of test signal V2. The control terminal of the eighth transistor MP4 is connected to the first selection sub-signal CD_SELB.

[0110] It should be noted that the fifth transistor MN3 and the sixth transistor MN4 have the same channel type and are connected to the same control signal, allowing them to switch synchronously; similarly, the seventh transistor MP3 and the eighth transistor MP4 have the same channel type and are connected to the same control signal, allowing them to switch synchronously. This creates two different paths for transmitting the first input voltage VIN1 to generate the first type of test signal V2.

[0111] In some embodiments, such as Figure 19 As shown, the first anti-interference submodule 33 includes a first anti-interference unit 331 and a second anti-interference unit 332. The first anti-interference unit 331 is used to transmit a first bias voltage VB1 to the first terminal of the eighth transistor MP4 and the second terminal of the seventh transistor MP3 according to the first selection sub-signal CD_SELB. The second anti-interference unit 332 is used to transmit a second bias voltage VB2 to the first terminal of the sixth transistor MN4 and the second terminal of the fifth transistor MN3 according to the second selection sub-signal CD_SELA.

[0112] It should be noted that the first anti-interference unit 331 can control the transmission of the first bias voltage VB1 through the first selection sub-signal CD_SELB, thereby changing the voltage of the first terminal of the eighth transistor MP4 or the second terminal of the seventh transistor MP3 to improve anti-interference capability. Similarly, the second anti-interference unit 332 can control the transmission of the second bias voltage VB2 through the second selection sub-signal CD_SELA, thereby changing the voltage of the first terminal of the sixth transistor MN4 or the second terminal of the fifth transistor MN3 to improve anti-interference capability.

[0113] In some embodiments, such as Figure 20 As shown, the first anti-interference unit 331 includes a first current source A1, a seventh resistor R7, a first capacitor C1, and a ninth transistor MN5. The first end of the first current source A1 is connected to the power supply terminal VPP; the first end of the seventh resistor R7 is connected to the second end of the first current source A1, and the second end of the seventh resistor R7 is connected to the ground terminal GND; the first end of the first capacitor C1 is connected to the first end of the seventh resistor R7, and the second end of the first capacitor C1 is connected to the ground terminal GND; the first terminal of the ninth transistor MN5 is connected to the first terminal of the seventh transistor MP3 and the second terminal of the eighth transistor MP4; the control terminal of the ninth transistor MN5 is connected to the first select sub-signal CD_SELB; and the second terminal of the ninth transistor MN5 is connected to the second terminal of the first current source A1, the first terminal of the seventh resistor R7, and the first terminal of the first capacitor C1.

[0114] It should be noted that the first current source A1, the seventh resistor R7, and the first capacitor C1 are used to generate the first bias voltage VB1, and the ninth transistor MN5 is used to control the transmission of the first bias voltage VB1.

[0115] In some embodiments, such as Figure 21 As shown, the second anti-interference unit 332 includes an eighth resistor R8, a second capacitor C2, a second current source A2, and a tenth transistor MP5. The first end of the eighth resistor R8 is connected to the power supply terminal VPP; the first end of the second capacitor C2 is connected to the power supply terminal VPP; the first end of the second current source A2 is connected to the ground terminal GND; the first terminal of the tenth transistor MP5 is connected to the first terminal of the fifth transistor MN3 and the second terminal of the sixth transistor MN4; the control terminal of the tenth transistor MP5 is connected to the second selector signal CD_SELA; and the second terminal of the tenth transistor MP5 is connected to the second terminal of the eighth resistor R8, the second terminal of the second capacitor C2, and the second terminal of the second current source A2.

[0116] It should be noted that the eighth resistor R8, the second capacitor C2, and the second current source A2 are used to generate the second bias voltage VB2, and the tenth transistor MP5 is used to control the transmission of the second bias voltage VB2.

[0117] In some embodiments, such as Figure 22 As shown, the fourth type of control signal includes the fifth drive signal BUF_SELA, the sixth drive signal BUF_SELB, the seventh drive signal BUFD_SELA, the eighth drive signal BUFD_SELB, and the ninth drive signal BUFBS_SELB. The second logic submodule 12 includes a third logic unit 121, a fourth logic unit 122, and a first bootstrap unit 123. The third logic unit 121 is used to generate the fifth drive signal BUF_SELA and the sixth drive signal BUF_SELB based on the second enable signal BUF_EN and the second sampling signal BUF_SAMP. The fourth logic unit 122 is used to generate the seventh drive signal BUFD_SELA and the eighth drive signal BUFD_SELB based on the fifth drive signal BUF_SELA and the sixth drive signal BUF_SELB. The first bootstrap unit 123 is used to generate the ninth drive signal BUFBS_SELB based on the second input voltage VIN2, the first sampling signal Sample, and the sixth drive signal BUF_SELB.

[0118] It should be noted that the first bootstrap unit 123 can be a bootstrap circuit, which is used to enhance the linearity of the transmission gate and improve the switching speed. The second input voltage VIN2 is the input voltage of the buffer 50.

[0119] In some embodiments, such as Figure 23 As shown, the third logic unit 121 includes an eighth NAND gate AN8, an eighteenth NOT gate N18, and a first non-overlapping clock processing subunit 1211. The two inputs of the eighth NAND gate AN8 are respectively connected to the second enable signal BUF_EN and the second sampling signal BUF_SAMP. The input of the eighteenth NOT gate N18 is connected to the output of the eighth NAND gate AN8. The input of the first non-overlapping clock processing subunit 1211 is connected to the output of the eighteenth NOT gate N18. The two outputs of the first non-overlapping clock processing subunit 1211 are used to generate the fifth driving signal BUF_SELA and the sixth driving signal BUF_SELB, respectively.

[0120] It should be noted that the first non-overlapping clock processing subunit 1211 can be a non-overlapping clock circuit. After the eighth NAND gate AN8 performs a NAND operation on the second enable signal BUF_EN and the second sampling signal BUF_SAMP, it is inverted by the eighteenth NOT gate N18. Then, the first non-overlapping clock processing subunit 1211 performs non-overlapping processing to generate multiple signals. The pulse edges of these signals do not overlap in time.

[0121] In some embodiments, such as Figure 24 As shown, the fourth logic unit 122 includes an even number of cascaded nineteenth NOT gates N19 and an even number of cascaded twentieth NOT gates N20. The input of the even number of cascaded nineteenth NOT gates N19 is connected to the fifth driving signal BUF_SELA, and the output of the even number of cascaded nineteenth NOT gates N19 generates the seventh driving signal BUFD_SELA. The input of the even number of cascaded twentieth NOT gates N20 is connected to the sixth driving signal BUF_SELB, and the output of the even number of cascaded twentieth NOT gates N20 generates the eighth driving signal BUFD_SELB.

[0122] It should be noted that an even number of cascaded nineteenth NOT gates N19 are used to delay the fifth drive signal BUF_SELA to generate the seventh drive signal BUFD_SELA. The number of nineteenth NOT gates N19 can be set according to the application scenario. Similarly, an even number of cascaded twentieth NOT gates N20 are used to delay the sixth drive signal BUF_SELB to generate the eighth drive signal BUFD_SELB. The number of twentieth NOT gates N20 can be set according to the application scenario.

[0123] In some embodiments, such as Figure 25 As shown, buffer 50 includes operational amplifier OP, first transmission gate CS1, second transmission gate CS2, eleventh transistor MN6, and twelfth transistor MN7. The inverting control terminal of the first transmission gate CS1 is connected to the fifth driving signal BUF_SELA, and the non-inverting control terminal of the first transmission gate CS1 is connected to the sixth driving signal BUF_SELB. The inverting control terminal of the second transmission gate CS2 is connected to the eighth driving signal BUFD_SELB, and the non-inverting control terminal of the second transmission gate CS2 is connected to the seventh driving signal BUFD_SELA. The first terminal of the eleventh transistor MN6 is connected to the output terminal of operational amplifier OP and the input terminal of second transmission gate CS2. The control terminal of the eleventh transistor MN6 is connected to the eighth driving signal BUFD_SELB, and the second terminal of the eleventh transistor MN6 is connected to ground GND. The first terminal of the twelfth transistor MN7 is connected to the second input terminal of operational amplifier OP and the output terminal of second transmission gate CS2 to generate a fourth type test signal V4. The control terminal of the twelfth transistor MN7 is connected to the ninth driving signal BUFBS_SELB, and the second terminal of the twelfth transistor MN7 is connected to the first input terminal of operational amplifier OP and the input terminal of first transmission gate CS1.

[0124] It should be noted that when the first transmission gate CS1 is turned on, the two input terminals of the operational amplifier OP can be short-circuited, bringing the operational amplifier OP into a balanced state and reducing offset. When the second transmission gate CS2 is turned on, the output voltage of the operational amplifier OP can be fed back to its non-inverting input terminal (+) to form a unity-gain buffer. At this time, the output voltage of the operational amplifier OP follows the voltage of the inverting input terminal (-). When the eleventh transistor MN6 is turned on, it is used to force the output terminal of the operational amplifier OP to ground, thereby resetting the voltage at the output terminal of the operational amplifier OP. When the twelfth transistor MN7 is turned on, the second input voltage VIN2 can be output directly without buffering.

[0125] In some embodiments, such as Figure 26 As shown, the first type of control signal includes the tenth drive signal SELB<5:0> and the eleventh drive signal SELA_BS<5:0>. The third logic submodule 13 includes a decoder 131, a second non-overlapping clock processing subunit 132, and a second bootstrap unit 133. The decoder 131 is used to decode the first selection control signal SEL<2:0> to generate the fourth intermediate signal VSEL<5:0>; the second non-overlapping clock processing subunit 132 is used to generate the tenth drive signal SELB<5:0> and the fifth intermediate signal SELA<5:0> based on the fourth intermediate signal; the second bootstrap unit 133 is used to generate the eleventh drive signal SELA_BS<5:0> based on the input signal VIN<5:0> from the multiplexer 20, the first sampling signal Sample, and the fifth intermediate signal.

[0126] It should be noted that the second non-overlapping clock processing subunit 132 can be a non-overlapping clock circuit. The second bootstrap unit 133 can be a bootstrap circuit.

[0127] In some embodiments, such as Figure 27 As shown, the multiplexer 20 includes multiple channel units 21 and a bias voltage generation unit 22. The channel units 21 are used to control the switching state of the channels according to the eleventh drive signal SELA_BS<5:0>. The bias voltage generation unit 22 is used to provide a third bias voltage VB3 for each channel unit 21.

[0128] It should be noted that in this embodiment, a bias voltage generation unit 22 is used to provide a corresponding third bias voltage VB3 for multiple channel units 21, which can reduce the number of bias voltage generation units 22 used, reduce power consumption and reduce area.

[0129] In some embodiments, such as Figure 28 As shown, each channel unit 21 includes a ninth resistor R9, a thirteenth transistor MN8, a fourteenth transistor MN9, and a fifteenth transistor MN10. The first terminal of the ninth resistor R9 is connected to the input signal VIN<5:0> connected to the multiplexer 20. The control terminal of the thirteenth transistor MN8 is connected to the eleventh drive signal SELA_BS<5:0>, and the second terminal of the thirteenth transistor MN8 is connected to the second terminal of the ninth resistor R9. The control terminal of the fourteenth transistor MN9 is connected to the eleventh drive signal SELA_BS<5:0>, and the first terminal of the fourteenth transistor MN9 is used to generate the corresponding third type test signal V1. The first terminal of the fifteenth transistor MN10 is connected to the first terminal of the thirteenth transistor MN8 and the second terminal of the fourteenth transistor MN9. The control terminal of the fifteenth transistor MN10 is connected to the tenth drive signal SELB<5:0>, and the second terminal of the fifteenth transistor MN10 is connected to the bias voltage generation unit 22 to receive the third bias voltage VB3.

[0130] It should be noted that the thirteenth transistor MN8 and the fourteenth transistor MN9 have the same channel type and their gates are connected to the same signal, allowing them to switch synchronously. When both the thirteenth transistor MN8 and the fourteenth transistor MN9 are turned on, the channel is in the on state; or, when both the thirteenth transistor MN8 and the fourteenth transistor MN9 are turned off, the channel is in the off state. The fifteenth transistor MN10 is used to control the transmission of the third bias voltage VB3 according to the tenth drive signal SELB<5:0>, which can improve the anti-interference capability of channel unit 21.

[0131] In some embodiments, such as Figure 29 As shown, the bias voltage generation unit 22 includes a third current source A3, a third capacitor C3, and a tenth resistor R10. The first end of the third current source A3 is connected to the power supply terminal VPP; the first end of the third capacitor C3 is connected to the ground terminal GND; the first end of the tenth resistor R10 is connected to the ground terminal GND, and the second end of the tenth resistor R10 is connected to the second end of the third current source A3, the second end of the third capacitor C3, and the second terminal of the fifteenth transistor MN10.

[0132] It should be noted that the third current source A3, the third capacitor C3, and the tenth resistor R10 are used to generate the third bias voltage VB3.

[0133] In some embodiments, such as Figure 30 As shown, the peripheral device 110 used to generate the input signal of the multiplexer 20 includes multiple input units 1101. Each input unit 1101 includes an eleventh resistor R11, a first switch K1, a second switch K2, and a twelfth resistor R12. The first end of the eleventh resistor R11 is connected to the first power supply voltage VDD. The first end of the first switch K1 is connected to the second end of the eleventh resistor R11. The first end of the second switch K2 is connected to the second end of the first switch K1 and an input terminal of the multiplexer 20. The first end of the twelfth resistor R12 is connected to the second end of the second switch K2, and the second end of the twelfth resistor R12 is connected to the second power supply voltage VSS.

[0134] It should be noted that the multiplexer 20 exemplarily has five input terminals, which are respectively connected to the VIN generated by each input unit 1101. <0> ...VIN <5> When the first switch K1 is on and the second switch K2 is off, VIN <0> ...VIN <5> It is high level; or, when the first switch K1 is open and the second switch K2 is open, VIN <0> ...VIN <5> It is a low level.

[0135] In some embodiments, such as Figure 31 As shown, the third type of control signal includes the twelfth drive signal BWDP_SELA, the thirteenth drive signal BWDP_SELB, the fourteenth drive signal BWDN_SELA, and the fifteenth drive signal BWDN_SELB. The fourth logic submodule 14 includes a fifth logic unit 141, a sixth logic unit 142, a seventh logic unit 143, and an eighth logic unit 144. The fifth logic unit 141 is used to generate a sixth intermediate signal based on the first sampling signal Sample, the first selection control signal SEL<2:0>, and the third enable signal BWD_EN. The sixth logic unit 142 is used to generate a seventh intermediate signal sela0 and an eighth intermediate signal selb0 based on the third selection control signal BWD_SEL. The seventh logic unit 143 is used to generate the twelfth drive signal BWDP_SELA and the thirteenth drive signal BWDP_SELB based on the sixth intermediate signal and the seventh intermediate signal sela0. The eighth logic unit 144 is used to generate the fourteenth drive signal BWDN_SELA and the fifteenth drive signal BWDN_SELB based on the sixth intermediate signal and the eighth intermediate signal selb0.

[0136] It should be noted that, in this embodiment, the twelfth driving signal BWDP_SELA, the thirteenth driving signal BWDP_SELB, the fourteenth driving signal BWDN_SELA, and the fifteenth driving signal BWDN_SELB can be generated based on the combination of the fifth logic unit 141, the sixth logic unit 142, the seventh logic unit 143, and the eighth logic unit 144, so as to control the second voltage generation module 40 to generate the second type of test signal V3.

[0137] In some embodiments, such as Figure 32 As shown, the fifth logic unit 141 includes a ninth NAND gate AN9, a twenty-first NOT gate N21, a tenth NAND gate AN10, a twenty-second NOT gate N22, an eleventh NAND gate AN11, and a twenty-third NOT gate N23. The three inputs of the ninth NAND gate AN9 are respectively connected to the three bits of the first selection control signal SEL<2:0>. The input of the twenty-first NOT gate N21 is connected to the output of the ninth NAND gate AN9. The two inputs of the tenth NAND gate AN10 are respectively connected to the first sampling signal Sample and the third enable signal BWD_EN. The input of the twenty-second NOT gate N22 is connected to the output of the tenth NAND gate AN10. The first input of the eleventh NAND gate AN11 is connected to the output of the twenty-first NOT gate N21, and the second input of the eleventh NAND gate AN11 is connected to the output of the twenty-second NOT gate N22. The input of the twenty-third NOT gate N23 is connected to the output of the eleventh NAND gate AN11, and the output of the twenty-third NOT gate N23 generates a sixth intermediate signal.

[0138] It should be noted that after performing a NAND operation on the three bits of the first selection control signal SEL<2:0> by the ninth NAND gate AN9, the signal is inverted by the twenty-first NOT gate N21. After performing a NAND operation on the first sample signal Sample and the third enable signal BWD_EN by the tenth NAND gate AN10, the signal is inverted by the twenty-second NOT gate N22. After performing a NAND operation on the output signals of the ninth NAND gate AN9 and the tenth NAND gate AN10 by the eleventh NAND gate AN11, the signal is inverted by the twenty-third NOT gate N23 to generate the sixth intermediate signal.

[0139] In some embodiments, such as Figure 33 As shown, the sixth logic unit 142 includes a twenty-fourth NOT gate N24, a twenty-fifth NOT gate N25, and a twenty-sixth NOT gate N26. The input of the twenty-fourth NOT gate N24 is connected to the third selection control signal BWD_SEL; the input of the twenty-fifth NOT gate N25 is connected to the output of the twenty-fourth NOT gate N24, and the output of the twenty-fifth NOT gate N25 generates the seventh intermediate signal sela0; the input of the twenty-sixth NOT gate N26 is connected to the output of the twenty-fifth NOT gate N25, and the output of the twenty-sixth NOT gate N26 generates the eighth intermediate signal selb0.

[0140] It should be noted that the twenty-fourth NOT gate N24 and the twenty-fifth NOT gate N25 delay the third selection control signal BWD_SEL to generate the seventh intermediate signal sela0, which is then inverted by the twenty-sixth NOT gate N26 to generate the eighth intermediate signal selb0.

[0141] In some embodiments, such as Figure 34 As shown, the seventh logic unit 143 includes a twelfth NAND gate AN12, a twenty-seventh NOT gate N27, and a third non-overlapping clock processing subunit 1431. The first input terminal of the twelfth NAND gate AN12 is connected to the output terminal of the twenty-third NOT gate N23, and the second input terminal of the twelfth NAND gate AN12 is connected to the output terminal of the twenty-fifth NOT gate N25. The input terminal of the twenty-seventh NOT gate N27 is connected to the output terminal of the twelfth NAND gate AN12. The input terminal of the third non-overlapping clock processing subunit 1431 is connected to the output terminal of the twenty-seventh NOT gate N27. The two output terminals of the third non-overlapping clock processing subunit 1431 generate the twelfth driving signal BWDP_SELA and the thirteenth driving signal BWDP_SELB, respectively.

[0142] It should be noted that after the twelfth NAND gate AN12 performs NAND operation on the sixth and seventh intermediate signals sela0, it is inverted by the twenty-seventh NOT gate N27, and then processed by the third non-overlapping clock processing subunit 1431 to generate the twelfth driving signal BWDP_SELA and the thirteenth driving signal BWDP_SELB. The third non-overlapping clock processing subunit 1431 can be a non-overlapping clock circuit.

[0143] In some embodiments, such as Figure 35 As shown, the eighth logic unit 144 includes a thirteenth NAND gate AN13, a twenty-eighth NOT gate N28, and a fourth non-overlapping clock processing subunit 1441. The first input of the thirteenth NAND gate AN13 is connected to the output of the twenty-third NOT gate N23, and the second input of the twelfth NAND gate AN12 is connected to the output of the twenty-sixth NOT gate N26. The input of the twenty-eighth NOT gate N28 is connected to the output of the thirteenth NAND gate AN13. The input of the fourth non-overlapping clock processing subunit 1441 is connected to the output of the twenty-eighth NOT gate N28. The two outputs of the fourth non-overlapping clock processing subunit 1441 generate the fourteenth driving signal BWDN_SELA and the fifteenth driving signal BWDN_SELB, respectively.

[0144] It should be noted that after the thirteenth NAND gate AN13 performs NAND operation on the sixth intermediate signal and the eighth intermediate signal selb0, it is inverted by the twenty-eighth NOT gate N28, and then processed by the fourth non-overlap clock processing subunit 1441 to generate the fourteenth drive signal BWDN_SELA and the fifteenth drive signal BWDN_SELB. The fourth non-overlap clock processing subunit 1441 can be a non-overlap clock circuit.

[0145] In some embodiments, such as Figure 36 As shown, the second voltage generation module 40 includes a second selection transmission submodule 41 and a second anti-interference submodule 42. The second selection transmission submodule 41 is used to select and transmit a first reference voltage or a second reference voltage according to the thirteenth driving signal BWDP_SELB and the fourteenth driving signal BWDN_SELA to generate a second type of test signal V3. The second anti-interference submodule 42 is used to transmit a third bias voltage VB3 or a fourth bias voltage VB4 to the second selection transmission submodule 41 according to the twelfth driving signal BWDP_SELA and the fifteenth driving signal to improve the anti-interference capability of the second selection transmission submodule 41.

[0146] It should be noted that the second selective transmission submodule 41 can transmit the first reference voltage or the second reference voltage in a time-division multiplexing manner, thereby forming a second type of test signal V3 based on the transmitted first reference voltage or second reference voltage.

[0147] In some embodiments, such as Figure 37 As shown, the second selection transmission submodule 41 includes a sixteenth transistor MN11, a seventeenth transistor MN12, an eighteenth transistor MP6, and a nineteenth transistor MP7. The control electrode of the sixteenth transistor MN11 is connected to the fourteenth driving signal BWDN_SELA, and the second electrode of the sixteenth transistor MN11 is connected to the first reference voltage. The control electrode of the seventeenth transistor MN12 is connected to the fourteenth driving signal BWDN_SELA, and the second electrode of the seventeenth transistor MN12 is connected to the first electrode of the sixteenth transistor MN11. The control electrode of the eighteenth transistor MP6 is connected to the thirteenth driving signal BWDP_SELB, and the second electrode of the eighteenth transistor MP6 is connected to the second reference voltage. The control electrode of the nineteenth transistor MP7 is connected to the thirteenth driving signal BWDP_SELB, and the second electrode of the nineteenth transistor MP7 is connected to the first electrode of the eighteenth transistor MP6. The first electrode of the nineteenth transistor MP7 is connected to the first electrode of the seventeenth transistor MN12 to generate a second type of test signal V3.

[0148] It should be noted that the sixteenth transistor MN11 and the seventeenth transistor MN12 have the same channel type and their gates are connected to the same signal, so they can switch synchronously to control the transmission of the first reference voltage. The eighteenth transistor MP6 and the nineteenth transistor MP7 have the same channel type and their gates are connected to the same signal, so they can switch synchronously to control the transmission of the second reference voltage.

[0149] In some embodiments, such as Figure 38 As shown, the second anti-interference submodule 42 includes a third anti-interference unit 421 and a fourth anti-interference unit 422. The third anti-interference unit 421 is used to transmit a third bias voltage VB3 to the first terminal of the sixteenth transistor MN11 and the second terminal of the seventeenth transistor MN12 according to the fifteenth driving signal BWDN_SELB. The fourth anti-interference unit 422 is used to transmit a fourth bias voltage VB4 to the first terminal of the eighteenth transistor MP6 and the second terminal of the nineteenth transistor MP7 according to the twelfth driving signal BWDP_SELA.

[0150] It should be noted that the third anti-interference unit 421 can suppress noise interference by applying a third bias voltage VB3 between the first terminal of the sixteenth transistor MN11 and the second terminal of the seventeenth transistor MN12 when both the sixteenth transistor MN11 and the seventeenth transistor MN12 are turned off. Similarly, the fourth anti-interference unit 422 can suppress noise interference by applying a fourth bias voltage VB4 between the first terminal of the eighteenth transistor MP6 and the second terminal of the nineteenth transistor MP7 when both the eighteenth transistor MP6 and the nineteenth transistor MP7 are turned off.

[0151] In some embodiments, such as Figure 39 As shown, the third anti-interference unit 421 includes a fourth current source A4, a thirteenth resistor R13, a fourth capacitor C4, and a twentieth transistor MN13. The first terminal of the fourth current source A4 is connected to the power supply terminal VPP; the first terminal of the thirteenth resistor R13 is connected to the ground terminal GND; the first terminal of the fourth capacitor C4 is connected to the ground terminal GND; the first terminal of the twentieth transistor MN13 is connected to the first terminal of the sixteenth transistor MN11 and the second terminal of the seventeenth transistor MN12; the control terminal of the twentieth transistor MN13 is connected to the fifteenth drive signal BWDN_SELB; and the second terminal of the twentieth transistor MN13 is connected to the second terminal of the fourth current source A4, the second terminal of the thirteenth resistor R13, and the second terminal of the fourth capacitor C4.

[0152] It should be noted that the fourth current source A4, the thirteenth resistor R13, and the fourth capacitor C4 are used to generate the third bias voltage VB3, and the twentieth transistor MN13 is used to control the transmission of the third bias voltage VB3.

[0153] In some embodiments, such as Figure 40 As shown, the fourth anti-interference unit 422 includes a fourteenth resistor R14, a fifth capacitor C5, a fifth current source A5, and a twenty-first transistor MP8. The first terminal of the fourteenth resistor R14 is connected to the power supply terminal VPP; the first terminal of the fifth capacitor C5 is connected to the power supply terminal VPP; the first terminal of the fifth current source A5 is connected to the ground terminal GND; the first terminal of the twenty-first transistor MP8 is connected to the second terminal of the fourteenth resistor R14, the second terminal of the fifth capacitor C5, and the second terminal of the fifth current source A5; the control terminal of the twenty-first transistor MP8 is connected to the twelfth drive signal BWDP_SELA; and the second terminal of the twenty-first transistor MP8 is connected to the first terminal of the eighteenth transistor MP6 and the second terminal of the nineteenth transistor MP7.

[0154] It should be noted that the fourteenth resistor R14, the fifth capacitor C5, and the fifth current source A5 are used to generate the fourth bias voltage VB4, and the twenty-first transistor MP8 is used to control the transmission of the fourth bias voltage VB4.

[0155] Figure 41 The timing diagram of the first logic submodule 11 is shown. Here, sar_clk is the system clock signal of the analog-to-digital converter 60. When the first enable signal CD_EN is low, the first voltage generation module 30 can be controlled not to generate the first type of test signal V2; or, when the first enable signal CD_EN is high, the first voltage generation module 30 can be controlled to generate the first type of test signal V2. The second selection control signal CD_SEL<1:0> is used to control the voltage value of the first input voltage VIN1. The second selection sub-signal CD_SELA is the same as the first sampling signal Sample, and the first selection sub-signal CD_SELB is the inverse of the second selection signal CD_SELA.

[0156] Config1 represents the first operating state of the first voltage generation module 30 when the first selection sub-signal CD_SELB is high and the second selection sub-signal CD_SELA is low. Config2 represents the second operating state of the first voltage generation module 30 when the first selection sub-signal CD_SELB is low and the second selection sub-signal CD_SELA is high.

[0157] The first selection control signal SEL<2:0>, configured as 110, can control the multiplexer 20 to not select any channel. The first type of test signal V2 outputs four voltages according to the configuration of the second selection control signal CD_SEL<1:0>, which are then fed to the SARADC for quantization.

[0158] When detecting whether the analog-to-digital converter 60 is malfunctioning, the second enable signal BUF_EN is set to a low level to control the bypass of the buffer 50, and the first type of test signal V2 is directly output to the analog-to-digital converter 60 for quantization. The quantization result of the first type of test signal V2 is used to determine whether the analog-to-digital converter 60 is malfunctioning. Since the specific value of the first type of test signal V2 is controllable, the theoretical quantization value corresponding to the first type of test signal V2 is also known. If the quantization result of the analog-to-digital converter 60 is the same as the theoretical quantization value, it indicates that the analog-to-digital converter 60 is functioning normally; or, if the quantization result of the analog-to-digital converter 60 is different from the theoretical quantization value, it indicates that the analog-to-digital converter 60 is malfunctioning.

[0159] Figure 42 The timing diagram of the second logic submodule 12 is shown. Here, SAMP_T represents the duration between the falling edge of the second sampling signal BUF_SAMP and the falling edge of the first sampling signal Sample. BUF_SAMP_T represents the duration between the rising edge of the second sampling signal BUF_SAMP and its falling edge. Delay represents the delay between the pulse edge of the sixth drive signal BUF_SELB and the pulse edge of either the seventh or eighth drive signal BUFD_SELA. The first Non-Overlap indicates that the falling edge of the fifth drive signal BUF_SELA is earlier than the rising edge of the sixth drive signal BUF_SELB. The second Non-Overlap indicates that the rising edge of the fifth drive signal BUF_SELA is later than the falling edge of the sixth drive signal BUF_SELB, and the falling edge of the fifth drive signal BUF_SELA is earlier than the rising edge of the sixth drive signal BUF_SELB.

[0160] When checking whether the buffer 50 is malfunctioning, the second selection control signal CD_SEL<1:0> is configured to 01 or 10, and the first selection control signal SEL<2:0> is configured to 110, which can control the multiplexer 20 to not select any channel. The first type of test signal V2 generates two voltages to the input terminal of the buffer 50 according to the configuration of the first selection control signal SEL<2:0>, and after buffering, the output is the fourth type of test signal V4.

[0161] The first enable signal CD_EN, the second enable signal BUF_EN, and the second sampling signal BUF_SAMP are all set to high level, and the third enable signal BWD_EN is set to low level. Buffer 50 operates in unity gain mode. The quantization result of the fourth type of test signal V4 is used to determine whether the function of buffer 50 is abnormal.

[0162] Since the first type of test signal V2 is known, and the fourth type of test signal V4 after buffering is also known, the theoretical quantization value corresponding to the fourth type of test signal V4 is also known. If the quantization result of the analog-to-digital converter 60 is the same as the theoretical quantization value, it means that the function of the buffer 50 is normal; or, if the quantization result of the analog-to-digital converter 60 is different from the theoretical quantization value, it means that the function of the buffer 50 is abnormal.

[0163] When there is no detection of whether buffer 50 is malfunctioning, the normal operating timing of buffer 50 is as follows: Figure 42 As shown, there is a channel state switch. The high voltage of the ninth drive signal BUFBS_SELB is VDD+VIN2. When VIN2 increases to VDD, it can reach a maximum of 2VDD. Here, VIN2 represents the second input voltage VIN2, and VDD represents the first power supply voltage VDD.

[0164] Figure 43 The timing diagram of the third logic submodule 13 is shown. The waveform of the first sampling signal Sample is the same as the waveform of the eleventh drive signal SELA_BS<5:0>. Config1 represents the first operating state of the multiplexer 20 when the eleventh drive signal SELA_BS<5:0> is low. Config2 represents the second operating state of the multiplexer 20 when the eleventh drive signal SELA_BS<5:0> is high. The configuration of the first selection control signal SEL<2:0> differs in Config1 and Config2.

[0165] When the function of the multiplexer 20 is checked for abnormality, the first enable signal CD_EN, the second enable signal BUF_EN, and the third enable signal BWD_EN are set to low level to shut down the corresponding first voltage generation module 30, buffer 50, and second voltage generation module 40. The first selection control signal SEL<2:0> is set to 000~101 respectively to select VIN. <0> ~VIN <5> V1 is used as the third type of test signal. The quantization result of the third type of test signal V1 is used to determine whether the function of the multiplexer 20 is abnormal.

[0166] Since the third type of test signal V1 is known, the theoretical quantization value corresponding to the third type of test signal V1 is also known. If the quantization result of the analog-to-digital converter 60 is the same as the theoretical quantization value, it means that the function of the multiplexer 20 is normal; or, if the quantization result of the analog-to-digital converter 60 is different from the theoretical quantization value, it means that the function of the multiplexer 20 is abnormal.

[0167] Among them, the high level of the eleventh drive signal SELA_BS<5:0> is VDD+VIN, and can reach a maximum of 2VDD.

[0168] When detecting whether the connection between the analog-to-digital converter circuit 100 and the peripheral device 110 is broken, the first enable signal CD_EN and the second enable signal BUF_EN are set to low level to shut down the first voltage generation module 30 and the buffer 50; the third enable signal BWD_EN is set to high level to control the second voltage generation module 40 to generate the second type of test signal V3. The third selection control signal BWD_SEL selects the precharge voltage to be REFP or REFN. During the precharge phase, the first selection control signal SEL<2:0> is set to 111, shutting down all channels of the multiplexer 20, and the voltage of the second type of test signal V3 is precharged to REFP / REFN. After the precharge is completed, the first selection control signal SEL<2:0> is set to 000~101 to select the channel connected to the peripheral device 110.

[0169] If peripheral 110 is open-circuited, the quantization result of analog-to-digital converter 60 is the quantization result of the second type of test signal V3; if peripheral 110 is connected normally, the quantization result of analog-to-digital converter 60 is the quantization result of the third type of test signal V1 provided by peripheral 110. Since the third type of test signal V1 or the second type of test signal V3 is known, the theoretical quantization value corresponding to the third type of test signal V1 or the second type of test signal V3 is also known. If the quantization result of analog-to-digital converter 60 is the same as the theoretical quantization value of the third type of test signal V1, it indicates that peripheral 110 is connected normally; or, if the quantization result of analog-to-digital converter 60 is the same as the theoretical quantization value of the second type of test signal V3, it indicates that peripheral 110 is open-circuited.

[0170] like Figure 44 As shown, this application embodiment also provides a chip 200, which includes the analog-to-digital conversion circuit 100 described above. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. It is understood that since the chip 200 provided in this embodiment includes an analog-to-digital converter circuit 100, it can also generate a first type of control signal, a second type of control signal, and a fourth type of control signal through the logic control module 10. The multiplexer 20 controls the switching state of the corresponding channel according to the first type of control signal, the first voltage generation module 30 generates a first type of test signal V2 according to the second type of control signal, the buffer 50 quantizes the first type of test signal V2 according to the fourth type of control signal, and the analog-to-digital converter 60 generates the quantization result of the first type of test signal V2. Based on the quantization result, it is determined whether the function of the analog-to-digital converter 60 is abnormal. This allows the analog-to-digital converter circuit 100 to perform self-checks on whether the function of the analog-to-digital converter 60 is abnormal, thereby improving the working reliability of the analog-to-digital converter circuit 100.

[0171] like Figure 45 As shown in the illustration, this application also provides an electronic device 300, which includes a device body and the aforementioned analog-to-digital conversion circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0172] It is understood that since the electronic device 300 provided in this embodiment includes an analog-to-digital converter circuit 100 or a chip 200, it can also generate a first type of control signal, a second type of control signal, and a fourth type of control signal through the logic control module 10. The multiplexer 20 controls the switching state of the corresponding channel according to the first type of control signal, the first voltage generation module 30 generates a first type of test signal V2 according to the second type of control signal, the buffer 50 quantizes the first type of test signal V2 according to the fourth type of control signal, and the analog-to-digital converter 60 generates the quantization result of the first type of test signal V2. Based on the quantization result, it is determined whether the function of the analog-to-digital converter 60 is abnormal. This allows the analog-to-digital converter circuit 100 to perform self-checks on whether the function of the analog-to-digital converter 60 is abnormal, thereby improving the working reliability of the analog-to-digital converter circuit 100.

[0173] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes: The logic control module is used to generate the first type of control signal, the second type of control signal, and the fourth type of control signal. A multiplexer is used to control the switching state of the corresponding channel according to the first type of control signal; The first voltage generation module is used to generate a first type of test signal based on the second type of control signal; A buffer is used to directly output the first type of test signal according to the fourth type of control signal; An analog-to-digital converter is used to generate quantization results of the first type of test signal, so as to determine whether the function of the analog-to-digital converter is abnormal based on the quantization results.

2. The analog-to-digital converter circuit as described in claim 1, characterized in that, The logic control module controls all channels of the multiplexer to be in an open state, and controls the buffer to directly output the first type of test signal to the analog-to-digital converter, so as to determine whether the analog-to-digital converter is functioning normally based on the quantization result of the first type of test signal.

3. The analog-to-digital converter circuit as described in claim 2, characterized in that, The logic control module includes: The first logic submodule is used to generate the second type of control signal based on the first sampling signal, the first enable signal, the first selection control signal, and the second selection control signal; The second logic submodule is used to generate the fourth type of control signal based on the first sampling signal, the second enable signal, the second sampling signal, and the input signal of the buffer; The third logic submodule is used to generate the first type of control signal based on the first sampling signal, the first selection control signal, and the input signal accessed by the multiplexer.

4. The analog-to-digital converter circuit as described in claim 3, characterized in that, The second type of control signal includes a first selection sub-signal, a second selection sub-signal, a first drive signal, a second drive signal, a third drive signal, and a fourth drive signal. The first logic sub-module includes: The first logic unit is configured to generate a first intermediate signal, a first selection sub-signal, and a second selection signal based on the first sampling signal, the first enable signal, and the first selection control signal. The second logic unit is used to generate the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal based on the second selection control signal and the first intermediate signal.

5. The analog-to-digital converter circuit as described in claim 4, characterized in that, The first logic unit includes: The first logic subunit is configured to generate the first intermediate signal based on the first sampling signal, the first enable signal, and the first selection control signal. The second logic subunit is used to generate the first selection sub-signal and the second selection sub-signal based on the first intermediate signal.

6. The analog-to-digital converter circuit as described in claim 4, characterized in that, The second logic unit includes: The third logic subunit is used to generate a second intermediate signal and a third intermediate signal according to the second selection control signal; The fourth logic subunit is used to generate the first drive signal based on the first intermediate signal and the second intermediate signal; The fifth logic subunit is used to generate the second driving signal based on the first intermediate signal and the third intermediate signal; The sixth logic subunit is used to generate the third driving signal based on the first intermediate signal and the second intermediate signal; The seventh logic subunit is used to generate the fourth driving signal based on the first intermediate signal, the second intermediate signal, and the third intermediate signal.

7. The analog-to-digital converter circuit as described in claim 4, characterized in that, The first voltage generation module includes: A voltage generation submodule is used to generate a corresponding first input voltage based on the first driving signal, the second driving signal, the third driving signal, and the fourth driving signal; The first selection transmission submodule is used to select the first input voltage to be transmitted according to the first selection sub-signal and the second selection sub-signal in order to generate the first type of test signal; The first anti-interference submodule is used to transmit a first bias voltage or a second bias voltage to the first selection transmission submodule according to the first selection sub-signal and the second selection sub-signal, so as to improve the anti-interference capability of the first selection transmission submodule.

8. The analog-to-digital converter circuit as described in claim 7, characterized in that, The voltage generation submodule includes: The first voltage generating unit is configured to generate a first initial input voltage corresponding to the first power supply voltage based on the first driving signal and the second driving signal. The second voltage generating unit is used to generate a second initial input voltage corresponding to the second power supply voltage according to the third driving signal and the fourth driving signal; The first input voltage is the result of the combination of the first initial input voltage and the second initial input voltage.

9. The analog-to-digital converter circuit as described in claim 7, characterized in that, The first anti-interference submodule includes: The first anti-interference unit is used to transmit a first bias voltage between the first terminal of the eighth transistor and the second terminal of the seventh transistor in the first selection transmission submodule according to the first selection sub-signal. The second anti-interference unit is used to transmit a second bias voltage between the second terminal of the sixth transistor and the first terminal of the fifth transistor in the first selection transmission submodule according to the second selection sub-signal; Wherein, the second terminal of the fifth transistor is connected to the first input voltage, the control terminal of the fifth transistor is connected to the second selection sub-signal, the control terminal of the sixth transistor is connected to the second selection sub-signal, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, the control terminal of the seventh transistor is connected to the first selection sub-signal, the second terminal of the eighth transistor is connected to the first terminal of the sixth transistor, and the control terminal of the eighth transistor is connected to the first selection sub-signal.

10. A chip, characterized in that, The chip includes the analog-to-digital conversion circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 10 disposed on the device body.

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