Gigabit photoelectric transceiver with link interlocking protection function and control method

Abstract

The invention relates to a gigabit photoelectric transceiver with a link interlocking protection function and a control method, the photoelectric transceiver comprises an MCU chip, a PHY chip, an electric port module, an optical port module, a power supply module and an auxiliary circuit, the optical port module is an SFP optical module, the electric port module is an RJ45 interface, the MCU chip communicates with the PHY chip, the MCU chip is further connected with the SFP optical module, and the auxiliary circuit is connected with the power supply module. The PHY chip is responsible for conversion and transmission of Ethernet physical layer signals, the PHY chip is connected with the SFP optical module, the RJ45 interface is connected with the PHY chip through the MDI / MDIX adaptive circuit, the auxiliary circuit comprises a DC-DC converter, an LED indicating lamp and a crystal oscillator circuit providing clock signals required by the system, the LED indicating lamp is connected with the MCU chip and controlled by the MCU chip, and the MCU chip is connected with the auxiliary circuit. According to the invention, through centralized monitoring and active control of the MCU chip, logic interlocking between the optical port and the electric port is realized. When one end detects a fatal fault, the MCU can immediately cut off the other end, thereby preventing invalid data transmission and fault diffusion, and greatly improving the network reliability.

Description

Technical Field

[0001] This invention relates to the field of network communication equipment technology, and in particular to a gigabit optical transceiver with link interlock protection function and its control method. Background Technology

[0002] With the rapid development of information technology and network applications, Gigabit Ethernet has become the mainstream network standard in enterprise, data center, and industrial environments. Optical transceivers, as key devices in network cabling that convert electrical signals to optical signals, play an irreplaceable role in extending transmission distances, enhancing anti-interference capabilities, and connecting different physical media (such as twisted-pair cables and optical fibers). Among them, Gigabit optical transceivers combining SFP-packaged hot-swappable optical modules with RJ45 electrical ports are widely used due to their flexibility and convenience.

[0003] Existing gigabit optical transceivers, in actual deployment and operation, especially in scenarios with extremely high requirements for network stability and reliability (such as industrial control, financial transactions, and core links for security monitoring), have revealed the following significant technical shortcomings:

[0004] 1. Lack of effective link interlocking and fault isolation mechanisms: Although the optical and electrical ports of traditional transceivers are physically and protocol-wise connected, they are relatively independent in terms of logical control and fault response. When a serious fault occurs on one side of the link (e.g., optical signal loss due to fiber breakage or optical module damage, or optical module transmission failure), the other side of the link usually remains in normal operation. This "one-sided fault" mode causes data packets to be continuously lost on the faulty link and may spread the impact of the fault to connected network devices, making rapid fault isolation impossible. For example, after the optical port fails, the electrical port continues to send a signal indicating that the link is normal to the upstream device, causing data to be continuously sent to the "black hole" link, resulting in the interruption of critical business data and making it difficult to quickly locate the problem.

[0005] 2. Insufficient system reliability: Under power fluctuations or abnormal conditions, traditional equipment may lose configuration parameters or enter unpredictable states due to the inability to execute an orderly shutdown process. Furthermore, prolonged failures of the optoelectronic modules can lead to localized overheating. The lack of an active shutdown mechanism not only increases power consumption but also poses potential safety risks.

[0006] 3. Low efficiency in operation and maintenance and fault diagnosis: Due to the lack of integrated and intelligent interlocking control logic, when a network interruption occurs, maintenance personnel need to check the optical path and electrical path separately, making the troubleshooting process cumbersome. The equipment itself cannot intuitively and quickly indicate the root cause of the fault through the linkage changes of the optical port and electrical port status, which increases the complexity of network maintenance and the average repair time.

[0007] Therefore, there is an urgent need in this field for a novel gigabit optical transceiver solution that not only performs basic photoelectric conversion but also possesses intelligent link status awareness, rapid fault diagnosis, and proactive interlocking protection capabilities. This enables rapid fault isolation and recovery at the hardware level, significantly improving the reliability and availability of the entire network link. This invention arose in response to this technological context. Summary of the Invention

[0008] To address the aforementioned technical problems, the first objective of this invention is to provide a gigabit optical transceiver with link interlock protection functionality. This transceiver possesses link status awareness, rapid fault diagnosis, and proactive interlock protection capabilities, significantly improving the reliability and availability of the entire network link. The second objective of this invention is to provide a control method for this gigabit optical transceiver with link interlock protection functionality.

[0009] To achieve the first objective mentioned above, the present invention adopts the following technical solution:

[0010] A gigabit optical transceiver with link interlock protection includes an MCU chip, a PHY chip, an electrical port module, an optical port module, a power supply module, and auxiliary circuitry. The optical port module is an SFP optical module, and the electrical port module is an RJ45 interface. The MCU chip communicates with the PHY chip and is also connected to the SFP optical module. The PHY chip is responsible for the conversion and transmission of Ethernet physical layer signals. The SFP optical module is responsible for converting electrical signals into optical signals for long-distance transmission and simultaneously receiving optical signals and converting them back into electrical signals. The RJ45 interface is connected to the PHY chip via an MDI / MDIX adaptive circuit. The auxiliary circuitry includes a DC-DC converter, LED indicators, and a crystal oscillator circuit that provides the clock signal required by the system. The power supply module provides various voltages required by each module via the DC-DC converter. The LED indicators are connected to and controlled by the MCU chip. The MCU monitors the status of the SFP optical module, the RJ45 interface, and the remote electrical port, and adjusts the on / off state of the SFP optical module and the RJ45 interface accordingly.

[0011] As a preferred embodiment, the MCU chip is connected to the SGMII pin of the PHY chip via the MDC / MDIO pin, enabling the MCU chip to read and configure the PHY chip.

[0012] As a preferred embodiment, the PHY chip also has LED0 pin, LED1 pin, and LED2 pin. The MCU chip controls the status of the LED indicator lights of the SFP optical module and the RJ45 interface according to the status of the three signals of LED0 pin, LED1 pin, and LED2 pin.

[0013] As a preferred embodiment, the PHY chip also has SDS_RXP pin, SDS_RXN pin, SDS_TXP pin, and SDS_TXN pin. The PHY chip achieves high-speed SERDS signal transmission with the SFP optical module through the above pins.

[0014] As a preferred embodiment: the SFP optical module has SDA / SCL pins, and the PHY chip adjusts the signal of the SFP optical module through the SDA / SCL pins.

[0015] As a preferred embodiment, the SFP optical module also has a TXFault pin and an RX_LOS pin, through which the MCU chip reads the status of the SFP optical module or controls the SFP optical module.

[0016] As a preferred embodiment: the MCU chip is equipped with a GPIO interface, through which the LED indicator is controlled; the PHY chip and the MCU chip are also equipped with heat sinks.

[0017] To achieve the second objective mentioned above, the present invention adopts the following technical solution:

[0018] A control method for a gigabit optical transceiver with link interlock protection function, using any of the optical transceivers described above, includes an initialization phase, a main loop phase, and a fault handling phase. The specific steps are as follows:

[0019] S1, Initialization Phase

[0020] After the system is powered on, it performs hardware reset sequentially, including PHY chip initialization, USART serial port initialization, MDC / MDIO initialization, and GPIO status control initialization.

[0021] Determine if the communication between the PHY chip and the MCU chip is normal. If the communication is abnormal, stop the machine and report an error. If the communication is normal, configure the PHY chip in SGMII mode, initialize the link state structure, and read the initial state.

[0022] S2, Main Loop Phase

[0023] The main loop executes every 100ms and mainly includes:

[0024] S21, State Polling

[0025] A complete status check is performed every 2 seconds. By reading the corresponding registers of the PHY chip, the status of the local optical port, the remote electrical port, the local electrical port, and the optical signal loss status are obtained.

[0026] S22, Interlock Control

[0027] When an optical port fault is detected: the MCU chip immediately sets the TX_Disable pin high to shut down the SFP optical module, and controls the electrical port and PHY chip to enter Power Down mode through the GPIO pin, while turning off the LED0 / LED1 indicator lights and recording the fault log.

[0028] When the optical port is restored: the MCU chip clears the TX_Disable signal, wakes up the electrical port and PHY chip, reinitializes the link parameters, lights up the LED indicator and starts flashing;

[0029] The LED indicator has three components: a green LED that is constantly lit when the power supply is normal, a yellow LED that flashes when the link is active, and a red LED that is constantly lit in full-duplex mode and turns off in half-duplex mode. The LED0 pin of the PHY chip controls the green LED, the LED1 pin controls the yellow LED, and the LED2 pin controls the red LED.

[0030] S3, Fault Handling Phase

[0031] Differentiated processing is performed for different fault scenarios:

[0032] A. Optical port failure: Immediately shut down the electrical port to prevent data packet loss, and start a 100ms polling detection and recovery. If recovery is not achieved within 5 seconds, enter safe mode.

[0033] B. Electrical port failure: Keep the optical port working normally, attempt automatic negotiation recovery, and record the electrical port bit error rate on the PHY chip;

[0034] C. Power failure: When the VCC5 pin of the MCU chip is detected to be powered down, the critical state is saved to the backup register, an ordered shutdown sequence is executed, and a reset is triggered by the watchdog timer.

[0035] As a preferred embodiment, in step S22, when the state of the optical port changes, the state of the remote electrical port must be set to UNKNOWN. In step S22, when the state of the optical port remains UP, the state of the remote electrical port needs to be judged. When the remote electrical port changes from UP to DOWN, the electrical port needs to be closed immediately; when the remote electrical port changes from UP to UP, the electrical port needs to be opened immediately; when the remote electrical port is in other states, the electrical port state remains unchanged.

[0036] As a preferred embodiment, in step S1, the MCU chip resets the PHY chip through the NRST pin, and the MCU chip also initializes the clock configuration.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] This invention achieves logical interlocking between optical and electrical ports through centralized monitoring and active control by an MCU chip. When a fatal fault is detected at one end, the MCU can immediately disconnect the other end, preventing invalid data propagation and fault spread, isolating the impact of the fault within the local device, and greatly improving network reliability.

[0039] This invention offloads protection logic to the MCU chip at the device hardware level, achieving millisecond-level fault detection and response, which is much faster than relying on intervention from upper-layer network management software. This significantly reduces service interruption time and improves system response speed and self-healing capabilities.

[0040] This invention clarifies that the MCU chip serves as the control core, connecting not only to the PHY chip but also directly to the SFP optical module. This enables the MCU chip to acquire complete status information of the entire system (optical port, local electrical port, and remote electrical port), providing a data foundation for subsequent refined control strategies. Attached Figure Description

[0041] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute a limitation thereof.

[0042] Figure 1 This is a schematic diagram of the MCU chip structure of the present invention;

[0043] Figure 2 This is a schematic diagram of the structure of the PHY chip of the present invention;

[0044] Figure 3 This is a schematic diagram of the SFP optical module of the present invention;

[0045] Figure 4 This is a schematic diagram of the overall process of the method of the present invention. Detailed Implementation

[0046] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0047] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0048] Furthermore, in the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more, unless explicitly defined otherwise.

[0050] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0051] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0052] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0053] like Figures 1 to 3 As shown, a gigabit optical transceiver with link interlock protection includes an MCU chip, a PHY chip, an electrical port module, an optical port module, a power supply module, and auxiliary circuitry. The optical port module is an SFP optical module, and the electrical port module is an RJ45 interface. The MCU chip communicates with the PHY chip and is also connected to the SFP optical module. The PHY chip is responsible for the conversion and transmission of Ethernet physical layer signals. The SFP optical module is responsible for converting electrical signals into optical signals for long-distance transmission and simultaneously receiving optical signals and converting them back into electrical signals. The RJ45 interface is connected to the PHY chip via an MDI / MDIX adaptive circuit. The auxiliary circuitry includes a DC-DC converter, LED indicators, and a crystal oscillator circuit that provides the clock signal required by the system. The power supply module provides various voltages required by each module via the DC-DC converter. The LED indicators are connected to and controlled by the MCU chip. The MCU monitors the status of the SFP optical module, the RJ45 interface, and the remote electrical port, and adjusts the connection / disconnection of the SFP optical module and the RJ45 interface accordingly.

[0054] The power supply module, DC-DC converter, crystal oscillator circuit, and other auxiliary circuits in the above structure ensure that each chip and module can obtain stable and clean power and clock signals, which is the fundamental guarantee for the long-term stable operation of the equipment.

[0055] The MCU chip communicates with the PHY chip via the MDC / MDIO interface to complete SGMII mode configuration and link status polling. The MCU chip also has a reset circuit: hardware reset of the PHY chip is achieved through the NRST pin; the MCU chip also has a clock system: employing a 25MHz / 125MHz dual crystal oscillator design to meet different speed requirements; the MCU chip also has a debug interface: integrating SWDIO / SWCLK debug pins to support online program updates.

[0056] The optical port module adopts an SFP hot-swappable cage structure and supports LC interface optical modules. It mainly includes: SFP interface circuit: optical signal transmission and reception are realized through TD+ / TD- and RD+ / RD- differential lines; status detection: integrated status detection pins such as TX_Fault, RX_LOS, and MOD_ABS; interlock control: the MCU chip directly controls TX_Disable to turn off the optical port through GPIO pins.

[0057] The power module of the optoelectronic transceiver of this invention adopts a multi-stage step-down design, mainly including a DC-DC converter: four DC-DC converters U6 / U8 / U9 / U10 to realize the conversion from 24V to 5V / 3.3V / 1.8V / 1.0V; a filtering circuit: using a combination of 10μF / 100nF / 22μF capacitors to realize power filtering; and a protection circuit: integrating TVS diodes to realize power surge protection.

[0058] The PHY chip is a domestically produced chip that supports the 1000Base-T standard. It also features SDS_RXP, SDS_RXN, SDS_TXP, and SDS_TXN pins, which enable high-speed SERDES signal transmission between the PHY chip and the SFP optical module. Furthermore, the PHY chip has LED0, LED1, and LED2 pins. The MCU chip controls the status of the LED indicators on the SFP optical module and the RJ45 interface based on the states of these three pins.

[0059] The SFP optical module has SDA / SCL pins, through which the PHY chip adjusts the signal of the SFP optical module. The SFP optical module also has TXFault and RX_LOS pins, through which the MCU chip reads the status of the SFP optical module or controls the SFP optical module.

[0060] The MCU chip is equipped with a GPIO interface, which controls the LED indicator light; heat sinks are also provided on the PHY chip and the MCU chip.

[0061] like Figure 4 As shown, a control method for a gigabit optical transceiver with link interlock protection function is provided. This method uses any of the optical transceivers described above and includes an initialization phase, a main loop phase, and a fault handling phase. The specific steps are as follows:

[0062] S1, Initialization Phase

[0063] After the system is powered on, it performs hardware reset sequentially, including PHY chip initialization, USART serial port initialization, MDC / MDIO initialization, and GPIO status control initialization.

[0064] Determine if the communication between the PHY chip and the MCU chip is normal. If the communication is abnormal, stop the machine and report an error. If the communication is normal, configure the PHY chip in SGMII mode, initialize the link state structure, and read the initial state.

[0065] S2, Main Loop Phase

[0066] The main loop executes every 100ms and mainly includes:

[0067] S21, State Polling

[0068] A complete status check is performed every 2 seconds. By reading the corresponding registers of the PHY chip, the status of the local optical port, the remote electrical port, the local electrical port, and the optical signal loss status are obtained.

[0069] S22, Interlock Control

[0070] When an optical port fault is detected: the MCU chip immediately sets the TX_Disable pin high to shut down the SFP optical module, and controls the electrical port and PHY chip to enter Power Down mode through the GPIO pin, while turning off the LED0 / LED1 indicator lights and recording the fault log.

[0071] When the optical port is restored: the MCU chip clears the TX_Disable signal, wakes up the electrical port and PHY chip, reinitializes the link parameters, lights up the LED indicator and starts flashing;

[0072] The LED indicator has three components: a green LED that is constantly lit when the power supply is normal, a yellow LED that flashes when the link is active, and a red LED that is constantly lit in full-duplex mode and turns off in half-duplex mode. The LED0 pin of the PHY chip controls the green LED, the LED1 pin controls the yellow LED, and the LED2 pin controls the red LED.

[0073] S3, Fault Handling Phase

[0074] Differentiated processing is performed for different fault scenarios:

[0075] A. Optical port failure: Immediately shut down the electrical port to prevent data packet loss, and start a 100ms polling detection and recovery. If recovery is not achieved within 5 seconds, enter safe mode.

[0076] B. Electrical port failure: Keep the optical port working normally, attempt automatic negotiation recovery, and record the electrical port bit error rate on the PHY chip;

[0077] C. Power failure: When the VCC5 pin of the MCU chip is detected to be powered down, the critical state is saved to the backup register, an ordered shutdown sequence is executed, and a reset is triggered by the watchdog timer.

[0078] The above control method balances real-time performance with system overhead: it clearly defines the "100ms" main loop cycle and the "2-second" complete status detection cycle, which ensures timely fault response and avoids excessive processing resources being consumed by the MCU chip due to excessively frequent queries.

[0079] The above control method also enables differentiated and refined fault handling:

[0080] Optical port failure: Take the most stringent isolation measures (shut down the power port) and set up polling recovery and safe mode to prevent the system from oscillating in a repeated flapping state.

[0081] Electrical port failure: Adopt a relatively mild strategy (keep the optical port and try to negotiate), because electrical port failures usually have a small impact and are easy to recover automatically, which reflects the intelligence of the strategy.

[0082] Power failure: An orderly shutdown process is designed, and the watchdog timer ensures the system's recoverability, reflecting a high-reliability design philosophy and preventing data corruption or device "bricking".

[0083] The control method described above also provides clear status indications: the explicit definition of the three-color LED function makes the device status (power, link, activity, duplex mode) clear at a glance, which greatly facilitates on-site operation and maintenance.

[0084] In step S22, when the state of the optical port changes, the state of the remote electrical port must be set to UNKNOWN. In step S22, when the state of the optical port remains UP, the state of the remote electrical port needs to be judged. When the remote electrical port changes from UP to DOWN, the electrical port needs to be closed immediately. When the remote electrical port changes from UP to UP, the electrical port needs to be opened immediately. When the remote electrical port is in other states, the electrical port state remains unchanged.

[0085] The optoelectronic transceiver of this invention features link interlock protection, enabling millisecond-level fault response and ensuring synchronous shutdown of both ports. It also employs an FR-4 (TG170) substrate and heat sink design, supporting a wide operating temperature range of -55℃ to +85℃. Furthermore, the entire optoelectronic transceiver is made with 100% domestically produced components, ensuring supply chain security. The optoelectronic transceiver of this invention also complies with IEC61000-4-2 / 4-5 standards and has passed the ESD 8kV test.

[0086] The control method of this invention uses a three-state joint judgment: it makes decisions by comprehensively considering the states of the local optical port, the local electrical port, and the remote electrical port, and automatically manages the power consumption of the electrical port according to the link status. The MCU chip of this invention not only senses the local state but also effectively senses the state of the remote device, ensuring the integrity of the state perception. In this invention, remote sensing is achieved by reading the internal status register of the PHY chip, which reflects the electrical port connection status of the peer network device. This invention also has a fault isolation mechanism: it appropriately handles the remote state when the optical port is abnormal, avoiding misjudgments. In summary, the method of this invention ensures accurate perception and intelligent control of the network link status, improving the reliability and energy efficiency of the system.

[0087] This invention's gigabit optoelectronic transceiver achieves high-speed, reliable optoelectronic signal conversion through precise hardware design and intelligent control methods, making it particularly suitable for scenarios with stringent reliability requirements, such as ship communication and industrial control. Its MTBF (Mean Time Between Failures) of ≥20,000 hours meets military-grade standards, providing reliable protection for critical network infrastructure.

[0088] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A gigabit optical transceiver with link interlock protection function, characterized in that: The system includes an MCU chip, a PHY chip, an electrical port module, an optical port module, a power supply module, and auxiliary circuitry. The optical port module is an SFP optical module, and the electrical port module is an RJ45 interface. The MCU chip communicates with the PHY chip and is also connected to the SFP optical module. The PHY chip is responsible for the conversion and transmission of Ethernet physical layer signals. The SFP optical module is responsible for converting electrical signals into optical signals for long-distance transmission and simultaneously receiving optical signals and converting them back into electrical signals. The RJ45 interface is connected to the PHY chip via an MDI / MDIX adaptive circuit. The auxiliary circuitry includes a DC-DC converter, LED indicators, and a crystal oscillator circuit that provides the clock signal required by the system. The power supply module provides various voltages required by each module via the DC-DC converter. The LED indicators are connected to and controlled by the MCU chip. The MCU monitors the status of the SFP optical module, the RJ45 interface, and the remote electrical port, and adjusts the on / off state of the SFP optical module and the RJ45 interface accordingly.

2. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The MCU chip is connected to the SGMII pin of the PHY chip via the MDC / MDIO pin, enabling the MCU chip to read and configure the PHY chip.

3. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The PHY chip also has LED0 pin, LED1 pin, and LED2 pin. The MCU chip controls the status of the LED indicator lights of the SFP optical module and the RJ45 interface according to the status of the three signals of LED0 pin, LED1 pin, and LED2 pin.

4. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The PHY chip also has SDS_RXP, SDS_RXN, SDS_TXP, and SDS_TXN pins. The PHY chip uses these pins to achieve high-speed SERDS signal transmission with the SFP optical module.

5. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The SFP optical module has SDA / SCL pins, and the PHY chip adjusts the signal of the SFP optical module through the SDA / SCL pins.

6. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The SFP optical module also has a TXFault pin and an RX_LOS pin. The MCU chip reads the status of the SFP optical module or controls the SFP optical module through the above pins.

7. A gigabit optical transceiver with link interlock protection function according to claim 1, characterized in that: The MCU chip is equipped with a GPIO interface, which controls the LED indicator light; heat sinks are also provided on the PHY chip and the MCU chip.

8. A control method for a gigabit optical transceiver with link interlock protection function, characterized in that, The optoelectronic transceiver described in any one of claims 1 to 7 includes an initialization phase, a main loop phase, and a fault handling phase. The specific method steps are as follows: S1, Initialization Phase After the system is powered on, it performs hardware reset sequentially, including PHY chip initialization, USART serial port initialization, MDC / MDIO initialization, and GPIO status control initialization. Determine if the communication between the PHY chip and the MCU chip is normal. If the communication is abnormal, stop the machine and report an error. If the communication is normal, configure the PHY chip in SGMII mode, initialize the link state structure, and read the initial state. S2, Main Loop Phase The main loop executes every 100ms and mainly includes: S21, State Polling A complete status check is performed every 2 seconds. By reading the corresponding registers of the PHY chip, the status of the local optical port, the remote electrical port, the local electrical port, and the optical signal loss status are obtained. S22, Interlock Control When an optical port fault is detected: the MCU chip immediately sets the TX_Disable pin high to shut down the SFP optical module, and controls the electrical port and PHY chip to enter Power Down mode through the GPIO pin, while turning off the LED0 / LED1 indicator lights and recording the fault log. When the optical port is restored: the MCU chip clears the TX_Disable signal, wakes up the electrical port and PHY chip, reinitializes the link parameters, lights up the LED indicator and starts flashing; The LED indicator has three components: a green LED that is constantly lit when the power supply is normal, a yellow LED that flashes when the link is active, and a red LED that is constantly lit in full-duplex mode and turns off in half-duplex mode. The LED0 pin of the PHY chip controls the green LED, the LED1 pin controls the yellow LED, and the LED2 pin controls the red LED. S3, Fault Handling Phase Differentiated processing is performed for different fault scenarios: A. Optical port failure: Immediately shut down the electrical port to prevent data packet loss, and start a 100ms polling detection and recovery. If recovery is not achieved within 5 seconds, enter safe mode. B. Electrical port failure: Keep the optical port working normally, attempt automatic negotiation recovery, and record the electrical port bit error rate on the PHY chip; C. Power failure: When the VCC5 pin of the MCU chip is detected to be powered down, the critical state is saved to the backup register, an ordered shutdown sequence is executed, and a reset is triggered by the watchdog timer.

9. The control method for a gigabit optical transceiver with link interlock protection function according to claim 8, characterized in that, In step S22, when the state of the optical port changes, the state of the remote electrical port must be set to UNKNOWN. In step S22, when the state of the optical port remains UP, the state of the remote electrical port needs to be judged. When the remote electrical port changes from UP to DOWN, the electrical port needs to be shut down immediately. When the remote electrical port changes from UP to UP, the electrical port needs to be turned on immediately; when the remote electrical port is in other states, the electrical port state remains unchanged.

10. The control method for a gigabit optical transceiver with link interlock protection function according to claim 8, characterized in that, In step S1, the MCU chip resets the PHY chip through the NRST pin, and the MCU chip also initializes the clock configuration.

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