Instruction transmission method and device

Abstract

The embodiment of the invention discloses an instruction transmission method and device, and the main technical scheme comprises the steps: obtaining a first instruction sent by a first device based on a first protocol, the first instruction comprising a first address and a first verification value corresponding to the first address; the first instruction is converted into a second instruction, the second instruction is obtained based on a second protocol, and the second instruction comprises a second address and a first verification value; generating a second verification value based on the second address, and updating the first verification value included in the second instruction into the second verification value; and transmitting the updated second instruction to the second equipment. According to the method provided by the invention, the check value can be updated, so that the subsequent downstream equipment can check the second address based on the second check value, the validity of the check value is ensured, and the security of an instruction transmission process is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication between devices, and in particular to a command transmission method and device. BACKGROUND

[0002] With the increasing intelligence of automobiles, the complexity of electronic systems of automobiles also increases rapidly, and the electronic systems often include multiple devices, and different devices can use different protocols for data transmission. If two devices using different protocols communicate, the command sent by the sending device needs to be processed by the protocol conversion module before it can successfully reach the corresponding receiving device.

[0003] Safety problems caused by electronic failures are also increasingly concerned, and it is particularly important to safely implement communication between devices. The prior art can add a check value to the address of the command, and the receiving device needs to check the check value included in the address in the request, but the protocol conversion module usually only has the function of address conversion and cannot process the check value included in the address, resulting in errors in the check value transmitted to the receiving device, and the safety of command transmission needs to be improved. SUMMARY

[0004] The present application provides a command transmission method and device to improve the safety of command transmission.

[0005] The present application provides the following solutions: According to a first aspect, a command transmission method is provided, applied to a network controller, the method comprising: obtaining a first command sent by a first device based on a first protocol, the first command including a first address and a corresponding first check value; converting the first command into a second command, the second command being obtained based on a second protocol, the second command including a second address and the first check value; generating a second check value based on the second address, and updating the first check value included in the second command to the second check value; transmitting the updated second command to a second device.

[0006] According to an implementable manner in an embodiment of the present application, if the first protocol is AXI protocol and the second protocol is AHB protocol, the second address includes multiple sub-addresses, and the generating of the second check value based on the second address comprises: generating the second check value corresponding to each of the multiple sub-addresses based on the multiple sub-addresses.

[0007] According to an implementable manner in an embodiment of the present application, before converting the first command into the second command, the method further comprises: obtaining a calculation check value based on the first address and a preset parity check mode, the parity check mode being one of an odd parity check mode and an even parity check mode; comparing the calculation check value with the first check value; if the calculation check value is consistent with the first check value, continuing to perform the step of converting the first instruction into a second instruction, otherwise, reporting first interrupt information.

[0008] According to an implementable manner in the embodiments of the present application, the conversion of the first instruction into a second instruction comprises: inputting the first instruction into a first protocol conversion path to obtain a second instruction output by the first protocol conversion path, and inputting the first instruction into a second protocol conversion path to obtain a second instruction output by the second protocol conversion path, the first protocol conversion path and the second protocol conversion path being two paths with same logical functions but different physical lines; performing a check on the second instruction output by the first protocol conversion path and the second instruction output by the second protocol conversion path, if the check is passed, taking the second instruction output by the first protocol conversion path as the converted second instruction, otherwise, reporting second interrupt information.

[0009] According to an implementable manner in the embodiments of the present application, the conversion of the first instruction into a second instruction comprises: inputting the first instruction into a first protocol conversion path at a first time to obtain a second instruction output by the first protocol conversion path, and inputting the first instruction into a second protocol conversion path at a second time to obtain a second instruction output by the second protocol conversion path, wherein the first time and the second time are different by a preset clock period; the check on the second instruction output by the first protocol conversion path and the second instruction output by the second protocol conversion path comprises: based on the preset clock period, compensating a pulse signal corresponding to the second instruction output by the first protocol conversion path to obtain a compensated pulse signal corresponding to the second instruction, comparing the compensated pulse signal corresponding to the second instruction with a pulse signal corresponding to the second instruction output by the second protocol conversion path, and if the compensated pulse signal corresponding to the second instruction is consistent with the pulse signal corresponding to the second instruction output by the second protocol conversion path, the check is passed.

[0010] According to an implementable manner in embodiments of the present application, the second instruction includes a plurality of type fields. The comparison of the compensated second instruction corresponding pulse signal and the second protocol conversion path output second instruction corresponding pulse signal includes: The plurality of type fields are respectively taken as current type fields to perform the following steps to obtain comparison results of the type fields: based on the compensated second instruction current type field corresponding pulse signal and the second protocol conversion path output second instruction current type field corresponding pulse signal, a current type field comparison result is obtained; The comparison results of the type fields are logically processed to obtain a target comparison result; Based on the target comparison result, it is determined whether the compensated second instruction corresponding pulse signal and the second protocol conversion path output second instruction corresponding pulse signal are consistent.

[0011] According to a second aspect, an instruction transmission device is provided, which is arranged in a network controller, and the device includes: An acquisition unit is configured to acquire a first instruction issued by a first device based on a first protocol, the first instruction including a first address and a corresponding first check value; A conversion unit is configured to convert the first instruction into a second instruction, the second instruction being obtained based on a second protocol, the second instruction including a second address and the first check value, the second address being obtained based on the first address; A generation unit is configured to generate a second check value based on the second address, and update the first check value included in the second instruction to the second check value; A transmission unit is configured to transmit the updated second instruction to a second device.

[0012] According to a third aspect, a computer readable storage medium is provided, which stores a computer program, the program being executed by a processor to implement the steps of the method of any one of the first aspect.

[0013] According to a fourth aspect, an electronic device is provided, which includes: One or more processors; and A memory associated with the one or more processors, the memory being configured to store program instructions, the program instructions being executed by the one or more processors to perform the steps of the method of any one of the first aspect.

[0014] According to a fifth aspect, a computer program product is provided, which includes a computer program, the computer program being executed by a processor to implement the steps of the method of any one of the first aspect.

[0015] According to the specific embodiments provided in the present application, the present application discloses the following technical effects: 1) The present application can convert the first instruction issued by the first device based on the first protocol into a second instruction, and update the first check value corresponding to the first address included in the first instruction to the second check value corresponding to the second address included in the second instruction. That is, when the protocol conversion is performed, since the address in the instruction is changed, the check value may be incorrect, and the method of the present application can update the check value, so that the subsequent downstream device can verify the second address based on the second check value, thereby ensuring the effectiveness of the check value and improving the safety of the instruction transmission process.

[0016] 2) When converting the first instruction into the second instruction, the first address can be split into multiple sub-addresses (i.e., the second address includes multiple sub-addresses), and the present application can generate a second check value corresponding to each sub-address, so as to facilitate subsequent verification of each sub-address, thereby improving the correctness of the conversion process and the safety of the instruction transmission.

[0017] 3) Before converting the first instruction into the second instruction, the first address is verified to ensure the correctness of the first address during the process from being issued by the first device to before conversion, thereby improving the safety of the transmission.

[0018] 4) The present application inputs the first instruction into the first protocol conversion path and the second protocol conversion path respectively, obtains the second instruction output by the two protocol conversion paths respectively, and verifies the second instruction output by the two protocol conversion paths respectively. This method can exclude errors in the transmission and processing process of the signal itself, thereby ensuring the correctness and reliability of the protocol conversion process.

[0019] 5) The moment when the first instruction is input into the first protocol conversion path and the second protocol conversion path has a difference in the preset clock period, which can more effectively exclude the influence of noise and other factors on the signal transmission, thereby ensuring the correctness of the protocol conversion process.

[0020] 6) The comparison result of each type field is determined, and the comparison results of the type fields are logically processed to obtain a target comparison result. In this way, the comparison process is refined, the target comparison result can be obtained more quickly, and it is more convenient to subsequently analyze the error of the second instruction that does not pass the verification, thereby improving the safety of the entire conversion process.

[0021] Of course, any product implementing the present application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below only illustrate some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0023] Figure 1 The flow chart of the instruction transmission method provided by the embodiments of the present application.

[0024] Figure 2 The principle block diagram of the comparison method provided by the embodiments of the present application.

[0025] Figure 3 The design block diagram of a network controller or a protocol conversion module provided by the embodiments of the present application.

[0026] Figure 4 The overall flow chart of the instruction transmission process provided by the embodiments of the present application.

[0027] Figure 5 The schematic block diagram of the instruction transmission device provided by the embodiments of the present application.

[0028] Figure 6 The schematic block diagram of the electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0031] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0032] Depending on the context, the word "if" as used herein can be interpreted to mean "when" or "while" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be interpreted to mean "when it is determined" or "in response to determining" or "when [a stated condition or event] is detected" or "in response to detecting [a stated condition or event]."

[0033] The scenario corresponding to the present application can be a communication scenario among a plurality of devices included in an electronic system of an automobile. The instruction transmission method of the present application is applied to a network controller, wherein the network controller is used for transmission of data flow and control of protocol, and more specifically, the instruction transmission method of the present application is actually executed by a protocol conversion module included in the network controller, for example, when converting a first instruction based on an AXI protocol into a second instruction based on an AHB protocol, the protocol conversion module can be an XHB module, that is, the instruction transmission method of the present application is applied to the XHB module.

[0034] Currently, there are some instruction transmission technologies. In the electronic system of an automobile, the buses (i.e. the protocols mentioned later, which can be understood as the transmission rules of data) used by different devices can be different. If communication is needed between two devices using different protocols, a protocol conversion module in the network controller can be used to convert the data first and then continue to transmit. Specifically, the protocol conversion module is used to convert a first instruction to obtain a second instruction. However, such conversion can only convert a first address included in the first instruction into a second address, and does not update a first check value corresponding to the first address, so that the first check value cannot be used to check the second address later.

[0035] In view of this, the present application provides a new idea. Figure 1 The instruction transmission method flowchart provided for the embodiments of the present application can be executed by the network controller or the protocol conversion module mentioned above. As shown in Figure 1 The method can include the following steps: Step 101, obtaining a first instruction issued by a first device based on a first protocol, the first instruction including a first address and a corresponding first check value.

[0036] Step 102, converting the first instruction into a second instruction, the second instruction being obtained based on a second protocol, the second instruction including a second address and the first check value.

[0037] Step 103, generating a second check value based on the second address, and updating the first check value included in the second instruction to the second check value.

[0038] Step 104, transmitting the updated second instruction to a second device.

[0039] As can be seen from the above process, this application can convert a first instruction issued by a first device based on a first protocol into a second instruction, and update the first checksum corresponding to the first address included in the first instruction to the second checksum corresponding to the second address included in the second instruction. In other words, during protocol conversion, the checksum may be incorrect due to changes in the address within the instruction. The method of this application can update the checksum so that downstream devices can subsequently verify the second address based on the second checksum, ensuring the validity of the checksum and improving the security of the instruction transmission process.

[0040] The following describes in detail each step of the above process and the effects that can be further produced, with reference to the embodiments. It should be noted that the terms "first" and "second" involved in this disclosure do not have limitations in terms of size, order, or quantity, but are only used to distinguish them in name. For example, "first device" and "second device" are used to distinguish two devices, and "first protocol" and "second protocol" are used to distinguish two protocols.

[0041] First, the above step 101, namely "obtaining the first instruction issued by the first device based on the first protocol", will be described in detail with reference to the embodiments.

[0042] In this embodiment, a first instruction issued by the first device based on a first protocol is first obtained. Typically, the first instruction includes a read / write field (used to determine whether the first instruction is a read instruction or a write instruction), a starting address field (used to indicate the starting address of the read or write instruction), and an address length field (used to indicate the address length corresponding to the read or write instruction), etc. In this application, the first instruction includes a first address and its corresponding first check value. Here, the first address is the information corresponding to the starting address field, and the first check value is essentially used to verify whether the information corresponding to the starting address field is correct.

[0043] The first check value corresponding to the first address can be determined by the first device. As one possible approach, when the check method of this application is a sum check, the steps to determine the first check value are: add all the values ​​in the first address (or perform other mathematical operations) to obtain a value of fixed length, which is used as the first check value. For example, if the first address is 1001, the first check value can be 1+0+0+1=2.

[0044] As another possible approach, when the verification method of this application is hash verification, the steps to determine the first verification value are as follows: using a hash function (such as MD5, SHA-1, SHA-256, etc.) to calculate the first address and generate a hash value of fixed length as the first verification value.

[0045] As another feasible approach, when the verification method of this application is parity check, the steps for determining the first check value are as follows: If it is odd parity mode, add the first check value to the first address. By adjusting the first check value, ensure that the number of "1"s in the first address after adding the first check value is odd. For example, if the first address is 1001, the first address after adding the first check value is 10011 (the number of "1"s is 3) if it is even parity mode. If it is even parity mode, add the first check value to the first address. By adjusting the first check value, ensure that the number of "1"s in the first address after adding the first check value is even. For example, if the first address is 1001, the first address after adding the first check value is 10010 (the number of "1"s is 2).

[0046] The following describes step 102, namely "converting the first instruction into the second instruction", in detail with reference to the embodiments.

[0047] In practical command transmission scenarios, cross-protocol transmission refers to the scenario that occurs when data is transmitted between different network protocol layers or protocol types. In this case, if the command is to be transmitted correctly, the first command needs to be converted into a second command. The second command is based on the first command and the second protocol, and includes a second address and a first checksum.

[0048] For example, the first protocol supports long burst transmission, while the second protocol only supports short burst transmission. When converting the first instruction to the second instruction, the first instruction under long burst transmission needs to be split into multiple second instructions under short burst transmission. After splitting, the first address is mapped to multiple sub-addresses.

[0049] Specifically, if the first protocol is the AXI protocol and the second protocol is the AHB protocol, after the first instruction is converted into the second instruction, the second address in the second instruction includes multiple sub-addresses.

[0050] Among them, AXI (Advanced eXtensible Interface) is a high-performance bus protocol in the AMBA 3.0 standard proposed by ARM. It adopts a multi-channel independent design (5 independent channels: write address, read address, write data, read data, and write response), supports high-bandwidth, low-latency point-to-point interconnection, supports long burst transmission, and can continuously transmit multiple data. It is mostly used in high-end processors and multi-core systems. AHB (Advanced High-performance Bus) is a high-performance bus protocol in the AMBA 2.0 standard proposed by ARM. It adopts a single-channel design and supports short burst transmission, that is, a single transmission, with only one data transmitted per cycle. It is mostly used in early MCUs and simple SoC chips.

[0051] For example, a first device issues a first instruction based on the AXI protocol. The first instruction has a starting address of 0x1000, a burst type of INCR (incrementing address), a burst length of 4 (transmitting 4 data items), an instruction type of write instruction, and write data D0-D3. The first checksum is P0. Using an XHB module (a protocol conversion module, a bridge module for converting between AXI and AHB protocols (such as XHB-400)), the first instruction is converted into a second instruction, specifically into a second instruction consisting of 4 single bursts. Specifically, the first single burst has a starting address of 0x1000, an instruction type of write instruction, and write data D0; the second single burst has a starting address of 0x1004, an instruction type of write instruction, and write data D1; the third single burst has a starting address of 0x1008, an instruction type of write instruction, and write data D2; and the fourth single burst has a starting address of 0x100C, an instruction type of write instruction, and write data D3. The starting address of each single burst corresponds to a sub-address in the second instruction.

[0052] Another instruction transmission scenario exists: unaligned transmission. Unaligned transmission refers to data whose storage address does not meet its natural alignment requirements, necessitating splitting or special handling during transmission or access. For example, if 4 bytes of data are stored at address 0x1003 (not a multiple of 4), this is called "unaligned storage." When the network controller attempts to transmit this data, due to the unaligned address, it can read it in two steps: first, read the data corresponding to 0x1003-0x1004, then read the data including 0x1005-0x1006, and then merge and transmit them. If the data is stored at address 0x1004 (a multiple of 4), the network controller can directly read the data corresponding to 0x1004-0x1007.

[0053] In this scenario, although the protocol remains unchanged, the first instruction still needs to be converted into the second instruction, that is, the first address needs to be converted into the second address. At this time, the address in the instruction changes, and the checksum also needs to be updated simultaneously. Therefore, the instruction transmission method provided in this application can also be used in unaligned transmission. After converting the first instruction into the second instruction, a second checksum corresponding to the second address is generated based on the second address included in the second instruction.

[0054] It should be noted that, in order to further ensure the correctness of the first address in the first instruction, this application may verify the first address before conversion. Specifically, the first address included in the first instruction is verified based on the first check value included in the first instruction.

[0055] If this application uses parity checking, a calculated check value can be obtained based on the first address included in the first instruction and a preset parity checking mode. The parity checking mode can be either odd parity or even parity. For example, if the parity checking mode is odd parity, the first address is 1001, and the first check value is 1. The calculated check value of the first address in odd parity mode is 1. The step of determining the calculated check value is the same as the step of determining the first check value in step 101, and will not be repeated here. Then, the calculated check value and the first check value are compared. If the calculated check value and the first check value are consistent, the step of converting the first instruction into the second instruction continues; otherwise, the first interrupt information is reported.

[0056] It should be noted that, in this application, as one possible approach, if the calculated checksum matches the first checksum, the step of converting the first instruction into the second instruction continues; if the calculated checksum does not match the first checksum, the step of converting the first instruction into the second instruction stops, and a first interruption message is reported. Here, the first interruption message indicates that there is an error in the transmitted first checksum, requiring the electronic system to control the first device to resend the first instruction, i.e., to clear the interruption and resend the data.

[0057] As another possible approach, regardless of whether the calculated checksum and the first checksum match, the step of converting the first instruction into the second instruction is executed. However, if the calculated checksum and the first checksum do not match, a first interruption message can be reported. In this case, the first interruption message facilitates the subsequent analysis of the cause and location of the transmission error by the electronic system, or facilitates the electronic system to issue a notification on whether to stop continuing data transmission based on the first interruption message.

[0058] It should also be noted that the above method is only one possible implementation. In practical applications, the first protocol can also refer to the AHB protocol, and the second protocol can refer to the AXI protocol. Of course, the first and second protocols can also refer to other protocols. As long as the address changes during the conversion instruction process, but the checksum is not updated, the method of this application can be used to generate a new checksum to meet the checksum requirements of downstream devices.

[0059] Furthermore, this application provides a dual-path redundancy design to improve the reliability of bus communication. Specifically, in the XHB module, the same instruction (such as a write instruction or a read instruction) is transmitted through two independent physical paths: one is the main path (i.e., the first protocol conversion path involved later), and the other is the redundant path (i.e., the second protocol conversion path involved later). Finally, the outputs of the two are compared to detect whether there is a transmission error.

[0060] Specifically, the first instruction is input into the first protocol conversion path to obtain the second instruction output by the first protocol conversion path, and the first instruction is input into the second protocol conversion path to obtain the second instruction output by the second protocol conversion path. The first protocol conversion path and the second protocol conversion path are two paths with the same logical function but different physical circuits (such as different wires or different circuit modules).

[0061] The second instruction output from the first protocol conversion path and the second instruction output from the second protocol conversion path are used for verification. As one possible approach, if the verification passes, the second instruction output from the first protocol conversion path is used as the converted second instruction; if the verification fails, data transmission is stopped, and a second interruption message is reported. This second interruption message indicates an error occurred during the conversion process, requiring the first instruction to be re-converted.

[0062] As another possible approach, regardless of whether the verification passes or fails, the second instruction output by the first protocol conversion path is used as the converted second instruction. However, if the verification fails, a second interruption message can be reported. This second interruption message facilitates subsequent analysis of the cause and location of the transmission error by the electronic system, or allows the electronic system to issue a notification to stop further data transmission based on the second interruption message.

[0063] Furthermore, to eliminate interference from noise and other factors, this application inputs the first instruction into the first protocol conversion path at different times than it inputs into the second conversion path. Specifically, the first instruction is input into the first protocol conversion path at a first time to obtain the second instruction output by the first protocol conversion path, and the first instruction is input into the second protocol conversion path at a second time to obtain the second instruction output by the second protocol conversion path. The first time and the second time differ by a preset clock cycle; for example, the first instruction is input into the second protocol conversion path with a delay of two clock cycles.

[0064] Then, based on a preset clock cycle, the pulse signal corresponding to the second instruction output by the first protocol conversion path is compensated to obtain the compensated pulse signal corresponding to the second instruction. For example, if the first instruction is input into the second protocol conversion path after a two-clock-cycle delay, the pulse signal corresponding to the second instruction output by the second protocol conversion path will also have a two-clock-cycle delay. In this case, the pulse signal corresponding to the second instruction output by the first protocol conversion path can be delayed by two clock cycles to ensure that the second instructions output by the two protocol conversion paths can be compared in the future.

[0065] Then, the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction output by the second protocol conversion path are compared. If the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction output by the second protocol conversion path are the same, the verification passes.

[0066] In the above comparison process, this application can directly compare the second instruction output by the first protocol conversion path and the second instruction output by the second protocol conversion path, that is, compare the second instruction in binary form. As a preferred implementation, this application compares the differences between the pulse signals corresponding to the two output second instructions. This is because pulse signals can more accurately reflect the real-time state of the circuit. In dynamic transmission, signals may experience momentary errors due to noise, delay, or hardware failure. By comparing the instantaneous values ​​of the pulse signals, these errors can be detected in a timely manner.

[0067] Next, to further facilitate the electronic system in determining the location of the error, the pulse signals corresponding to the multiple type fields included in the second instruction can be compared separately. Specifically, the type field refers to the read / write field, starting address field, address length field, and write data field included in the instruction. During instruction transmission, each type field is transmitted by a signal line in the protocol conversion path. This application can compare the pulse signal corresponding to each type field (i.e., the pulse signal output by each signal line) separately. That is, multiple type fields are used as the current type field to perform the following steps to obtain the comparison result of each type field: Based on the pulse signal corresponding to the current type field in the compensated second instruction (i.e., the pulse signal output by the signal line corresponding to the current type field in the compensated second instruction) and the pulse signal corresponding to the current type field in the second instruction output by the second protocol conversion path (i.e., the pulse signal output by the signal line corresponding to the current type field in the second instruction output by the second protocol conversion path), the comparison result of the current type field is obtained. For example, the comparison result can be represented by "0" or "1". "0" means that the pulse signal corresponding to the current type field in the compensated second instruction is the same as the pulse signal corresponding to the current type field in the second instruction output by the second protocol conversion path, and "1" means that the pulse signal corresponding to the current type field in the compensated second instruction is not the same as the pulse signal corresponding to the current type field in the second instruction output by the second protocol conversion path.

[0068] The comparison results of each type of field are processed by OR logic to obtain the target comparison result. Continuing with the previous example, if the comparison result of the read / write field is "0", the comparison result of the starting address field is "1", the comparison result of the address length field is "0", and the comparison result of the write data field is "0", the OR logic is performed and the target comparison result is "1", that is, the pulse signal corresponding to the compensated second instruction is inconsistent with the pulse signal corresponding to the second instruction output by the second protocol conversion path.

[0069] In simple terms, if a "1" appears in the comparison results of any of the fields, the target comparison result is also "1". The pulse signal corresponding to the compensated second instruction will not match the pulse signal corresponding to the second instruction output by the second protocol conversion path, and the verification will fail. Only when the comparison results of all fields are "0" will the pulse signal corresponding to the compensated second instruction match the pulse signal corresponding to the second instruction output by the second protocol conversion path, and the verification will pass.

[0070] This application provides a principle block diagram describing the above comparison method, such as... Figure 2 As shown, a first instruction is input into a first protocol conversion path to obtain a second instruction output by the first protocol conversion path. The first instruction is then delayed by a preset clock period and input into a second protocol conversion path to obtain a second instruction output by the second protocol conversion path. The pulse signal corresponding to the second instruction output by the first protocol conversion path is compensated to obtain a compensated pulse signal corresponding to the second instruction, i.e., the pulse signal corresponding to the second instruction output by the first protocol conversion path is also delayed by a preset clock period. Then, the pulse signal corresponding to the compensated second instruction is compared with the pulse signal corresponding to the second instruction output by the second protocol conversion path. If they match, the second instruction output by the first protocol conversion path is used as the converted second instruction; otherwise, a second interrupt information is reported.

[0071] The following describes in detail step 103, namely "generating a second check value based on the second address and updating the first check value included in the second instruction to the second check value", with reference to the embodiments.

[0072] In the instruction transmission scenario mentioned in step 102, the addresses included in the instructions before and after the conversion change. However, the current network controller or protocol conversion module only transmits the first check value corresponding to the first address without performing verification and processing on it, which makes the first check value transmitted to the second device invalid, and the second device cannot verify the correctness of the second address.

[0073] Therefore, this application provides a method for generating a second check value. Specifically, the second check value is generated based on a second address, and the steps are the same as those for generating the first check value corresponding to the first address, and will not be repeated here.

[0074] If this application uses parity checking, it can generate a second check value corresponding to the second address based on the second address and a preset parity checking mode, where the parity checking mode is consistent with the parity checking mode when generating the first check value, and update the first check value included in the second instruction to the second check value.

[0075] Using the example from step 102, the starting address of the first instruction is 0x1000 (binary representation: 0001 00000000 0000), and the first parity value is P0. In odd parity mode, P0 is 0, and in even parity mode, P0 is 1. Then, the first instruction is converted into the second instruction.

[0076] The second instruction includes a first single burst with a starting address of 0x1000 (binary representation: 00010000 0000 0000), and a second checksum of P1 corresponding to the first single burst. In odd parity mode, P1 is 0, and in even parity mode, P1 is 1. The second instruction includes a second single burst with a starting address of 0x1004 (binary representation: 0001 0000 0000 0100), and a second checksum of P2 corresponding to the second single burst. In odd parity mode, P2 is 1, and in even parity mode, P2 is 0. The second instruction includes a third single burst with a starting address of 0x1008 (binary representation: 0001 0000 0000 1000), and a second checksum of P3 corresponding to the third single burst. In odd parity mode, P3 is 1, and in even parity mode, P3 is 0. The second instruction includes a fourth single burst with a starting address of 0x100C (binary representation: 0001). (0000 0000 1100), the second check value corresponding to the fourth single burst is P4. If it is in odd parity mode, P4 is 0, and if it is in even parity mode, P4 is 1.

[0077] Then, the first check value in the second instruction is updated to the generated second check value. If the second instruction includes multiple single bursts (each single burst corresponds to a sub-address), each updated sub-address should correspond to a second check value.

[0078] The following describes step 104, namely "transmitting the updated second instruction to the second device", in detail with reference to the embodiments.

[0079] In this embodiment, the updated second instruction is transmitted to the second device. This second instruction includes a second address and its corresponding second checksum. The second device can use the second checksum to verify the second address to ensure its correctness and security. If the second address includes multiple sub-addresses, each sub-address can be verified based on its corresponding second checksum. For example, if this application uses parity checking, the second device can determine the calculated checksum corresponding to the second address based on the second address and a preset parity checking pattern. If the calculated checksum of the second address matches the second checksum of the second address, it indicates that the second address was correctly transmitted to the second device. If they do not match, the second device can choose to report an interruption or request the first device to retransmit the data.

[0080] To facilitate a comprehensive description of the method in this application, a design block diagram of a network controller or protocol conversion module is provided, such as... Figure 3 As shown, the network controller or protocol conversion module includes three sub-modules, namely the verification sub-module, the generation sub-module, and the comparison sub-module. The verification sub-module is used to verify the input first instruction, that is, to calculate the verification value based on the first address included in the first instruction and the preset parity check mode. If the calculated verification value is consistent with the first verification value, the step of converting the first instruction into a second instruction continues. In the embodiments of this application, the verification sub-module can be enabled or disabled. When the verification sub-module is disabled, this application will not verify the input first instruction.

[0081] The comparison submodule compares the differences between the second instruction obtained using the first protocol conversion path and the second instruction obtained using the second protocol conversion path to determine whether they are consistent. It should be noted that when inputting the first instruction to the second protocol conversion path, a preset clock period can be delayed. Correspondingly, the preset clock period can be compensated for the second instruction obtained using the first protocol conversion path, resulting in a compensated second instruction. The comparison submodule is actually used to compare the difference between the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction obtained using the second protocol conversion path.

[0082] The generation submodule is used to generate the second check value corresponding to the second address of the second instruction obtained by converting the path using the first protocol.

[0083] This application also provides an overall flowchart of the instruction transmission process, such as... Figure 4 As shown. This application allows the first instruction to be input first. Figure 3In the verification submodule involved, if the calculated checksum corresponding to the first address matches the first checksum corresponding to the first address, the first instruction is then input into the comparison submodule. Otherwise, a first interrupt signal is reported before the first instruction is input into the comparison submodule. The comparison submodule verifies the second instructions output by the first protocol conversion path and the second protocol conversion path, respectively. If the verification passes, the second instruction output by the first protocol conversion path is input into the generation submodule. Otherwise, a second interrupt signal is reported before the second instruction output by the first protocol conversion path is input into the comparison submodule, so that the comparison submodule generates the second checksum corresponding to the second address in the second instruction. In addition, to verify the necessity of the generation submodule, an error mechanism can be injected into the generation submodule when the car is powered on, causing the generation submodule to fail to generate the second checksum correctly. When the second device detects that the second address cannot be verified, it can report a third interrupt message. This method can verify the necessity of the generation submodule. It is because of the existence of the generation submodule that the subsequent device can verify the second address.

[0084] The methods provided in this application can be applied not only to automotive electronic systems, but also to instruction transmission processes between different devices in scenarios such as industrial control, aerospace, robotics, and communication base stations. This application does not limit these applications.

[0085] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0086] According to another embodiment, an instruction transmission device is provided. Figure 5 A schematic block diagram of the instruction transmission apparatus according to one embodiment is shown, the apparatus being disposed on a network controller. Figure 5 As shown, the device 500 includes an acquisition unit 501, a conversion unit 502, a generation unit 503, and a transmission unit 504, and further includes a verification module 505. The main functions of each component are as follows: The acquisition unit 501 is configured to acquire a first instruction issued by the first device based on a first protocol, the first instruction including a first address and its corresponding first check value.

[0087] The conversion unit 502 is configured to convert a first instruction into a second instruction, the second instruction being obtained based on a second protocol, the second instruction including a second address and a first check value, the second address being obtained based on the first address.

[0088] The generation unit 503 is configured to generate a second check value based on a second address, and update the first check value included in the second instruction to the second check value.

[0089] The transmission unit 504 is configured to transmit the updated second instruction to the second device.

[0090] As one possible implementation, if the first protocol is the AXI protocol and the second protocol is the AHB protocol, then the second address includes multiple sub-addresses. When generating the second check value based on the second address, the generating unit 503 can be specifically configured to generate the second check value corresponding to each of the multiple sub-addresses.

[0091] Furthermore, before converting the first instruction into the second instruction, the verification module 505 can be specifically configured to: calculate a verification value based on the first address and a preset parity check mode, wherein the parity check mode is one of odd parity check mode and even parity check mode; compare the calculated verification value with the first verification value; if the calculated verification value and the first verification value are consistent, then continue to execute the step of converting the first instruction into the second instruction; otherwise, report the first interrupt information.

[0092] As one possible embodiment, when the conversion unit 502 converts the first instruction into the second instruction, it can be specifically configured to: input the first instruction into a first protocol conversion path to obtain a second instruction output by the first protocol conversion path, and input the first instruction into a second protocol conversion path to obtain a second instruction output by the second protocol conversion path, wherein the first protocol conversion path and the second protocol conversion path are two paths with the same logical function but different physical lines; verify the second instruction output by the first protocol conversion path and the second instruction output by the second protocol conversion path, and if the verification passes, use the second instruction output by the first protocol conversion path as the converted second instruction; otherwise, report the second interrupt information.

[0093] As one possible embodiment, when the conversion unit 502 inputs a first instruction into a first protocol conversion path to obtain a second instruction output by the first protocol conversion path, and inputs a first instruction into a second protocol conversion path to obtain a second instruction output by the second protocol conversion path, it can be specifically configured to: input the first instruction into the first protocol conversion path at a first moment to obtain a second instruction output by the first protocol conversion path, and input the first instruction into the second protocol conversion path at a second moment to obtain a second instruction output by the second protocol conversion path, wherein the first moment and the second moment differ by a preset clock period.

[0094] When the conversion unit 502 performs verification using the second instruction output from the first protocol conversion path and the second instruction output from the second protocol conversion path, it can be specifically configured to: compensate the pulse signal corresponding to the second instruction output from the first protocol conversion path based on a preset clock period to obtain the compensated pulse signal corresponding to the second instruction; compare the compensated pulse signal corresponding to the second instruction with the pulse signal corresponding to the second instruction output from the second protocol conversion path; if the compensated pulse signal corresponding to the second instruction is consistent with the pulse signal corresponding to the second instruction output from the second protocol conversion path, the verification passes.

[0095] As one possible implementation, the second instruction includes multiple type fields.

[0096] When comparing the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction output by the second protocol conversion path, the conversion unit 502 can be specifically configured to: perform the following steps with multiple type fields as the current type fields to obtain the comparison results of each type field: obtain the comparison result of the current type field based on the pulse signal corresponding to the current type field in the compensated second instruction and the pulse signal corresponding to the current type field in the second instruction output by the second protocol conversion path; perform OR logic processing on the comparison results of each type field to obtain the target comparison result; and determine whether the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction output by the second protocol conversion path are consistent based on the target comparison result.

[0097] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for apparatus or apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the description of the method embodiments. The apparatus or apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0098] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0099] In addition, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method described in any of the foregoing method embodiments.

[0100] And an electronic device, comprising: One or more processors; and A memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the steps of the method described in any of the foregoing method embodiments.

[0101] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the foregoing method embodiments.

[0102] in, Figure 6An exemplary architecture of an electronic device is shown, which may include a processor 610, a video display adapter 611, a disk drive 612, an input / output interface 613, a network interface 614, and a memory 620. The processor 610, video display adapter 611, disk drive 612, input / output interface 613, network interface 614, and memory 620 can communicate with each other via a communication bus 630.

[0103] The processor 610 can be implemented using a general-purpose CPU, microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits to execute relevant programs and implement the technical solution provided in this application.

[0104] The memory 620 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 620 can store the operating system 621 for controlling the operation of the electronic device 600, and the basic input / output system (BIOS) 622 for controlling the low-level operations of the electronic device 600. Additionally, it can store a web browser 623, a data storage management system 624, and an instruction transmission device 500, etc. The aforementioned instruction transmission device 500 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 620 and executed by the processor 610.

[0105] Input / output interface 613 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0106] Network interface 614 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0107] Bus 630 includes a pathway for transmitting information between various components of the device, such as processor 610, video display adapter 611, disk drive 612, input / output interface 613, network interface 614, and memory 620.

[0108] It should be noted that although the above-described device only shows the processor 610, video display adapter 611, disk drive 612, input / output interface 613, network interface 614, memory 620, bus 630, etc., in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0109] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer program product. This computer program product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0110] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A command transmission method, applied to a network controller, characterized in that, The method includes: Obtain a first instruction issued by the first device based on a first protocol, wherein the first instruction includes a first address and its corresponding first check value; The first instruction is converted into a second instruction, which is obtained based on a second protocol and includes a second address and the first check value. Based on the second address, a second check value is generated, and the first check value included in the second instruction is updated to the second check value; The updated second instruction is transmitted to the second device.

2. The method according to claim 1, characterized in that, If the first protocol is the AXI protocol and the second protocol is the AHB protocol, then the second address includes multiple sub-addresses, and generating a second check value based on the second address includes: Based on the multiple sub-addresses, generate a second check value corresponding to each of the multiple sub-addresses.

3. The method according to claim 1, characterized in that, Before converting the first instruction into the second instruction, the method further includes: Based on the first address and the preset parity check mode, a check value is calculated, wherein the parity check mode is one of odd check mode and even check mode. Compare the calculated check value with the first check value; If the calculated verification value matches the first verification value, then continue with the step of converting the first instruction into the second instruction; otherwise, report the first interrupt information.

4. The method according to claim 1, characterized in that, The step of converting the first instruction into a second instruction includes: The first instruction is input into the first protocol conversion path to obtain the second instruction output by the first protocol conversion path, and the first instruction is input into the second protocol conversion path to obtain the second instruction output by the second protocol conversion path. The first protocol conversion path and the second protocol conversion path are two paths with the same logical function but different physical lines. The second instruction output by the first protocol conversion path and the second instruction output by the second protocol conversion path are used for verification. If the verification passes, the second instruction output by the first protocol conversion path is used as the converted second instruction; otherwise, the second interrupt information is reported.

5. The method according to claim 4, characterized in that, The step of inputting the first instruction into a first protocol conversion path to obtain a second instruction output by the first protocol conversion path, and inputting the first instruction into a second protocol conversion path to obtain a second instruction output by the second protocol conversion path, includes: The first instruction is input into the first protocol conversion path at a first moment to obtain the second instruction output by the first protocol conversion path, and the first instruction is input into the second protocol conversion path at a second moment to obtain the second instruction output by the second protocol conversion path, wherein the first moment and the second moment differ by a preset clock period; The verification using the second instruction output from the first protocol conversion path and the second instruction output from the second protocol conversion path includes: Based on the preset clock period, the pulse signal corresponding to the second instruction output by the first protocol conversion path is compensated to obtain the compensated pulse signal corresponding to the second instruction; the compensated pulse signal corresponding to the second instruction is compared with the pulse signal corresponding to the second instruction output by the second protocol conversion path; if the compensated pulse signal corresponding to the second instruction is consistent with the pulse signal corresponding to the second instruction output by the second protocol conversion path, the verification is successful.

6. The method according to claim 5, characterized in that, The second instruction includes multiple type fields; The comparison of the pulse signal corresponding to the compensated second instruction and the pulse signal corresponding to the second instruction output by the second protocol conversion path includes: The following steps are performed on each of the multiple type fields as the current type field to obtain the comparison result of each type field: Based on the pulse signal corresponding to the current type field in the compensated second instruction and the pulse signal corresponding to the current type field in the second instruction output by the second protocol conversion path, the comparison result of the current type field is obtained; The comparison results of each type of field are processed by OR logic to obtain the target comparison result; Based on the target comparison result, it is determined whether the pulse signal corresponding to the compensated second instruction is consistent with the pulse signal corresponding to the second instruction output by the second protocol conversion path.

7. A command transmission device, disposed in a network controller, characterized in that, The device includes: The acquisition unit is configured to acquire a first instruction issued by the first device based on a first protocol, wherein the first instruction includes a first address and its corresponding first check value. The conversion unit is configured to convert the first instruction into a second instruction, the second instruction being obtained based on a second protocol, the second instruction including a second address and the first check value, the second address being obtained based on the first address; The generation unit is configured to generate a second check value based on the second address, and update the first check value included in the second instruction to the second check value; The transmission unit is configured to transmit the updated second instruction to the second device.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 6.

9. An electronic device, characterized in that, include: One or more processors; as well as A memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 6.

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