Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: forming a shallow trench isolation structure in a substrate; etching the surface of the substrate in a gate forming region adjacent to the shallow trench isolation structure; partial etching is carried out on the shallow trench isolation structure adjacent to the grid electrode forming region so as to expose a corner region of the substrate; and carrying out oxidation treatment on the grid electrode forming region to form a grid insulating layer. According to the invention, the corner region of the shallow trench isolation structure is actively etched before gate oxide oxidation, so that sufficient oxygen supply in the region in the subsequent oxidation process is ensured, the gate oxide layer with uniform thickness is formed, the technical problem that the gate oxide layer at the corner of the shallow trench isolation structure is thinned is fundamentally solved, and the production efficiency is improved. And the reliability and the voltage withstanding characteristic of the high-voltage device are obviously improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In recent years, as semiconductor devices have become smaller and more powerful, structures integrating core devices and high-voltage (HV) devices on the same substrate have become increasingly common. Specifically, with the rise of back-gate technology, which forms the metal gate after the source / drain, the height of the devices must be adjusted when there is a difference in gate oxide thickness between the core device and the high-voltage device to avoid problems such as over-polishing during gate planarization (CMP).

[0003] For high-voltage devices, the silicon substrate surface is typically etched before gate oxidation. However, in the corner regions of shallow trench isolation (STI) structures, since oxygen supply mainly occurs on one side of the silicon substrate surface, insufficient oxidation can lead to localized thinning of the gate oxide layer in these corner regions. This localized thinning of the gate oxide layer can result in decreased transistor reliability and increased leakage current, making it difficult to ensure stable device characteristics.

[0004] To address these issues, a dedicated masking process is typically required to reduce the impact of corner areas and improve the reliability and efficiency of non-volatile memory structures. However, this process increases manufacturing costs and complicates the manufacturing process due to the use of a dedicated mask. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its manufacturing method that can effectively suppress the thinning of the high-voltage gate oxide layer in the corner region of the STI structure without affecting the core device structure.

[0006] To address the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0007] A shallow trench isolation structure is formed in the substrate;

[0008] In the gate formation region adjacent to the shallow trench isolation structure, the surface of the substrate is etched;

[0009] Partial etching is performed on the shallow trench isolation structure adjacent to the gate formation region to expose the corner region of the substrate;

[0010] The gate forming region is oxidized to form a gate insulating layer.

[0011] Optionally, the step of partially etching the shallow trench isolation structure includes:

[0012] The shallow trench isolation structure was wet-etched using a hydrofluoric acid solution.

[0013] Optionally, the step of etching the surface of the substrate is as follows:

[0014] The surface of the substrate is subjected to anisotropic dry etching using a gas containing HBr or Cl2.

[0015] Optionally, after partially etching the shallow trench isolation structure, the process may also include:

[0016] Isotropic etching is performed on the corner region of the substrate to round the corner region.

[0017] Furthermore, the isotropic etching uses CF4 plasma or XeF2 gas.

[0018] Optionally, after partially etching the shallow trench isolation structure, the process may also include:

[0019] The exposed corner regions of the substrate are oxidized to form an oxide layer;

[0020] Remove the oxide layer to smooth the corner area.

[0021] Furthermore, the oxidation treatment is thermal oxidation at a temperature of 900℃~1100℃, and the oxide layer thickness is 1nm~20nm.

[0022] Optionally, the steps of partially etching the shallow trench isolation structure and etching the substrate surface are performed using the same mask layer.

[0023] On the other hand, the present invention also provides a semiconductor device, comprising:

[0024] Substrate;

[0025] Shallow trench isolation structures formed in the substrate;

[0026] A high-voltage device formed on the substrate, the high-voltage device including a gate insulating layer, the thickness of the gate insulating layer at the corner region of the shallow trench isolation structure being uniform with the thickness of its central region.

[0027] Optionally, the gate insulation layer of the high-voltage device has a thickness of 50nm to 200nm, and the corner region has a smooth curved surface structure.

[0028] Compared with the prior art, the present invention has the following unexpected technical effects:

[0029] This invention provides a semiconductor device and its manufacturing method. The manufacturing method includes the following steps: forming a shallow trench isolation structure in a substrate; etching the surface of the substrate in a gate formation region adjacent to the shallow trench isolation structure; partially etching the shallow trench isolation structure adjacent to the gate formation region to expose the corner region of the substrate; and oxidizing the gate formation region to form a gate insulating layer. This invention, by actively etching the corner region of the shallow trench isolation structure before gate oxide oxidation, ensures sufficient oxygen supply in this region during subsequent oxidation, thereby forming a gate oxide layer of uniform thickness. This fundamentally solves the technical problem of thinning gate oxide at the corner of the shallow trench isolation structure, significantly improving the reliability and withstand voltage characteristics of high-voltage devices. Attached Figure Description

[0030] Figure 1 The diagram shown is a cross-sectional view of a semiconductor device structure provided in Embodiment 1 of the present invention.

[0031] Figure 2 The diagram shown is a cross-sectional view of a silicon oxide layer and a silicon nitride layer formed on a substrate according to Embodiment 1 of the present invention.

[0032] Figure 3 The diagram shown is a cross-sectional view of the silicon oxide layer and silicon nitride layer after etching in Embodiment 1 of the present invention.

[0033] Figure 4 The diagram shown is a cross-sectional view of an STI formed according to Embodiment 1 of the present invention.

[0034] Figure 5 The diagram shown is a cross-sectional view of Embodiment 1 of the present invention with the silicon nitride layer removed.

[0035] Figure 6 The diagram shown is a cross-sectional view of the first well region formed in Embodiment 1 of the present invention.

[0036] Figure 7 The diagram shown is a cross-sectional view of the high-voltage LDD region formed in Embodiment 1 of the present invention.

[0037] Figure 8 The diagram shown is a cross-sectional view of the silicon nitride layer formed in Embodiment 1 of the present invention.

[0038] Figure 9 The diagram shown is a cross-sectional view of the silicon nitride and silicon oxide layers after etching, according to Embodiment 1 of the present invention.

[0039] Figure 10 The diagram shown is a cross-sectional view of a substrate surface A after dry etching according to an embodiment of the present invention.

[0040] Figure 11 The diagram shown is a cross-sectional view of the high-voltage grid region formed in Embodiment 1 of the present invention.

[0041] Figure 12 The diagram shown is a cross-sectional view of the gate insulating layer formed in Embodiment 1 of the present invention.

[0042] Figure 13 The diagram shown is a cross-sectional view of Embodiment 1 of the present invention with the silicon nitride layer removed.

[0043] Figure 14 The diagram shown is a cross-sectional view of the second well region formed in Embodiment 1 of the present invention.

[0044] Figure 15 The diagram shown is a cross-sectional view of Embodiment 1 of the present invention after the remaining silicon oxide layer has been removed.

[0045] Figure 16 The diagram shown is a cross-sectional view of an insulating layer formed according to Embodiment 1 of the present invention.

[0046] Figure 17 The diagram shown is a cross-sectional view of the first and second pseudo-gates formed according to Embodiment 1 of the present invention.

[0047] Figure 18 The diagram shown is a cross-sectional view of the core LDD formed in Embodiment 1 of the present invention.

[0048] Figure 19 The diagram shown is a cross-sectional view of the sidewall insulating layer formed in Embodiment 1 of the present invention.

[0049] Figure 20 The diagram shown is a cross-sectional view of the source and drain regions formed in Embodiment 1 of the present invention.

[0050] Figure 21 The diagram shown is a cross-sectional view of the source electrode and drain electrode formed in Embodiment 1 of the present invention.

[0051] Figure 22 The diagram shown is a cross-sectional view of the interlayer formed in Embodiment 1 of the present invention.

[0052] Figure 23 The diagram shown is a cross-sectional view of Embodiment 1 of the present invention after the removal of the first and second pseudo-gates.

[0053] Figure 24 The diagram shown is a cross-sectional view of the gate electrode formed in Embodiment 1 of the present invention.

[0054] Figure 25 As shown Figure 24 A partially enlarged sectional view.

[0055] Figure 26A The image shown is a cross-sectional enlarged view of the interface between the gate insulating layer and the STI in the prior art.

[0056] Figure 26BThe image shown is a cross-sectional enlarged view of the interface between the gate insulation layer and the STI in the high-voltage device of Embodiment 1 of the present invention.

[0057] Figure 27 The diagram shown is a cross-sectional view of the high-voltage grid region formed in Embodiment 2 of the present invention.

[0058] Figure 28 As shown Figure 27 Enlarged sectional view of block diagram E.

[0059] Figure 29 The diagram shown is a cross-sectional view of the high-voltage grid region formed in Embodiment 3 of the present invention.

[0060] Figure 30A As shown Figure 29 Enlarged sectional view of block diagram F.

[0061] Figure 30B The figure shown is a cross-sectional view of the substrate corner region after smoothing treatment according to Embodiment 3 of the present invention.

[0062] Explanation of reference numerals in the attached figures:

[0063] 10-Substrate; 12-Second well region; 14-STI; 16-First source region; 18-First source electrode; 20-First drain region; 22-First drain electrode; 24-Core LDD; 26-First gate insulating layer; 28-First gate electrode; 30-First sidewall insulating layer; 32-First well region; 34-Second source region; 36-Second source electrode; 38-Second drain region; 40-Second drain electrode; 42-High voltage LDD region; 44-Second gate insulating layer; 46-Second gate electrode; 48-Second sidewall insulating layer; 50-Interlayer layer; 60-Silicon oxide layer; 62-First silicon nitride layer; 64-Second silicon nitride layer; 66-Insulating layer; 68a-First dummy gate; 68b-Second dummy gate; 70-Oxide layer; 100-Semiconductor device; 102-Core device; 104-High voltage device. Detailed Implementation

[0064] The following will provide a more detailed description of a semiconductor device and its manufacturing method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0065] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0066] To make the objectives and features of the present invention more apparent and understandable, specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention.

[0067] Example 1

[0068] The semiconductor device provided in this embodiment includes a substrate; a shallow trench isolation structure formed in the substrate; and a high-voltage device formed on the substrate. The high-voltage device includes a gate insulating layer, the thickness of which is uniform at the corner region of the shallow trench isolation structure and at its central region. This device has a high-voltage gate oxide layer of uniform thickness, and particularly in the critical STI corner region, there are no weak points, thereby avoiding electric field concentration and premature breakdown, resulting in higher reliability, more stable electrical performance, and a longer service life.

[0069] Detailed Figure 1 This is a cross-sectional schematic diagram of the semiconductor device structure according to an embodiment of the present invention. Figure 1 As shown, substrate 10 can be a silicon substrate. Semiconductor device 100 has a MOSFET structure, which integrates core device 102 and high-voltage device 104. It should be noted that... Figure 1 For illustrative purposes, the dimensions of each part differ from the actual dimensions of the semiconductor device 100 for the purpose of clearly showing the structure.

[0070] The core device 102 includes a second well region 12, an STI (Shallow Trench Isolation) structure 14, a first source region 16, a first source electrode 18, a first drain region 20, a first drain electrode 22, a core LDD 24, a first gate insulating layer 26, a first gate electrode 28, and a first sidewall insulating layer 30.

[0071] The second well region 12 is a p-well doped with p-type impurities in the substrate 10. The second well region 12 can be formed by ion implantation of p-type impurities such as boron (B), aluminum (Al), and gallium (Ga) into the substrate 10, followed by ion activation through a heat treatment process at around 1000°C. The depth of the second well region 12 from the surface of the substrate 10 is preferably greater than or equal to 0.2 μm and less than or equal to 0.8 μm.

[0072] In substrate 10, an STI 14 structure ensures electrical insulation between adjacent devices. STI 14 is a structure consisting of a trench formed within substrate 10 filled with silicon oxide. An oxide substrate with a thickness of approximately 10 nm, formed by an ISSG oxidation process, can be disposed on the sidewalls and bottom of the trench. STI 14 can be, for example, deposited using a CVD process with a HARP oxide layer having a thickness greater than or equal to 200 nm and less than or equal to 1000 nm. The surface of STI 14 is planarized to approximately flush with the surface of substrate 10 using a CMP process.

[0073] The first source region 16 and the first drain region 20 are n-type impurity doped regions. The first source region 16 and the first drain region 20 are formed by high-concentration ion implantation with n-type impurities such as phosphorus (P) or arsenic (As), with an implantation energy of 1 keV to 50 keV and an implantation dose of 1 × 10⁻⁶. 15 / cm 2 The first source electrode 18 and the first drain electrode 22 are formed in the first source region 16 and the first drain region 20, respectively. The first source electrode 18 and the first drain electrode 22 are preferably silicide layers of metals such as cobalt (Co) or nickel (Ni).

[0074] The core LDD 24 is a shallow, low-concentration doped region located between the first source region 16, the first drain region 20, and the first gate insulating layer 26. The core LDD 24 is doped with a low dose (1×10⁻⁶) of n-type impurities such as phosphorus (P) or arsenic (As) at an implantation energy of 1 keV to 50 keV. 13 / cm 2 ~1×10 15 / cm 2 Formed by ion implantation (left and right).

[0075] The first gate insulating layer 26 is an insulating layer used to form the channel region of the core device 102. The first gate insulating layer 26 is preferably a stacked structure of a silicon oxide layer and a high-k layer. The silicon oxide layer is formed, for example, by an ISSG oxidation process, and its thickness is preferably greater than or equal to 0.2 nm and less than or equal to 3 nm. Hafnium oxide (HfO2) is formed on the silicon oxide layer by an ALD process, with a thickness greater than or equal to 0.5 nm and less than or equal to 10 nm. In addition, a TiN capping layer with a thickness greater than or equal to 2 nm and less than or equal to 5 nm can also be deposited.

[0076] The first gate electrode 28 is an electrode layer for applying a gate voltage to the first gate insulating layer 26. The first gate electrode 28 may be made of metal or silicide, etc. The first gate electrode 28 may be, for example, an aluminum (Al) layer, a tungsten (W) layer, or a titanium nitride (TiN) layer formed by PVD or CVD processes. The first gate electrode 28 is planarized by CMP process after the interlayer layer 50 is formed. The interlayer layer 50 is, for example, made of oxide. The first sidewall insulating layer 30 is an insulating layer protecting the sides of the first gate electrode 28. The first sidewall insulating layer 30 is, for example, made of silicon nitride (SiN). The first sidewall insulating layer 30 is formed by depositing silicon nitride (SiN) by CVD process with a deposition thickness of 50 Å to 200 Å; and then performing anisotropic dry etching.

[0077] The high-voltage device 104 includes a first well region 32, an STI 14, a second source region 34, a second source electrode 36, a second drain region 38, a second drain electrode 40, a high-voltage LDD 42, a second gate insulating layer 44, a second gate electrode 46, and a second sidewall insulating layer 48.

[0078] The first well region 32 is a p-well doped with p-type impurities in the substrate 10. The first well region 32 can be formed by ion implantation of p-type impurities such as boron (B), aluminum (Al), and gallium (Ga) into the substrate 10, followed by ion activation through a heat treatment process at around 1050°C. The depth of the first well region 32 from the surface of the substrate 10 is preferably greater than or equal to 0.5 μm and less than or equal to 8 μm.

[0079] The second source region 34 and the second drain region 38 are n-type impurity doped regions. The second source region 34 and the second drain region 38 are formed by ion implantation with n-type impurities such as phosphorus (P) or arsenic (As), with an implantation energy of 1 keV to 50 keV and an implantation dose of 1 × 10⁻⁶. 15 / cm 2 The two regions are then activated by ionization via an RTA process. Furthermore, a second source electrode 36 and a second drain electrode 40 are formed on the surfaces of the second source region 34 and the second drain region 38, respectively. The second source electrode 36 and the second drain electrode 40 are preferably silicide layers of metals such as cobalt (Co) or nickel (Ni).

[0080] High-voltage LDD 42 is powered by injection energy ranging from 20keV to 800keV and 1×10 12 / cm 2 ~1×10 14 / cm 2 It is formed by injecting n-type impurities such as phosphorus (P) or arsenic (As) in a specific dose. By using a high-voltage LDD 42, the electric field concentration at the edge of the second gate insulating layer 44 can be reduced.

[0081] The second gate insulating layer 44 is a silicon oxide layer formed by a thermal oxidation process, with a thickness greater than or equal to 50 nm and less than or equal to 200 nm, and the corner region has a smooth curved surface structure. This thickness of gate oxide layer can meet the requirements of high-voltage applications; combined with the smooth curved corner structure, it ensures uniform electric field distribution and excellent insulation performance under high voltage.

[0082] The second gate insulating layer 44 is formed in the semiconductor device 100 in such a manner that the oxide layer thickness at the interface between the second gate insulating layer 44 and the STI 14 is approximately the same as the oxide layer thickness at the central portion of the second gate insulating layer 44 (i.e., uniform). This device has a high-voltage gate oxide layer of uniform thickness, particularly in the critical region of the STI corner where there are no weak points, thereby avoiding electric field concentration and premature breakdown, resulting in higher reliability, more stable electrical performance, and a longer lifespan.

[0083] The second gate electrode 46 is an electrode layer used to apply a gate voltage to the second gate insulating layer 44. The second gate electrode 46 may be made of metal or silicide. The second gate electrode 46 may be an aluminum (Al) layer, a tungsten (W) layer, or a titanium nitride (TiN) layer formed by PVD or CVD processes. The second gate electrode 46 is planarized by CMP process after the interlayer layer 50 is formed. The second sidewall insulating layer 48 is an insulating layer protecting the sides of the second gate electrode 46. The second sidewall insulating layer 48 is, for example, made of silicon nitride (SiN). The second sidewall insulating layer 48 is formed by depositing silicon nitride (SiN) by CVD process with a deposition thickness of 50 Å to 200 Å; and then performing anisotropic dry etching.

[0084] In addition to the core device 102 and the high-voltage device 104, the semiconductor device 100 may also include a medium-voltage device (such as a medium-voltage MOSFET). Furthermore, a structure in which the n-type and p-type semiconductors are interchanged may also be adopted.

[0085] This embodiment also provides a method for manufacturing a semiconductor device, including the following steps:

[0086] An STI insulating structure is formed on the substrate;

[0087] In the gate formation region adjacent to the STI insulating structure, the surface of the silicon substrate is etched;

[0088] The STI insulating structure adjacent to the gate formation region is etched to expose the corner region of the silicon substrate; and

[0089] The gate forming region is oxidized to form a gate oxide layer.

[0090] This embodiment ensures sufficient oxygen supply in the corner area of ​​the shallow trench isolation structure by actively etching before gate oxide oxidation, thereby forming a gate oxide layer of uniform thickness. This fundamentally solves the technical problem of thinning gate oxide layer at the corner of the shallow trench isolation structure, and significantly improves the reliability and withstand voltage characteristics of high voltage devices.

[0091] The following combination Figures 2-29 , Figures 30A-30B The manufacturing method of the semiconductor device provided in this embodiment will be described in detail.

[0092] Figure 2 The diagram shown is a cross-sectional view of a silicon oxide layer and a silicon nitride layer formed on a substrate in this embodiment. Figure 2 As shown, in step S10, firstly, a silicon oxide layer 60 is formed on the surface of the substrate 10 by a thermal oxidation process. Preferably, the substrate 10 is a single-crystal silicon substrate, and a silicon oxide layer 60 with a thickness greater than or equal to 5 nm and less than or equal to 20 nm is formed by surface heat treatment in an oxidizing atmosphere. The silicon oxide layer 60 can be formed by a thermal oxidation process based on dry oxidation or in-situ steam generation (ISSG).

[0093] Next, a first silicon nitride layer 62 is formed on the silicon oxide layer 60. The thickness of the first silicon nitride layer 62 is preferably greater than or equal to 30 nm and less than or equal to 200 nm. The first silicon nitride layer 62 can be deposited by low-pressure chemical vapor deposition (LPCVD) using dichlorosilane (SiH2Cl2) and ammonia (NH3) as feed gases, or by plasma-enhanced chemical vapor deposition (PECVD). The first silicon nitride layer 62 serves as a hard mask in the subsequent process of forming STI 14, protecting the surface of the substrate 10 from the effects of the selective etching process.

[0094] Figure 3 The diagram shown is a cross-sectional view after etching the silicon oxide and silicon nitride layers in this embodiment. Figure 3As shown, in step S12, firstly, photoresist PR is coated on the first silicon nitride layer 62, and a photoresist PR with a uniform thickness is formed by spin coating. Subsequently, a predetermined pattern is formed through a photolithography process including exposure and development. This pattern is configured to have openings corresponding to the STI 14 regions formed in subsequent processes.

[0095] Following this, using photoresist PR as a mask, selective dry etching is performed on the silicon oxide layer 60 and the first silicon nitride layer 62. This etching can be anisotropic dry etching using fluorocarbon gases. Specifically, a plasma with C4F8, CF4, and Ar as the main components can be used.

[0096] Through this step, openings corresponding to the formation regions of STI 14 are formed in the silicon oxide layer 60 and the first silicon nitride layer 62 formed on the substrate 10.

[0097] Finally, the photoresist PR used in the patterning process in the previous step is removed. The photoresist PR can be removed, for example, by oxygen plasma ashing and cleaning with organic solvents.

[0098] Figure 4 The diagram shown is a cross-sectional view illustrating the formation of the STI in this embodiment. Figure 4 As shown, in step S14, firstly, anisotropic dry etching is performed on the substrate 10 in the formation region of STI14 to form trenches with a predetermined depth. During etching, a plasma mainly composed of HBr and Cl2 can be used. Additionally, a small amount of O2 can be incorporated to improve the perpendicularity of the sidewalls. Etching conditions preferably include, for example, a pressure of 10 Pa to 50 Pa, a radio frequency (RF) power of several hundred watts, and a substrate temperature of approximately 60°C. The depth of the formed trenches is preferably greater than or equal to 0.2 μm and less than or equal to 0.5 μm, and the width can be set to the width required for insulation between devices.

[0099] Following this, the inner walls of the trench are subjected to ISSG oxidation to form an oxide liner approximately 10 nm thick. This reduces the interface energy level and suppresses the increase in leakage current. Subsequently, a high aspect ratio process (HARP) is used to perform CVD deposition of a silicon oxide layer within the formed trench to form an STI 14 filling the trench. The thickness of the deposited STI 14 oxide layer is preferably greater than or equal to 200 nm and less than or equal to 1000 nm. After filling STI 14, surface planarization is performed by chemical mechanical polishing (CMP) to achieve approximate flushness with the surface of the substrate 10.

[0100] The STI 14 formed through this step electrically isolates adjacent devices, thereby ensuring high insulation and high flatness in subsequent component fabrication processes.

[0101] Figure 5 The diagram shown is a cross-sectional view of this embodiment with the silicon nitride layer removed. Figure 5 As shown, in step S16, the first silicon nitride layer 62 is removed by wet etching. The first silicon nitride layer 62 is etched, for example, with a heated aqueous solution of phosphoric acid (H3PO4). This step exposes the underlying silicon oxide layer 60. This silicon oxide layer 60 keeps the substrate surface oxidized before the gate oxide layer is formed in the next step, preventing direct exposure of silicon.

[0102] Figure 6 The diagram shown is a cross-sectional view illustrating the formation of the first well region in this embodiment. Figure 6 As shown, in step S18, firstly, after forming photoresist PR on substrate 10 by spin coating, a predetermined pattern is formed by photolithography processes including exposure and development. The patterning method of photoresist PR results in an opening in the region corresponding to the first well region 32 formed in subsequent processes.

[0103] Subsequently, using photoresist PR as a mask, substrate 10 undergoes multiple ion implantations to form the first well region 32. The implanted impurities are p-type impurities, specifically boron (B), aluminum (Al), or gallium (Ga). To control the impurity distribution along the depth direction of the well region, the implantation conditions involve two to five implantations performed sequentially in descending order of energy. Preferably, the implantation energy of the first implantation is greater than or equal to 1 MeV and the implantation dose is 1 × 10⁻⁶. 12 / cm 2 The final injection energy was approximately 50 keV to 500 keV, and the injection dose was 1 × 10⁻⁶. 12 / cm 2 Left and right. Thus, a first well region 32 is formed within a depth of greater than or equal to 0.5 μm and less than or equal to 8 μm from the surface of the substrate 10.

[0104] Next, after the ion implantation process is completed, the photoresist PR is removed. The photoresist PR can be removed by oxygen plasma ashing and cleaning with organic solvents.

[0105] Subsequently, heat treatment is performed, for example, at a temperature of around 1000°C to 1050°C, to activate the impurities within the first well region 32.

[0106] Figure 7 The diagram shown is a cross-sectional view illustrating the formation of the high-voltage LDD region in this embodiment. Figure 7As shown, in step S20, firstly, photoresist PR is applied to the substrate 10 by spin coating, and a predetermined pattern is formed by photolithography processes including exposure and development. The patterning method of the photoresist PR allows for the selective formation of openings in the areas used to form the high-voltage LDD region 42.

[0107] Subsequently, using photoresist PR as a mask, ion implantation is performed on substrate 10 to form a high-voltage LDD region 42. The implanted impurities are n-type impurities, specifically phosphorus (P) or arsenic (As). The purpose of setting the high-voltage LDD region 42 is to alleviate the electric field concentration at the edge of the second gate insulating layer 44 and ensure withstand voltage.

[0108] During ion implantation, multiple implantations under different conditions are preferred. For example, multiple implantations with different implantation energies can be performed, with the number of implantations ranging from one to approximately four. The initial implantation energy is approximately 500 keV, and the dose is 1 × 10⁻⁶. 12 / cm 2 The injection energy was then successively reduced to 200 keV and 100 keV, and the corresponding injections were performed, thereby achieving the desired depth and concentration distribution in the high-voltage LDD region 42.

[0109] Finally, after ion implantation, the photoresist PR is removed. The photoresist PR can be completely removed by oxygen plasma ashing and organic solvent cleaning. In subsequent processes, impurities are activated through heat treatment to ensure stable electrical properties in the high-voltage LDD region 42.

[0110] Figure 8 The diagram shown is a cross-sectional view illustrating the formation of a silicon nitride layer in this embodiment. Figure 8 As shown, in step S22, a second silicon nitride layer 64 is formed. The second silicon nitride layer 64 is used as an etching mask layer in subsequent processes. The thickness of the second silicon nitride layer 64 is preferably greater than or equal to 10 nm and less than or equal to 50 nm. The second silicon nitride layer 64 can be formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). For example, in the case of using LPCVD, preferably, the feed gas is dichlorosilane (SiH2Cl2) and ammonia (NH3), the deposition temperature is 600°C to 800°C, and the pressure is approximately 50 Pa to 200 Pa.

[0111] Figure 9 The diagram shown is a cross-sectional view after etching the silicon nitride and silicon oxide layers in this embodiment. Figure 9As shown, in step S24, firstly, photoresist PR is uniformly coated on substrate 10 by spin coating. Then, a predetermined pattern is formed by photolithography processes including exposure and development. The patterning method of photoresist PR is such that, in addition to forming openings corresponding to the high-voltage gate oxide layer formation area, openings are also formed corresponding to the areas where partial etching of substrate 10 (step S26) and partial etching of STI 14 (step S28) are performed in subsequent processes.

[0112] Next, photoresist PR is used as an etching mask to remove the second silicon nitride layer 64 and silicon oxide layer 60 from the opening, exposing the substrate 10 and STI 14. The etching of the silicon oxide layer 60 is preferably performed using a dry etching process with a fluorocarbon gas, while the etching of the second silicon nitride layer 64 is preferably performed using a dry etching process with a nitrogen-containing fluorocarbon gas. For example, the etching of the silicon oxide layer 60 is preferably performed using a dry etching process with plasma containing CF4 or C4F8, while the etching of the second silicon nitride layer 64 is preferably performed using a dry etching process with plasma containing CH2F2 or C3F6. Furthermore, during the etching of the second silicon nitride layer 64, a portion of region B of the STI 14 is etched.

[0113] Finally, remove the photoresist (PR).

[0114] Figure 10 The diagram shown is a cross-sectional view of the substrate surface A after dry etching in this embodiment. Figure 10 As shown, in step S26, dry etching is performed on surface A of substrate 10. The photoresist PR can be removed by oxygen plasma ashing and organic solvent cleaning. After removing the photoresist, dry etching is performed on the surface of substrate 10 within the area where the opening was formed in step S24.

[0115] The dry etching process is preferably anisotropic dry etching using chlorine-based or bromine-based gases. For example, a plasma with HBr or Cl2 as the main component can be used. As process conditions, the pressure, RF power, and substrate temperature can be appropriately set. The surface etching depth of the silicon substrate 10 is preferably greater than or equal to 10 nm and less than or equal to 100 nm. This anisotropic dry etching step allows for precise control of the etching depth of the silicon substrate, forming steep sidewalls, which lays the foundation for subsequently defining a precise high-voltage gate region.

[0116] Figure 11 The diagram shown is a cross-sectional view illustrating the formation of the high-voltage grid region in this embodiment. Figure 11As shown, in step S28, the silicon oxide layer in region C of the STI 14 exposed in the opening is further etched to form a high-voltage gate region. This step aims to adjust the edge portion of the STI 14 to a shape suitable for the subsequent formation of a second gate insulating layer 44 with a uniform thickness, avoiding steep steps at the edge portion of the junction between the STI 14 and the second gate insulating layer 44.

[0117] The etching described above can be a wet etching process using hydrofluoric acid (HF). A 1%–10% aqueous HF solution or buffered ammonium fluoride (BHF) can be used. After removing the silicon oxide layer 60, deionized water rinsing and spin drying can be performed to clean the surface of the substrate 10.

[0118] This step is a characteristic step of this embodiment. After processing through this step, the central portion of the second gate insulating layer 44 and the boundary portion with STI 14 can achieve a uniform thickness, thereby reducing leakage current or oxide layer breakdown. Simultaneously, this step uses wet etching, which has a high selectivity for silicon oxide in STI 14, accurately and uniformly removing material from specific areas of STI 14 without damaging the silicon substrate. The process is simple and highly controllable. Furthermore, this step uses the same mask as step S26, eliminating the need for additional mask formation and removal. This step completes the etching of the substrate and STI in one step using the same mask layer, greatly simplifying the manufacturing process, saving additional photolithography and mask removal steps, thereby significantly reducing production costs and improving process efficiency. At the same time, this ensures precise alignment of the etched areas, improving the structural consistency and performance uniformity of the device.

[0119] Figure 12 The diagram shown is a cross-sectional view illustrating the formation of the gate insulating layer in this embodiment. Figure 12 As shown, in step S30, a second gate insulating layer 44 is formed on the surface of the substrate 10 within the high-voltage gate region where the opening is formed. The purpose of forming the second gate insulating layer 44 is to insulate the channel region within the high-voltage device 104, thereby ensuring stable electric field characteristics. The second gate insulating layer 44 can be formed primarily by thermal oxidation. Oxidation is performed by heating in an oxygen atmosphere or an atmosphere containing oxygen and water vapor at a temperature of 900°C to 1150°C. The thickness of the second gate insulating layer 44 is preferably greater than or equal to 50 nm and less than or equal to 200 nm. With a thickness within this range, the second gate insulating layer 44 can have a high-voltage characteristic greater than or equal to 20V.

[0120] Furthermore, the second gate insulating layer 44 may not be entirely formed by thermal oxidation, but may be partially formed by chemical vapor deposition (CVD). In this case, a thin thermal oxide layer is first formed on the silicon surface of the substrate 10 by oxidation, and then silicon oxide is deposited on the thermal oxide layer by CVD to ensure the required thickness. Preferably, the CVD method is LPCVD or PECVD.

[0121] The formed second gate insulating layer 44 is a continuous layer, and it has approximately the same thickness both at the junction with STI 14 and in the central portion, thus avoiding the problem of thinning due to steeper corners in the prior art. This reduces insulation breakdown or leakage current in the second gate insulating layer 44, improving the reliability of the semiconductor device 100.

[0122] Figure 13 The diagram shown is a cross-sectional view of this embodiment with the silicon nitride layer removed. Figure 13 As shown, in step S32, the remaining first silicon nitride layer 62 is removed by wet etching. When removing the first silicon nitride layer 62 by wet etching, a heated aqueous solution of phosphoric acid (H3PO4) is preferably used, for example.

[0123] Figure 14 The diagram shown is a cross-sectional view illustrating the formation of the second well region in this embodiment. Figure 14 As shown, in step S34, firstly, photoresist PR is uniformly coated on substrate 10 by spin coating, and a predetermined pattern is formed by photolithography. The patterning method of photoresist PR is such that only the portion corresponding to the second well region 12 of the core device 102 forms an opening, while other areas remain covered.

[0124] Subsequently, using photoresist PR as a mask, substrate 10 undergoes multiple ion implantations to form the second well region 12. The implanted impurities are p-type, typically boron (B), aluminum (Al), gallium (Ga), etc. The implantation conditions are preferably two to five implantations performed sequentially in descending order of energy (energy range, for example, 500 keV to 10 keV). The implantation dose is 1 × 10⁻⁶. 12 / cm 2 ~1×10 13 / cm 2 Left and right. Thus, a second well region 12 is formed within a depth of greater than or equal to 0.2 μm and less than or equal to 0.8 μm from the surface of the substrate 10.

[0125] Finally, after the ion implantation process is completed, the photoresist PR is removed. The photoresist PR can be removed by oxygen plasma ashing and organic solvent cleaning. Subsequently, a heat treatment is performed, for example, at a temperature of approximately 1050°C, to activate the impurities implanted into the second well region 12.

[0126] In this embodiment, a step of forming a gate insulating layer in the medium-voltage device region can be provided between step S30 and step S32.

[0127] Specifically, a silicon nitride layer for protecting the medium-voltage device region is first deposited on substrate 10. The thickness of this nitride layer is preferably greater than or equal to 10 nm and less than or equal to 50 nm, and can be deposited using LPCVD or PECVD methods. Subsequently, photoresist is applied by spin coating and patterned by photolithography to form openings corresponding to the medium-voltage gate region. Afterward, using the photoresist as a mask, selective dry etching is performed on the silicon nitride layer and the underlying silicon oxide layer to expose the silicon surface of substrate 10. The etching of silicon preferably uses a fluorocarbon gas, while the etching of the silicon oxide layer can use a gas containing CF4 or CH2F2.

[0128] After removing the photoresist, the exposed surface of the substrate 10 is dry-etched, with an etching range greater than or equal to 1 nm and less than or equal to 50 nm. Subsequently, a sacrificial oxide layer is formed by thermal oxidation or CVD. The resulting silicon oxide layer has a thickness greater than or equal to 1 nm and less than or equal to 20 nm.

[0129] In addition, after step S32, a step (not shown) can be set to form a medium-voltage LDD (MVLDD) and a gate insulating layer in the medium-voltage device region.

[0130] Specifically, photoresist is first uniformly coated onto substrate 10 using spin coating, and then a pattern corresponding to the medium-voltage device region is formed using photolithography. The patterning method of the photoresist ensures that the area to be formed of the MVLDD has an opening, while other areas remain covered. Subsequently, using the photoresist as a mask, ion implantation is performed on substrate 10. The implanted impurities are n-type impurities phosphorus (P) or arsenic (As), and the implantation conditions are preferably multiple implantations with different implantation energies, with one to four implantations. For example, the energy of each implantation can be in the range of 10keV to 100keV, and the dose can be 1×10⁻⁶. 13 / cm 2 The photoresist is then removed after ion implantation, allowing for the desired depth and concentration distribution.

[0131] After the MVLDD is formed, the gate insulating layer for the medium-voltage device is then formed. First, the sacrificial oxide layer is removed by wet etching, and the silicon surface is cleaned. Subsequently, the gate insulating layer is formed by combining in-situ vapor generation (ISSG) oxidation with CVD processes. Preferably, the thickness of the gate insulating layer is greater than or equal to 5 nm and less than or equal to 30 nm.

[0132] Figure 15 The diagram shown is a cross-sectional view of this embodiment after the remaining silicon oxide layer has been removed. Figure 15As shown, in step S36, the remaining silicon oxide layer 60 is removed. The purpose of this step is to expose the clean surface of the substrate 10. The etching of the silicon oxide layer 60 can be performed using a wet etching process with hydrofluoric acid (HF). A 1% to 10% aqueous HF solution or buffered ammonium fluoride (BHF) can be used. After removing the silicon oxide layer 60, deionized water rinsing and spin drying can be performed to clean the surface of the substrate 10.

[0133] Figure 16 The diagram shown is a cross-sectional view illustrating the formation of an insulating layer in this embodiment. Figure 16 As shown, in step S38, an insulating layer 66 is formed in the core device 102 region and the source and drain regions of the high-voltage device 104. Specifically, firstly, a thermal oxidation process using in-situ vapor generation (ISSG) is performed on the surface of the substrate 10 to form an initial oxide layer. Preferably, the thickness of the silicon oxide layer formed by ISSG oxidation is greater than or equal to 0.2 nm and less than or equal to 3.0 nm. This silicon oxide layer is used to ensure interface stability with the subsequently formed high-dielectric-constant layer.

[0134] Following this, a high-dielectric-constant insulating layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). This high-dielectric-constant layer can be made of materials such as hafnium oxide (HfO2) or zirconium oxide (ZrO2). The thickness of this high-dielectric-constant insulating layer is preferably greater than or equal to 0.5 nm and less than or equal to 10 nm. The purpose of selecting this high-dielectric-constant insulating layer is to obtain stable threshold voltage characteristics while reducing gate leakage current.

[0135] In addition, titanium nitride (TiN) is formed on the high-dielectric-constant insulating layer as a gate capping layer. This capping layer can be formed by ALD or PVD. The thickness of the capping layer is preferably greater than or equal to 2 nm and less than or equal to 5 nm. The function of this capping layer is to prevent oxidation of the high-dielectric-constant insulating layer and to achieve adjustment of the work function.

[0136] This step yields an insulating layer 66, which consists of a stacked structure of an ultrathin silicon oxide layer, a high-dielectric-constant insulating layer, and a capping layer. The insulating layer 66 serves as the first gate insulating layer 26 inside the core device 102.

[0137] Figure 17 The diagram shown is a cross-sectional view illustrating the formation of the first and second pseudo-gates in this embodiment. Figure 17 As shown, in step S40, a first dummy gate 68a is formed in the gate region of the core device 102, and a second dummy gate 68b is formed in the gate region of the high-voltage device 104. The purpose of setting the first dummy gate 68a and the second dummy gate 68b is to precisely define the position of the gate before the formation of the first gate electrode 28 and the second gate electrode 46, and to provide the structure required for the source-drain two-region implantation process and the sidewall formation step.

[0138] A polycrystalline silicon layer is deposited on substrate 10 using chemical vapor deposition (CVD). This polycrystalline silicon layer serves as a dummy gate material, and its thickness is preferably greater than or equal to 10 nm and less than or equal to 100 nm. The polycrystalline silicon layer can be formed using an LPCVD process that utilizes a gas with silane (SiH4) as the main component.

[0139] Subsequently, a hard mask layer for dummy gate patterning is formed. This hard mask is a stacked structure of a silicon nitride layer and a silicon oxide layer. The thickness of the nitride layer is, for example, approximately 5 nm to 20 nm, and the thickness of the oxide layer is, for example, approximately 3 nm to 10 nm. These two layers can be deposited using CVD. Afterward, photoresist is applied by spin coating, and a predetermined pattern is formed by exposure and development. Then, using the photoresist as a mask, anisotropic dry etching is performed on the hard mask layer to form openings in the dummy gate region. For this etching, a fluorocarbon gas (CF4, CHF3, etc.) is preferably used. After the hard mask is etched, the photoresist is removed. Subsequently, anisotropic dry etching is performed on the polysilicon layer using the hard mask to pattern it, thereby forming the first dummy gate 68a and the second dummy gate 68b. The etching of the polysilicon layer can use a gas containing Cl2 or HBr.

[0140] Figure 18 The diagram shown is a cross-sectional view of the core LDD formed in this embodiment. Figure 18 As shown, in step S42, a core LDD 24 is formed in the source and drain regions adjacent to the gate region of the core device 102. Specifically, photoresist PR is applied to the surface of the substrate 10 by spin coating, and a predetermined pattern is formed by photolithography. The patterning of the photoresist PR results in an opening in the area of ​​the core device 102, while other areas remain covered. Simultaneously, the location of the core LDD 24 is precisely defined by using the already formed first dummy gate 68a as a mask.

[0141] Subsequently, using photoresist PR and the first dummy gate 68a as a mask, ion implantation is performed on substrate 10 to form core LDD24. The implanted impurity is n-type impurity phosphorus (P) or arsenic (As). Preferably, the implantation energy is in the range of 1keV to 50keV, and a relatively low implantation dose (1×10⁻⁶) is used. 13 / cm 2 ~1×10 15 / cm 2 (Left and right). In addition, the injection angle can be tilted as needed to adjust the injection amount below the first gate insulating layer 26.

[0142] After the ion implantation step, the photoresist PR is removed. The photoresist PR can be removed by oxygen plasma ashing and organic solvent cleaning. By setting the core LDD 24, the electric field at the channel edge in the core device 102 can be reduced, thereby mitigating the performance degradation caused by hot carriers.

[0143] Figure 19 The diagram shown is a cross-sectional view illustrating the formation of a sidewall insulating layer in this embodiment. Figure 19 As shown, in step S44, a first sidewall insulating layer 30 and a second sidewall insulating layer 48 are formed on the sidewalls of the first dummy gate 68a of the core device 102 and the second dummy gate 68b of the high voltage device 104, respectively.

[0144] In detail, firstly, a silicon nitride layer is formed by chemical vapor deposition (CVD). The thickness of the silicon nitride layer is preferably greater than or equal to 1 nm and less than or equal to 10 nm. Subsequently, a silicon oxide layer is formed by CVD or thermal oxidation. The thickness of the silicon oxide layer is preferably greater than or equal to 1 nm and less than or equal to 10 nm. Then, a silicon nitride layer is formed again by CVD. The thickness of this silicon nitride layer is preferably greater than or equal to 1 nm and less than or equal to 30 nm. After forming each layer, anisotropic dry etching is performed to retain only the insulating layers on the sidewalls of the first dummy gate 68a and the second dummy gate 68b, thereby forming the first sidewall insulating layer 30 and the second sidewall insulating layer 48. Dry etching can be performed using a plasma containing CF4, CHF3, and Ar.

[0145] Figure 20 The diagram shown is a cross-sectional view illustrating the formation of the source and drain regions in this embodiment. Figure 20 As shown, in step S46, a first source region 16 and a first drain region 20 are formed in the core device 102, and a second source region 34 and a second drain region 38 are formed in the high-voltage device 104.

[0146] In detail, firstly, photoresist is applied to the substrate 10 using spin coating, and then a predetermined pattern is formed by photolithography. The patterning of the photoresist creates openings in the first source region 16 and the first drain region 20 in the core device 102, and in the second source region 34 and the second drain region 38 in the high-voltage device 104, while other areas remain covered. Simultaneously, by using the formed first sidewall insulating layer 30 and the second sidewall insulating layer 48 as masks, the positions of the first source region 16 and the first drain region 20 in the core device 102, and the second source region 34 and the second drain region 38 in the high-voltage device 104, can be precisely defined.

[0147] Subsequently, ion implantation is performed on substrate 10 to form a first source region 16, a first drain region 20, a second source region 34, and a second drain region 38. In this ion implantation, n-type impurities of phosphorus (P) or arsenic (As) are preferably implanted. Preferably, the implantation energy is in the range of 1 keV to 50 keV, and the implantation dose is approximately 1 × 10⁻⁶. 15 / cm 2 Left and right. In addition, the implantation angle can be tilted as needed to control the area of ​​ion implantation.

[0148] Next, after ion implantation is complete, the photoresist is removed.

[0149] Subsequently, for activation purposes, RTA is performed at, for example, around 1000°C to ensure conductivity.

[0150] Figure 21 The diagram shown is a cross-sectional view illustrating the formation of the source and drain electrodes in this embodiment. Figure 21 As shown, in step S48, firstly, a first source electrode 18, a first drain electrode 22, a second source electrode 36, and a second drain electrode 40 are formed in the first source region 16 and the first drain region 20 of the core device 102 and the second source region 34 and the second drain region 38 of the high voltage device 104, respectively.

[0151] Subsequently, a silicon nitride layer is formed on the entire surface of the substrate 10. The thickness of the silicon nitride layer is approximately 5 nm to 20 nm, and it can be deposited by LPCVD or PECVD. This silicon nitride layer serves as a protective layer to prevent unnecessary reactions during silanization, thereby ensuring selectivity. Subsequently, corresponding portions of the silicon nitride layer are selectively removed by photolithography and anisotropic dry etching, so that only the first source region 16 and the first drain region 20 of the core device 102, and the second source region 34 and the second drain region 38 of the high-voltage device 104 are exposed.

[0152] As needed, pre-amorphization ion implantation is also performed on the first source region 16 and the first drain region 20 of the core device 102, as well as the second source region 34 and the second drain region 38 of the high-voltage device 104. During this process, inert ions such as germanium (Ge) are implanted at low energies of several keV to disrupt the surface crystallization state. This allows the silicide reaction to occur uniformly and reduces the defect density at the interface.

[0153] Following this, a silicide treatment is performed. This involves depositing a metal such as cobalt (Co) or nickel (Ni) via sputtering or CVD to react with silicon. This reaction is accelerated by RTA and performed for a short time as the first processing stage to form an initial silicide layer. Afterward, unreacted metals are selectively removed, and a secondary annealing is performed as needed to obtain a low-resistivity silicide layer (CoSi2 or NiSi). Through this process, a first source electrode 18 and a first drain electrode 22 can be formed in the first source region 16 and the first drain region 20 of the core device 102, respectively. Similarly, a second source electrode 36 and a second drain electrode 40 can be formed in the second source region 34 and the second drain region 38 of the high-voltage device 104, respectively.

[0154] Figure 22 The diagram shown is a cross-sectional view illustrating the interlayer structure formed in this embodiment. Figure 22 As shown, in step S50, an interlayer layer 50 is first formed on the substrate 10, and then planarized by chemical mechanical polishing (CMP). Specifically, a silicon nitride layer is first formed on the surface of the substrate 10, and then a silicon oxide layer is stacked on the silicon nitride layer. The silicon nitride layer serves as a CMP stop layer. The thickness of the silicon nitride layer is approximately several nm to tens of nm. The silicon nitride layer can be formed by LPCVD or PECVD. After this, a silicon oxide layer is formed. The thickness of the silicon oxide layer is preferably greater than or equal to 20 nm and less than or equal to 1000 nm. The silicon oxide layer can be formed by tetraethoxysilane chemical vapor deposition (TEOS-CVD) or HARP oxidation. After the interlayer layer 50 is formed, surface planarization is performed by CMP. This polishing process continues until the top surfaces of the first dummy gate 68a and the second dummy gate 68b are exposed.

[0155] Figure 23 The diagram shown is a cross-sectional view of this embodiment after removing the first and second pseudo-gates. Figure 23 As shown, in step S52, the first dummy gate 68a and the second dummy gate 68b are removed. Specifically, anisotropic dry etching is performed on the first dummy gate 68a and the second dummy gate 68b exposed by CMP treatment to completely remove the polysilicon layer. This etching process can employ a plasma process, which can use chlorine-based or bromine-based gases (Cl2, HBr, etc.).

[0156] Figure 24 The diagram shown is a cross-sectional view illustrating the formation of the gate electrode in this embodiment. Figure 24 As shown, in step S54, the first gate electrode 28 of the core device 102 and the second gate electrode 46 of the high-voltage device 104 are formed. Specifically, the gate trench formed after removing the first dummy gate 68a and the second dummy gate 68b is filled with metal material and planarized using a CMP process, thereby forming the first gate electrode 28 and the second gate electrode 46.

[0157] Specifically, firstly, a metal barrier layer is formed on the first gate insulating layer 26 and the second gate insulating layer 44 on the sidewalls and bottom of the gate trench as needed. This metal barrier layer is preferably titanium nitride (TiN). The metal barrier layer can be formed by ALD or PVD. The thickness of the metal barrier layer is preferably greater than or equal to 2 nm and less than or equal to 10 nm.

[0158] Subsequently, gate metal is filled into the gate trench. The gate metal can be a conductive metal such as aluminum (Al), tungsten (W), or molybdenum (Mo). The filling method can be CVD or PVD. Furthermore, multiple layers of metal can be stacked as needed. The thickness of the first gate electrode 28 and the second gate electrode 46 allows for complete filling of the gate trench and permits removal of any remaining portion by CMP.

[0159] After filling the gate metal, the remaining portions of the first gate electrode 28 and the second gate electrode 46 are removed while exposing the surface of the interlayer layer 50 through a CMP process.

[0160] Figure 25 As shown Figure 24 A partially enlarged sectional view. Figure 26A The image shown is a cross-sectional enlarged view of the interface between the gate insulating layer and the STI in the prior art. Figure 26B The image shown is an enlarged cross-sectional view of the interface between the gate insulation layer and the STI in a high-voltage device according to an embodiment of the present invention. Figure 26A As can be seen, the thickness of the second gate insulating layer 44 at the corner region D of STI 14 is often significantly thinner than that in its central portion. It is speculated that this is because in the prior art, the corner region of STI 14 is not subjected to step S28, which exposes the substrate 10, before oxidation treatment. The oxidation process depends on the oxygen diffusion path; due to insufficient oxygen supply in the corner region adjacent to STI 14, the oxide layer cannot grow sufficiently, resulting in uneven thickness. This uneven thickness can lead to localized electric field concentration, potentially reducing the reliability of the second gate insulating layer 44 and increasing the risk of insulation breakdown.

[0161] like Figure 26BAs shown, according to this embodiment, before oxidizing the second gate insulating layer 44, step S28 is performed to etch the corner region D of the STI 14, thereby exposing a portion of the substrate 10 in the corner region of the STI 14. This allows for uniform oxygen supply during the oxidation process, resulting in a continuous second gate insulating layer 44 with a thickness approximately the same as the central portion, including the corner region of the STI 14. Furthermore, the silicon etching process softens the steep shape of the corner region of the STI 14, reducing the steps in the second gate insulating layer 44 and suppressing electric field concentration. Therefore, compared to the prior art, this embodiment significantly improves the reliability of the second gate insulating layer 44, enhances its breakdown voltage characteristics, and extends device lifetime.

[0162] Example 2

[0163] Compared with Example 1, step S28 in this example uses a different step S28'.

[0164] Figure 27 The diagram shown is a cross-sectional view illustrating the formation of the high-voltage grid region in this embodiment. Figure 27 As shown, the purpose of the etching process in step S28' is to mitigate the steepness of the corner shape near the junction of STI 14 and substrate 10 in the high-voltage device 104. This process enables the formation of a uniform oxide layer thickness during the formation of the second gate insulating layer 44, thereby improving reliability.

[0165] Step S28' includes the following in detail:

[0166] First, the silicon oxide layer in region C of STI 14 exposed in the opening is further etched.

[0167] In addition to etching STI 14 in step S28, isotropic etching is performed on the silicon to round the corner region G near the junction of STI 14 and substrate 10. During the isotropic etching process, fluorocarbon gases such as CF4 can be converted into plasma, allowing the F radicals in the plasma to chemically react with the silicon, converting it into volatile SiF4. Alternatively, reactive halogen gases such as XeF2 can react directly with the silicon of substrate 10, thereby removing surface solids through chemical dissolution. This method does not require plasma; simply introducing gas in a pulsed manner into the vacuum reaction chamber allows for control of the reaction, achieving high isotropy and selectivity. This step, by rounding the sharp corners through isotropic etching, further eliminates electric field concentration points, resulting in more uniform gate oxide layer growth and significantly improving the long-term reliability and breakdown resistance of the device.

[0168] Among them, CF4 plasma or XeF2 gas has excellent isotropic etching characteristics on silicon, which can efficiently and controllably achieve smoothing of corner areas and obtain ideal curved surface shapes.

[0169] Figure 28 As shown Figure 27 Enlarged sectional view of block diagram E. (See attached image.) Figure 28 As shown, by employing isotropic etching, the steep shape of the corner region G of the substrate 10 can be softened, transforming it into a smooth shape with a radius of curvature. This shape change reduces the local differences in oxidation rate during the formation of the second gate insulating layer 44, thereby making the thickness of the formed second gate insulating layer 44 more uniform.

[0170] Example 3

[0171] Compared with Example 1, step S28 in this example uses a different step S28''.

[0172] Figure 29 The diagram shown is a cross-sectional view of the high-voltage grid region formed in Embodiment 3 of the present invention. Figure 30A As shown Figure 29 Enlarged sectional view of block diagram F. Figure 30B The diagram shown is a cross-sectional view of the substrate corner region after smoothing treatment according to Embodiment 3 of the present invention. Figure 29 , Figures 30A-30B As shown, the purpose of the etching process in step S28'' is to first form an oxide layer 70 by oxidizing the surface of the substrate 10, and then to mitigate the steepness of the corner shape near the junction of the STI 14 and the substrate 10 in the high-voltage device 104 by removing the oxide layer 70. In other words, instead of directly etching the substrate 10, the corner region G obtains a smooth curved shape by forming the oxide layer 70 and then removing it.

[0173] Detailed, such as Figure 30A As shown, the portion of STI 14 exposed adjacent to substrate 10 after etching in step S28 is oxidized to form oxide layer 70. This oxidation process is, for example, a thermal oxidation process performed in an oxygen atmosphere or an atmosphere containing water vapor. The oxidation temperature can be, for example, in the range of 900°C to 1100°C. The thickness of oxide layer 70 is preferably greater than or equal to 1 nm and less than or equal to 20 nm. Thermal oxidation within this temperature range results in the best growth rate and oxide layer quality; controlling the thickness within this range allows for precise control of the removal amount per cycle, which is beneficial for achieving a smooth and uniform corner morphology.

[0174] like Figure 30BAs shown, the formed oxide layer 70 is then removed by wet etching with an aqueous solution of hydrofluoric acid (HF) or buffered ammonium fluoride (BHF). The oxide layer 70 is completely removed, exposing the surface of the substrate 10 again. This oxidation and etching process can be repeated multiple times as needed to obtain a smooth corner shape with curvature for the substrate 10.

[0175] By employing a cyclic "oxidation-stripping" process, alternating between thermal oxidation and wet etching, corner smoothing can be achieved gently and in a highly controllable manner, avoiding surface damage and roughness issues that may result from direct silicon etching. In other words, this process softens the steep shape of the corner region of the substrate 10, transforming it into a smooth shape with a radius of curvature. This shape change reduces local differences in oxidation rates during the formation of the second gate insulating layer 44, resulting in a more uniform thickness of the formed second gate insulating layer 44.

[0176] In summary, this invention provides a semiconductor device and its manufacturing method. The manufacturing method includes the following steps: forming a shallow trench isolation structure in a substrate; etching the surface of the substrate in a gate formation region adjacent to the shallow trench isolation structure; partially etching the shallow trench isolation structure adjacent to the gate formation region to expose the corner region of the substrate; and oxidizing the gate formation region to form a gate insulating layer. This invention, by actively etching the corner region of the shallow trench isolation structure before gate oxide oxidation, ensures sufficient oxygen supply in this region during subsequent oxidation, thereby forming a gate oxide layer of uniform thickness. This fundamentally solves the technical problem of thinning gate oxide at the corner of the shallow trench isolation structure, significantly improving the reliability and withstand voltage characteristics of high-voltage devices.

[0177] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0178] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A shallow trench isolation structure is formed in the substrate; In the gate formation region adjacent to the shallow trench isolation structure, the surface of the substrate is etched; Partial etching is performed on the shallow trench isolation structure adjacent to the gate formation region to expose the corner region of the substrate; The gate forming region is oxidized to form a gate insulating layer.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps for partially etching the shallow trench isolation structure include: The shallow trench isolation structure was wet-etched using a hydrofluoric acid solution.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps for etching the surface of the substrate are as follows: The surface of the substrate is subjected to anisotropic dry etching using a gas containing HBr or Cl2.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After partially etching the shallow trench isolation structure, the process also includes: Isotropic etching is performed on the corner region of the substrate to round the corner region.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The isotropic etching uses CF4 plasma or XeF2 gas.

6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After partially etching the shallow trench isolation structure, the process also includes: The exposed corner regions of the substrate are oxidized to form an oxide layer; Remove the oxide layer to smooth the corner area.

7. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The oxidation process is thermal oxidation at a temperature of 900℃~1100℃, and the oxide layer thickness is 1nm~20nm.

8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps of partially etching the shallow trench isolation structure and etching the substrate surface are performed using the same mask layer.

9. A semiconductor device, manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 8, characterized in that, include: Substrate; Shallow trench isolation structures formed in the substrate; A high-voltage device formed on the substrate, the high-voltage device including a gate insulating layer, the thickness of the gate insulating layer at the corner region of the shallow trench isolation structure being uniform with the thickness of its central region.

10. The semiconductor device as claimed in claim 9, characterized in that, The gate insulation layer of the high-voltage device has a thickness of 50nm to 200nm, and the corner region has a smooth curved surface structure.

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