Board-level packaging structure for chip with vertical structure and manufacturing method of board-level packaging structure
By employing copper-clad laminate and through-through post design in the packaging of vertical structure chips, the problem of poor support in traditional packaging frames is solved, achieving a high-density, low-cost packaging structure and improving the stability of the current path and heat dissipation efficiency.
Patent Information
- Application Number
- CN202511634396.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional packaging frameworks cannot meet the requirements of high density, modularity and low cost, especially in the packaging of vertical structure chips. They have problems such as poor support, easy deformation, pad misalignment and solder joint damage, making it difficult to guarantee the stability of electrode connection and packaging density.
Using copper-clad laminate as the core board and built-in through-conducting posts as a unified carrier, combined with refined connecting rib design and reinforced bumps, a vertical interconnect channel is constructed to provide a stable current path and mechanical support, and simplify the function of connecting ribs to improve pin density and processing accuracy.
It improves the mechanical stability and electrical performance of the package, shortens the current conduction distance, reduces impedance, enhances heat dissipation, increases the number of pins and panel utilization, and ensures the reliability of electrode connections and package density.
Smart Images
Figure CN121510985A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip manufacturing technology, and in particular to a board-level packaging structure for vertical structure chips and its manufacturing method. Background Technology
[0002] Traditional packaging mainly consists of a packaging frame, chip, bonding wires, and molding compound. As electronic products continue to evolve towards thinner, lighter, and higher-performance designs, the size of the packaging frame is also constantly evolving towards ultra-thinness. In current technology, integrated circuit chips, power devices, and LED chips are typically manufactured using a full-board packaging frame. This frame is generally made of copper material with a hollow structure formed by double-sided etching (e.g., ...). Figure 1 As shown in the figure, it includes the chip and wire bonding base island, the main connecting rib, and the secondary connecting rib between the connecting base island and the main connecting rib.
[0003] However, traditional packaging frames are increasingly unable to meet the current packaging industry's requirements for high density, modularity, and large-scale low cost. On the one hand, high-temperature tape needs to be attached to the bottom of the copper material during the packaging process to complete steps such as chip mounting, wire bonding, and molding. However, when the copper material is too thin, double-sided etching can easily cause frame deformation and reduce yield. At the same time, the high-temperature tape can easily cause problems such as excess adhesive and residual adhesive. On the other hand, the hollow structure of the whole board frame has poor support and needs to rely on thicker main connecting ribs and thinner secondary connecting ribs for support. This not only limits the improvement of pin density but also reduces processing efficiency.
[0004] Typically, the back substrate of a chip serves as its electrode, and there are also electrode pads on the back that need to be conductive. This type of chip is mainly used for discrete devices, such as LED chips where a metal electrode is formed on the back after the substrate is removed. Power devices like MOSFETs use a back metal layer as their electrode, and 3D IC packages use through-silicon vias (TSVs) to bring signals to the back metal layer as interconnect electrodes. Because the current or signal flows perpendicular to the chip surface and from the top electrode to the bottom electrode, it is called a vertical structure chip. Therefore, these types of chips are referred to as vertical structure chips in the industry. The problems mentioned earlier are particularly prominent in the packaging applications of vertical structure chips. This type of vertical structure design requires electrode leads and external interconnections to be implemented on the back, but the traditional frame's hollow structure has poor support, easily leading to problems such as pad misalignment and solder joint damage during alignment, mounting, molding, and cutting. It is difficult to ensure the stability of electrode connections and packaging density in large-scale board-level processing.
[0005] Therefore, how to provide a board-level packaging structure and its manufacturing method for vertical structure chips, while ensuring reliable conduction of the back electrode and unobstructed vertical current path, and improving mechanical stability, processing accuracy and pin density, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0006] The main objective of this invention is to provide a board-level packaging structure and its manufacturing method for vertical chips, aiming to solve the technical problems of poor conductivity, poor support performance and low processing density of vertical chips on traditional board-level fan-out packaging carrier frames.
[0007] To achieve the above objectives, the present invention provides a board-level packaging structure for vertical structure chips, characterized in that it comprises: a core board having a plurality of interconnected chip packaging units, each chip packaging unit having a base island and a connecting pad, and a first conductive post and a second conductive post penetrating the core board respectively disposed under the base island and the connecting pad; at least two first connecting ribs are disposed around the periphery of the base island, the first connecting ribs connecting to the base island of an adjacent chip packaging unit in the vertical direction, and a second connecting rib is disposed around the periphery of the connecting pad, the second connecting rib connecting to the base island of an adjacent chip packaging unit in the horizontal direction; a packaged chip mounted on the base island, a conductive structure being provided between the top pad of the packaged chip and the connecting pad; the two ends of the conductive structure being connected to the top pad of the packaged chip and the connecting pad respectively; a first packaging layer disposed on the core board, covering the packaged chip and the conductive structure; the base island being connected to the bottom of the core board through the first conductive post, and the connecting pad being connected to the top pad of the packaged chip through the second conductive post and the conductive structure.
[0008] Preferably, the conductive structure includes a third conductive post, a fourth conductive post, and a first circuit layer. The lower part of the third conductive post is connected to the upper pad of the packaged chip, the upper part of the third conductive post is connected to one end of the first circuit layer, the lower part of the fourth conductive post is connected to the connecting pad, and the upper part of the fourth conductive post is connected to the other end of the first circuit layer.
[0009] Preferably, the first connecting rib and the second connecting rib are provided with reinforcing protrusions, which are embedded in the first encapsulation layer.
[0010] Preferably, the first encapsulation layer has a wiring layer on the side facing away from the core board, one of the wiring layers being connected to the second conductive post; and the other wiring layer being connected to the first conductive post.
[0011] This invention also provides a method for manufacturing a board-level packaging structure for vertically oriented chips, characterized by comprising: step S100: setting a plurality of interconnected chip packaging units on a core board, and drilling a first via and a second via within the chip packaging units; step S200: forming a metal seed layer within the first via, the second via, and on the surface of the core board; step S300: fabricating base islands and connecting pads based on the metal seed layer, wherein a first connecting rib is formed on the periphery of the base island, the first connecting rib being connected to the base island in the vertically adjacent chip packaging unit, and the connecting pad having a periphery formed... A second connecting rib is formed, and the second connecting rib is connected to the base island in the chip packaging unit adjacent in the horizontal direction; Step S400: The packaged chip is mounted on the first circuit layer of the base island; Step S500: The first encapsulation is performed on the core board to form a first packaging layer, and a conductive structure is made in the packaging layer, the conductive structure electrically connecting the packaged chip and the second connecting rib respectively; Step S600: A pair of wiring layers are made on the bottom surface of the core board, and the two wiring layers are respectively connected to the first connecting rib and the second connecting rib; Step S700: The packaged product is obtained by cutting along the boundary of the chip packaging unit.
[0012] Preferably, in step S500, a third via and a fourth via are drilled in the first encapsulation layer. The third via exposes the pad of the encapsulation chip, and the bottom of the fourth via connects to the second connecting rib. The third via and the fourth via are then electroplated to fill the holes, forming a third via and a fourth via respectively. The process also includes step S510: filling the third via and the fourth via, and sequentially performing film application, exposure, development, etching, and film removal processes on the first encapsulation layer to form a first circuit layer. The first circuit layer electrically connects the encapsulation chip and the second connecting rib.
[0013] Preferably, the second encapsulation layer is formed by molding the first encapsulation layer, and the second encapsulation layer covers the first circuit layer.
[0014] Preferably, in step S300, the first connecting rib and the second connecting rib are formed by sequentially performing electroplating, applying photosensitive dry film, pattern exposure, development, etching and removing dry film on the core board, wherein the photosensitive dry film is applied to the first connecting rib and the second connecting rib.
[0015] Preferably, step S100 further includes drilling a pair of fifth vias within the chip packaging unit; step S300 further includes electroplating to fill the fifth vias to form reinforcing bumps, one of the reinforcing bumps being connected to the first connecting rib and the other of the reinforcing bumps being connected to the second connecting rib.
[0016] Preferably, the method further includes step S310: forming a second metal seed layer on the first connecting rib and the second connecting rib, and sequentially performing a photosensitive dry film application, pattern exposure, development, pattern electroplating and dry film removal processes to form at least one reinforcing bump, wherein at least one reinforcing bump is located on the first connecting rib and at least one reinforcing bump is located on the second connecting rib.
[0017] The technical solution provided by this invention differs from traditional packaging frames. The frame used in the board-level fan-out package is copper-clad laminate, which consists of a core material (prepreg) and copper foil. By employing a core board with built-in through-through conductive posts as a unified carrier, this structure utilizes the mechanical strength of the core board itself to provide overall support, replacing the traditional hollow frame that relies on main connecting ribs. This avoids the deformation problem of ultra-thin frames during processing and provides a stable foundation for the positioning and connection of the back electrodes of vertical structure chips. In this structure, the function of the connecting ribs is simplified, and their design can be developed towards finer linewidths and higher distribution densities, directly increasing the number of pins in the package and the panel utilization rate. Furthermore, this solution constructs a vertical interconnect channel penetrating the package body by combining the conductive posts inside the core board with the connecting ribs on the surface, establishing a direct current path for the vertical structure chip. This path shortens the current conduction distance, reduces impedance, and provides an effective heat dissipation path, thereby supporting the performance of the chip's electrical properties. Attached Figure Description
[0018] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0019] Figure 1 This is a schematic diagram of an embodiment of a conventional board-level packaging carrier structure; Figure 2 This is a schematic flowchart of the board-level packaging structure manufacturing method for vertical structure chips according to the present invention. Figure 3 This is a schematic diagram of a structure of an embodiment of the board-level packaging carrier for vertical structure chips according to the present invention; Figure 4 This is a schematic diagram of a cross-section of a chip packaging unit in a board-level packaging structure for vertical structure chips according to the present invention. Figure 5 This is a schematic diagram of a cross-section of a chip packaging unit in a board-level packaging structure for vertical structure chips according to the present invention. Figure 6 This is a schematic diagram of a cross-section of a chip packaging unit in a board-level packaging structure for vertical structure chips according to the present invention. Figure 7 This is a schematic diagram of a cross-section of a chip packaging unit in a board-level packaging structure for vertical structure chips according to the present invention. Figure 8 This is a partial structural diagram of the connecting rib in the board-level packaging structure for vertical structure chips according to the present invention. Figure 9 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 10 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 11 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 12 This is a schematic diagram of one embodiment of the board-level packaging structure for vertical structure chips according to the present invention; Figure 13 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 14 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 15 This is a schematic diagram of one embodiment of the board-level packaging structure for vertical structure chips according to the present invention; Figure 16 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 17 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 18 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention. Figure 19 This is a schematic diagram of a partial processing flow of the manufacturing method of the board-level packaging structure for vertical structure chips according to the present invention.
[0020] In the diagram: 1. Core board; 11. Chip packaging unit; 110. Base island; 111. Connecting pad; 21. First connecting rib; 211. First conductive post; 22. Second connecting rib; 221. Second conductive post; 23. Photosensitive dry film; 24. Electroplating layer; 25. Reinforcing bump; 26. Main body; 27. Bifurcation; 4. First encapsulation layer; 5. Second encapsulation layer; 51. Third conductive post; 52. Fourth conductive post; 6. Wiring layer; 7. Packaged chip; 71. Conductive structure; 711. First circuit layer; 72. Thickened layer; 81. First via; 82. Second via; 91. Main connecting rib; 92. Secondary connecting rib. Detailed Implementation
[0021] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected to" another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Thus, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.
[0022] Furthermore, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections via an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.
[0023] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0024] Please refer to Figure 11 and Figure 14 This invention provides a board-level packaging structure for vertically oriented chips, comprising: a core board 1, having a plurality of interconnected chip packaging units 11, each chip packaging unit 11 having a base island 110 and a connecting pad 111, with a first conductive post 211 and a second conductive post 221 penetrating the core board 1 respectively disposed under the base island 110 and the connecting pad 111; at least two first connecting ribs 21 are disposed on the periphery of the base island 110, the first connecting ribs 21 connecting to the base island 110 of an adjacent chip packaging unit 11 in the vertical direction, and a second connecting rib 22 is disposed on the periphery of the connecting pad 111. The connecting rib 22 connects the base island 110 of an adjacent chip packaging unit 11 in the horizontal direction; the packaged chip 7 is mounted on the base island 110, and a conductive structure 71 is provided between the top pad of the packaged chip 7 and the connecting pad 111; the two ends of the conductive structure 71 are respectively connected to the top pad of the packaged chip 7 and the connecting pad 111; the first packaging layer 4 is disposed on the core board 1, covering the packaged chip 7 and the conductive structure 71; the base island 110 is connected to the bottom of the core board 1 through the first conductive post 211, and the connecting pad 111 is connected to the top pad of the packaged chip 7 through the second conductive post 221 and the conductive structure 71.
[0025] In the technical solution provided by this invention, unlike the traditional packaging frame 9, the frame 9 used in the board-level fan-out package is copper-clad laminate. The copper-clad laminate consists of a core material (prepreg) and copper foil. By using a core board 1 with built-in through-through conductive posts as a unified carrier, this structure utilizes the mechanical strength of the core board 1 itself to bear the overall support, replacing the traditional hollow frame 9 that relies on main connecting ribs. This avoids the deformation problem of the ultra-thin frame 9 during processing and provides a stable foundation for the positioning and connection of the back electrode of the vertical structure chip. In this structure, the function of the connecting ribs is simplified, and their design can be developed towards finer linewidths and higher distribution density, directly increasing the number of pins in the package and the panel utilization rate. Furthermore, this solution combines the conductive posts in the core board 1 with the connecting ribs on the surface to construct a vertical interconnect channel that penetrates the package, establishing a direct current path for the vertical structure chip. This path shortens the current conduction distance, reduces impedance, and provides an effective heat dissipation path, thereby supporting the performance of the chip's electrical properties.
[0026] Please refer to Figure 11 and Figure 14The conductive structure 71 includes a third conductive post 51, a fourth conductive post 52, and a first circuit layer 711. The lower part of the third conductive post 51 is connected to the upper pad of the packaged chip 7, and the upper part of the third conductive post 51 is connected to one end of the first circuit layer 711. The lower part of the fourth conductive post 52 is connected to the connecting pad 111, and the upper part of the fourth conductive post 52 is connected to the other end of the first circuit layer 711. This conductive structure 71 enables cross-region electrical connections, providing the chip with highly flexible top surface wiring capabilities. This design transfers some lateral interconnect lines from the core board layer 1 to the top of the package layer, effectively reducing the complexity and density requirements of the core board layer 1 wiring, creating conditions for implementing more complex multi-chip interconnects or high-density I / O leads within a limited space.
[0027] Please refer to Figures 3 to 18 The first connecting rib 21 and the second connecting rib 22 are provided with reinforcing bumps 25, which are embedded in the first encapsulation layer 4. As a reinforcing skeleton embedded inside the encapsulation material, the reinforcing bumps 25 can effectively restrain the encapsulation material, reduce its warping deformation during the curing process, and together with the core plate 1 below, form a stable mortise and tenon support structure. This improves the mechanical stress and thermal stress resistance of the entire encapsulation carrier in subsequent processing, while preventing the connecting ribs from pulling on the pads of the encapsulation chip 7, reducing the probability of solder balls falling off the pads.
[0028] Please refer to Figure 11 and Figure 14 The first encapsulation layer 4 has a wiring layer 6 on the side facing away from the core board 1. One wiring layer 6 is connected to the second conductive post 221; another wiring layer 6 is connected to the first conductive post 211. This structure directly forms the external electrode of the encapsulation structure. Through the low impedance path formed by the large-area wiring layer 6, the electrical connection performance and heat dissipation efficiency between the encapsulation body and the external circuit are optimized.
[0029] Please refer to Figures 4 to 7 The first connecting rib 21, the second connecting rib 22, and the reinforcing protrusion 25 are provided with a main body 26 and a branch portion 27. The main body 26 is straight, and the branch portion 27 is provided on one or both sides of the main body 26. The shape of the branch portion 27 includes rectangle, trapezoid, and continuous curved shape, which increases the bonding area between the connecting rib and the encapsulation layer in the lateral direction, thereby significantly improving the adhesion strength between the connecting rib and the encapsulation layer and helping to block the concentrated transmission of cutting stress. The angle between the branch portion 27 and the main body 26 is in the range of 0-45°, which can ensure that the branch portion 27 has effective extension and embedding force while maintaining a compact structure, thereby taking into account both stress dispersion effect and process feasibility, and further improving the resistance of the connecting rib to cutting stress.
[0030] Please refer to Figures 3 to 18The present invention also provides a method for manufacturing a board-level packaging structure for vertical structure chips, comprising: step S100: setting a plurality of interconnected chip packaging units 11 on a core board 1, and drilling a first through hole 81 and a second through hole 82 in the chip packaging unit 11; step S200: forming a metal seed layer in the first through hole 81, the second through hole 82 and on the surface of the core board 1; step S300: fabricating a base island 110 and a connecting pad 111 based on the metal seed layer, wherein a first connecting rib 21 is formed on the periphery of the base island 110, the first connecting rib 21 is connected to the base island 110 in the vertically adjacent chip packaging unit 11, and the connecting pad 111 is formed on the periphery of the base island 110. A second connecting rib 22 is formed on the side, and the second connecting rib 22 is connected to the base island 110 in the chip packaging unit 11 adjacent in the horizontal direction; Step S400: The packaged chip 7 is mounted on the first circuit layer 711 of the base island 110; Step S500: The first packaging layer 4 is formed by first molding on the core board 1, and a conductive structure 71 is made in the packaging layer, which electrically connects the packaged chip 7 and the second connecting rib 22 respectively; Step S600: A pair of wiring layers 6 are made on the bottom surface of the core board 1, and the two wiring layers 6 are connected to the first connecting rib 21 and the second connecting rib 22 respectively; Step S700: The packaged product is obtained by cutting along the boundary of the chip packaging unit 11.
[0031] This manufacturing method effectively overcomes the problems of processing deformation, misalignment, and low yield caused by insufficient structural support in traditional hollow frames 9. Simultaneously, the collaborative design of the core board 1 and the connecting ribs, while ensuring structural stability, creates conditions for the finer and higher-density design of the connecting ribs, thereby significantly improving the pin density of the package. Furthermore, this manufacturing process establishes a stable, low-impedance vertical current path for the vertical structure chip by systematically constructing vertical interconnect channels (such as vias, connecting ribs, and circuit layers) inside and on the surface of the core board 1.
[0032] Please refer to Figures 11 to 14In step S500, a third and a fourth via are drilled within the first encapsulation layer 4. The third via exposes the pads of the packaged chip 7, and the bottom of the fourth via connects to the second connecting rib 22. Electroplating fills the third and fourth vias, forming a third via 51 and a fourth via 52, respectively. The method also includes step S510: filling the third and fourth vias, and sequentially performing film application, exposure, development, etching, and film removal processes on the first encapsulation layer 4 to form a first circuit layer 711. The first circuit layer 711 electrically connects the packaged chip 7 and the second connecting rib 22. By creating vias within the first encapsulation layer 4 and patterning them to form the second circuit layer, this method achieves an electrical connection between the packaged chip 7 and the second connecting rib 22 at the top of the molding compound. This process moves some of the lateral interconnect lines from the core board 1 layer to the top of the package layer, reducing the density pressure of the core board 1 wiring and providing design flexibility for more complex multi-chip interconnects or high-density I / O fan-out within a single package, while avoiding the complex processes involved in adding extra lines to the core board 1 layer.
[0033] Please refer to Figures 11 to 14 A second encapsulation layer 5 is formed by molding the first encapsulation layer 4, and the second encapsulation layer 5 covers the first circuit layer. This encapsulation layer can effectively prevent the second circuit layer from oxidizing, scratching or short-circuiting during subsequent processing and use, and enhances the overall insulation and mechanical strength of the package, thereby improving the long-term operational reliability of the final packaged product in harsh environments.
[0034] Please refer to Figures 15 to 18 In step S300, electroplating, applying photosensitive dry film 23, pattern exposure, development, etching, and dry film removal are sequentially performed on the core board 1 to form the first connecting rib 21 and the second connecting rib 22, wherein the photosensitive dry film 23 is applied to the first connecting rib 21 and the second connecting rib 22. This process adopts a subtractive method, first depositing metal in the electroplating area, and then using the photosensitive dry film 23 and pattern etching process to remove the metal in the non-electroplated areas. This ensures that the electroplated layer 24 is retained only at the target pattern position, improves the accuracy and consistency of the circuit and connecting ribs, avoids electrical failures caused by residual metal, and facilitates high-density wiring.
[0035] Please refer to Figures 8 to 18Step S100 further includes drilling a pair of fifth vias within the chip packaging unit 11; step S300 further includes electroplating to fill the fifth vias to form reinforcing bumps 25, one reinforcing bump 25 being connected to the first connecting rib 21 and the other reinforcing bump 25 being connected to the second connecting rib 22. Step S310 further includes forming a second metal seed layer on the first connecting rib 21 and the second connecting rib 22, and sequentially performing a photosensitive dry film 23 application, pattern exposure, development, pattern electroplating, and dry film removal processes to form at least one reinforcing bump 25, with at least one reinforcing bump 25 located on the first connecting rib 21 and at least one reinforcing bump 25 located on the second connecting rib 22. This solution, by further forming reinforcing bumps 25 on the existing connecting ribs, allows the connecting ribs to extend vertically and embed into the packaging layer, enhancing the adhesion and bonding strength between the metal ribs and the molding material, effectively dispersing and blocking the transmission path of cutting stress, and improving the overall packaging reliability.
[0036] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A board-level packaging structure for vertically oriented chips, characterized in that, include: The core board (1) is provided with a number of connected chip packaging units (11). Each chip packaging unit (11) is provided with a base island (110) and a connecting pad (111). A first conductive post (211) and a second conductive post (221) penetrating the core board (1) are respectively provided under the base island (110) and the connecting pad (111). The base island (110) is provided with at least two first connecting ribs (21) on its periphery. The first connecting ribs (21) connect to the base island (110) of an adjacent chip packaging unit (11) in the vertical direction. The connecting pad (111) is provided with a second connecting rib (22) on its periphery. The second connecting rib (22) connects to the base island (110) of an adjacent chip packaging unit (11) in the horizontal direction. A packaged chip (7) is mounted on the base island (110), and a conductive structure (71) is provided between the top pad of the packaged chip (7) and the connecting pad (111). The two ends of the conductive structure (71) are respectively connected to the top pad and the connecting pad (111) of the packaged chip (7). The first encapsulation layer (4) is disposed on the core board (1) and covers the encapsulated chip (7) and the conductive structure (71). The base island (110) is connected to the bottom of the core board (1) through the first conductive post (211), and the connecting pad (111) is connected to the top pad of the packaged chip (7) through the second conductive post (221) and the conductive structure (71).
2. The board-level packaging structure for vertical structure chips according to claim 1, characterized in that, The conductive structure (71) includes a third conductive post (51), a fourth conductive post (52), and a first circuit layer (711). The lower part of the third conductive post (51) is connected to the upper pad of the packaged chip (7), the upper part of the third conductive post (51) is connected to one end of the first circuit layer (711), the lower part of the fourth conductive post (52) is connected to the connecting pad (111), and the upper part of the fourth conductive post (52) is connected to the other end of the first circuit layer (711).
3. The board-level packaging structure for vertical structure chips according to claim 2, characterized in that, The first connecting rib (21) and the second connecting rib (22) are provided with reinforcing bumps (25), which are embedded in the first encapsulation layer (4).
4. The board-level packaging structure for vertical structure chips according to claim 3, characterized in that, The first encapsulation layer (4) Deviation One side of the core board (1) is provided with a wiring layer (6), one of the wiring layers (6) is connected to the second conductive post (221); and one of the wiring layers (6) is connected to the first conductive post (211).
5. A method for manufacturing a board-level packaging structure for vertically oriented chips, characterized in that, include: Step S100: A plurality of connected chip packaging units (11) are set on the core board (1), and a first through hole (81) and a second through hole (82) are drilled in the chip packaging unit (11). Step S200: A metal seed layer is formed in the first through hole (81), the second through hole (82), and on the surface of the core plate (1); Step S300: Based on the metal seed layer, a base island (110) and a connecting pad (111) are fabricated, wherein a first connecting rib (21) is formed on the periphery of the base island (110), the first connecting rib (21) is connected to the base island (110) in the vertically adjacent chip packaging unit (11), and a second connecting rib (22) is formed on the periphery of the connecting pad (111), the second connecting rib (22) is connected to the base island (110) in the horizontally adjacent chip packaging unit (11); Step S400: Mount the packaged chip (7) onto the first circuit layer (711) of the base island (110); Step S500: A first encapsulation layer (4) is formed on the core board (1) and a conductive structure (71) is made in the encapsulation layer. The conductive structure (71) is electrically connected to the encapsulated chip (7) and the second connecting rib (22). Step S600: A pair of wiring layers (6) are made on the bottom surface of the core plate (1), and the two wiring layers (6) are respectively connected to the first connecting rib (21) and the second connecting rib (22); Step S700: Cut along the boundary of the chip packaging unit (11) to obtain the packaged product.
6. The method for manufacturing a board-level packaging structure for a vertical chip according to claim 5, characterized in that, In step S500, a third through hole and a fourth through hole are drilled in the first encapsulation layer (4). The third through hole exposes the pad of the encapsulation chip (7). The bottom of the fourth through hole is connected to the second connecting rib (22). The third through hole and the fourth through hole are filled by electroplating to form a third through post (51) and a fourth through post (52) respectively. It also includes step S510: filling the third and fourth through holes, and performing a first circuit layer (711) on the first packaging layer (4) by sequentially applying a film, exposing, developing, etching and removing the film. The first circuit layer (711) is electrically connected to the packaged chip (7) and the second connecting rib (22).
7. The method for manufacturing a board-level packaging structure for a vertical chip according to claim 6, characterized in that, A second encapsulation layer (5) is formed by molding the first encapsulation layer (4), and the second encapsulation layer (5) covers the first circuit layer (711).
8. The method for manufacturing a board-level packaging structure for a vertical chip according to claim 7, characterized in that, In step S300, the first connecting rib (21) and the second connecting rib (22) are formed by electroplating, applying photosensitive dry film (23), pattern exposure, development, etching and removing dry film in sequence on the core board (1), wherein the photosensitive dry film (23) is applied to the first connecting rib (21) and the second connecting rib (22).
9. The method for manufacturing a board-level packaging structure for a vertical chip according to claim 8, characterized in that, Step S100 also includes drilling a pair of fifth through holes in the chip packaging unit (11); Step S300 further includes electroplating to fill the fifth through hole to form a reinforcing bump (25), one of the reinforcing bumps (25) being connected to the first connecting rib (21), and another of the reinforcing bumps (25) being connected to the second connecting rib (22).
10. The method for manufacturing a board-level packaging structure for a vertical chip according to claim 9, characterized in that, It also includes step S310: forming a second metal seed layer on the first connecting rib (21) and the second connecting rib (22), and sequentially performing the processes of applying photosensitive dry film (23), pattern exposure, development, pattern electroplating and dry film removal to form at least one reinforcing bump (25), wherein at least one reinforcing bump (25) is located on the first connecting rib (21) and at least one reinforcing bump (25) is located on the second connecting rib (22).