User calibration-free isolation metering chip and metering method

Abstract

The invention discloses a user calibration-free isolation metering chip and a metering method, and belongs to the technical field of integrated circuits. The metering chip comprises a first sub-chip, a second sub-chip, a substrate and a packaging frame, wherein the first sub-chip is used for rectifying a high-frequency signal into a direct-current voltage; sampling the current and the voltage, and processing a sampling signal to obtain a metering signal; the second sub-chip is used for modulating an external input direct-current voltage into a high-frequency signal and sending the high-frequency signal to the first sub-chip through the substrate; receiving the metering signal sent by the first sub-chip, and processing the metering signal; the substrate is used for isolating and transmitting energy and signals between the first sub-chip and the second sub-chip; the packaging frame is provided with a frame parasitic resistor, and the first sub-chip, the second sub-chip and the substrate are sealed together through customized packaging. According to the metering chip, further calibration of a user at a system level in a traditional scheme can be omitted, isolation of high-voltage and low-voltage side signals and a power supply is achieved through a single chip, the system integration degree is improved, and the cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a user-calibration-free isolated metering chip and metering method. Background Technology

[0002] Current common electricity metering schemes require dedicated shunt resistors for current acquisition, and dedicated metering chips to convert current and voltage information into digital signals, calculate power and RMS values, and then use a microprocessor to perform electricity metering. However, since the signal acquisition end is on the 220V high-voltage side and the main control board with the microprocessor as its core is on the low-voltage side, the power supply and communication between the two need to be isolated between strong and weak currents. However, existing isolation power supplies and digital signal isolators are expensive, resulting in high development costs for users.

[0003] Furthermore, existing solutions use alloy resistors such as manganese copper for the shunt resistors to ensure temperature stability and avoid measurement errors caused by self-heating. However, the shunt resistors in existing solutions must be implemented using discrete components, which is expensive. When integrated with the metering chip, users need additional system-level calibration to meet measurement accuracy requirements, further increasing development costs. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide a user-calibration-free isolated metering chip and metering method to address the shortcomings of the prior art.

[0005] To address the aforementioned technical problems, in a first aspect, a user-calibration-free isolated metering chip is disclosed, comprising a first sub-chip, a second sub-chip, a substrate, and a packaging frame.

[0006] The first sub-chip is used to receive high-frequency signals sent by the second sub-chip, rectify the high-frequency signals into DC voltage, and use the DC voltage to power the first sub-chip; sample the current and voltage to obtain sampling signals, process the sampling signals to obtain metering signals, and send the metering signals to the second sub-chip;

[0007] The second sub-chip is used to modulate the external input DC voltage into a high-frequency signal, and send the high-frequency signal to the first sub-chip through the substrate; it also receives the metering signal sent by the first sub-chip, processes the metering signal, and obtains the processed signal.

[0008] The substrate is used to isolate and transmit signals between the first sub-chip and the second sub-chip.

[0009] The packaging frame is used to carry the first sub-chip, the second sub-chip, and the substrate; a frame parasitic resistor is provided on the packaging frame, and the frame parasitic resistor is used to realize current sampling.

[0010] The first sub-chip, the second sub-chip, and the substrate are encapsulated together using a custom packaging framework.

[0011] Furthermore, the external current passes through the package frame, forming a voltage drop across the frame's parasitic resistance. This voltage drop is used to read the current value through the first sub-chip. Existing solutions using off-chip shunt resistors require additional system-level calibration when integrated with the metering chip, further increasing development costs. The frame parasitic resistance in this application is equivalent to the shunt resistor, and by integrating the frame parasitic resistance onto the package frame, the complete metering chip, including the frame parasitic resistance, can achieve high-precision chip-level calibration at the factory stage, eliminating the need for further system-level calibration in traditional solutions and reducing overall calibration costs.

[0012] Furthermore, a coil is provided on the substrate, and the second sub-chip transmits the high-frequency signal to the first sub-chip through coil isolation. The first sub-chip is the current and voltage signal sampling terminal, which is the high-voltage side, while the second sub-chip communicates with the peripheral chip (main control board), which is the low-voltage side. The high-frequency signal is rectified into DC voltage by the first sub-chip to provide power to the first sub-chip. The power is transmitted through the substrate coil to achieve strong and weak voltage isolation, which facilitates system integration with the main control board.

[0013] Furthermore, the first sub-chip transmits the metering signal to the second sub-chip via a first isolation medium. The metering signal is transmitted through the first isolation medium, achieving signal isolation. The aforementioned user-calibration-free isolated metering chip achieves high-voltage and low-voltage side signal isolation and power supply isolation on a single chip, realizing isolated metering, improving system integration, and reducing costs.

[0014] Furthermore, the first sub-chip includes a rectifier, a metering module, and a signal transmitter. The rectifier is used to rectify the high-frequency signal into the DC voltage. The metering module is used to sample the current and voltage to obtain a sampled signal and process the sampled signal to obtain a metering signal. The signal transmitter is used to send the metering signal to the second sub-chip through a first isolation medium.

[0015] Furthermore, the first sub-chip also includes a clock recovery circuit, which extracts a clock signal from the high-frequency signal. This clock signal is used to provide a clock for the first sub-chip. Clock synchronization is achieved through high-frequency signal transmission, avoiding the need for additional clock generation or clock isolation transmission channels, thus reducing hardware overhead.

[0016] Furthermore, the second sub-chip includes a power modulator, a clock generation circuit, and a demodulation module. The power modulator modulates an externally input DC voltage into a high-frequency signal at the MHz level. The clock generation circuit provides the modulation signal required by the power modulator. The demodulation module receives the metering signal, demodulates and digitally processes it to obtain a processed signal. The demodulation module also sends the processed signal to an external chip for communication.

[0017] Furthermore, the packaging frame includes a first frame and a second frame. The first frame carries the first sub-chip, and the frame parasitic resistance is disposed on the first frame. The second frame carries the substrate and the second sub-chip. An isolation safety distance is provided between the first frame and the second frame. The first sub-chip, the second sub-chip, and the substrate achieve isolated power and signal transmission through wire bonding. The packaging frame achieves full integration of the equivalent shunt resistor. The complete metering chip, including the frame parasitic resistance, can achieve high-precision chip-level calibration at the factory stage, eliminating the need for further system-level calibration by the user in traditional solutions. Through the packaging frame, the user-calibration-free isolated metering chip achieves high-voltage and low-voltage side signal isolation and power isolation on a single chip, realizing isolated metering, improving system integration, and reducing costs.

[0018] Furthermore, the parasitic resistance of the frame is disposed on the first frame by: setting a first silver-plated area and a second silver-plated area on the first frame for chip wire bonding. The middle part of the first silver-plated area and the second silver-plated area is a finite resistance area. By wire bonding with the inside of the first sub-chip, the voltage drop between the first silver-plated area and the second silver-plated area can be read, thereby realizing current sampling. By integrating the frame parasitic resistance on the package frame, the user-calibration-free isolated metering chip can achieve high-precision chip-level calibration at the factory stage, eliminating the need for further system-level calibration by the user in traditional solutions.

[0019] Furthermore, the bearing area of ​​the second frame substrate is hollowed out to improve power transmission efficiency.

[0020] Furthermore, to reduce the length of the grounding wire, a third silver-plated area is provided on the second frame, which is used for grounding the second sub-chip.

[0021] Furthermore, the substrate comprises two or more metal plates, with an isolation dielectric layer disposed between the metal plates. Selecting a suitable isolation dielectric layer can meet the kV-level isolation requirements.

[0022] Furthermore, the first isolation medium is disposed within the first sub-chip and / or the second sub-chip, thereby improving the integration density.

[0023] Furthermore, the first isolation medium is disposed within the substrate to achieve a higher degree of isolation.

[0024] Furthermore, the first isolation medium is an on-chip capacitor or an on-chip coil.

[0025] Furthermore, the first isolation medium is a metal capacitor or a substrate coil.

[0026] Furthermore, to stabilize the voltage, an external filter capacitor is connected to the rectifier.

[0027] Furthermore, the metering module includes a sampling unit and a metering unit. The sampling unit includes two channels, current and voltage, for sampling the current and voltage respectively to obtain sampling signals. The metering unit is used to process the sampling signals to obtain metering signals. The signal processing includes, but is not limited to, digital filtering, calculating power, RMS value, energy information, and encoding modulation.

[0028] Furthermore, the first sub-chip, the second sub-chip, and the substrate are packaged together by a packaging frame using an SOP16 (Small Outline Package, 16 pins) type.

[0029] Furthermore, including the input pins IP and IN, in order to increase the overcurrent capability, the pins IP and IN are implemented by connecting two pins in parallel. The pins IP and IN are connected to the first frame respectively. The external current passes through the IP and IN pins and through the first frame, forming a voltage drop on the parasitic resistance of the frame.

[0030] Secondly, a user-calibration-free isolated metering method is disclosed, which uses the aforementioned user-calibration-free isolated metering chip and includes the following steps:

[0031] The second sub-chip modulates the external input DC voltage into a high-frequency signal, and sends the high-frequency signal to the first sub-chip through the substrate;

[0032] The first sub-chip receives a high-frequency signal sent by the second sub-chip, rectifies the high-frequency signal into a DC voltage, and uses the DC voltage to power the first sub-chip; it samples the current and voltage to obtain a sampling signal, processes the sampling signal to obtain a metering signal, and sends the metering signal to the second sub-chip;

[0033] The second sub-chip receives the metering signal sent by the first sub-chip, processes the metering signal, and obtains the processed signal. The processed signal is then sent to an external chip for communication.

[0034] Furthermore, after receiving the high-frequency signal sent by the second sub-chip, the first sub-chip extracts a clock signal from the high-frequency signal, and the clock signal is used to provide a clock for the first sub-chip.

[0035] Beneficial effects: This invention proposes a user-calibration-free isolated metering chip, which significantly reduces the development cost of power metering systems while ensuring high accuracy in the following aspects:

[0036] (1) In response to the existing solutions that use off-chip shunt resistors, this invention adopts custom chip packaging technology. By using a custom packaging framework, the equivalent shunt resistor is fully integrated. As a result, the chip can be calibrated at the chip level during the manufacturing process, eliminating the need for further system-level calibration by the user in traditional solutions.

[0037] (2) This invention proposes a solution for integrating isolated power supplies and isolated digital signals during the chip packaging stage. A single chip achieves strong and weak signal isolation. Currently, general-purpose isolated power supplies or isolated digital signals are expensive, partly due to the need for customized packaging and frames, and partly because general-purpose products need to meet various load conditions, resulting in complex designs. In this invention, regarding the former, since integrating the shunt resistor also requires a customized packaging frame, the costs of both are shared, reducing the overall cost at the system level. Regarding the latter, since the load current of a dedicated metering chip is known and controllable, the design of the isolated power supply and isolated signal can be specifically simplified, further reducing system costs. Attached Figure Description

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0039] Figure 1 This is a schematic diagram of the structure of a user-calibration-free isolated metering chip provided in an embodiment of this application.

[0040] Figure 2 This is another structural schematic diagram of a user-calibration-free isolated metering chip provided in an embodiment of this application.

[0041] Figure 3 This is another structural schematic diagram of a user-calibration-free isolated metering chip provided in an embodiment of this application.

[0042] Figure 4 This is another structural schematic diagram of a user-calibration-free isolated metering chip provided in an embodiment of this application.

[0043] Figure 5 This is a schematic diagram of the structure of the first sub-chip in a user calibration-free isolation metering chip provided in an embodiment of this application.

[0044] Figure 6 This is a schematic diagram of the structure of the second sub-chip in a user calibration-free isolation metering chip provided in an embodiment of this application.

[0045] Figure 7 This is a schematic diagram of a customized frame and wire bonding in a user-calibration-free isolated metering chip provided in an embodiment of this application.

[0046] Figure 8 This is a schematic diagram of a customized frame in a user-calibration-free isolated metering chip provided in an embodiment of this application. Detailed Implementation

[0047] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0048] This application provides a user-calibration-free isolated metering chip for applications in instrument-based metering and smart power consumption. It is suitable for smart furniture, smart appliances, and smart lighting, and can also be used in charging piles, battery management, and new energy vehicles. The proposed chip architecture incorporates a current sampling resistor, truly achieving user-level error calibration-free operation. The chip internally implements strong and weak current isolation, facilitating system integration with the main control board. This chip avoids the strong and weak current isolation problems associated with system-integrated metering functions and lowers the metering technology threshold for user product development.

[0049] The first embodiment of this application discloses a user-calibration-free isolated metering chip, such as... Figure 1 As shown, the device includes a first sub-chip Die #1, a second sub-chip Die #2, a substrate, and a packaging frame. The first sub-chip Die #1 is used to receive high-frequency signals sent by the second sub-chip Die #2, rectify the high-frequency signals into a DC voltage VDD, and use the DC voltage VDD to power the first sub-chip Die #1. The device also samples the current and voltage to obtain sampling signals, processes the sampling signals to obtain metering signals, and sends the metering signals to the second sub-chip Die #2.

[0050] The second sub-chip Die#2 is used to modulate the external input DC voltage VCC into a high-frequency signal, and send the high-frequency signal to the first sub-chip Die#1 through the substrate; it receives the metering signal sent by the first sub-chip Die#1, processes the metering signal, and obtains the processed signal.

[0051] The substrate is used to isolate and transmit signals between the first sub-chip Die#1 and the second sub-chip Die#2.

[0052] The packaging frame is used to carry the first sub-chip Die#1, the second sub-chip Die#2, and the substrate; the packaging frame is provided with a frame parasitic resistor, which is used to realize current sampling.

[0053] The first sub-chip Die #1, the second sub-chip Die #2, and the substrate are encapsulated together using a packaging frame.

[0054] External current passes through the packaging frame, forming a voltage drop across the frame's parasitic resistance. The voltage drop is then read out by the first sub-chip, Die#1.

[0055] like Figure 2 As shown, a coil TF1 is provided on the substrate, and the second sub-chip Die#2 transmits the high-frequency signal to the first sub-chip Die#1 through coil isolation.

[0056] The first sub-chip Die#1 sends the metering signal to the second sub-chip Die#2 through the first isolation medium.

[0057] like Figure 2 As shown, the first sub-chip Die#1 includes a rectifier, a metering module, and a signal transmitter STX. The rectifier is used to rectify the high-frequency signal into the DC voltage VDD. The metering module is used to sample the current and voltage to obtain a sampled signal, and process the sampled signal to obtain a metering signal. The signal transmitter STX is used to transmit the metering signal to the second sub-chip Die#2 through a first isolation medium. The rectifier, metering module, and signal transmitter STX can adopt existing technologies, and this embodiment of the invention is not limited thereto.

[0058] Optional, such as Figure 5 As shown, the rectifier can be connected to an external filter capacitor C.

[0059] like Figure 5 As shown, the first sub-chip Die#1 further includes a clock recovery circuit (CLK recovery circuit), which is used to extract a clock signal CLK from the high-frequency signal. The clock signal CLK is used to provide a clock for the first sub-chip Die#1. The clock recovery circuit can adopt existing technology, and this embodiment of the invention is not limited thereto.

[0060] The metering module includes a sampling unit and a metering unit. The sampling unit includes two channels: current and voltage, used to sample the current and voltage respectively to obtain sampling signals. The metering unit is used to process the sampling signals to obtain metering signals. The signal processing includes, but is not limited to, digital filtering, calculating power, RMS value, and energy information, and performing encoding modulation. The sampling unit and metering unit can adopt existing technologies, and this embodiment of the invention is not limited thereto.

[0061] like Figure 6As shown, the second sub-chip Die#2 includes a power modulator PTX, a clock generation circuit, and a demodulation module SRX. The clock generation circuit can use a high-frequency oscillator RCH. The power modulator PTX is used to modulate the external input DC voltage into a high-frequency signal at the MHz level. The high-frequency oscillator RCH is used to provide the modulation signal required by the power modulator PTX. The demodulation module SRX is used to receive the metering signal, demodulate and digitally process the metering signal to obtain the processed signal. The power modulator PTX, the high-frequency oscillator RCH, and the demodulation module SRX can adopt existing technologies, and this embodiment of the invention is not limited thereto.

[0062] In one optional implementation, the first isolation medium is disposed within a first sub-chip Die #1 and / or a second sub-chip Die #2. The first isolation medium is an on-chip capacitor or an on-chip coil. For example, the first isolation medium is disposed within the first sub-chip Die #1 and the second sub-chip Die #2, such as... Figure 2 As shown, on-chip capacitors C1 and C2 can be connected to the output of the signal transmitter STX. The metering signal is sent to the second sub-chip Die #2 after passing through on-chip capacitors C1 and C2. After being sent to the second sub-chip Die #2, the metering signal passes through on-chip capacitors C3 and C4 before being sent to the demodulation module SRX. Both the first sub-chip Die #1 and the second sub-chip Die #2 contain a first isolation medium to further improve isolation. Optionally, the first isolation medium (on-chip capacitors C1 and C2) can be located within the first sub-chip Die #1, or the first isolation medium (on-chip capacitors C3 and C4) can be located within the second sub-chip Die #2.

[0063] In another alternative implementation, the first isolation medium is disposed within the substrate. The first isolation medium is a metal capacitor or a substrate coil. For example, ... Figure 3 As shown, the first isolation medium can be metal capacitors C1 and C2. The signal transmitter STX of the first sub-chip Die#1 sends the measurement signal to the substrate. The measurement signal is then sent to the demodulation module SRX in the second sub-chip Die#2 via the metal capacitors C1 and C2 inside the substrate. Figure 4 As shown, the first isolation medium can also be the substrate coil TF2. The signal transmitter STX of the first sub-chip Die#1 sends the measurement signal to the substrate. The measurement signal is sent to the demodulation module SRX in the second sub-chip Die#2 via the substrate coil TF2 inside the substrate.

[0064] like Figure 7As shown, the packaging frame includes a first frame HV and a second frame LV. The first frame HV carries the first sub-chip Die #1, and the frame parasitic resistance is set on the first frame HV. The second frame LV carries the substrate and the second sub-chip Die #2. An isolation safety distance is provided between the first frame HV and the second frame LV, and the isolation safety distance is not limited. The first sub-chip Die #1, the second sub-chip Die #2, and the substrate achieve isolated transmission of power and signals through wire bonding. The first sub-chip Die #1, the second sub-chip Die #2, and the substrate are encapsulated by the packaging frame. Different packaging forms can be adopted according to the application pin requirements and isolation requirements.

[0065] The parasitic resistance of the frame is set on the first frame HV by: setting a first silver-plated area A and a second silver-plated area B on the first frame HV for chip wire bonding. The middle part of the first silver-plated area A and the second silver-plated area B is a finite resistance area. By bonding with the first sub-chip Die#1, the voltage drop between the first silver-plated area A and the second silver-plated area B can be read to achieve current sampling.

[0066] The second frame LV substrate bearing area is hollowed out.

[0067] A third silver-plated area C is provided on the second frame LV, and the third silver-plated area C is used for grounding the second sub-chip Die#2.

[0068] The substrate comprises two or more metal plates, with an insulating dielectric layer disposed between the metal plates.

[0069] In one alternative implementation, the first sub-chip, the second sub-chip, and the substrate are packaged together by a packaging frame using an SOP16 package type.

[0070] like Figure 7 As shown, the user calibration-free isolation metering chip includes input pins IP and IN. Pins IP and IN are implemented by connecting two pins in parallel. Pins IP and IN are connected to the first frame. External current passes through the first frame via the IP and IN pins, forming a voltage drop across the parasitic resistance of the frame.

[0071] Example

[0072] The overall architecture of this embodiment is as follows: Figure 2 As shown:

[0073] Firstly, the parasitic resistance of the packaging frame is utilized to achieve the current sampling function. The entire system consists of three sub-chips: Die #1, Die #2, and a substrate. These three are packaged together into a single chip using a custom chip packaging frame. Die #1 includes input pins IP and IN, DC voltage pin VDD, high-frequency signal receiving pins PRXP and PRXN, and metering signal transmitting pins STXP and STXN. Die #2 includes an external input DC voltage pin VCC, high-frequency signal transmitting pins PTXP and PTXN, metering signal receiving pins SRXP and SRXN, a ground pin GND, and a pin TX for communication with external chips.

[0074] External current enters the first sub-chip Die#1 through the IP and IN pins, forming a voltage drop across the frame's parasitic resistance. This voltage drop is used by the first sub-chip Die#1 to read the current value. The voltage is read through the VP pin. The IN pin is also multiplexed as the metering ground of the first sub-chip Die#1. The metering signal is transmitted to the second sub-chip Die#2 via the signal transmitter STX with on-chip capacitor isolation. After being re-encoded by the second sub-chip Die#2, it communicates externally through the TX pin.

[0075] The second sub-chip, Die #2, simultaneously modulates the external input DC voltage VCC into a high-frequency signal. This signal is then connected to a coil (transformer) on the substrate via the PTXP and PTXN pins. This coil (transformer) is connected to the PRXP and PRXN pins of the first sub-chip, Die #1, and energy is transferred between them via coil isolation. This energy is the modulated high-frequency signal, including clock and power information. Upon receiving this high-frequency signal, the PRXP and PRXN pins of the first sub-chip, Die #1, rectify it into a DC signal VDD to power Die #1. Simultaneously, the second sub-chip, Die #2, also transmits its clock information CLK to the first sub-chip, Die #1, via coil isolation, achieving signal synchronization.

[0076] (1) First sub-chip Die#1 architecture

[0077] Figure 5 The diagram shows the internal architecture of the first sub-chip, Die#1. The modulated high-frequency differential signals PRXP and PRXN are first rectified into a DC voltage VDD by a rectifier to power the chip itself. For a stable voltage, an external filter capacitor C can be optionally connected to the VDD pin. The transmitted high-frequency signals can also have clock information extracted by a clock recovery circuit (CLK recovery circuit) to provide a clock for the first sub-chip, Die#1, thereby reducing hardware overhead and ensuring clock synchronization.

[0078] The metering module includes a sampling unit and a metering unit. The sampling unit contains two channels: current and voltage, to sample signals and obtain sampled signals. The metering unit (a metering DSP, Digital Signal Processor) processes the sampled signals to obtain metered signals. This signal processing includes, but is not limited to, digital filtering, calculating power, RMS value, and energy information, and performing encoding and modulation. In addition, the first sub-chip Die#1 also includes an internal reference source (BGR+bias), a voltage regulator (LDO, low dropout regulator), and a power-on reset (POR) module. The internal reference source provides a reference for the current and voltage channels, the voltage regulator provides regulated power to the internal digital circuits, and the power-on reset module monitors the chip's power supply status. The internal reference source, voltage regulator, and power-on reset modules can utilize existing technologies, and this embodiment of the invention does not limit their application.

[0079] (2) Figure 5 This is a diagram of the internal architecture of the second sub-chip, Die#2. The external input DC voltage VCC is first modulated into a MHz-level signal by the power modulator PTX, and then transmitted through the PTXP and PTXN pins. Figure 1 The substrate coil is connected in the chip. The required modulation signal is generated by the on-chip high-frequency oscillator RCH. The metering signal transmitted from the first sub-chip Die#1 through on-chip capacitor isolation is received by the SRXP and SRXN pins of the second sub-chip Die#2, demodulated and digitally processed by the SRX demodulation module, and finally communicates with the peripheral chip through the TX pin. In addition, the second sub-chip Die#2 also includes modules such as a bandgap voltage reference circuit (BGR), a voltage regulator (LDO), a power-on / off reset module (POR), and an electronic fuse. The bandgap voltage reference circuit is used to provide a reference for the chip, the voltage regulator is used to power the internal digital circuit, the power-on / off reset module is used to monitor the chip's power supply status, and the electronic fuse is used for factory calibration. The bandgap voltage reference circuit, voltage regulator, power-on / off reset module, and electronic fuse can adopt existing technologies, and this embodiment of the invention is not limited thereto.

[0080] In this scheme, power is transmitted through a substrate coil to achieve strong and weak voltage isolation. Metering signals are isolated via on-chip capacitors. The first sub-chip, Die #1, is the high-voltage side, and the second sub-chip, Die #2, is the low-voltage side. Isolated metering is achieved through die packaging on a single chip.

[0081] (3) Customization of frame and substrate

[0082] The first sub-chip Die #1, the second sub-chip Die #2, and the substrate are encapsulated using a custom frame, which integrates a current sampling resistor (frame parasitic resistance). A detailed schematic is shown below. Figure 7 As shown. The package used can be implemented in SOP16 form. Of course, the package type is not limited to SOP16. Depending on the application pin requirements and isolation requirements, other package types can also be used. To increase the overcurrent capability, pins IP and IN can be implemented using two pins connected in parallel. IP and IN are respectively connected to the internal first frame HV. The first frame is used to carry the first sub-chip Die#1, and the current sampling function is realized by utilizing the frame parasitic resistance of the first frame. A first silver-plated area A and a second silver-plated area B are set on the first frame HV for chip wire bonding. The middle part of the first silver-plated area AB is the finite resistance area. By connecting it to the internal part of the first sub-chip Die#1, the voltage drop of the AB area can be read to realize current measurement. The length and width design of the first frame depends on the size of the first sub-chip Die#1 and the required frame parasitic resistance, and there is no specific limitation.

[0083] The remaining pins on the left are used for voltage sampling (VP) and DC voltage (power output) (VDD), etc., and are not limited here.

[0084] The second frame's LV region is used to support the substrate and the second sub-chip, Die #2. A safety distance, such as 1mm, is maintained between the first and second frames; the specific size is not limited. Figure 6 As shown, the second sub-chip Die #2, the substrate, and the first sub-chip Die #1 achieve isolated power and signal transmission through wire bonding. The metering signal of the first sub-chip Die #1 is transmitted and demodulated through the second sub-chip Die #2 and then communicates externally via the second sub-chip Die #2. To improve power transmission efficiency, the supporting area of ​​the second frame substrate is hollowed out to ensure that there is no large area of ​​metal directly below the coil.

[0085] In addition, to secure the second frame, it can be grounded by connecting it to the top and bottom pins adjacent to its edge. To reduce the length of the ground wire, a third silver-plated area C can be provided on the second frame for grounding the second sub-chip Die#2.

[0086] The shape of the custom packaging frame is not limited to that of the custom packaging frame. Figure 7 Any geometric shape is acceptable as long as it achieves the same functional requirements. The positions of the first and second frames in the custom encapsulation framework are also not limited. Figure 7 Any other location is acceptable as long as it can fulfill the same functional requirements.

[0087] The substrate used comprises at least two metal layers, and can use four metal layers, with an insulating dielectric layer disposed between the metal layers. A suitable insulating dielectric layer, such as GHPL-830NS material, is selected to meet the kV level isolation requirements.

[0088] A schematic diagram of a standalone frame design without chips is shown below. Figure 8 As shown: The dimensions marked therein can be flexibly adjusted according to the actual chip size and other factors.

[0089] (1) This invention adopts chip-custom packaging technology, and achieves full integration of equivalent shunt resistor by using a custom packaging framework. The complete metering chip, which includes the parasitic resistance of the framework, can achieve high-precision chip-level calibration at the factory stage, eliminating the need for further system-level calibration by the user in traditional solutions.

[0090] (2) This invention achieves signal and power isolation between high-voltage and low-voltage sides on a single chip through a customized framework, improving system integration and reducing costs. Since the parasitic resistance of the framework also needs to be customized, the one-time cost of framework customization is shared by both parties.

[0091] (3) The power isolation described herein transmits energy through the substrate and then rectifies it. This solution is also used for clock transmission, achieving clock synchronization, avoiding the need for additional clock generation or clock isolation transmission channels, and reducing costs.

[0092] The second embodiment of this application discloses a user-calibration-free isolation metering method, which uses the above-mentioned user-calibration-free isolation metering chip and includes the following steps:

[0093] The second sub-chip modulates the external input DC voltage VCC into a high-frequency signal, and sends the high-frequency signal to the first sub-chip through the substrate;

[0094] The first sub-chip receives a high-frequency signal sent by the second sub-chip, rectifies the high-frequency signal into a DC voltage VDD, and uses the DC voltage to power the first sub-chip; it samples the current and voltage to obtain a sampling signal, processes the sampling signal to obtain a metering signal, and sends the metering signal to the second sub-chip;

[0095] The second sub-chip receives the metering signal sent by the first sub-chip, processes the metering signal, and obtains the processed signal.

[0096] In this embodiment, after the first sub-chip receives the high-frequency signal sent by the second sub-chip, it extracts the clock signal CLK from the high-frequency signal. The clock signal CLK is used to provide a clock for the first sub-chip.

[0097] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the content of the user-calibration-free isolated metrology method provided by this invention, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0098] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MUU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0099] This invention provides a user-calibration-free isolated metering chip and metering method. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A user-calibration-free isolated metering chip, characterized in that, Includes a first sub-chip, a second sub-chip, a substrate, and a packaging frame. The first sub-chip is used to receive high-frequency signals sent by the second sub-chip, rectify the high-frequency signals into DC voltage, and use the DC voltage to power the first sub-chip; sample the current and voltage to obtain sampling signals, process the sampling signals to obtain metering signals, and send the metering signals to the second sub-chip; The second sub-chip is used to modulate the external input DC voltage into a high-frequency signal, and send the high-frequency signal to the first sub-chip through the substrate; it also receives the metering signal sent by the first sub-chip, processes the metering signal, and obtains the processed signal. The substrate is used to isolate and transmit signals between the first sub-chip and the second sub-chip. The packaging frame is used to carry the first sub-chip, the second sub-chip, and the substrate; a frame parasitic resistor is provided on the packaging frame, and the frame parasitic resistor is used to realize current sampling. The first sub-chip, the second sub-chip, and the substrate are encapsulated together using a packaging frame.

2. The user-calibration-free isolated metering chip according to claim 1, characterized in that, External current passes through the packaging frame, forming a voltage drop across the frame's parasitic resistance. This voltage drop is then used to read the current value through the first sub-chip.

3. The user-calibration-free isolated metering chip according to claim 2, characterized in that, A coil is provided on the substrate, and the second sub-chip transmits the high-frequency signal to the first sub-chip through coil isolation.

4. The user-calibration-free isolated metering chip according to claim 3, characterized in that, The first sub-chip transmits the metering signal to the second sub-chip through the first isolation medium.

5. A user-calibration-free isolated metering chip according to claim 4, characterized in that, The first sub-chip includes a rectifier, a metering module, and a signal transmitter. The rectifier is used to rectify the high-frequency signal into the DC voltage. The metering module is used to sample the current and voltage to obtain a sampled signal, and to process the sampled signal to obtain a metering signal. The signal transmitter is used to send the metering signal to the second sub-chip through a first isolation medium.

6. A user-calibration-free isolated metering chip according to claim 5, characterized in that, The first sub-chip also includes a clock recovery circuit, which is used to extract a clock signal from the high-frequency signal, and the clock signal is used to provide a clock for the first sub-chip.

7. A user-calibration-free isolated metering chip according to claim 6, characterized in that, The second sub-chip includes a power modulator, a clock generation circuit, and a demodulation module. The power modulator is used to modulate an external input DC voltage into a high-frequency signal at the MHz level. The clock generation circuit is used to provide the modulation signal required by the power modulator. The demodulation module is used to receive the metering signal, demodulate and digitally process the metering signal to obtain the processed signal.

8. A user-calibration-free isolated metering chip according to claim 3, characterized in that, The packaging frame includes a first frame and a second frame. The first frame is used to carry the first sub-chip, and the frame parasitic resistance is set on the first frame. The second frame is used to carry the substrate and the second sub-chip. An isolation safety distance is set between the first frame and the second frame. The first sub-chip, the second sub-chip and the substrate achieve isolated transmission of power and signals through wire bonding.

9. A user-calibration-free isolated metering chip according to claim 8, characterized in that, The parasitic resistance of the frame is set on the first frame by: setting a first silver-plated area and a second silver-plated area on the first frame for chip wire bonding. The middle part of the first silver-plated area and the second silver-plated area is a finite resistance area. By bonding with the inside of the first sub-chip, the voltage drop between the first silver-plated area and the second silver-plated area can be read to achieve current sampling.

10. A user-calibration-free isolated metering chip according to claim 9, characterized in that, The second frame substrate bearing area is hollowed out.

11. A user-calibration-free isolated metering chip according to claim 10, characterized in that, A third silver-plated area is provided on the second frame, and the third silver-plated area is used for grounding the second sub-chip.

12. A user-calibration-free isolated metering chip according to claim 11, characterized in that, The substrate comprises two or more metal plates, with an insulating dielectric layer disposed between the metal plates.

13. A user-calibration-free isolated metering chip according to claim 4, characterized in that, The first isolation medium is disposed within the first sub-chip and / or the second sub-chip.

14. A user-calibration-free isolated metering chip according to claim 4, characterized in that, The first isolation medium is disposed within the substrate.

15. A user-calibration-free isolated metering chip according to claim 13, characterized in that, The first isolation medium is an on-chip capacitor or an on-chip coil.

16. A user-calibration-free isolated metering chip according to claim 14, characterized in that, The first isolation medium is a metal capacitor or a substrate coil.

17. A user-calibration-free isolated metering chip according to claim 7, characterized in that, The rectifier is connected to an external filter capacitor.

18. A user-calibration-free isolated metering chip according to claim 17, characterized in that, The metering module includes a sampling unit and a metering unit. The sampling unit includes two channels, current and voltage, for sampling the current and voltage respectively to obtain sampling signals. The metering unit is used to process the sampling signals to obtain metering signals. The signal processing includes, but is not limited to, digital filtering, calculating power, RMS value, energy information, and encoding modulation.

19. A user-calibration-free isolated metering chip according to claim 9, characterized in that, The first sub-chip, the second sub-chip, and the substrate are packaged together using a packaging frame, and the packaging type is SOP16.

20. A user-calibration-free isolated metering chip according to claim 19, characterized in that, It includes input pins IP and IN, which are implemented by connecting two pins in parallel. Pins IP and IN are connected to the first frame. External current passes through the first frame via the IP and IN pins, forming a voltage drop across the parasitic resistance of the frame.

21. A user-calibration-free isolated metering method, using the user-calibration-free isolated metering chip according to any one of claims 1-20, characterized in that, Includes the following steps: The second sub-chip modulates the external input DC voltage into a high-frequency signal, and sends the high-frequency signal to the first sub-chip through the substrate; The first sub-chip receives a high-frequency signal sent by the second sub-chip, rectifies the high-frequency signal into a DC voltage, and uses the DC voltage to power the first sub-chip; it samples the current and voltage to obtain a sampling signal, processes the sampling signal to obtain a metering signal, and sends the metering signal to the second sub-chip; The second sub-chip receives the metering signal sent by the first sub-chip, processes the metering signal, and obtains the processed signal.

22. A user-calibration-free isolated metrology method according to claim 21, characterized in that, After receiving the high-frequency signal sent by the second sub-chip, the first sub-chip extracts a clock signal from the high-frequency signal, and the clock signal is used to provide a clock for the first sub-chip.

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