Power consumption test method and device, power supply test method and device, and related product

Abstract

The invention provides a power consumption testing method and device, a power supply testing method and device and a related product, and relates to the technical field of chip testing. The method comprises the following steps: triggering a first process of a tested chip to run a preset low-load task every a first preset duration, so that the tested chip is maintained at the highest working frequency; in the periodic operation process of the low-load task, triggering a second process of the tested chip to operate a preset high-load task every second preset duration; recording the peak power consumption of the tested chip in the testing process; the dynamic voltage frequency adjusting function of the tested chip is in a starting state in the testing process. Therefore, when the highest working frequency is maintained, the second process of the tested chip is triggered to run the preset high-load task, so that the chip can reach the state of running the load with the maximum power consumption under the highest working frequency. And the peak power consumption of the chip can be stably and controllably measured.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and more specifically, to a power consumption testing method and apparatus, a power supply testing method and apparatus, and related products. Background Technology

[0002] In the chip design and verification process, accurate measurement of peak power consumption is crucial for system power supply, power design, thermal management, and system stability assessment.

[0003] In related technologies, large model applications are typically run with DVFS (Dynamic Voltage and Frequency Scaling) enabled because the power consumption of large model applications dynamically fluctuates depending on the workload, type, and intensity of the tasks. Therefore, it will reach the chip's peak power consumption at a certain moment.

[0004] However, when testing peak power consumption using this method, the timing of the peak power consumption is uncontrollable, making it impossible to reliably test the peak power consumption during actual chip use. Summary of the Invention

[0005] The purpose of this application is to provide a power consumption testing method and apparatus, a power supply testing method and apparatus, and related products to solve the problem of how to stably test the peak power consumption of a chip during actual use in related technologies.

[0006] This application provides a power consumption testing method, including: triggering a first process of the chip under test to run a preset low-load task at a first preset time interval to keep the chip under test at its highest operating frequency; during the periodic operation of the low-load task, triggering a second process of the chip under test to run a preset high-load task at a second preset time interval; recording the peak power consumption of the chip under test during the test; and ensuring that the dynamic voltage and frequency adjustment function of the chip under test is activated during the test.

[0007] In the above implementation, considering that the peak power consumption of a chip typically requires the chip to operate at its highest operating frequency under the most power-consuming load, by triggering the first process of the chip under test to run a preset low-load task at first preset intervals, the chip can be maintained at its highest operating frequency. While maintaining the highest operating frequency, triggering the second process of the chip under test to run a preset high-load task allows the chip to reach a state where it operates at its highest operating frequency under the most power-consuming load. Therefore, the peak power consumption of the chip can be obtained each time the chip under test is triggered to run a preset high-load task, making the process of measuring the chip's peak power consumption controllable. Simultaneously, since the dynamic voltage and frequency adjustment function is enabled during measurement, the measured peak power consumption can reflect the peak power consumption during actual use.

[0008] Furthermore, the first process of the chip under test is triggered to run a preset low-load task at each first preset time interval, including: the first process of the chip under test is triggered to perform a register access operation at each first preset time interval; the first preset time interval is less than the duration of the sampling window for the chip under test to perform dynamic voltage frequency adjustment.

[0009] The hardware busy signals of each module of the chip are combined into a single hardware busy signal for the chip core through an OR operation. Considering that the dynamic voltage and frequency adjustment judgment logic typically checks whether the hardware busy signal of the chip core has been pulled high within a preset time period, if not, the chip is triggered to reduce its frequency. In the above implementation, by performing a register access operation to access the register of a certain module within the chip, the hardware busy signal of that module will be pulled high. Since the hardware busy signal of the chip core is ORed together with the hardware busy signal of that module and other signals, by periodically performing register access operations to access the register, during the dynamic voltage and frequency adjustment judgment process, there will always be a point where the hardware busy signal of the chip core is in a high state. Therefore, the chip's dynamic voltage and frequency adjustment function will not trigger the chip to reduce its frequency, allowing the chip under test to maintain its highest operating frequency.

[0010] Furthermore, the first process of the chip under test is triggered to run a preset low-load task at each first preset time interval, including: the first process of the chip under test is triggered to execute preset code at each first preset time interval, the preset code including null instructions or arithmetic logic unit operations; the first preset time interval is less than the duration of the sampling window for the chip under test to perform dynamic voltage frequency adjustment.

[0011] Considering that the power consumption of a chip is minimal when running code consisting only of empty instructions, the above implementation simulates a scenario where lightweight tasks continuously occur by periodically running code consisting only of empty instructions. This ensures that the chip has continuous task demands, thereby prompting the dynamic voltage-frequency adjustment function to maintain the chip under test at its highest operating frequency.

[0012] Furthermore, triggering the second process of the chip under test to run a preset high-load task at every second preset time interval includes: sending the high-load task to the chip under test at every second preset time interval; the second process of the chip under test cyclically executing the high-load task for a third preset time interval; the third preset time interval is less than the second preset time interval.

[0013] Considering that the power consumption of the chip gradually increases and then stabilizes during high-load tasks, in the above implementation, by cyclically executing the high-load task for a third preset duration, the duration of peak power consumption can be extended, increasing the reliability of the measured peak power consumption.

[0014] Furthermore, the preset high-load task is determined in the following way: for each preset set of matrix multiplication parameters: when the chip under test is at a preset chip frequency, the set of matrix multiplication parameters is calculated using the chip under test, and the test power consumption generated by the chip under test is recorded; the matrix multiplication parameter corresponding to the largest test power consumption is taken as the high-load task.

[0015] Theoretically, the task that maximizes chip power consumption requires all transistors on the chip to switch simultaneously. However, in practical applications, there is currently no task that can simultaneously switch all transistors on a chip. By summarizing the known matrix multiplication parameters that users would typically use and testing the power consumption of these parameters at the same chip frequency, we can obtain the load with the highest power consumption in actual use. Using the matrix multiplication parameters corresponding to the highest test power consumption as a high-load task, and testing with this high-load task, we can measure the maximum peak power consumption that the chip can achieve in real-world applications.

[0016] This application provides a power supply testing method, including: triggering a first process of the chip under test to run a preset low-load task at a first preset time interval to keep the chip under test at its highest operating frequency; during the periodic operation of the low-load task, triggering a second process of the chip under test to run a preset high-load task at a second preset time interval; determining whether there is a problem with the power supply design based on the state of the chip under test during the test; and ensuring that the dynamic voltage and frequency adjustment function of the chip under test is activated during the test.

[0017] Considering that chips require a suitable power supply when handling loads, if the chip's state becomes abnormal during load processing, there may be deficiencies in the power supply design. In the above implementation, by observing the chip's state changes from low power consumption to peak power consumption, it is possible to accurately determine whether the chip's power supply design can meet the different power consumption variations in actual usage scenarios.

[0018] Furthermore, the power supply design is determined based on the status of the chip under test during the test, including: obtaining the log of the chip under test during the test; if information indicating power supply abnormality appears in the log, the chip power supply design is determined to be abnormal; otherwise, the chip power supply design is determined to be normal.

[0019] Considering that the chip's log can accurately record power supply anomaly alerts, in the above embodiment, the chip's log can accurately determine whether a power supply anomaly exists.

[0020] This application provides a power consumption testing device, including: a task testing module, used to trigger a first process of the chip under test to run a preset low-load task at a first preset time interval, so that the chip under test maintains the highest operating frequency; during the periodic operation of the low-load task, triggering a second process of the chip under test to run a preset high-load task at a second preset time interval; a recording module, used to record the peak power consumption of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is activated during the test.

[0021] This application provides a power supply testing device, including: a task testing module, used to trigger a first process of the chip under test to run a preset low-load task at a first preset time interval, so that the chip under test maintains the highest operating frequency; during the periodic operation of the low-load task, triggering a second process of the chip under test to run a preset high-load task at a second preset time interval; a power supply problem determination module, used to determine whether there is a problem with the power supply design based on the state of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is activated during the test.

[0022] This application provides an electronic device, including a processor and a memory. The memory stores computer-executable instructions that can be executed by the processor. The processor executes the computer-executable instructions to implement the power consumption test method or the power supply test method described above.

[0023] This application provides a storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the power consumption test method or the power supply test method described above.

[0024] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements the power consumption test method or the power supply test method described above.

[0025] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating a power consumption testing method provided in an embodiment of this application; Figure 2 A flowchart illustrating another power consumption testing method provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the peak power consumption scenario triggering provided in an embodiment of this application; Figure 4 A flowchart illustrating a power supply testing method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a power consumption testing device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a power supply testing device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0028] Figure label: 1: Task testing module; 2: Recording module; 3: Power supply problem determination module; 4: Communication interface; 5: Bus; 6: Processor; 7: Memory. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0030] The following explanations are provided for some of the technical terms appearing in this application: Average power consumption: The average energy consumption over a period of time.

[0031] Typical power consumption (TDP, Thermal Design Power): Thermal design power consumption under continuous load.

[0032] Peak power consumption: The maximum power consumed instantaneously by a chip during operation. Typically, peak power consumption is 2 to 3 times the typical power consumption.

[0033] Example 1 In the chip design and verification process, accurate measurement of peak power consumption is crucial for system power supply, power design, thermal management, and system stability assessment.

[0034] Currently, there are two methods for measuring peak power consumption: Method 1: With DVFS disabled, set the chip's highest operating frequency voltage group and continuously run high-load tasks to measure peak power consumption.

[0035] Method 2: Run large model applications for a long time with DVFS enabled.

[0036] However, the above two methods have the following problems: Measuring peak power consumption using Method 1 is problematic because DVFS is disabled, and the chip won't automatically adjust its frequency under continuous full load. This could trigger thermal throttling (over-temperature frequency throttling) or power capping (power supply system failure), leading to distorted peak power consumption measurements. Furthermore, due to the excessively high instantaneous power consumption, prolonged periods of this could cause the system's cooling system to be unable to meet the cooling requirements, or the system's power supply design to be inadequate.

[0037] Therefore, after triggering a peak power consumption scenario by measuring peak power consumption using Method 1, you need to wait for the chip temperature to drop, the frequency to return to normal, or the system to restart before you can test again.

[0038] The peak power consumption is measured by method two because the power consumption of a large model application will dynamically fluctuate with the changes in workload, type and intensity during operation. At certain times, the chip frequency will be at its highest operating frequency and running the maximum load task, thus allowing us to obtain the chip's peak power consumption.

[0039] However, measuring peak power consumption using method two does not reveal when a large-scale application will reach the chip's peak power consumption during operation. This leads to uncertainty in test timing.

[0040] In summary, constructing peak scenarios using the two methods described above has two limitations. The former is constrained by system heat dissipation and power supply, leading to inaccurate testing and potentially requiring system restarts. The latter involves randomness, with uncertain test duration.

[0041] A testing method is needed to stably and controllably trigger the chip to reach its peak power consumption periodically while DVFS is enabled.

[0042] Considering that peak chip power consumption is not generated by continuous full load, but by energy surges caused by sudden state changes and resource concurrency in a very short time. That is, peak power consumption usually occurs during the transient process when the chip suddenly enters a "high computing density task" from a "low activity state".

[0043] Based on this, a scenario can be constructed where the DVFS frequency range jumps to its maximum value under light load, and a sudden maximum load task is applied to test the chip's peak power consumption.

[0044] To address the above problems, embodiments of this application provide a power consumption testing method. See also... Figure 1 As shown, Figure 1 This is a basic flowchart illustrating the power consumption testing method provided in the embodiments of this application, including: Step S101: At each first preset time interval, the first process of the chip under test is triggered to run a preset low-load task, so that the chip under test is kept at the highest operating frequency.

[0045] Optionally, when a low-load task is executed by the chip under test, the power consumption of the chip under test is less than the preset power consumption.

[0046] The preset power consumption can be set to a relatively small value by technicians based on their experience.

[0047] For example, typical power consumption can be 100 times the preset power consumption. For example, the preset power consumption is 3W, the preset power consumption is 5W, etc.

[0048] Optionally, the chip enables dynamic voltage and frequency adjustment, with a first preset duration shorter than the sampling window duration for the chip under test to perform dynamic voltage and frequency adjustment. This window represents the duration for collecting historical information before performing logical judgments based on the dynamic voltage and frequency adjustment.

[0049] For example, in the dynamic voltage and frequency adjustment of the chip, a judgment is made every second. The judgment strategy is to determine whether the hardware busy signal of the chip core has been pulled high within the past 0.8 seconds. In this case, the sampling window is 0.8 seconds, and the first preset duration is less than 0.8 seconds, which can be set to 0.2 seconds, 500 milliseconds, etc. If the dynamic voltage and frequency adjustment of the chip is set to make a judgment every 500 milliseconds, and the judgment strategy is to determine whether the hardware busy signal of the chip core has been pulled high within the past 500 milliseconds, then the sampling window is 500 milliseconds, and the first preset duration is less than 500 milliseconds, which can be set to 200 milliseconds, 300 milliseconds, etc.

[0050] In this way, since the judgment strategy corresponding to the dynamic voltage and frequency adjustment of the chip usually sets a sampling window, and then performs subsequent logical judgments based on the data in the sampling window to determine the frequency direction of the chip, by setting the first duration to be shorter than the duration of the sampling window for the chip under test to perform dynamic voltage and frequency adjustment, information about the chip performing tasks can be obtained for each dynamic voltage and frequency adjustment, thus assuming that the chip always has task requirements, and thus dynamically maintaining the chip at the highest operating frequency.

[0051] In some embodiments, triggering the first process of the chip under test to run a preset low-load task at a first preset time interval includes: triggering the first process of the chip under test to perform a register access operation at a first preset time interval.

[0052] Optionally, register access operations may include register read operations and / or register write operations.

[0053] Optionally, the object of the register access operation can be a register of a block (functional module, a relatively independent hardware circuit unit with a specific function inside the chip), such as the MMU (Memory Management Unit) module, GPIO (General Purpose Input / Output) module, DMA (Direct Memory Access Controller) module, etc.

[0054] For example, assuming the register access operation targets a register in the MMU module, the first preset duration is 500 milliseconds. Every 500 milliseconds, the first process of the chip under test is triggered to read the register of the MMU module inside the chip via PCIe (a high-speed serial computer expansion bus standard), causing the MMU's busy signal to be pulled high. Since the chip core's hardware busy signal is obtained by ORing the MMU's busy signal with other signals, maintaining the chip core's highest frequency can be achieved simply by periodically accessing the register at the system end.

[0055] In other embodiments, the first process of the chip under test is triggered to run a preset low-load task at a first preset time interval, including: the first process of the chip under test is triggered to execute preset code at a first preset time interval.

[0056] When the preset code is executed by the chip under test, the power consumption of the chip under test is less than the preset power consumption.

[0057] Optionally, the default code includes nop instructions or arithmetic logic unit (ALU) operations.

[0058] Specifically, when the preset code consists of arithmetic logic unit (ALU) operations, only lightweight ALU operations can be performed. This means that when controlling the chip under test to run the preset code composed of ALU operations, the chip's power consumption is less than the preset power consumption.

[0059] For example, a technician can write a sample code, which may contain only null instructions, or only arithmetic logic unit (ALU) operations. Alternatively, the sample code may contain both null instructions and ALU operations. The technician can then fix the chip at a first set frequency, such as 1000 MHz. The chip is then made to run the sample code, and the actual power consumption is recorded. If the actual power consumption is less than the preset power consumption, the sample code can be used as the preset code.

[0060] Step S102: During the periodic operation of the low-load task, the second process of the chip under test is triggered to run a preset high-load task every second preset time interval.

[0061] In some embodiments, the second preset duration can be set by a technician based on experience.

[0062] Considering that when the chip is operating at its highest frequency, it will reach its peak power consumption after a high-load task is assigned. At this point, DVFS will intervene to reduce the chip's frequency. After the chip completes the high-load task, only low-load tasks will remain. Then, DVFS will start increasing the frequency again until the chip reaches and maintains its highest operating frequency. Therefore, if the second preset duration is set too short, the chip may not have returned to its highest operating frequency after completing the high-load task, leading to inaccurate peak power consumption measurements. If the second preset duration is set too long, fewer peak power consumption scenarios will be triggered within the same time frame, wasting test time. Therefore, technicians can set an appropriate second preset duration based on this idea.

[0063] In other embodiments, the second preset duration can be set by obtaining the upsampling time required for the chip to increase from the first preset frequency to the highest operating frequency, and setting the second preset duration based on the upsampling time.

[0064] The first preset frequency can be 0. Alternatively, the first preset frequency can be the frequency corresponding to typical power consumption.

[0065] Optionally, setting a second preset duration based on the upsampling duration may include using the upsampling duration as the second preset duration.

[0066] Optionally, setting a second preset duration based on the upsampling duration may include: adding a preset duration to the upsampling duration to obtain the second preset duration.

[0067] Thus, considering that DVFS intervention will stabilize the chip power consumption near its typical power consumption, the chip frequency will also drop to near the frequency corresponding to typical power consumption. Therefore, by testing the rise time required for the chip to rise from its typical power consumption frequency to its highest operating frequency, and ensuring that the second rise time is greater than or equal to the rise time, it can be guaranteed that the set second rise time will allow the chip to return to its highest operating frequency after completing a high-load task.

[0068] In some embodiments, when the chip under test is running a high-load task, the power consumption of the high-load task is greater than the typical power consumption of the chip under test.

[0069] In some embodiments, high-load tasks can be determined by: obtaining the chip type; determining the task type based on the chip type; obtaining a task database corresponding to the task type; for each task in the task database: running the task using the chip under test at a preset chip frequency, and recording the task power consumption generated by the chip under test; and identifying the task with the highest task power consumption as the high-load task. In this way, considering that different chips support different tasks, determining the task type by distinguishing the chip type allows us to obtain the load that the chip can generate with the highest power consumption under its supported task types.

[0070] In the above embodiments, determining the task type based on the chip type can be achieved by searching for the task type corresponding to the chip type in a preset type database. The type database stores the correspondence between chip types and task types.

[0071] For example, a chip may support multiple task types. A corresponding task database can be obtained for each task type. With the chip under test operating at a preset chip frequency, each task in each task database is tested to obtain the power consumption of each task. The task with the highest power consumption is then designated as the high-load task.

[0072] If a user wants to know the maximum power consumption of a chip under each task type, they can determine the task with the highest power consumption in each task database. For example: Suppose there are task types a and b. Task type a corresponds to task database aa, and task type b corresponds to task database bb. Task database aa contains 3 tasks. With the chip under test operating at a preset chip frequency, each task in task database aa is tested to obtain the power consumption of the 3 tasks. The task with the highest power consumption among the 3 tasks is designated as the high-load task for task type a. Task database bb contains 4 tasks. With the chip under test operating at a preset chip frequency, each task in task database bb is tested to obtain the power consumption of the 4 tasks. The task with the highest power consumption among the 4 tasks is designated as the high-load task for task type b. This allows users to easily understand the maximum power consumption that the chip can achieve when running different task types.

[0073] For example, assuming the chip is an NPU (embedded neural network processor) chip, the task type corresponding to the NPU chip could be matrix multiplication. Assuming the chip is a GPU (graphics processing unit) chip, the task type corresponding to the GPU chip could be rendering test tasks.

[0074] In one optional embodiment of the above, assuming the chip is an NPU chip and the task type corresponding to the NPU chip is matrix multiplication (GEMM), the high-load task can be determined in the following way: For each preset set of matrix multiplication parameters: when the chip under test is at a preset chip frequency, the chip under test is used to calculate the set of matrix multiplication parameters and the test power consumption generated by the chip under test is recorded; the matrix multiplication parameter corresponding to the maximum test power consumption is taken as the high-load task.

[0075] For example, all collectable matrix multiplication parameters are compiled into a matrix database. These parameters can be provided by the user or the customer. The chip is fixed at a second set frequency, for example, 1000MHz. The test power consumption of each set of matrix multiplication parameters is iterated, and finally, the set of parameters with the highest power consumption is selected as the high-load task.

[0076] Table 1 shows the test results for some matrix multiplication parameters. As shown in Table 1, LOOPS represents the number of loops. Power represents the chip's test power consumption. Data_type indicates the data type; specifically, INT8 represents an 8-bit integer, FP16 represents a 16-bit floating-point number, and FP32 represents a 32-bit floating-point number.

[0077] In Table 1, each row represents a set of matrix multiplication parameters for GEMM. A set of matrix multiplication parameters includes two matrices that participate in the matrix multiplication. Assume C = A × B. C is the result of the matrix multiplication, i.e., the output matrix; A and B are the two matrices participating in the matrix multiplication, and A and B belong to a set of matrix multiplication parameters.

[0078] When C = A × B, the shape of matrix A is M × K, the shape of matrix B is K × N, and the calculated shape of C is M × N.

[0079] Where M represents the number of rows in the output matrix C, and N represents the number of columns in the output matrix C. If A is not transposed, K represents the number of columns in A; or, if B is not transposed, K represents the number of rows in B.

[0080] Assuming A is the first matrix and B is the second matrix, a value of T_A of 0 indicates that the first matrix is ​​not transposed. A value of T_A of 1 indicates that the first matrix is ​​transposed. Similarly, a value of T_B of 0 indicates that the second matrix is ​​not transposed. A value of T_B of 1 indicates that the second matrix is ​​transposed. By transposing the matrices, we can ensure that the number of columns in the first matrix is ​​equal to the number of rows in the second matrix.

[0081] For example: when T_B is 1, C = A × B TThis means that after transposing matrix B, multiplying it by A yields an output matrix. If A has a size of M×K and B has a size of N×K, after transposing B, B becomes K×N, and C becomes M×N.

[0082] The second row in Table 1 indicates that the data type of the matrix is ​​INT8. The first matrix is ​​2048×3072, and the second matrix is ​​2048×3072. Neither the first nor the second matrix is ​​transposed. Calculating 200 multiplications of the first and second matrices results in a chip power consumption of 152W.

[0083] Table 1

[0084] In another optional embodiment described above, assuming the chip is a GPU chip and the task type corresponding to the GPU chip is a rendering test task, the high-load task can be determined in the following way: For each preset rendering test task: when the chip under test is at a preset chip frequency, the rendering test task is run using the chip under test, and the test power consumption generated by the chip under test is recorded; the rendering test task corresponding to the highest test power consumption is taken as the high-load task.

[0085] In some embodiments, triggering the second process of the chip under test to run a preset high-load task at a second preset time interval includes: sending a high-load task to the chip under test at a second preset time interval; and the second process of the chip under test cyclically executing the high-load task for a third preset time interval.

[0086] In some embodiments, the third preset duration is shorter than the second preset duration, and the third preset duration can be set by a technician based on experience.

[0087] Considering that the chip will reach its peak power consumption when operating at its highest frequency and under heavy load, DVFS will intervene to reduce the chip's frequency. If the third preset duration is set too short, DVFS may not have intervened yet, resulting in a short peak power consumption period. Conversely, if the third preset duration is set too long, DVFS will stabilize the chip's power consumption near its typical power consumption after intervention, making further testing meaningless and wasting test time. Therefore, technicians can set an appropriate third preset duration based on this principle.

[0088] For example, assuming the second preset duration is 10 seconds, the third preset duration can be set to 3 seconds. Suppose a high-load task is sent to the chip under test at 11:20:10, and the chip under test runs the high-load task repeatedly for 3 seconds. Then, at 11:20:20, a high-load task is sent to the chip under test again, and the chip under test runs the high-load task repeatedly for 3 seconds.

[0089] Step S103: Record the peak power consumption of the chip under test during the test process.

[0090] During the test, the dynamic voltage and frequency adjustment function of the chip under test was activated.

[0091] In some embodiments, the chip under test is connected to a voltage test instrument and a current test instrument, and the power consumption of the chip under test is determined by the values ​​of the voltage test instrument and the current test instrument.

[0092] Alternatively, the voltage testing instrument may be an oscilloscope.

[0093] Optionally, the current testing instrument can be a current tester, etc.

[0094] In the above embodiments, the power consumption of the chip under test is determined by the values ​​of the voltage test instrument and the current test instrument. That is, the voltage measured by the voltage test instrument is multiplied by the current measured by the current test instrument at the same time to obtain the power consumption at that time.

[0095] For example, power consumption can also be tested using an oscilloscope and a current probe. For instance, connect a current probe to one channel of the oscilloscope, such as CH1. Connect another common voltage probe to another channel of the oscilloscope, such as CH2. Ensure that the ground lines of both channels on the oscilloscope are common and synchronized with the time base. On the oscilloscope, enable the mathematical function to set the operation to CH1 × CH2. The instantaneous power waveform of the chip will be displayed on the oscilloscope screen.

[0096] In some embodiments, a test start time and a test end time can be set for the test process. At the test start time, the first process of the chip under test is triggered to run a preset low-load task for the first time. Simultaneously, during the periodic execution of the low-load task, the second process of the chip under test is triggered to run a preset high-load task at second preset intervals. At the test end time, the test stops.

[0097] In some embodiments, the total test duration can be set. Timing begins from the first triggering of the first process of the chip under test to run a preset low-load task, accumulating the test duration. The test stops when the total test duration is reached.

[0098] For example, this application provides another power consumption testing method, see [link to relevant documentation]. Figure 2 As shown, Figure 2 This is a basic flowchart illustrating the power consumption testing method provided in the embodiments of this application, including: Step S201: Accumulate test duration. Then execute steps S202 and S203.

[0099] In step S202, at each first preset time interval, the first process of the chip under test is triggered to run a preset low-load task, so that the chip under test is maintained at the highest operating frequency. Then, step S204 is executed.

[0100] Step S203: During the periodic operation of the low-load task, the second process of the chip under test is triggered to run a preset high-load task every second preset time interval. Then, step S204 is executed.

[0101] Step S204: Record the peak power consumption of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is enabled during the test. Then execute step S205.

[0102] Step S205: Determine whether the test duration has reached the total test duration; if it has reached the total test duration, proceed to step S206; if it has not reached the total test duration, proceed to step S201.

[0103] Step S206, end the test.

[0104] In this way, by recording the test start time and the current time, the test duration can be automatically determined. By comparing the test duration with the total test duration, the test can be automatically stopped without human intervention, making the testing more intelligent.

[0105] For example, assuming the chip under test is a GPGPU with a maximum operating frequency of 1.75 GHz, the first preset duration is 500 milliseconds, the second preset duration is 10 seconds, and the third preset duration is 3 seconds. A low-load task is run on the system side, which involves repeatedly reading the chip's internal registers every 500 milliseconds, causing the chip's DVFS to believe that the chip is constantly working and needs to increase its frequency, thus maintaining the chip at its maximum operating frequency of 1.75 GHz. Simultaneously, a high-load injection task is run on the system side, which involves repeatedly executing a GEMM calculation task every 10 seconds, with a task duration of 3 seconds. During each high-load injection task cycle, a peak power consumption scenario is triggered. Timing begins from the first run of the low-load task on the system side to obtain the test duration. When the test duration reaches the total test duration, the peak power consumption test task is terminated.

[0106] Assume the TDP of the GPGPU chip is 450W. The DVFS determination strategy of this GPGPU chip uses power consumption sampling at 1ms intervals. The test results for this GPGPU chip are as follows: Figure 3 As shown. Figure 3 This is a schematic diagram of peak power consumption scenario triggering. Figure 3The diagram illustrates the power consumption change process that generates a peak power consumption. It is divided into six stages. In stage 1, the chip is in an idle state, with the core clock frequency at 500MHz. In stage 2, a low-load task is executed, and DVFS raises the chip's core frequency to its maximum operating frequency of 1750MHz and maintains it. In stages 3 and 4, a high-load task is executed, and the chip's power consumption begins to rise to a maximum of around 880W. In stage 5, DVFS intervenes, the chip frequency decreases, and the final chip power consumption remains around 450W (TDP). In stage 6, the high-load task ends, but the low-load task continues. DVFS raises the chip's core frequency back to its maximum operating frequency of 1750MHz, awaiting the next high-load injection task. In other words, from stage 3 to the end of stage 5, this represents the execution time of a high-load injection task within a single cycle.

[0107] Therefore, considering that peak power consumption of a chip typically requires it to operate at its highest operating frequency under the most power-consuming load, triggering the first process of the chip under test to run a preset low-load task at first preset intervals maintains the chip at its highest operating frequency. While maintaining the highest operating frequency, triggering the second process of the chip under test to run a preset high-load task allows the chip to reach the state of operating at its highest operating frequency under the most power-consuming load. Thus, each time the chip under test is triggered to run a preset high-load task, the chip's peak power consumption can be obtained, making the peak power consumption measurement process controllable. Furthermore, since dynamic voltage and frequency adjustment is enabled during measurement, the measured peak power consumption reflects the peak power consumption during actual use.

[0108] Example 2 This application provides a power supply testing method. See also... Figure 4 As shown, Figure 4 This is a basic flowchart illustrating the power supply testing method provided in the embodiments of this application, including: Step S401: At each first preset time interval, the first process of the chip under test is triggered to run a preset low-load task, so that the chip under test is kept at the highest operating frequency.

[0109] Step S402: During the periodic operation of the low-load task, the second process of the chip under test is triggered to run a preset high-load task every second preset time interval.

[0110] Step S403: Determine whether there is a problem with the power supply design based on the status of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is enabled during the test.

[0111] In some embodiments, determining whether there is a problem with the power supply design based on the state of the chip under test during the test may include: obtaining the log of the chip under test during the test; if information indicating a power supply abnormality appears in the log, determining that the chip power supply design is abnormal; otherwise, determining that the chip power supply design is normal.

[0112] For example, during testing, the chip under test (DUT) may experience a card drop due to a power supply abnormality. Correspondingly, the information indicating a card drop can be considered one type of information indicative of a power supply abnormality. During testing, the DUT's logs will display some power supply-related prompts; any of these prompts indicating a power supply abnormality can be considered information indicative of a power supply abnormality.

[0113] Thus, the chip requires a corresponding power supply when handling a load. If the chip's state becomes abnormal during load processing, there may be deficiencies in its power supply design. By observing the chip's state changes from low power consumption to peak power consumption, it's possible to accurately determine whether the chip's power supply design can meet the different power consumption variations in actual usage scenarios. Since the duration of peak power consumption depends on the timing of DVFS frequency reduction, the worst-case scenario is when DVFS has just completed a power monitoring cycle and a sudden peak load task occurs. In this case, frequency reduction will only occur during the next DVFS judgment. In this scenario, the peak power consumption fills a full DVFS monitoring cycle, which is the most demanding scenario for system power supply capabilities. If the chip's power supply design is sound during this process, then the chip's power supply design can meet the subsequent usage requirements of the chip.

[0114] It is understood that the embodiments described in Embodiment 1 are also applicable in Embodiment 2 without conflict. For the sake of brevity, they will not be repeated here.

[0115] Example 3 Based on the same inventive concept, combined with Figure 5 As shown in the figure, this application provides a power consumption testing device, including: a task testing module 1 and a recording module 2.

[0116] The task testing module 1 is used to trigger the first process of the chip under test to run a preset low-load task at a first preset time interval, so that the chip under test maintains the chip under test at its highest operating frequency; during the periodic operation of the low-load task, the second process of the chip under test is triggered to run a preset high-load task at a second preset time interval. The recording module 2 is used to record the peak power consumption of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is enabled during the test.

[0117] In some embodiments, the task test module 1 is used to trigger the first process of the chip under test to run a preset low-load task at intervals of a first preset time by: triggering the first process of the chip under test to perform a register access operation at intervals of a first preset time; the first preset time is less than the duration of the sampling window for the chip under test to perform dynamic voltage frequency adjustment.

[0118] In some embodiments, the task test module 1 is used to trigger the first process of the chip under test to run a preset low-load task at intervals of a first preset time by: triggering the first process of the chip under test to execute preset code at intervals of a first preset time, the preset code including null instructions or arithmetic logic unit operations; the first preset time is less than the duration of the sampling window for the chip under test to perform dynamic voltage frequency adjustment.

[0119] In some embodiments, the task testing module 1 is used to trigger the second process of the chip under test to run a preset high-load task at intervals of a second preset time in the following manner: a high-load task is sent to the chip under test at intervals of a second preset time; the second process of the chip under test executes the high-load task cyclically for a third preset time; the third preset time is less than the second preset time.

[0120] In some embodiments, the task testing module 1 is used to determine the preset high-load task in the following way: for each preset set of matrix multiplication parameters: when the chip under test is at a preset chip frequency, the set of matrix multiplication parameters is calculated using the chip under test, and the test power consumption generated by the chip under test is recorded; the matrix multiplication parameter corresponding to the maximum test power consumption is taken as the high-load task.

[0121] It is understood that the embodiments described in Embodiment 1 are also applicable to Embodiment 3 without conflict. For the sake of brevity, they will not be repeated here.

[0122] Example 4 Based on the same inventive concept, combined with Figure 6 As shown in the figure, this application provides a power supply testing device, including: a task testing module 1 and a power supply problem determination module 3.

[0123] The task testing module 1 is used to trigger the first process of the chip under test to run a preset low-load task at a first preset time interval, so that the chip under test maintains the chip under test at the highest operating frequency; during the periodic operation of the low-load task, the second process of the chip under test is triggered to run a preset high-load task at a second preset time interval. The power supply problem determination module 3 is used to determine whether there is a problem with the power supply design based on the status of the chip under test during the test; the dynamic voltage and frequency adjustment function of the chip under test is activated during the test.

[0124] In some embodiments, the power supply problem determination module 3 is used to determine whether there is a problem with the power supply design based on the state of the chip under test during the test by: obtaining the log of the chip under test during the test; if information indicating power supply abnormality appears in the log, it is determined that the chip power supply design is abnormal; otherwise, it is determined that the chip power supply design is normal.

[0125] It is understood that the embodiments described in Embodiment 1 are also applicable to Embodiment 4 without conflict. For the sake of brevity, they will not be repeated here.

[0126] Example 5 Based on the same inventive concept, combined with Figure 7 As shown, this application embodiment provides an electronic device, including a processor 6 and a memory 7. Optionally, the device may further include a communication interface 4 and a bus 5. The processor 6, communication interface 4, and memory 7 can communicate with each other via the bus 5. The communication interface 4 can be used for information transmission. The processor 6 can call logical instructions in the memory 7 to execute the aforementioned power consumption test method or implement the aforementioned power supply test method.

[0127] Furthermore, the logical instructions in the aforementioned memory 7 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0128] The memory 7, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of this application. The processor 6 executes the program instructions / modules stored in the memory 7 to perform functional applications and data processing, that is, to implement the power consumption test method or the power supply test method described above.

[0129] The memory 7 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 7 may include high-speed random access memory and may also include non-volatile memory.

[0130] The aforementioned processors can be data processing cores such as GPUs (Graphics Processing Units), CPUs (Central Processing Units), AI (Artificial Intelligence), NPUs (Neural Network Processing Units), ISPs (Image Signal Processors), DPUs (Display Processing Units), VPUs (Video Processing Units), and DSPs (Digital Signal Processors), or processor chips used in scenarios involving large-scale data computation. The above are merely examples and should not be construed as limiting this application.

[0131] Among them, electronic devices can be computers or servers, etc.

[0132] This application provides a storage medium storing computer-executable instructions, which are configured to execute the power consumption test method described above, or to implement the power supply test method described above.

[0133] This application provides a computer program product, which includes a computer program stored on a storage medium. The computer program includes program instructions, which, when executed by a computer, cause the computer to perform the power consumption test method described above, or to implement the power supply test method described above.

[0134] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0135] The technical solutions of this application embodiment can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this application embodiment. The aforementioned storage medium can be a non-transitory storage medium, including various media capable of storing program code such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks, or it can be a transient storage medium.

[0136] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0137] The above descriptions are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Furthermore, the above embodiments can be combined with each other to form new embodiments without conflict.

Claims

1. A power consumption test method, characterized by, The method comprises the following steps: triggering a first process of the tested chip to run a preset low-load task every first preset time interval, so that the tested chip is maintained at a highest working frequency; during the periodic running of the low-load task, triggering a second process of the tested chip to run a preset high-load task every second preset time interval; recording a peak power consumption of the tested chip during a test process, wherein a dynamic voltage frequency adjustment function of the tested chip is in an enabled state during the test process.

2. The method of claim 1, wherein, The method comprises the following steps: triggering the first process of the tested chip to perform a register access operation every first preset time interval; and 3. The method of claim 1, wherein, the first preset time interval is shorter than a sampling window of the dynamic voltage frequency adjustment of the tested chip. The method comprises the following steps:

4. The method of claim 1, wherein, triggering the first process of the tested chip to run a preset low-load task every first preset time interval, wherein the preset low-load task comprises the following steps: triggering the first process of the tested chip to run a preset code every first preset time interval, wherein the preset code comprises an empty instruction or an arithmetic logic unit operation; and the first preset time interval is shorter than a sampling window of the dynamic voltage frequency adjustment of the tested chip.

5. The method of claim 1, wherein, The method comprises the following steps: triggering the second process of the tested chip to run a preset high-load task every second preset time interval, wherein the preset high-load task comprises the following steps: issuing the high-load task to the tested chip every second preset time interval; 6. A power supply test method characterized by, the second process of the tested chip cyclically executes the high-load task for a third preset time interval; and the third preset time interval is shorter than the second preset time interval. The preset high-load task is determined by the following method: for each set of preset matrix multiplication parameters, calculating the set of matrix multiplication parameters by using the tested chip when the tested chip is at a preset chip frequency, and recording a test power consumption generated by the tested chip; 7. The method of claim 6, wherein, the matrix multiplication parameters corresponding to the maximum test power consumption are taken as the high-load task. The method comprises the following steps: triggering a first process of the tested chip to run a preset low-load task every first preset time interval, so that the tested chip is maintained at a highest working frequency; 8. A power consumption testing apparatus, characterized by comprising: during the periodic running of the low-load task, triggering a second process of the tested chip to run a preset high-load task every second preset time interval; determining whether a power supply design has a problem according to a state of the tested chip during a test process, wherein a dynamic voltage frequency adjustment function of the tested chip is in an enabled state during the test process. The method comprises the following steps: obtaining a log of the tested chip during a test process; if information representing a power supply abnormality appears in the log, determining that the chip power supply design is abnormal; otherwise, determining that the chip power supply design is normal. The method comprises the following steps: a task test module, configured to trigger a first process of a tested chip to run a preset low-load task every first preset time interval, so that the tested chip is maintained at a highest working frequency; and during the periodic running of the low-load task, trigger a second process of the tested chip to run a preset high-load task every second preset time interval. A recording module is configured to record a peak power consumption of the chip under test during a test process, and a dynamic voltage and frequency scaling function of the chip under test is in an enabled state during the test process.

9. A power supply testing apparatus characterized by comprising: The method comprises: A task testing module is configured to trigger a first process of the chip under test to run a preset low-load task every first preset time interval, so that the chip under test is maintained at a highest working frequency; and trigger a second process of the chip under test to run a preset high-load task every second preset time interval during a period of running of the low-load task; A power supply problem determining module is configured to determine whether a power supply design has a problem according to a state of the chip under test during a test process, and the dynamic voltage and frequency scaling function of the chip under test is in the enabled state during the test process.

10. An electronic device, comprising: The processor executes the computer executable instructions to implement the power consumption test method of any one of claims 1 to 5, or implement the power supply test method of any one of claims 6 or 7.

11. A storage medium, characterized by The storage medium stores computer executable instructions, and the computer executable instructions, when called and executed by the processor, cause the processor to implement the power consumption test method of any one of claims 1 to 5, or implement the power supply test method of any one of claims 6 or 7.

12. A computer program product, characterised in that, The computer program product comprises a computer program, and the computer program, when executed by the processor, implements the power consumption test method of any one of claims 1 to 5, or implements the power supply test method of any one of claims 6 or 7.

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