High-loading-capacity double-loop quick response LDO (Low Dropout Regulator) circuit
By using a high-load-capacity dual-loop fast-response LDO circuit, and utilizing active capacitor multiplication technology and a buffer-stage fast adjustment circuit, the shortcomings of LDO circuits in terms of load capacity and transient response are solved, achieving faster response speed and more stable output.
Patent Information
- Application Number
- CN202511871195.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-02-13
AI Technical Summary
Existing LDO circuits are insufficient in terms of load capacity and transient response, making it difficult to meet the requirements of modern precision control instruments.
A high-load-capacity dual-loop fast-response LDO circuit is adopted. The positions of the primary and secondary poles are changed by active capacitor multiplication technology. Combined with a buffer stage fast adjustment circuit and a current limiting circuit, the circuit's load-carrying capacity and load transient response are enhanced.
It significantly improves the load-carrying capacity and transient response speed of LDO circuits, reduces overshoot voltage and recovery time, and saves the area of external capacitors.
Smart Images
Figure CN121523486A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of power management, and particularly relates to a high-load-capacity double-loop fast-response LDO circuit. BACKGROUND
[0002] A low-dropout linear regulator (LDO) is a kind of key power management chip, and its core function is to provide a stable and low-noise direct-current output voltage when the input voltage and load condition change. Because the LDO has the advantages of simple structure, few peripheral components, low noise and high power supply rejection ratio (PSRR), the LDO is widely applied to fields such as portable electronic devices, medical instruments, communication systems and radio frequency circuits which have high requirements on power quality.
[0003] With the rapid development of various precision control instruments, the requirements for the load capacity and load transient response of the internal power management module are also increasing day by day. SUMMARY
[0004] In view of the above problems, the application provides a high-load-capacity double-loop fast-response LDO circuit, which has a significant improvement in load capacity and load transient response compared with a conventional LDO with an off-chip capacitor.
[0005] To achieve the above application purposes, the technical scheme of the application is as follows:
[0006] The high-load-capacity double-loop fast-response LDO circuit comprises a reference current source, a reference voltage source, a bias circuit, an error amplifier, a buffer stage fast adjustment circuit, a compensation capacitor, a feedback network, a current limiting circuit, an output stage adjustment tube and an off-chip capacitor.
[0007] The bias circuit provides bias for the error amplifier.
[0008] The error amplifier, the feedback network, the output stage adjustment tube and the off-chip capacitor form an LDO architecture with an off-chip capacitor.
[0009] The compensation capacitor is compensated by using an active capacitor multiplication technology, the primary and secondary pole positions are changed, and the load capacity of the circuit is strengthened.
[0010] The buffer stage fast adjustment circuit provides a fast response loop for the LDO to respond to load jump, and reduces the overshoot voltage and recovery time when the load jump occurs.
[0011] The current limiting circuit limits the gate voltage of the adjustment tube through the breakdown clamping of the Zener diode, and realizes the current limiting function.
[0012] The reference current source is used to provide bias current for the error amplifier.
[0013] The reference voltage source is configured to provide a reference input voltage for the error amplifier.
[0014] Further, the biasing circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor.
[0015] The gate and the drain of the first PMOS transistor are connected to each other, and are connected to a reference current source and the gate of the second PMOS transistor; the sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply VCC; the gate and the drain of the first NMOS transistor are connected to each other, and are connected to the drain of the second PMOS transistor; the gate and the drain of the second NMOS transistor are connected to each other, and are connected to the source of the first NMOS transistor; and the source of the second NMOS transistor is connected to a ground rail.
[0016] Further, the error amplifier comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor.
[0017] The gate of the third PMOS transistor is connected to the gate of the first PMOS transistor; the source of the third PMOS transistor is connected to the power supply VCC; the drain of the third PMOS transistor is connected to the sources of the fourth PMOS transistor and the fifth PMOS transistor; the gate of the fourth PMOS transistor is connected to a reference voltage VREF; the gate of the fifth PMOS transistor is connected to a feedback voltage VFB; the drain of the fourth PMOS transistor is connected to the source of the third NMOS transistor and the drain of the fifth NMOS transistor; the drain of the fifth PMOS transistor is connected to the source of the fourth NMOS transistor and the drain of the sixth NMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to the gate of the second NMOS transistor; the sources of the fifth NMOS transistor and the sixth NMOS transistor are connected to the ground rail; the gate and the drain of the eighth PMOS transistor are connected to each other, and are connected to the drain of the third NMOS transistor and the gate of the ninth PMOS transistor; the gate and the drain of the sixth PMOS transistor are connected to each other, and are connected to the source of the eighth PMOS transistor and the gate of the seventh PMOS transistor; the sources of the sixth PMOS transistor and the seventh PMOS transistor are connected to the power supply VCC; the drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor; the drain of the ninth PMOS transistor is connected to the drain of the fourth NMOS transistor, as an output of the error amplifier.
[0018] Further, the buffer stage rapid adjustment circuit comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, a second resistor, a tenth PMOS transistor and an eleventh PMOS transistor.
[0019] The gate of the seventh NMOS transistor is connected to the output of the error amplifier; the sources of the seventh and eighth NMOS transistors are connected to one end of the first resistor; the other end of the first resistor is connected together with one end of the second and third resistors and the source of the tenth NMOS transistor as the output of the LDO; the gate and drain of the tenth PMOS transistor are interconnected and connected to the drain of the seventh NMOS transistor and the gate of the eleventh PMOS transistor; the sources of the tenth and eleventh PMOS transistors are connected to the power supply VCC; the gate and drain of the eighth NMOS transistor are interconnected and connected to the drain of the eleventh PMOS transistor and the gate and drain of the ninth NMOS transistor as the output of the buffer stage fast adjustment circuit; the source of the ninth NMOS transistor is connected to one end of the second resistor.
[0020] Furthermore, the compensation capacitor is a first capacitor;
[0021] One end of the first capacitor is connected to the gate of the first PMOS transistor; the other end is connected to the output of the error amplifier.
[0022] Furthermore, the feedback network includes a third resistor and a fourth resistor;
[0023] One end of the third resistor is connected to the LDO output; the other end of the third resistor is connected to one end of the fourth resistor, and the connection point is connected to the gate of the fifth PMOS transistor as a feedback voltage node; the other end of the fourth resistor is connected to the ground rail.
[0024] Furthermore, the current limiting circuit includes a first Zener diode and a second Zener diode;
[0025] The cathode of the first Zener tube is connected to the output of the error amplifier; the anode of the first Zener tube is connected to the cathode of the second Zener tube; and the anode of the second Zener tube is connected to the ground rail.
[0026] Furthermore, the output stage regulating transistor is the tenth NMOS transistor;
[0027] The gate of the tenth NMOS transistor is connected to the output of the buffer stage fast adjustment circuit; the drain of the tenth NMOS transistor is connected to the power supply VCC; and the source of the tenth NMOS transistor is connected to the output of the LDO.
[0028] Furthermore, the ratio of the first PMOS transistor to the second PMOS transistor is 1:1; the ratio of the first PMOS transistor to the third PMOS transistor is 1:N; the ratio of the first NMOS transistor to the third NMOS transistor and the fourth NMOS transistor is 1:N; the ratio of the second NMOS transistor to the fifth NMOS transistor and the sixth NMOS transistor is 1:2N; where N is any integer greater than zero.
[0029] The beneficial effects of this invention are as follows: by using active capacitor multiplication technology for compensation, the positions of the primary and secondary points are changed, the circuit's load-carrying capacity is enhanced, and a buffer stage fast adjustment loop is added, which can achieve a fast response to load jumps and effectively reduce the overshoot voltage and recovery time when load jumps occur; from another perspective, it can reduce the external capacitor and save area. Attached Figure Description
[0030] Figure 1 This is a transistor-level schematic diagram of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention.
[0031] Figure 2 This is a schematic diagram of a traditional LDO circuit with external capacitors.
[0032] Figure 3 This is a simulation diagram of the loop stability of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention under heavy load conditions.
[0033] Figure 4 The high-load-capacity dual-loop fast-response LDO circuit proposed in this invention is shown in the simulation diagram of the stability of the heavy-load loop in the absence of a compensation network.
[0034] Figure 5 This is a simulation diagram of the loop stability of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention under light load conditions.
[0035] Figure 6 This is a simulation diagram of the load-skipping transient of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention, under two conditions: with and without a buffer stage fast adjustment circuit.
[0036] Figure 7 This is a simulation diagram of the load dump transient of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention, under two conditions: with and without a buffer stage fast adjustment circuit. Detailed Implementation
[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] This invention proposes a high-load-capacity dual-loop fast-response LDO circuit, comprising a reference current source, a reference voltage source, a bias circuit, an error amplifier, a buffer stage fast adjustment circuit, a compensation capacitor, a feedback network, a current limiting circuit, an output stage adjustment transistor, and an external capacitor, such as...Figure 1 As shown, the circuit power supply is connected to VCC.
[0039] The bias circuit includes: NMOS transistors: MN1, MN2; PMOS transistors: MP1, MP2
[0040] The bias circuit replicates the reference current source to other branches to power other modules.
[0041] The error amplifier, feedback network, output stage adjustment transistors, and external capacitors include: NMOS transistors: MN3, MN4, MN5, MN6, MN10; PMOS transistors: MP3, MP4, MP5, MP6, MP7, MP8, MP9; resistors: R1, R2; and capacitor: COUT. These four parts together form a traditional LDO architecture with external capacitors, such as... Figure 2 As shown.
[0042] The current limiting circuit includes Zener transistors: D1 and D2. The Zener transistors clamp the gate potential of MN7 so that it does not exceed the clamping value, and therefore the gate potential of MN10 will also not exceed the clamping value, thus limiting the current magnitude.
[0043] The reference current source is used to provide bias current for the error amplifier.
[0044] The reference voltage source is used to provide a reference input voltage for the error amplifier.
[0045] Furthermore, the bias circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
[0046] The gate and drain of the first PMOS transistor are interconnected and connected to both the reference current source and the gate of the second PMOS transistor; the sources of the first and second PMOS transistors are connected to the power supply VCC; the gate and drain of the first NMOS transistor are interconnected and connected to both the drain of the second PMOS transistor; the gate and drain of the second NMOS transistor are interconnected and connected to both the source of the first NMOS transistor; the source of the second NMOS transistor is connected to the ground rail.
[0047] Furthermore, the error amplifier includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
[0048] The gate of the third PMOS transistor is connected to the gate of the first PMOS transistor; the source of the third PMOS transistor is connected to the power supply VCC; the drain of the third PMOS transistor is connected to the sources of the fourth and fifth PMOS transistors; the gate of the fourth PMOS transistor is connected to the reference voltage VREF; the gate of the fifth PMOS transistor is connected to the feedback voltage VFB; the drain of the fourth PMOS transistor is connected to the source of the third NMOS transistor and the drain of the fifth NMOS transistor; the drain of the fifth PMOS transistor is connected to the source of the fourth NMOS transistor and the drain of the sixth NMOS transistor; the gates of the fifth and sixth NMOS transistors are connected to... The gate of the second NMOS transistor is connected to the ground rail; the sources of the fifth and sixth NMOS transistors are connected to the ground rail; the gate and drain of the eighth PMOS transistor are interconnected and connected to the drain of the third NMOS transistor and the gate of the ninth PMOS transistor; the gate and drain of the sixth PMOS transistor are interconnected and connected to the source of the eighth PMOS transistor and the gate of the seventh PMOS transistor; the sources of the sixth and seventh PMOS transistors are connected to the power supply VCC; the drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor; the drain of the ninth PMOS transistor is connected to the drain of the fourth NMOS transistor, serving as the output of the error amplifier.
[0049] Furthermore, the buffer stage fast adjustment circuit includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, a second resistor, a tenth PMOS transistor, and an eleventh PMOS transistor;
[0050] The gate of the seventh NMOS transistor is connected to the output of the error amplifier; the sources of the seventh and eighth NMOS transistors are connected to one end of the first resistor; the other end of the first resistor is connected together with one end of the second and third resistors and the source of the tenth NMOS transistor as the output of the LDO; the gate and drain of the tenth PMOS transistor are interconnected and connected to the drain of the seventh NMOS transistor and the gate of the eleventh PMOS transistor; the sources of the tenth and eleventh PMOS transistors are connected to the power supply VCC; the gate and drain of the eighth NMOS transistor are interconnected and connected to the drain of the eleventh PMOS transistor and the gate and drain of the ninth NMOS transistor as the output of the buffer stage fast adjustment circuit; the source of the ninth NMOS transistor is connected to one end of the second resistor.
[0051] Furthermore, the compensation capacitor is a first capacitor;
[0052] One end of the first capacitor is connected to the gate of the first PMOS transistor; the other end is connected to the output of the error amplifier.
[0053] Furthermore, the feedback network includes a third resistor and a fourth resistor;
[0054] One end of the third resistor is connected to the LDO output; the other end of the third resistor is connected to one end of the fourth resistor, and the connection point is connected to the gate of the fifth PMOS transistor as a feedback voltage node; the other end of the fourth resistor is connected to the ground rail.
[0055] Furthermore, the current limiting circuit includes a first Zener diode and a second Zener diode;
[0056] The cathode of the first Zener tube is connected to the output of the error amplifier; the anode of the first Zener tube is connected to the cathode of the second Zener tube; and the anode of the second Zener tube is connected to the ground rail.
[0057] Furthermore, the output stage regulating transistor is the tenth NMOS transistor;
[0058] The gate of the tenth NMOS transistor is connected to the output of the buffer stage fast adjustment circuit; the drain of the tenth NMOS transistor is connected to the power supply VCC; and the source of the tenth NMOS transistor is connected to the output of the LDO.
[0059] Furthermore, the ratio of the first PMOS transistor to the second PMOS transistor is 1:1; the ratio of the first PMOS transistor to the third PMOS transistor is 1:N; the ratio of the first NMOS transistor to the third NMOS transistor and the fourth NMOS transistor is 1:N; the ratio of the second NMOS transistor to the fifth NMOS transistor and the sixth NMOS transistor is 1:2N; where N is any integer greater than zero.
[0060] The compensation capacitor is capacitor C1, and its two ends are respectively connected to the gate of MP1 and the output terminal of the error amplifier.
[0061] like Figure 2 The diagram shows the structure of a traditional LDO circuit with external capacitors. Due to the presence of these external capacitors, the dominant pole is typically located at the output node of the LDO circuit. When the circuit is under heavy load, the dominant pole increases in size and moves closer to the secondary node, potentially causing loop instability. In this invention, since the current ratio of the branches containing MP1 and MN4 is 1:N, according to the active capacitor multiplication theory, this is equivalent to connecting an N-fold capacitor (C1) to the output of the error amplifier. The error amplifier output has an equivalent large capacitor; therefore, even with the external capacitors, the dominant pole of the circuit remains at the output node of the error amplifier, and the LDO output node becomes the secondary node. Under heavy load, the secondary node moves further away, making the system more stable. Compared to traditional LDO circuits with external capacitors, this effectively improves the circuit's load-carrying capacity.
[0062] like Figure 3 The figure shows the loop stability simulation of a high-load-capacity dual-loop fast-response LDO circuit proposed in this invention under heavy load (100mA). It can be seen from the figure that its bandwidth is 2.68MHz and its phase margin is 80°.
[0063] like Figure 4 As shown in the figure, the high-load-capacity dual-loop fast-response LDO circuit proposed in this invention is a simulation diagram of the loop stability under heavy load (100mA) without compensation network. It can be seen from the figure that its bandwidth is 2.5MHz and the phase margin is 36°. Figure 3 Figure 4 The comparison shows that this compensation network significantly improves stability under heavy load conditions.
[0064] Furthermore, as the above analysis shows, under this compensation, the output node of the error amplifier is the dominant pole, and the LDO output is the secondary pole. Under light load, the secondary pole tends to move closer to the dominant pole, which may lead to instability. For example... Figure 5 The figure shows the loop stability simulation of the high-load-capacity dual-loop fast-response LDO circuit proposed in this invention under light load (1mA). The figure shows a bandwidth of 740kHz and a phase margin of 75°. The results indicate that the phase margin is not significantly different under light and heavy load conditions. This is because under light load conditions, the secondary point and the left-half-plane zero introduced by the compensation capacitor C1 are approximately equal, resulting in better zero-point compensation. Therefore, it can be seen that this invention exhibits good stability under both light and heavy load conditions.
[0065] The buffer stage fast adjustment circuit includes: NMOS transistors: MN7, MN8, MN9; PMOS transistors: MP10, MP11; resistors: R1, R2.
[0066] When a load change occurs, taking an increase in load current as an example, since the current source at the tail of the buffer stage fast adjustment circuit is composed of resistor R1 and one end is connected to VOUT, when the VOUT voltage undershoots, the current flowing through R1 and MN7 will increase. The increased current is sent to the branch containing MN9 and R2 through current mirrors MP10 and MP11 to charge COUT, providing a fast recovery loop for the LDO circuit, so that VOUT can recover to the reference value more quickly.
[0067] like Figure 6 The figure shows the load-slip transient simulation of the high-load-capacity dual-loop fast-response LDO circuit proposed in this invention, with and without a buffer stage fast adjustment circuit. The load jumps from 1mA to 10mA within 5ns. As can be seen from the figure, the output voltage of this invention drops by 140mV in a very short time and then stabilizes after 3us. In contrast, without the buffer stage fast adjustment circuit, the output voltage drops by 170mV in a very short time and then stabilizes after 4us. The comparison demonstrates that the buffer stage fast adjustment circuit in this invention significantly improves the load-slip transient performance of the LDO circuit.
[0068] Similarly, Figure 7The figure shows the load dump transient simulation of the high-load-capacity dual-loop fast-response LDO circuit proposed in this invention, with and without a buffer stage fast adjustment circuit. The load jumps from 10mA to 1mA within 5ns. As can be seen from the figure, the output voltage of this invention rises by 106mV in a very short time and then stabilizes after 860ns; while without the buffer stage fast adjustment circuit, the output voltage rises by 140mV in a very short time and then stabilizes after 1.1us. The comparison shows that the buffer stage fast adjustment circuit in this invention also significantly improves the load dump transient performance of the LDO circuit.
[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high-load-capacity dual-loop fast-response LDO circuit, characterized in that, It includes a reference current source, a reference voltage source, a bias circuit, an error amplifier, a buffer stage fast adjustment circuit, a compensation capacitor, a feedback network, a current limiting circuit, an output stage adjustment transistor, and an external capacitor; The bias circuit provides bias for the error amplifier; An LDO architecture with external capacitors consists of an error amplifier, a feedback network, an output stage adjustment transistor, and an external capacitor. The compensation capacitor uses active capacitance multiplication technology to compensate, changing the positions of the primary and secondary poles and enhancing the circuit's load-carrying capacity. The buffer stage fast adjustment circuit provides the LDO with a fast response loop to handle load changes, reducing the overshoot voltage and recovery time when load changes occur; The current limiting circuit limits the gate voltage of the regulating transistor by the breakdown clamping of the Zener diode, thereby achieving the current limiting function. The reference current source is used to: provide bias current for the error amplifier; The reference voltage source is used to provide a reference input voltage for the error amplifier.
2. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The bias circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The gate and drain of the first PMOS transistor are interconnected and connected to both the reference current source and the gate of the second PMOS transistor; the sources of the first and second PMOS transistors are connected to the power supply VCC; the gate and drain of the first NMOS transistor are interconnected and connected to both the drain of the second PMOS transistor; the gate and drain of the second NMOS transistor are interconnected and connected to both the source of the first NMOS transistor. The source of the second NMOS transistor is connected to the ground rail.
3. The high-load-capacity dual-loop fast-response LDO circuit according to claim 2, characterized in that, The error amplifier includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The gate of the third PMOS transistor is connected to the gate of the first PMOS transistor; the source of the third PMOS transistor is connected to the power supply VCC; the drain of the third PMOS transistor is connected to the sources of the fourth and fifth PMOS transistors; the gate of the fourth PMOS transistor is connected to the reference voltage VREF; the gate of the fifth PMOS transistor is connected to the feedback voltage VFB; the drain of the fourth PMOS transistor is connected to the source of the third NMOS transistor and the drain of the fifth NMOS transistor; the drain of the fifth PMOS transistor is connected to the source of the fourth NMOS transistor and the drain of the sixth NMOS transistor; the gates of the fifth and sixth NMOS transistors are connected to... The gate of the second NMOS transistor is connected to the ground rail; the sources of the fifth and sixth NMOS transistors are connected to the ground rail; the gate and drain of the eighth PMOS transistor are interconnected and connected to the drain of the third NMOS transistor and the gate of the ninth PMOS transistor; the gate and drain of the sixth PMOS transistor are interconnected and connected to the source of the eighth PMOS transistor and the gate of the seventh PMOS transistor; the sources of the sixth and seventh PMOS transistors are connected to the power supply VCC; the drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor; the drain of the ninth PMOS transistor is connected to the drain of the fourth NMOS transistor, serving as the output of the error amplifier.
4. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The buffer stage fast adjustment circuit includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, a second resistor, a tenth PMOS transistor, and an eleventh PMOS transistor; The gate of the seventh NMOS transistor is connected to the output of the error amplifier; the sources of the seventh and eighth NMOS transistors are connected to one end of the first resistor; the other end of the first resistor is connected together with one end of the second and third resistors and the source of the tenth NMOS transistor to serve as the output of the LDO. The gate and drain of the tenth PMOS transistor are interconnected and connected to the drain of the seventh NMOS transistor and the gate of the eleventh PMOS transistor; the sources of the tenth and eleventh PMOS transistors are connected to the power supply VCC; the gate and drain of the eighth NMOS transistor are interconnected and connected to the drain of the eleventh PMOS transistor and the gate and drain of the ninth NMOS transistor as the output of the buffer stage fast adjustment circuit. The source of the ninth NMOS transistor is connected to one end of the second resistor.
5. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The compensation capacitor is the first capacitor; One end of the first capacitor is connected to the gate of the first PMOS transistor; the other end is connected to the output of the error amplifier.
6. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The feedback network includes a third resistor and a fourth resistor; One end of the third resistor is connected to the LDO output; the other end of the third resistor is connected to one end of the fourth resistor, and the connection point is connected to the gate of the fifth PMOS transistor as a feedback voltage node; the other end of the fourth resistor is connected to the ground rail.
7. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The current limiting circuit includes a first Zener diode and a second Zener diode; The cathode of the first Zener tube is connected to the output of the error amplifier; the anode of the first Zener tube is connected to the cathode of the second Zener tube; and the anode of the second Zener tube is connected to the ground rail.
8. The high-load-capacity dual-loop fast-response LDO circuit according to claim 1, characterized in that, The output stage regulating transistor is the tenth NMOS transistor; The gate of the tenth NMOS transistor is connected to the output of the buffer stage fast adjustment circuit; the drain of the tenth NMOS transistor is connected to the power supply VCC; and the source of the tenth NMOS transistor is connected to the output of the LDO.
9. The high-load-capacity dual-loop fast-response LDO circuit according to claim 3, characterized in that, The ratio of the first PMOS transistor to the second PMOS transistor is 1:1; the ratio of the first PMOS transistor to the third PMOS transistor is 1:N; the ratio of the first NMOS transistor to the third NMOS transistor and the fourth NMOS transistor is 1:N; the ratio of the second NMOS transistor to the fifth NMOS transistor and the sixth NMOS transistor is 1:2N; N is any integer greater than zero.