Packet display compensation

Abstract

An electronic device may include a display having a native domain. The image to be displayed may have a packet domain, centrally dented with groups having different resolutions based on the user's gaze point and / or other characteristics. The images may be compensated in the packet domain using one or more compensation circuits. For example, the depressed image may be compensated for horizontal crosstalk, multi-line horizontal crosstalk, and / or IR drop in the packet domain. Alternatively or in addition, the display may include a frame buffer, and the images may be written into the frame buffer with an intra-frame pause. The intra-frame pause may be initiated based on decentration of a given image, or may be initiated in response to a signal from a frame buffer that the frame buffer has been full.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 988,577, filed December 19, 2024, and U.S. Provisional Patent Application No. 63 / 682,325, filed August 12, 2024, which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, including electronic devices with displays. BACKGROUND

[0003] Electronic devices often include displays that provide visual content to a viewer. The display can include an array of display pixels, such as organic light-emitting diode display pixels or liquid crystal display pixels. Display driver circuitry coupled to the array of display pixels can control operation of the array of display pixels. SUMMARY

[0004] One aspect of the disclosure provides a display. The display can include an array of pixels configured to display an image and display driver circuitry coupled to the array of pixels. The display driver circuitry is configured to foveate the image displayed by the array of pixels by adjusting a first resolution of a first group of pixels of the array of pixels and a second resolution of a second group of pixels of the array of pixels. The display can also include compensation circuitry configured to apply a compensation to the foveated image based on the first resolution of the first group of pixels and the second resolution of the second group of pixels.

[0005] One aspect of the disclosure provides a method of displaying an image using an array of pixels. The method can include generating a stream of image data forming an image, foveating the image into a foveated space in which a first group of pixels of the array of pixels has a first resolution and a second group of pixels of the array of pixels has a second resolution, and applying a compensation to the image in the foveated space based on the first resolution of the first group of pixels and the second resolution of the second group of pixels.

[0006] One aspect of the disclosure provides an electronic device. The electronic device can include a sensor and a display. The display can include an array of pixels configured to display an image and display driver circuitry coupled to the array of pixels. The display driver circuitry can be configured to foveate the image displayed by the array of pixels into a foveated space based on a measurement from the sensor. The display can also include compensation circuitry configured to apply a compensation to the image in the foveated space. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic diagram of an illustrative electronic device with a display in accordance with some embodiments.

[0008] Figure 2 is a top view of an exemplary display providing an image to a viewer in accordance with some embodiments.

[0009] Figure 3 is a front view of an exemplary image with foveated grouping regions in accordance with some embodiments.

[0010] Figure 4A and Figure 4B is a diagram of an exemplary open-loop intra-frame pause (IFP) in accordance with some embodiments.

[0011] Figure 5 is a diagram of an exemplary closed-loop IFP in accordance with some embodiments.

[0012] Figure 6 is an exemplary timing diagram for grouped image data readout using IFP in accordance with some embodiments.

[0013] Figure 7 is a diagram of exemplary horizontal cross-talk artifacts in an image in accordance with some embodiments.

[0014] Figure 8 is a diagram of exemplary horizontal cross-talk compensation circuitry for grouped image data in accordance with some embodiments.

[0015] Figure 9 is a diagram of exemplary multi-line horizontal cross-talk artifacts in an image in accordance with some embodiments.

[0016] Figure 10A and Figure 10B is an exemplary timing diagram for multi-line horizontal cross-talk in an image displayed on a display with grouped scanning in accordance with some embodiments.

[0017] Figure 11 is an exemplary timing diagram for multi-line horizontal cross-talk in an image displayed on a display with native scanning in accordance with some embodiments.

[0018] Figure 12 is a diagram of exemplary multi-line horizontal cross-talk compensation circuitry for grouped image data in accordance with some embodiments.

[0019] Figure 13 is a diagram of exemplary IR drop artifacts in an image in accordance with some embodiments.

[0020] Figure 14 is a diagram of exemplary circuitry that can be used for IR drop compensation in accordance with some embodiments.

[0021] Figure 15 is a diagram of exemplary IR drop compensation circuitry in accordance with some embodiments.

[0022] Figure 16 This is a flowchart of exemplary method steps for compensating for central concavity in a grouped space, according to some implementation schemes. Detailed Implementation

[0023] Figure 1 The illustration shows exemplary electronic devices of various types that may be equipped with displays. Electronic device 10 may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player or other handheld or portable electronic device, a smaller device (such as a wristwatch, a wristband, a headset or handset, an augmented reality (AR) headset and / or a virtual reality (VR) headset, a device embedded in glasses or other equipment worn on a user's head, or other wearable or micro-devices), a display, a computer monitor containing an embedded computer, a computer monitor not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), or other electronic equipment.

[0024] like Figure 1 As shown, electronic device 10 may have control circuitry 12. Control circuitry 12 may be configured to perform operations within electronic device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code and other data used to perform operations within electronic device 10 are stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) within control circuitry 12. Software code may sometimes be referred to as software, data, program instructions, commands, or code. Non-transitory computer-readable storage medium (sometimes commonly referred to as memory) may include non-volatile memory such as non-volatile random access memory (NVRAM), one or more hard disk drives (e.g., disk drives and / or solid-state drives), one or more removable flash drives, or other removable media. Memory may also include volatile memory such as random access memory (e.g., dynamic random access memory and / or static random access memory). Software stored on non-transitory computer-readable storage medium may be executed on processing circuitry of control circuitry 12. Processing circuitry may include application-specific integrated circuits (ASICs) having processing circuitry, one or more microprocessors, digital signal processors, graphics processing units, central processing units (CPUs), or other processing circuitry.

[0025] exist Figure 1In the example of FIG. 1, control circuitry 12 can include system circuitry 17 (sometimes referred to as system on a chip (SoC) 17) that integrates one or more microprocessors, multi-core processors, microcontrollers, application-specific integrated circuits, and / or other types of processing circuitry for control circuitry 12. Control circuitry 12 can also include one or more graphics processing units (GPUs) 16 and display driver circuitry 18. Display driver circuitry 18 can include one or more integrated circuits (e.g., display driver integrated circuits) that implement thin-film transistor driver circuitry, data programming or load circuitry, timing controllers, and / or other suitable circuitry for operating display components, such as display pixels in a display.

[0026] To support communication between device 10 and external equipment, control circuitry 12 can use communication circuitry 20 to communicate. Communication circuitry 20 can include antennas, radio-frequency transceiver circuitry, radio components, and other wireless communication circuitry and / or wired communication circuitry. In some example configurations, portions of communication circuitry 20 (e.g., radio components or baseband processors) can be implemented or included as part of the processing circuitry of control circuitry 12.

[0027] Communication circuitry 20 can support one-way and / or two-way wireless communication between device 10 and external equipment over one or more wireless links. As an example, communication circuitry 20 can include wireless communication circuitry that supports communication over a wireless personal area network link (e.g., a Bluetooth® link), a wireless local area network link (e.g., a Wi-Fi® link), a near-field communication link, a cellular network link (e.g., a 60 GHz link or other millimeter wave link and / or other cellular network link using other radio frequency bands), and / or any other suitable wired or wireless communication link. As another example, communication circuitry 20 can include wired communication circuitry that supports communication over a Universal Serial Bus (USB) link, a High-Definition Multimedia Interface (HDMI) link, a Thunderbolt link, and / or any other suitable wired communication link. As another example, communication circuitry 20 can include wired communication circuitry that supports communication over a Universal Serial Bus (USB) link, a High-Definition Multimedia Interface (HDMI) link, a Thunderbolt link, and / or any other suitable wired communication link.

[0028] Device 10 (if desired) can include power circuitry for sending and / or receiving wired and / or wireless power, and can include a battery or other energy storage device. For example, device 10 can include a coil and a rectifier circuit that uses the coil to receive wireless power provided to components in device 10 (e.g., an energy storage device, control circuitry 12, etc.).

[0029] Input-output devices in device 10, such as input-output device 22, can be used to receive input provided to device 10 (e.g., captured images, user speech or other sound input, user haptic or other force input, etc.) and / or to provide output from device 10 to an external environment (e.g., to a user of device 10 and / or to external equipment). In particular, a user can provide commands to control the operation of device 10 through input-output device 22, and can use input-output device 22 to receive status information and other output from device 10. As examples, input-output device 22 can include buttons, joysticks, scroll wheels, trackpads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, and / or other electrical components.

[0030] In addition, input-output device 22 can include one or more displays, such as display 24. Display 24 can be a touchscreen display that includes a touch sensor for gathering touch input from a user, or display 24 can be insensitive to touch. The touch sensor of display 24 can be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, light-based touch sensors, and / or other suitable touch sensor arrangements.

[0031] Display 24 can be an organic light-emitting diode display, a liquid crystal display, an electrophoretic display, an electro-wetting display, a plasma display, a microelectromechanical systems display, a display having an array of pixels formed from crystalline semiconductor light-emitting diode dies (sometimes referred to as micro-LEDs), and / or a display based on another desired display technology. Configurations in which display 24 is an organic light-emitting diode display are sometimes described as examples herein.

[0032] Display 24 can have a rectangular shape (i.e., display 24 can have a rectangular footprint and a rectangular perimeter edge extending around the rectangular footprint) or can have another suitable shape. Display 24 can be planar or can have a curved profile.

[0033] Some types of electronic device 10 can include two displays 24. In one possible arrangement, a first display 24 can be positioned on one side of the device 10 and a second display 24 can be positioned on a second, opposite side of the device 10. Thus, the first and second displays 24 can have a back-to-back arrangement, providing visual content in opposite directions (e.g., to different users). One or both of the displays 24 can be curved. Alternatively or additionally, in another possible arrangement, such as in a head-mounted device, the device 10 can include a first display 24 that displays images for a user’s first eye and a second display 24 that displays images for a user’s second eye.

[0034] The sensors in the input-output devices 22 can include force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors such as microphones, touch and / or proximity sensors such as capacitive sensors (e.g., two-dimensional capacitive touch sensors integrated into the displays 24, two-dimensional capacitive touch sensors that overlap the displays 24, and / or touch sensors that form buttons, trackpads, or other input devices that are not associated with the displays), and other sensors. If desired, the sensors in the input-output devices 22 can include optical sensors such as optical sensors that emit and detect light, ultrasonic sensors, optical touch sensors, optical proximity sensors, and / or other touch and / or proximity sensors, monochrome and color ambient light sensors, image sensors, fingerprint sensors, temperature sensors, sensors for measuring three-dimensional touchless gestures (“air gestures”), pressure sensors, sensors for detecting position, orientation, and / or motion (e.g., accelerometers, magnetic sensors such as compass sensors, gyroscopes, and / or inertial measurement units containing some or all of these sensors), health sensors, radio frequency sensors, depth sensors (e.g., structured light sensors and / or depth sensors based on stereoscopic imaging devices), optical sensors such as self-mixing sensors and optical detection and ranging (lidar) sensors that acquire time-of-flight measurements, humidity sensors, moisture sensors, gaze tracking sensors, and / or other sensors.

[0035] Device 10 may include a camera and other components forming part of gaze and / or head tracking system 26. The camera or other components of system 26 may be oriented toward the viewer's intended position and may track the viewer's eyes and / or head (e.g., images and other information captured by system 26 may be analyzed by control circuitry 12 to determine the position of the viewer's eyes (e.g., the user's gaze point) and / or head). This head position information obtained by system 26 may be used to determine the appropriate orientation in which it should guide the displayed content from display 24. Eye and / or head tracking system 26 may include any desired number / combination of infrared and / or visible light detectors. Eye and / or head tracking system 26 may optionally include a light emitter to illuminate the scene.

[0036] In operation, circuitry 12 can be used to run software, such as operating system code and applications, on device 10. During operation of device 10, the software running on control circuitry 12 can display images on display 24 using the pixel array in display 24. During some operations, the image displayed on display 24 can be adjusted based on input to input-output device 22. For example, the image displayed on display 24 can be centrally concave based on measurements from eye-tracking system 26, such as based on the user's gaze point.

[0037] Figure 2 A top view of an illustrative head-mounted device is shown. (See attached image.) Figure 2 As shown, a head-mounted device, such as electronic device 10, may have a head-mounted support structure, such as a housing 15. The housing 15 may include portions (e.g., head-mounted support structure 15T) for allowing the device 10 to be worn on a user's head. The support structure 15T may be formed of fabric, polymer, metal, and / or other materials. The support structure 15T may form a strap or other head-mounted support structure to help support the device 10 on the user's head. The main support structure of the housing 15 (e.g., a head-mounted housing such as a main housing portion 15M) may support electronic components such as a display 24.

[0038] The main housing portion 15M can include a housing structure formed from metal, polymer, glass, ceramic, and / or other materials. For example, the housing portion 15M can have a housing wall on the front face F and housing walls on the adjacent top, bottom, left, and right faces formed from rigid polymer or other rigid support structure, and these rigid walls can optionally be covered with electronic components, fabric, leather, or other soft materials, etc. The housing portion 15M can also have internal support structures such as a frame (chassis) and / or structures that perform multiple functions such as controlling airflow and heat dissipation while providing structural support. The walls of the housing portion 15M can enclose the internal components 38 in the internal region 34 of the device 10, and can separate the internal region 34 from the environment (external region 36) surrounding the device 10. The internal components 38 can include integrated circuits, actuators, batteries, sensors (e.g., Figure 1 The input-output device 22), and / or other circuitry and structures for the device 10. The housing 15 can be configured to be worn on a user's head, and can form eyewear, frame eyewear, a hat, a mask, a helmet, goggles, and / or other head-mounted device. Configurations in which the housing 15 forms goggles are sometimes described as examples herein.

[0039] The front face F of the housing 15 can face outward away from a user's head and face. The opposite back face R of the housing 15 can face a user. Portions of the housing 15 located on the back face R (e.g., portions of the main housing 15M) can form a cover such as cover 15C (sometimes referred to as a visor). The presence of the cover 15C on the back face R can help to conceal internal housing structures, internal components 38, and / or other structures in the internal region 34 from being seen by a user.

[0040] The device 10 can have one or more cameras such as camera 46. Figure 2 The camera 46 mounted on the front face F and facing outward (toward the front of the device 10 and away from a user) can sometimes be referred to herein as a forward or front-facing camera. The camera 46 can capture visual odometry information, image information processed to locate objects in a user's field of view (e.g., so that virtual content can be properly registered with respect to real-world objects), image content for display in real-time for a user of the device 10, and / or other suitable image data. For example, the forward (front) camera 46 can allow the device 10 to monitor movement of the device 10 with respect to the environment surrounding the device 10 (e.g., the camera can be used to form part of a visual odometry system or a visual inertial odometry system). The forward camera 46 can also be used to capture images of the environment for display to a user of the device 10. If desired, images from multiple forward cameras can be merged with each other and / or forward camera content can be merged with computer-generated content for a user.

[0041] Device 10 can have any suitable number of cameras 46. For example, device 10 can have at least one, at least two, at least four, at least six, at least eight, at least ten, at least 12, less than 20, less than 14, less than 12, less than 10, 4-10, or other desired number of cameras 46. Cameras 46 can be sensitive at infrared wavelengths (e.g., cameras 46 can be infrared cameras), can be sensitive at visible wavelengths (e.g., cameras 46 can be visible cameras), and / or cameras 46 can be sensitive at other wavelengths. If desired, cameras 46 can be sensitive at both visible and infrared wavelengths.

[0042] Device 10 can have left and right optical modules 40. Optical modules 40 can support electronic and optical components such as light emitting components and lenses, and thus can sometimes be referred to as optical assemblies, optical systems, optical component support structures, lens and display support structures, electronic component support structures, or housing structures. Each optical module can include a respective display 24, lens 30, and support structure such as support structure 32. Support structure 32, which can sometimes be referred to as a lens support structure, optical component support structure, optical module support structure, or optical module portion, or lens barrel, can include a hollow cylindrical body structure with open ends or other support structure for housing display 24 and lens 30. Support structure 32 may, for example, include a left lens barrel supporting left display 24 and left lens 30 and a right lens barrel supporting right display 24 and right lens 30.

[0043] Display 24 can include an array of pixels or other display device to produce an image. Display 24 may, for example, include organic light emitting diode pixels formed on a substrate with thin film circuitry and / or formed on a semiconductor substrate, pixels formed from crystalline semiconductor dies, liquid crystal display pixels, scanning display devices, and / or other display devices for producing an image.

[0044] Lens 30 can include one or more lens elements for providing image light from display 24 to a respective eyebox 13. Lenses can be implemented using refractive glass lens elements (or lens elements of another suitable material such as polycarbonate), using catadioptric lens structures (catadioptric lenses), using Fresnel lenses, using holographic lenses, and / or other lens systems.

[0045] Display (display panel) 24 can operate together to form a display of device 10 when a user's eye is positioned in eyebox 13 (e.g., a user's eye can view an image provided by a respective left and right optical module 40 in eyebox 13 so that a stereoscopic image is created for the user). When a user views the display, a left image from the left optical module fuses with a right image from the right optical module.

[0046] It may be desirable to monitor the user's eyes when they are within the eye-fitting zone 13. For example, it may be desirable to use a camera to capture images of the user's pupil, iris, or other parts of the user's eye for user authentication. It may also be desirable to monitor the direction of the user's gaze. Gaze tracking information can be used as a form of user input and / or can be used to determine where in the image content resolution should be locally enhanced in a small-aperture imaging system. Information about the position of the user's pupil can be used to calculate a compensation function for the image frame displayed by the display 24. To ensure that the device 10 can capture a satisfactory eye image when the user's eyes are within the eye-fitting zone 13, each optical module 40 may be provided with one or more cameras (such as camera 42) and one or more light sources (such as light-emitting diodes 44) or other light-emitting devices (such as lasers, lamps, etc.). Camera 42 and light-emitting diodes 44 may form an eye and / or head tracking system 26. Figure 1 As part of the system, camera 42 and LED 44 can operate at any suitable wavelength (visible, infrared, and / or ultraviolet). For example, LED 44 can emit infrared light that is invisible (or nearly invisible) to the user. This allows for continuous eye monitoring without interfering with the user's ability to view the image on display 24.

[0047] In operation, the light-emitting diode 44 can emit light reflected from the user's eye and / or create a light spot on the user's eye. The camera 42 can measure the light reflected from the user's eye and / or detect the light spot to determine the user's gaze (e.g., the user's point of fixation). Although Figure 2 Camera 42 and LED 44 are shown, but this is merely illustrative. Generally, the gaze tracking system in device 10 (e.g., Figure 1 The system 26) may include any suitable light source and any suitable light sensor.

[0048] although Figure 2 Device 10 has been shown as including two displays 24, but this is merely illustrative. In general, device 10 may include any desired number of displays, such as a single display for viewing by both eyes. Additionally, although... Figure 2Device 10 is described as a head-mounted device. Device 10 can generally be any desired device, such as computing devices such as laptops, computer monitors containing embedded computers, tablets, cellular phones, media players or other handheld or portable electronic devices, smaller devices (such as wristwatches, hanging devices, headphones or handset devices, devices embedded in glasses or other equipment worn on a user's head, or other wearable or micro-devices), displays, computer monitors containing embedded computers, computer monitors not containing embedded computers, gaming devices, navigation devices, head-mounted devices, embedded systems (such as systems in which electronic equipment with displays is installed in kiosks or cars), or other electronic equipment.

[0049] In some implementations, the image displayed on the display 24 may be dynamically concave based on the region of interest (e.g., the location of the user's gaze (e.g., the user's gaze point)). Figure 3 An illustrative example is shown in the figure.

[0050] like Figure 3 As shown, the user can view the content displayed on one or more monitors (such as...). Figure 2 The image 50 displayed on the display 24 has a gaze point 51 (such as that generated by a gaze tracker in the device 10). Figure 1 (The gaze tracker in the eye and / or head tracking system 26) determines the image 50. The image 50 may be dynamically concave (also referred to herein as warping or grouping) based on the gaze point 51. For example, pixel group 52 in image 50 may be rendered at full resolution, pixel group 54 in image 50 may be rendered at half resolution (e.g., every two pixels in group 54 may have the same output), and pixel group 56 in image 50 may be rendered at quarter resolution (e.g., every four pixels in group 56 may have the same output). However, this concave rendering is merely illustrative. In general, image 50 may be concave in any suitable manner based on the gaze point 51.

[0051] Centering image 50 into pixel groups allows for faster processing and / or lower computational and storage requirements. Generally, image 50 can be dynamically centered to optimize resolution and / or quality in one or more regions of interest, which may be determined based on the user's gaze point (e.g., gaze point 51) and / or other suitable characteristics (e.g., the content to be displayed in image 50).

[0052] although Figure 3Image 50 is shown, which has a vertical central concavity in a group extending horizontally across image 50, but this is merely illustrative. In general, image 50 may be vertically or horizontally centrally concave (e.g., in a group extending vertically across image 50).

[0053] Regardless of the central concavity of image 50, central concavitating image 50 into groups with different resolutions can result in large buffer requirements. Specifically, rows in group 52 can be read at the same (or similar) speed as they are written into the frame buffer. However, rows in groups 54 and 56 can be read at a slower speed when they are written into the frame buffer (e.g., because each read row in the central concavity space corresponds to two or four rows in the native space). Therefore, it may be necessary to utilize intra-frame pauses to read rows of image 50 to ensure that the frame buffer does not become overloaded. Figure 4A and Figure 4B An illustrative example is shown in the figure.

[0054] like Figure 4A As shown, schematic diagram 58 can be used in a buffer for writing images (such as image 50) to device 10 (e.g., in...). Figure 1 Intra-Frame Pause (IFP) is implemented when the device 10 is part of the control circuitry 12. Specifically, a lookup table (LUT) 68 can be generated in offline LUT generation. Known information about system timing 60, panel timing 62, and grouping 64 can be used in the IFP algorithm 66 to generate LUT 68. System timing 60 may include timing information about the entire device 10 or a subset of the device 10, which includes the control circuitry (e.g., Figure 1 12) Control circuit 12) Display driver circuit (e.g., Figure 1 The display driver circuit 18) and / or other circuitry related to the display. Panel timing 62 may include information about the operation of pixels in the display and the speed of components associated with the display. Grouping 64 may relate to pixel grouping when an image is to be displayed in a concave manner, an example of which is shown in... Figure 3 As shown in the image.

[0055] IFP algorithm 66 can generate IFP LUT 68, which can have each gaze location in image 50 (e.g., Figure 3The IFP information for the gaze point 51 in the image. For example, the IFP LUT 68 may include the gaze point range within the image and / or the IFP information for each gaze point. The IFP information in the IFP LUT 68 may include information about the duration and timing of the intra-frame pause used when writing image data into the frame buffer. Specifically, given the gaze point 51, the IFP LUT 68 may indicate when an intra-frame pause should be initiated and how long the intra-frame pause should last while image data is written into the buffer. In some embodiments, the IFP LUT 68 may include IFP information for all gaze positions in the electronic device 10 and the associated grouping of images and displays.

[0056] During the operation of device 10, it can be used Figure 4B An exemplary flowchart 71 is provided. Specifically, gaze 70 and IFP LUT 68 may be provided to the system-on-chip (SoC) 74. Gaze 70 may include the user's gaze point (e.g., Figure 3 (51 in the gaze point). The SoC 74 can be associated with the display 24, and can be connected to, if needed, the display 24. Figure 1 The SoC 17 corresponds to this. Based on the gaze 70 and the corresponding IFP information in the IFP LUT68, the SoC 74 can read the image 50 to the display driver integrated circuit (DDIC) 76, which can be used with... Figure 1 The display driver circuit 18 corresponds to this. The readout will include groups of pixels in the image 50 separated by IFP.

[0057] Specifically, rows of image 50 can be written to a partial frame buffer in the DDIC 76. The partial frame buffer stores rows, which can then be read from the buffer. This is because image 50 is grouped (e.g., as...). Figure 3 As shown), some rows will include pixel information from multiple rows of the display panel at its native resolution. These rows will take longer to read out to the display panel. Therefore, reading image 50 into a buffer with IFP will ensure that the buffer does not overflow.

[0058] although Figure 4A An IFP LUT 68 generated using IFP algorithm 66 is shown, but this is merely illustrative. In some implementations, IFP algorithm 66 can be used to directly calculate IFP information for SoC 74. In other words, IFP algorithm 66 can replace... Figure 4B The IFP LUT 68 in flowchart 71, and the IFP algorithm 66 can be used to calculate the IFP duration and timing based on the user's gaze at each image frame.

[0059] Figure 4A and Figure 4BThe example is open-loop, without any feedback on the state of the partial frame buffer in the DDIC 76. However, this is merely illustrative. In some implementations, a closed loop can be used to determine the IFP when image data is read out to the partial frame buffer. Figure 5 An illustrative example is shown in the figure.

[0060] like Figure 5 As shown, a closed loop 78 can be formed between SoC 74 and DDIC 76. Specifically, at step 79, SoC 74 can write image data 85 (e.g., a pixel stream of rows of image 50) into a portion of the frame buffer of DDIC 76.

[0061] When a partial frame buffer is full (or nearly full), at step 80, DDIC 76 can communicate the buffer full status 87 of the partial frame buffer to SoC 74.

[0062] At step 81, SoC 74 may pause writing image data, as shown in IFP 89 between SoC 74 and DDIC 76.

[0063] At step 82, when DDIC 76 has read enough image data from a portion of the frame buffer and the portion of the frame buffer is empty (or nearly empty), DDIC 76 can communicate the buffer empty state 91 of the portion of the frame buffer to SoC 74 (e.g., there is available memory in the frame buffer). The process can then proceed along line 83, and SoC 74 can resume writing image data to the portion of the buffer in DDIC 76. In this way, a closed loop can be used to control the writing of image data from SoC 74 to DDIC 76.

[0064] although Figure 5 The illustration shows DDIC 76 sending a buffer full state 87 to SoC 74 in step 80 and a buffer empty state 91 to SoC 74 in step 82, but this is merely illustrative. In general, DDIC 76 can convey that there is sufficient space in the partial frame buffer to accommodate additional image data from SoC 74. For example, any suitable threshold of storage space in the partial frame buffer can be used, and DDIC 76 can convey a status to SoC 74 when the storage space in the partial frame buffer is below (or above) the threshold.

[0065] Figure 6 The diagram illustrates the buffer requirements when using an IFP. As shown in Figure 86, image data 85, including rows 85A, 85B, 85C, 85D, and 85E, can be written to buffer 90 over time. As an illustrative example, an IFP 89 may exist between rows 85C and 85D.

[0066] At time 90A, line 85A can be written into buffer 90 at location 95A. At time 90B, line 85B can be written into buffer 90 at location 95B. At time 90C, line 85C can be written into buffer 90 at location 95C. As indicated at time 90C, line 85C can be written to half of buffer 90 while the line stored in location 93A has not yet been read out of buffer 90. Thus, IFP 89 can be used to pause additional lines of image data from being written while the buffer is being read out.

[0067] Specifically, at time 90IA, no new image data can be written into buffer 90, thus the data at locations 93A and 95C can remain in place. At time 90IB, the image data stored in location 93A can be read out (e.g., to display circuitry). In this way, the gap between the current readout location of buffer 90 (location 93B) and the current write location of buffer 90 (location 95C) can be reduced.

[0068] IFP 89 can remain paused during times 90IC, 90ID, and 90IE until the image data stored in location 93B is read out and line 85D is written into location 95D in buffer 90. At time 90E, line 85E can be written into location 95E in buffer 90.

[0069] By incorporating IFP 89, which can be used one or more times in a single image readout, the size of the buffer can be reduced, as indicated by buffer size 97. Generally, the IFP used can be used to match the write speed into the buffer with the readout speed out of the buffer (e.g., through IFP algorithm 66 (e.g., based on foveation of the image) or closed loop 78 of FIGS. 4 and Figure 5 In this way, a smaller buffer can be needed.

[0070] In some embodiments, instead of or in addition to reading out images with intra-frame pauses, it can be desirable to apply one or more compensations to the image after it is foveated (e.g., while the image is in the foveation / packet space). For example, the foveated image can be compensated for horizontal cross-talk, multi-line horizontal cross-talk, IR drop, and / or other characteristics. Applying the compensations in the foveation space can reduce the power requirements of the associated electronics.

[0071] Figure 7 An illustrative example of applying a compensation for horizontal cross-talk is shown in FIG. 10. Specifically, one or more horizontal cross-talk (HXT) artifacts 100 can exist in image 98 relative to source content 96 (e.g., a source of an image to be displayed on display 24). When there are adjacent dark and bright regions, as shown in image 98, horizontal cross-talk can occur. In this example, HXT artifacts 100 can be caused by the display 24 (e.g., a liquid crystal display) having a non-uniform backlight (e.g., a backlight that is not uniform across the display 24).Figure 7 As shown, adjacent pixels in the display may cause horizontal crosstalk artifacts 100. However, this horizontal crosstalk can be compensated to provide a final image 102 corresponding to the source content 96 (e.g., without horizontal crosstalk artifacts). Figure 8 An illustrative example of a compensation circuit that can be used to compensate for horizontal crosstalk is shown.

[0072] like Figure 8 As shown, the horizontal crosstalk compensation circuit 104 may include a voltage-load weighted LUT 108 that receives a pixel stream 106 (also referred to herein as pixel values ​​106). The pixel stream 106 may correspond to image data that has been centrally concave.

[0073] Voltage-load weighted LUT 108 can convert gray levels in pixel stream 106 into given weights based on the load effect that the gray levels of pixels in pixel stream 106 will have on the horizontal gate lines of the display. In parallel, storage device 109 can store the values ​​of pixel stream 106. Line weight averaging circuit 110 can receive weights from LUT 108 and information about grouping of image data from multiplexer (MUX) 112. Specifically, MUX 112 can determine whether grouping is in use (e.g., whether pixel stream 106 is concave) and grouping factors (e.g., 1x, 2x, or 4x for a given row or column, see [link to relevant documentation]). Figure 3 It can be used as input and can output grouping information to the line weight averaging circuit 110.

[0074] The line weight averaging circuit 110 can average the load on each gate line based on the load weight from LUT 108 and the grouping information received from MUX 112. For example, if pixels are grouped (e.g., in groups of 2 or 4), the line weight averaging circuit 110 will determine that a pixel will have a greater impact on the gate line and increase the weight value of that line. Therefore, the line weight averaging circuit 110 and MUX 112 can be collectively referred to herein as the resolution determination circuit. In other words, when the image is in the concave / grouping domain, the line weight averaging circuit 110 and MUX 112 can determine the resolution of a given pixel group and adjust the load on each gate line based on that resolution.

[0075] The compensation LUT 114 may receive a weighted average from circuit 110 and pixel values ​​from storage device 109. The compensation LUT 114 may include compensation for each pixel value based on the weighted average from circuit 110.

[0076] The position-based adjustment frame 116 can receive compensation from LUT 114, as well as information about the position of pixels in the native non-recessed space of the display. Specifically, frame 116 can use coordinate transformation circuitry 118 (which can determine the coordinate transformation based on grouped coordinates 115 received from circuitry in the display) to determine the position (e.g., xy position) of the grouped pixels in the native space of the display, and can correct the compensation from LUT 114 based on that position. For example, different lines of image data may have different numbers of pixels (e.g., due to the chamfered corners of the display), which can cause some lines to have different loads than others.

[0077] Adjustment box 120 can receive position correction compensation from box 116 and can apply any suitable scaling, offset and / or other adjustments to the compensation.

[0078] Then, as shown in the junction 124, the adjusted compensation from frame 120 can be applied to the original pixel values ​​received from storage device 109. The compensated pixel values ​​can then be output as output 126. In this way, when pixel value 106 is in a grouping domain (e.g., when the image formed by pixel value 106 is concave), pixel value 106 can be compensated for horizontal crosstalk. In other words, individual compensation can be determined for groups of pixels in the image, thereby saving power and computational requirements while compensating for horizontal crosstalk.

[0079] although Figure 7 and Figure 8 Correction of horizontal crosstalk in image data grouped by line / row has been described, but this is merely illustrative. Horizontal crosstalk can be compensated in image data grouped vertically and / or horizontally.

[0080] It can replace or compensate for multi-line horizontal crosstalk (MLHXT) in addition to compensating for horizontal crosstalk. Figure 9 An illustrative example is shown below.

[0081] like Figure 9 As illustrated in the exemplary example, one or more MLHXT artifacts 132 may exist in the image 130 relative to the source content 128 (e.g., the source of the image to be displayed on the display 24). MLHXT artifacts 132 may be caused by data lines and / or power lines that provide noise when reading the image. However, this crosstalk can be compensated for to provide the final image 134 corresponding to the source content 128. Figure 10A and Figure 10B An illustrative example of MLHXT crosstalk affecting image data is shown.

[0082] like Figure 10AAs shown, in timing diagram 136, rows N-2 to N+3 of image data can include portions 138 that are read out in the presence of ELVSS noise 140. In diagram 136, each row can correspond to a row in the native domain of the display panel (e.g., in full resolution group 52 of the foveated image), so each portion 138 can be individually compensated. Figure 3

[0083] In Figure 10B diagram 137, rows N-2 and N-1 can have portions 142 that are read out in the presence of ELVSS noise 140, rows N and N+1 can have portions 144 that are read out in the presence of ELVSS noise 140, and rows N+2 and N+3 can have portions 146 that are read out in the presence of ELVSS noise 140. In diagram 137, the rows are grouped in twos (e.g., in half resolution group 54 of the foveated image). Thus, if the display is operating in the grouped mode, the groups of two rows can be compensated together (e.g., a single compensation can be applied to rows N-2 and N-1). Figure 3

[0084] However, in some implementations, the display can operate in the native mode. As shown in the illustrative example of Figure 11 , row N-2 can have a portion 150 that is read out in the presence of ELVSS noise 160, row N-1 can have a portion 152 that is read out in the presence of ELVSS noise 160, row N can have a portion 154 that is read out in the presence of ELVSS noise 160, row N+1 can have a portion 156 that is read out in the presence of ELVSS noise 160, and row N+2 can have a portion 158 that is read out in the presence of ELVSS noise 160. When one or more of rows N-2 to N+3 are not grouped (e.g., in different groups of the foveated image or in a non-foveated image), each row can be individually compensated. However, if one or more of rows N-2 to N+3 are grouped (e.g., in the same group of the foveated image), the compensation for the grouped rows can be averaged. For example, rows N-2 and N-1 can be compensated with the same compensation determined as the average of the errors in rows N-2 and N-1.

[0085] Regardless of whether the display panel is operating in the grouped mode or the native mode, a schematic diagram of the MLHXT compensation circuit is shown as Figure 12 .

[0086] In Figure 12 ​​In the example of FIG. 18, the MLHXT compensation circuit 176 can include an interline switching calculation circuit 180 having an interline group average circuit 196 that receives interline switching pixel value differences 190. The interline switching pixel value differences 190 can be determined by subtracting image data from a given row from image data from a previous row. The interline group average circuit 196 can output average interline switching pixel differences that average the interline switching pixel value differences within each group for each row. Specifically, the interline group average circuit 196 can weight the average based on the location of the pixels in the native domain and / or grouping domain (given by output 195) from the pixel location circuit 193 (e.g., the pixel location circuit 193 can determine the location of the grouping image data in the native domain / space and / or grouping domain of the display panel) using the location of the pixels in the native domain and / or grouping domain (given by output 195) from the pixel location circuit 193 (e.g., the pixel location circuit 193 can determine the location of the grouping image data in the native domain / space and / or grouping domain of the display panel) to determine the average interline switching pixel differences for each group. Thus, these average interline switching pixel differences can be referred to as group average (interline switching difference) values. Figure 3

[0087] The average circuit 196 can be coupled to and output the group average interline switching difference values for each row to a spatial interpolation calculator circuit 200. The group average interline switching difference values can indicate how (e.g., the degree or amount) the interline switching of each group affects the neighboring pixels or pixel groups (e.g., the degree or amount that the interline switching of each group plays a role in the interference source capacity). The spatial interpolation calculator circuit 200 can transform or convert the group average interline switching difference values to corresponding group interline switching influence values (e.g., each group interline switching influence value indicates the degree or amount that a pixel group is affected or sacrificed by the interline switching of the pixel group in the same row). The spatial interpolation calculator circuit 200 can perform a cross-correlation between the different group average interline switching difference values of a pixel row (and based on the relative position of the groups) to characterize (e.g., determine) the interline switching influence on each group and obtain the interline switching influence values for each group. The spatial interpolation calculator circuit 200 can sometimes be referred to as a spatial interpolation calculation circuit, a spatial interpolation calculator, a circuit, a cross-correlation circuit, a transformation circuit, or a conversion circuit.

[0088] The interline switching calculation circuit 180 can include a queue 202 (e.g., a first-in-first-out (FIFO) storage circuit) that is coupled to and configured to receive the interline switching (influence) values from the circuit 200. Specifically, the queue 202 (or generally a storage circuit) can store (e.g., hold) the interline switching influence values for the groups in a given row, in N previous rows, and in M subsequent rows (e.g., the interline switching influence value for each of these groups). The queue 202 can store the grouping data as well as the pixel position information 199 from the pixel location circuit 193. Specifically, if the grouping data corresponds to two rows of pixels, the queue 202 can store information about when the grouping data is read out.

[0089] In​Figure 12 In the example of FIG. 18, the inter-phase switching calculation circuit 182 can include an inter-phase group average circuit 198 that receives the inter-phase switching pixel value difference 192. The inter-phase switching pixel value difference 192 can be determined by subtracting the difference between groups on a given frame and a previous frame. The inter-phase group average circuit 198 can output average inter-phase switching pixel difference values that average the inter-phase switching pixel value difference 192 within each group for each row. Specifically, the inter-phase group average circuit 198 can use the position of the pixels in native domain and / or grouped domain (given by output 195) from the pixel position circuit 193 to weight the average values based on the grouping region (e.g., whether the group is full resolution, half resolution, or quarter resolution) as shown in FIG. 19. Thus, these average inter-phase switching pixel difference values can be referred to as group average (inter-phase switching difference) values. Figure 3

[0090] The average circuit 198 can be coupled to and output the group average inter-phase switching difference values for each row to circuit 200. The group average inter-phase switching difference values can be indicative of how (e.g., the degree or amount) inter-phase switching of each group affects neighboring pixels or groups of pixels (e.g., the degree or amount that inter-phase switching of each group plays a role in the interference source capacity). The circuit 200 can transform or convert the group average inter-phase switching difference values to corresponding group inter-phase switching impact values (e.g., each group inter-phase switching impact value is indicative of the degree or amount that a group of pixels is affected or sacrificed by inter-phase switching of a group of pixels in the same row). The circuit 200 can perform a cross-correlation between different group average inter-phase switching difference values of a row of pixels (and based on the relative position of the groups) to characterize (e.g., determine) the inter-phase switching impact on each group and obtain the inter-phase switching impact values for each group.

[0091] The inter-phase switching calculation circuit 182 can include a queue 204 (e.g., a first-in-first-out (FIFO) storage circuit) that is coupled to and configured to receive the inter-phase switching (impact) values from the circuit 200. Specifically, the queue 204 (or generally a storage circuit) can store (e.g., hold) the inter-phase switching impact values for the groups in a given row, in N previous rows, and in M subsequent rows (e.g., the inter-phase switching impact value for each of these groups). The queue 204 can store the grouped data as well as the pixel position information 197 from the pixel position circuit 193. Specifically, if the grouped data corresponds to two rows of pixels, the queue 204 can store information about when to read out the grouped data.

[0092] In Figure 12 ​In the illustrative example of FIG. 2, the circuit 180 and the circuit 182 can have separate set averaging and storage circuits (e.g., queues), and can share the circuit 200. If desired, separate circuits 200 can be provided for the circuit 180 and the circuit 182, and / or other circuits can be shared between the circuit 180 and the circuit 182. Alternatively, a single one of the circuit 180 or the circuit 182 (rather than both) can be used.

[0093] The queues 202 and 204 can each be coupled to a line-before impact calculation circuit 206 and a line-after impact calculation circuit 208. In particular, the line-before impact calculation circuit 206 can receive line-to-line switching impact values for previous lines (e.g., N previous lines) from the queue 202, and can receive phase-to-phase switching impact values for the previous lines (e.g., N previous lines) from the queue 204. The line-before impact calculation circuit 206 can determine (e.g., calculate) the impact of switching of pixel values in these previous lines on the impact values for a given line being compensated. For example, the line-before impact calculation circuit 206 can include a combination of selection circuits, multiplication circuits, and summation circuits to calculate the impact values for the given line based on the line-to-line switching impact values and the phase-to-phase switching impact values for the previous lines.

[0094] The line-after impact calculation circuit 208 can receive line-to-line switching impact values for subsequent lines (e.g., M subsequent lines) from the queue 202, and can receive phase-to-phase switching impact values for the subsequent lines (e.g., M subsequent lines) from the queue 204. The line-after impact calculation circuit 208 can determine (e.g., calculate) the impact of switching of pixel values in these subsequent lines on the impact values for a given line being compensated. For example, the line-after impact calculation circuit 208 can include a combination of selection circuits, multiplication circuits, and summation circuits to calculate the impact values for the given line based on the line-to-line switching impact values and the phase-to-phase switching impact values for the subsequent lines.

[0095] The line-to-line switching impact values and the phase-to-phase switching impact values can be scaled or otherwise processed by the circuits 206 and 208 and / or prior to being received by the circuits 206 and 208, as appropriate.

[0096] The switching-induced impact values of the previous line of pixels values output by circuit 206 for a given row and the switching-induced impact values of the subsequent line of pixels values output by circuit 208 for the given row (as well as any other impact values, such as the impact values induced by the switching of the pixel values in the given row itself) can be combined at a summation circuit 210 coupled to circuits 206 and 208. In addition to this, summation circuit 210 can use the positions of the pixels in the native domain and / or the grouped domain (positions 205) from pixel position circuit 193, as well as the gain of each line 203 from line gain circuit 201. Line gain circuit 201 can determine whether a given line in the image is grouped / foveated, as well as the given resolution of those lines. Specifically, if the lines are read out by group and the display is scanned in native mode, the impact values for the group can be multiplied, summed, and averaged. However, if the lines are read out by group and the display is scanned in group mode, the impact values can correspond to each group in a one-to-one fashion.

[0097] Thus, summation circuit 210 can provide a combined switching impact value for each group of a given row of pixels that is compensated. The combined switching impact value indicates the degree or amount of impact on the group caused by the inter-line switching and the inter-phase switching associated with each group.

[0098] Summation circuit 210 can be coupled to and provide each group combined switching impact value to a pixel position interpolator 212 (e.g., impact value interpolation circuit). Because the combined switching impact values are provided on a per-pixel group basis, and the pixel value compensation is performed on a per-pixel basis, pixel position interpolator 212 can interpolate a pixel-specific (per-pixel) impact value for a given pixel value based on the position of the pixel (to which the pixel value is to be loaded) in the compensated row and based on the combined switching impact value for each group of the row. Specifically, pixel position interpolator 212 can use the positions of the pixels in the native domain and / or the grouped domain (positions 207) from pixel position circuit 193. Pixel position interpolator 212 can be implemented using any suitable type of interpolation circuit (e.g., linear interpolation circuit, polynomial interpolation circuit, etc.).

[0099] Pixel interpolator 212 can be coupled to and provide each pixel impact value to a compensation interpolator 214 (e.g., compensation value interpolation circuit). Compensation interpolator 214 can be implemented using any suitable type of interpolation circuit (e.g., linear interpolation circuit, polynomial interpolation circuit, etc.). Specifically, based on the received per-pixel impact value and the pixel value to be compensated, as well as the positions of the pixels in the native domain and / or the grouped domain (positions 209) from pixel position circuit 193, compensation interpolator 214 can generate a compensation value for the pixel value. The compensation value provided by compensation interpolator 214 can adjust the pixel value as appropriate to offset the inter-line switching crosstalk and the inter-phase switching crosstalk that impacted the programming of the pixel value.

[0100] If desired, the compensation values output from the compensation interpolator 214 are further adjustable by additional downstream compensation adjustment circuitry 216. These compensation adjustment circuitry 216 can perform any combination of adjustments, such as adjustments based on pixel array position (e.g., applying a weight or scaling factor according to the array position of the pixel for which the pixel value is to be loaded), generally tunable adjustments (e.g., controllable by system or user input), compensation switch adjustments (e.g., to invalidate the compensation value based on a determination that compensation should not be applied to a given pixel value), and the like.

[0101] The compensation circuitry 176 can generally apply the resulting compensation values (e.g., as output directly from the compensation interpolator 214 or after further processing by the adjustment circuitry 216) to the corresponding pixel values for which the compensation values were generated. In Figure 12 In the example of FIG. 2, the adder circuitry 218 in the compensation circuitry 176 can receive the pixel values (e.g., the same pixel values provided to the compensator interpolator 214) and the compensation values output from the compensator interpolator 214 (optionally via the adjustment circuitry 216), and sum these values to generate corresponding compensated pixel values. The compensated pixel values can be programmed into corresponding pixels of the display 24 (e.g., with or without additional downstream processing of the compensated pixel values) during respective phases on shared data lines and using corresponding gate lines. In this way, the compensation circuitry 176 can determine and apply compensation for MLHXT on the grouped image data.

[0102] The components of the compensation circuitry 176 can be implemented in one or more integrated circuits (such as a microcontroller, an application specific integrated circuit, or other type of processing circuitry with or without integrated memory, and memory or other data storage integrated circuits), can be implemented using discrete logic or other discrete components, can be implemented using one or more state machines, and / or any other suitable implementation.

[0103] In some embodiments, it can be desirable to compensate for IR drop within an image on the display 24. In particular, as shown in the illustrative example of FIG. 2, one or more IR drop artifact regions 224 can be present in the image 222 relative to the source content 220 (e.g., the source of the image to be displayed on the display 24). The IR drop artifact regions can be caused by voltage drops across resistors in the display. However, the IR drop can be compensated to provide a final image 226 that corresponds to the source content 220. Figure 13 In the example of FIG. 2, the compensation circuitry 176 can receive the pixel values (e.g., the same pixel values provided to the compensator interpolator 214) and the compensation values output from the compensator interpolator 214 (optionally via the adjustment circuitry 216), and sum these values to generate corresponding compensated pixel values. The compensated pixel values can be programmed into corresponding pixels of the display 24 (e.g., with or without additional downstream processing of the compensated pixel values) during respective phases on shared data lines and using corresponding gate lines. In this way, the compensation circuitry 176 can determine and apply compensation for MLHXT on the grouped image data. Figure 14 An illustrative example of compensating for IR drop in grouped image data is shown in FIG. 3.

[0104] As shown in FIG. 3, the display circuitry 236 (e.g., the display driver circuitry 34 of FIG. 1) can receive the grouped image data 302 (e.g., the image data 32 of FIG. 1) and the compensation values 304 (e.g., the compensation values 214 of FIG. 2). The display circuitry 236 can apply the compensation values 304 to the grouped image data 302 to generate compensated image data 306. Figure 14 As shown in FIG. 3, the display circuitry 236 (e.g., the display driver circuitry 34 of FIG. 1) can receive the grouped image data 302 (e.g., the image data 32 of FIG. 1) and the compensation values 304 (e.g., the compensation values 214 of FIG. 2). The display circuitry 236 can apply the compensation values 304 to the grouped image data 302 to generate compensated image data 306. Figure 1The control circuitry 12 (as part of the system) may include a graphics processing unit (GPU) 238 and a display driver integrated circuit (DDIC) 240. When a given image is rendered, the GPU 238 may have full-frame information of the given image. During rendering, the GPU 238 may sample a given number of pixels (e.g., several pixels) of frame data in each IR drop region zone to provide a coarse estimate of the current difference between frames.

[0105] The IR downblock in DDIC 240 can receive sampled frame data from GPU 238 via connection 239 before the current frame is read out to DDIC 240, thereby allowing DDIC 240 to adjust the IR downcompensation weights based on a coarse estimate. Figure 15 An exemplary IR drop compensation circuit that can be used in this process is shown.

[0106] like Figure 14 As shown in the IR drop compensation circuit 242, the GPU 238 can provide current 246 from the current frame and current 248 from the previous frame to the display circuit, such as... Figure 14 The DDIC 240. Subtractor 250 can be used to subtract current 246 from current 248 (e.g., by comparing the latter to the former). Similarly, IR drop block (IRA) 244 can provide pixel value 252 (e.g., average pixel-level data) from the current frame (received from GPU 238 before the current frame is read out) and pixel value 254 from the previous frame. Subtractor 256 can be used to subtract pixel value 252 from pixel value 254 (e.g., by comparing the latter to the former). The difference between these two values ​​can then be subtracted using subtractor 258. If the difference from subtractor 258 is greater than threshold 260, GPU 238 can adjust the IR drop compensation at step 266 (e.g., to reduce the calculated difference). If the difference from subtractor 258 is less than threshold 260, no adjustment is needed at step 264, and the process can be repeated. In this way, GPU 238 and IRA 244 can be used for IR drop compensation.

[0107] IR drop can be compensated for image data with horizontal and / or vertical grouping. Specifically, to compensate for IR drop, the generated current can be estimated. Because the image data is grouped, the estimated generated current can be weighted based on the grouping of the image data. For example, for pixels in a 2x region (e.g., Figure 3 The estimated generated current can be weighted by 2x for pixels in group 54, while for pixels in the 4x region (e.g., ...). Figure 3 The pixels in group 56 can be weighted by 4x.

[0108] Additionally, the location of the IR drop can be determined, as this location can be used to determine the compensation level. Specifically, the location can be determined by performing bilinear interpolation in the native pixel domain. For example, for pixels in a 2x region (e.g., Figure 3 For pixels in group 54), it can be assumed that the estimated IR drop is located at the center of the two native pixel locations. For pixels in the 4x region (e.g., Figure 3 (of the pixels in group 56), it can be assumed that the estimated IR drop is located at the center of the four native pixel locations.

[0109] The IR drop can be compensated in the grouped domain by weighting the estimated generated current for each group and interpolating in the native pixel domain to determine the location of the IR drop.

[0110] although Figures 3 to 15 Several compensations applicable to images in the grouping domain have been described, but these are merely illustrative. In general, images can be centrally concave or dynamically warped / grouped to optimize resolution or quality in the region of interest (e.g., gaze). Compensation can be applied to images for, for example, horizontal crosstalk, multiline horizontal crosstalk, IR drop, uniformity, and / or other display aberrations in the grouping domain. Generally, in combination... Figures 3 to 15 Any compensation described herein (and / or any other suitable compensation) may be applied together or in any combination to the image data in the group domain. Figure 16 An exemplary method for compensating for central concavity in a central concavity region is shown.

[0111] like Figure 16 As shown in flowchart 270, at step 272, an image data stream can be generated to form an image. The image data stream can be generated by control circuitry in the device, such as... Figure 1 The control circuit 12 (e.g., display driver circuit 18) generates it.

[0112] At step 274, the image can be centrally concave. The image can be based on the user's gaze point (e.g., as shown in the image). Figure 3 (As shown), the content to be displayed and / or the electronic device, the user, and / or any other desired characteristics of the displayed content are centrally concave. An image can be centrally concave, where different groups of images have different resolutions based on one or more regions of interest in the image.

[0113] At step 276, one or more compensations may be applied to the concave image. For example, a horizontal crosstalk compensation circuit (e.g., Figure 8 Circuit 104), multi-line horizontal crosstalk compensation circuit (e.g., Figure 12 Circuit 176), IR drop compensation circuit (e.g., Figure 15Compensation circuitry (e.g., compensation circuitry 242) and / or any other suitable / desired compensation circuitry can be used to compensate for foveated images when in a foveated space (e.g., in a bin domain).

[0114] In particular, to compensate for images in a bin domain, a mapping can be performed between a bin domain and a native domain of a display. The mapping can encode for compensation differences due to a variable area (e.g., a plurality of pixels) of a native domain being programmed with a single pixel value in a bin domain.

[0115] Although some embodiments herein have described compensating for line-binned image data, this is merely illustrative. In general, any suitable image data (such as vertically and / or horizontally binned image data) can be compensated for as in a bin domain.

[0116] According to one embodiment, a display includes: a pixel array configured to display images; a display driver circuit coupled to the pixel array, wherein the display driver circuit is configured to foveate the images displayed by the pixel array by adjusting a first resolution of a first group of pixels of the pixel array and a second resolution of a second group of pixels of the pixel array; and a compensation circuit configured to apply compensation to a foveated image based on the first resolution of the first group of pixels and the second resolution of the second group of pixels.

[0117] According to another embodiment, the compensation circuit is optionally configured to compensate for horizontal crosstalk based on the first resolution and the second resolution.

[0118] According to another embodiment, the compensation circuit optionally includes a resolution determination circuit configured to determine the first resolution and the second resolution.

[0119] According to another embodiment, the compensation circuit optionally further includes a coordinate conversion circuit configured to determine locations of the first group of pixels and the second group of pixels in the foveated image and in a native space.

[0120] According to another embodiment, the compensation circuit is optionally configured to compensate for multi-line horizontal crosstalk based on the first resolution and the second resolution.

[0121] According to another embodiment, the compensation circuit optionally includes: a pixel location circuit configured to determine locations of the first group of pixels and the second group of pixels in the foveated image and in a native domain; and an inter-line bin averaging circuit configured to determine the first resolution and the second resolution and average a difference between the pixels based on the first resolution and the second resolution.

[0122] According to another embodiment, the compensation circuit is optionally configured to compensate for IR drop based on the first resolution and the second resolution.

[0123] According to another embodiment, the compensation circuit optionally includes a graphics processing unit (GPU) and an IR drop circuit, and the display optionally further includes a display driver integrated circuit (DDIC), wherein the DDIC is configured to receive current from the GPU and average pixel-level data from the IR drop circuit to compare frame data from a current frame to frame data from a previous frame and compare average pixel-level data from the current frame to average pixel-level data from the previous frame.

[0124] According to another embodiment, the GPU is optionally configured to compensate for the first set of pixels and the second set of pixels in response to the DDIC determining that a difference between the frame data and the average pixel-level data across the current frame and the previous frame is greater than a threshold.

[0125] According to another embodiment, the display optionally further includes a system on a chip (SoC) and a frame buffer coupled to the SoC, wherein the SoC is configured to write image data generated by the pixel array into the frame buffer with intra-frame pauses.

[0126] According to another embodiment, the SoC is optionally configured to initiate the intra-frame pauses based on a lookup table.

[0127] According to another embodiment, the SoC is optionally configured to initiate the intra-frame pauses in response to a first signal from the frame buffer that the frame buffer is full.

[0128] According to another embodiment, the SoC is optionally configured to resume writing the image data into the frame buffer in response to a second signal from the frame buffer that there is available storage space in the frame buffer.

[0129] According to one embodiment, a method of displaying an image using a pixel array includes generating a stream of image data forming an image, foveating the image into a foveated space in which a first set of pixels of the pixel array has a first resolution and a second set of pixels of the pixel array has a second resolution, and applying compensations to the image in the foveated space based on the first resolution of the first set of pixels and the second resolution of the second set of pixels.

[0130] According to another embodiment, applying the compensations to the image in the foveated space optionally includes compensating for horizontal crosstalk in the image based on the first resolution and the second resolution.

[0131] According to another embodiment, applying the compensations to the image in the foveated space optionally includes compensating for multi-line horizontal crosstalk in the image based on the first resolution and the second resolution.

[0132] According to another embodiment, applying the compensations to the image in the foveated space optionally includes compensating for IR drop based on the first resolution and the second resolution.

[0133] According to another embodiment, the method optionally further includes writing the stream of image data into a frame buffer with an intra-frame pause.

[0134] According to one embodiment, an electronic device includes: a sensor; and a display including: a pixel array configured to display images; a display driver circuit coupled to the pixel array, wherein the display driver circuit is configured to foveate the images displayed by the pixel array into a foveated space based on measurements from the sensor; and a compensation circuit configured to apply compensations to the image in the foveated space.

[0135] According to another embodiment, the sensor is optionally a gaze tracker, the display driver circuit is configured to foveate the images based on a gaze measured by the gaze sensor, the display driver circuit is further configured to foveate the images by adjusting a first resolution of a first set of pixels of the pixel array and a second resolution of a second set of pixels of the pixel array, and the compensation circuit is configured to apply the compensations based on the first resolution and the second resolution.

[0136] The foregoing is merely illustrative and various modifications can be made to the described embodiments. Such modifications can be made to the foregoing in accordance with various embodiments. The foregoing embodiments can be implemented individually, or in any combination.

Claims

1. A display, the display comprising: A pixel array configured to display an image; Display driver circuitry coupled to the pixel array, wherein the display driver circuitry is configured to centrally concave the image displayed by the pixel array by adjusting a first resolution of a first group of pixels and a second resolution of a second group of pixels in the pixel array; and A compensation circuit configured to apply compensation to a centrally concave image based on the first resolution of the first group of pixels and the second resolution of the second group of pixels.

2. The display of claim 1, wherein the compensation circuit is configured to compensate for horizontal crosstalk based on the first resolution and the second resolution.

3. The display according to claim 2, wherein the compensation circuit includes a resolution determination circuit configured to determine the first resolution and the second resolution.

4. The display of claim 2, wherein the compensation circuit further comprises a coordinate transformation circuit configured to determine the positions of the first group of pixels and the second group of pixels in the concave image and in native space.

5. The display of claim 1, wherein the compensation circuit is configured to compensate for multiline horizontal crosstalk based on the first resolution and the second resolution.

6. The display according to claim 5, wherein the compensation circuit comprises: A pixel positioning circuit, configured to determine the positions of the first group of pixels and the second group of pixels in the central concave image and in the native domain; and An inter-pixel group averaging circuit is configured to determine a first resolution and a second resolution and to average the difference between the pixels based on the first resolution and the second resolution.

7. The display of claim 1, wherein the compensation circuit is configured to compensate for IR drop based on the first resolution and the second resolution.

8. The display of claim 7, wherein the compensation circuit includes a graphics processing unit (GPU) and an IR drop circuit, and the display further includes: Display driver integrated circuit (DDIC), wherein the DDIC is configured to receive current from the GPU and average pixel-level data from the IR drop circuit to compare frame data from the current frame with frame data from the previous frame, and to compare the average pixel-level data from the current frame with the average pixel-level data from the previous frame.

9. The display of claim 8, wherein the GPU is configured to compensate the first group of pixels and the second group of pixels in response to the DDIC determining that the difference between the frame data across the current frame and the previous frame and the average pixel-level data is greater than a threshold.

10. The display according to claim 1, further comprising: System-on-a-Chip (SoC); and A frame buffer coupled to the SoC, wherein the SoC is configured to write image data generated by the pixel array into the frame buffer using an intra-frame pause.

11. The display of claim 10, wherein the SoC is configured to initiate the intra-frame pause based on a lookup table.

12. The display of claim 10, wherein the SoC is configured to initiate the intra-frame pause in response to a first signal from the frame buffer indicating that the frame buffer is full.

13. The display of claim 12, wherein the SoC is configured to resume writing the image data into the frame buffer in response to a second signal from the frame buffer indicating the presence of available storage space.

14. A method for displaying an image using a pixel array, the method comprising: Generate an image data stream that forms the image; The image is centrally concave into a central concave space, in which the first group of pixels of the pixel array has a first resolution, and the second group of pixels of the pixel array has a second resolution; as well as Compensation is applied to the image in the central concave space based on the first resolution of the first group of pixels and the second resolution of the second group of pixels.

15. The method of claim 14, wherein applying the compensation to the image in the concave space comprises compensating for horizontal crosstalk in the image based on the first resolution and the second resolution.

16. The method of claim 14, wherein applying the compensation to the image in the concave space comprises compensating for multiline horizontal crosstalk in the image based on the first resolution and the second resolution.

17. The method of claim 14, wherein applying the compensation to the image in the concave space comprises compensating for IR drop based on the first resolution and the second resolution.

18. The method according to claim 14, further comprising: The image data stream is written to the frame buffer using an intra-frame pause.

19. An electronic device, the electronic device comprising: sensor; and The display includes: A pixel array configured to display an image. Display driver circuitry coupled to the pixel array, wherein the display driver circuitry is configured to centrally concave the image displayed by the pixel array into a central concave space based on measurements from the sensor. A compensation circuit configured to apply compensation to the image in the central concave space.

20. The electronic device of claim 19, wherein the sensor is a gaze tracker, the display driver circuit is configured to centrally concave the image based on a gaze measured by the gaze sensor, the display driver circuit is further configured to centrally concave the image by adjusting a first resolution of a first group of pixels of the pixel array and a second resolution of a second group of pixels of the pixel array, and the compensation circuit is configured to apply the compensation based on the first resolution and the second resolution.

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