RISC-V-oriented eBPF loop vectorization compiling method and device

Abstract

The invention provides an RISC-V-oriented eBPF cycle vectorization compiling method and device, and the method comprises the steps: generating an RVV vector machine code, executing the parallel operation when a condition is satisfied, achieving the parallel processing of a single instruction and multiple data, carrying out the serial conversion of the time dimension of eBPF cycle into the parallel spatial dimension of an RVV vector, remarkably improving the processing throughput, and improving the compiling efficiency. And the task response time delay and the CPU occupancy rate are reduced. According to the RVV vector execution mode, a large number of repeated loop control instructions and memory read-write instructions can be reduced, the register overflow problem caused by eBPF scalar register resource shortage is relieved, the cache pressure and the branch prediction failure rate are reduced, and the energy efficiency ratio is increased. Meanwhile, an RVV vector machine code and a scalar fallback code are generated, a parallel priority and scalar bottom double execution path is formed, and it is ensured that under the conditions that a hardware environment is not supported, the data size does not reach a threshold value, vectorization verification fails or operation is abnormal, the scalar fallback code can be seamlessly switched to be executed.

Description

Technical Field

[0001] This application relates to the fields of computer architecture and program compilation technology, and in particular to an eBPF loop vectorization compilation method and apparatus for RISC-V. Background Technology

[0002] eBPF (extended Berkeley Packet Filter) is a widely used programmable execution framework in the Linux kernel. However, in the process of compiling eBPF programs into executable code for the target architecture, existing technologies struggle to accurately identify code segments suitable for vectorization, leading to a series of technical problems: eBPF program performance is limited, making it difficult to overcome the inherent bottleneck of scalar execution; the value of the underlying hardware's parallel computing power cannot be fully realized, resulting in significant gaps in architecture adaptation; and high-performance-requirement business scenarios are difficult to implement, limiting the application boundaries of eBPF. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems in the related art.

[0004] Therefore, the first objective of this application is to propose an eBPF loop vectorization compilation method for RISC-V.

[0005] The second objective of this application is to propose an eBPF loop vectorization compiler for RISC-V.

[0006] The third objective of this application is to propose an electronic device.

[0007] The fourth objective of this application is to provide a computer-readable storage medium.

[0008] The fifth objective of this application is to provide a computer program product.

[0009] The sixth objective of this application is to propose a chip.

[0010] To achieve the above objectives, the first aspect of this application proposes an eBPF loop vectorization compilation method for RISC-V, comprising: Load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode; The annotated eBPF bytecode is parsed to generate RVV vector machine code and scalar backoff code that is semantically equivalent to eBPF scalars. In response to the hardware environment and data volume meeting the conditions for parallelization, the RVV vector machine code is executed to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code. In response to hardware conditions or data volume not meeting the conditions for parallelization, the scalar backoff code is executed to perform sequential scalar processing on multiple iterative operations within the loop region.

[0011] To achieve the above objectives, a second aspect of this application provides an eBPF loop vectorization compilation apparatus for RISC-V, comprising: A loading module, which is used to load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode; A generation module is used to parse the annotated eBPF bytecode to generate RVV vector machine code and scalar backoff code that is equivalent to eBPF scalar semantics. The first compilation module is used to execute the RVV vector machine code in response to the hardware environment and data volume meeting the parallelization conditions, so as to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code. The second compilation module is used to execute the scalar backoff code in response to the hardware environment or the amount of data not meeting the conditions for parallelization, so as to perform sequential scalar processing on multiple iterative operations in the loop region.

[0012] To achieve the above objectives, a third aspect of this application provides an electronic device, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the steps of the RISC-V-oriented eBPF cyclic vectorization compilation method proposed in the first aspect of this application.

[0013] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium that, when executed by a processor of an electronic device, enables the electronic device to perform the steps of the RISC-V-oriented eBPF cyclic vectorization compilation method proposed in the first aspect of this application.

[0014] To achieve the above objectives, a fifth aspect of this application provides a computer program product, including a computer program that, when executed by a processor in a communication device, implements the steps of the RISC-V-oriented eBPF circular vectorization compilation method proposed in the first aspect of this application.

[0015] To achieve the above objectives, a sixth aspect of this application provides a chip including one or more interface circuits and one or more processors; the interface circuits are used to receive signals and send the signals to the processors, the signals including computer instructions; when the processor executes the computer instructions, the chip causes the chip to perform the steps of the RISC-V-oriented eBPF cyclic vectorization compilation method proposed in the first aspect of this application.

[0016] In this embodiment, bytecode parsing is performed based on annotations generated by the LLVM compilation environment. This eliminates the need to bypass the original eBPF security verification logic. Memory access and instruction execution of the vector machine code adhere to the eBPF memory model and security constraints, preventing the introduction of new security risks such as out-of-bounds errors and illegal calls, thus ensuring the security of kernel-mode execution. By generating RVV vector machine code and performing parallel computation when conditions are met, "single instruction multiple data" parallel processing is achieved. This transforms the "temporal serial" nature of eBPF loops into the "spatial parallel" nature of RVV vectors. For data-intensive logic such as packet traversal, traffic statistics, memory page monitoring, and malicious feature matching, this significantly improves processing throughput, reduces task response latency and CPU utilization, and effectively solves the scalar execution performance bottleneck in high-bandwidth, high-concurrency scenarios. The RVV vector execution mode reduces a large number of repetitive loop control instructions and memory read / write instructions, alleviating register overflow problems caused by the scarcity of eBPF scalar register resources, reducing I-Cache pressure and branch prediction failure rate. Compared to pure scalar execution, it reduces CPU computing power and power consumption under the same task completion conditions, improving energy efficiency. Simultaneously generating RVV vector machine code and scalar backoff code, a dual execution path of "parallel priority, scalar fallback" is formed. This ensures seamless switching to scalar backoff code execution even in scenarios such as hardware environments that do not support RVV, data volumes that do not reach the minimum vectorization threshold, vectorization verification failures, or runtime anomalies. The entire process does not disrupt the original semantics of eBPF programs, guarantees strict consistency of computation results, avoids business interruptions or functional abnormalities, and improves the robustness and availability of eBPF programs.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart illustrating a RISC-V-oriented eBPF loop vectorization compilation method provided in this application embodiment; Figure 2A flowchart illustrating another RISC-V-oriented eBPF loop vectorization compilation method provided in this application embodiment; Figure 3 A schematic diagram of the structure of an eBPF loop vectorization compiler for RISC-V provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a chip according to an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0020] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" and "suppose" as used herein can be interpreted as "when," "when," or "in response to a determination."

[0022] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0023] eBPF (extended Berkeley Packet Filter), a widely used programmable execution framework in the Linux kernel, has deeply penetrated numerous data-intensive core scenarios such as network acceleration, system observability, security monitoring, traffic statistics, and load balancing, thanks to its kernel-level programmability, low overhead, and high flexibility. It has become a key technological bridge connecting upper-layer business needs with underlying hardware resources. However, in the process of compiling eBPF programs into executable code for the target architecture, existing technologies face the bottleneck of "difficulty in accurately identifying code fragments suitable for vectorization." This problem is not isolated but has triggered a series of chain-reaction technical challenges, severely restricting the release of eBPF technology's value and the expansion of its application scenarios.

[0024] In some scenarios, eBPF programs suffer from performance limitations, struggling to overcome the inherent bottleneck of scalar execution. The core value of vectorization lies in its ability to transform the serial iteration of batch data into multi-element parallel processing of a single instruction through Single Instruction Multiple Data (SIMD) parallel computation, thereby significantly improving execution efficiency. However, current technologies cannot accurately locate vectorizable core logic in eBPF programs, such as looping through packet payloads, counting traffic, managing memory page access frequency, and matching malicious features. This forces eBPF programs to rely solely on serial execution of scalar instructions. This execution mode not only fails to utilize hardware parallel computing power but also increases I-Cache pressure and branch prediction failure rates due to the repeated generation of numerous loop control instructions and memory read / write instructions. Furthermore, eBPF is equipped with only 11 general-purpose scalar registers (R0-R10), making it prone to register overflows in complex computational scenarios. This leads to additional memory access overhead, ultimately resulting in low program throughput, increased response latency, and difficulty in handling high-concurrency, large-scale data processing demands.

[0025] In some scenarios, the value of the parallel computing power of the underlying hardware cannot be fully realized, and there are significant gaps in architecture adaptation. Modern processors, to enhance their data parallel processing capabilities, are generally equipped with dedicated vector extension units, such as RISC-V's RVV (Vector Extension), x86's AVX, and ARM's NEON. Among these, RVV, as an open-source architecture, offers advantages such as variable VLEN (vector length), configurable SEW / LMUL (element width / register group ratio), and grouped access to multiple registers. However, because current technology cannot accurately identify vectorizable code segments of eBPF, it cannot convert eBPF bytecode into vector instructions adapted to the underlying hardware, resulting in the long-term idle state of the vector computing power of these hardware components. For example, servers, embedded devices, cloud instances based on the RISC-V architecture, or high-performance x86 / ARM platforms can only rely on scalar execution when running eBPF programs. The high-performance potential of the hardware cannot be released through the eBPF framework, resulting in an awkward situation of "strong demand for upper-layer eBPF applications, redundant computing power of lower-layer hardware, and a gap in the intermediate adaptation process." This not only reduces the return on hardware investment but also exacerbates the complexity of eBPF adaptation between different architectures.

[0026] In some scenarios, high-performance requirements hinder the implementation of eBPF, severely limiting its application boundaries. With the rapid development of 5G / 6G, cloud computing, and edge computing, many core business scenarios place stringent performance demands on eBPF programs: real-time packet filtering on backbone networks exceeding 100Gbps requires processing millions of data packets per second; data center traffic load balancing demands millisecond-level response latency; equipment health monitoring for industrial controllers needs to guarantee real-time performance under low computing power; and security detection on cloud servers requires rapid matching of massive amounts of malicious features. However, existing technologies suffer from performance bottlenecks due to insufficient vectorized recognition capabilities, making it difficult for eBPF programs to meet these requirements. For example, issues such as packet dropping, missed detections, and excessive response latency may occur, and it may even be unable to replace traditional dedicated hardware solutions. This not only hinders the implementation of eBPF in high-value, high-performance scenarios but also limits its expansion from general computing scenarios to more core and critical business areas, restricting the large-scale development and technological iteration of the eBPF ecosystem.

[0027] The following describes, with reference to the accompanying drawings, an eBPF loop vectorization compilation method and apparatus for RISC-V according to embodiments of this application.

[0028] Figure 1 This is a flowchart illustrating a RISC-V-oriented eBPF loop vectorization compilation method provided in an embodiment of this application.

[0029] like Figure 1 As shown, this RISC-V-oriented eBPF loop vectorization compilation method includes, but is not limited to, the following steps: S101: Load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode.

[0030] In one feasible implementation, the architecture and functionality of the LLVM (Low Level Virtual Machine) compilation environment are defined. The LLVM compilation environment is a modular, reusable collection of compiler and toolchain technologies that provides complete compilation support from source code to object code, including stages such as lexical analysis, syntax analysis, semantic analysis, optimization, and code generation. In the eBPF compilation process, LLVM plays a crucial role in converting eBPF programs written in high-level programming languages ​​(such as C) into low-level bytecode (a representation between high-level programming languages ​​and machine code).

[0031] In one feasible implementation, the eBPF source code to be compiled is loaded into the LLVM compilation environment. The LLVM front-end tool (such as Clang) performs lexical analysis, syntax analysis, semantic analysis, optimization, and code generation on the eBPF source code. This includes structured vector metadata annotations containing access patterns, cell sizes, cycle boundaries, and minimum vectorization thresholds. These annotations are embedded into a custom segment of the eBPF ELF file (Executable and Linkable Format), and the compilation outputs eBPF bytecode carrying complete vectorized metadata annotations.

[0032] It should be noted that optimizations include constant folding, dead code elimination, etc. During the optimization process, the front-end tool will retain or add annotation information. This annotation information is used for debugging, performance analysis, and security verification. The annotation information may contain the mapping relationship between source code and bytecode, variable type information, control flow graphs, etc.

[0033] S102, parse the annotated eBPF bytecode to generate RVV vector machine code and scalar backoff code that is semantically equivalent to eBPF scalars.

[0034] In one feasible implementation, a kernel-mode vectorized JIT enhancement module is used to load the annotated eBPF bytecode. This module achieves high-performance acceleration in the kernel-mode environment by combining just-in-time (JIT) compilation technology with hardware vector instruction sets. The module performs structured parsing of the annotations, verifying the legality of the annotation format, the positional matching between the bytecode and the annotated regions, and simultaneously performing a secondary security check (confirming that there are no illegal helper calls, no atomic operations, and that memory access addresses originate from the verified base address and offset within the loop region).

[0035] In one feasible implementation, for the quantifiable loop regions annotated with annotations, the kernel-mode vectorized JIT enhancement module establishes a parallel mapping of the eBPF virtual registers and RVV vector registers using the RVV (RISC-V Vector) "length-agnostic" programming model; it converts the eBPF source code to be compiled into native RVV memory access instructions and vector arithmetic logic instructions corresponding to unit-stride / strided / gather / scatter; and through strip-mining mechanism and tail masking, it performs semantic equivalence on the native RVV memory access instructions and vector arithmetic logic instructions to obtain RVV vector machine code.

[0036] In one feasible implementation, for non-vectorized regions and vectorized fallback scenarios annotated with annotations, the standard eBPF-JIT compiler is invoked to generate scalar fallback code that is strictly consistent with the semantics of the eBPF source code. In the scalar fallback code, all necessary context information (such as register states, memory mappings, etc.) is ensured to be correctly saved and restored to guarantee program continuity and correctness.

[0037] In some embodiments, the kernel-mode vectorized JIT enhancement module includes at least a vector configuration generation unit, an instruction classification and parallel translation unit, and a loop generation unit. The vector configuration generation unit generates vector length configuration instructions based on the remaining loop iterations and processor vector register configuration in the eBPF source code. The instruction classification and parallel translation unit divides the eBPF instruction region within the loop area of ​​the eBPF source code into parallelizable logic instructions and non-parallelizable instructions, and maps the parallelizable logic instructions to RISC-V vector extension instructions. The loop generation unit generates eBPF loop stepping control and loop termination control instructions based on the vector length configuration.

[0038] For example, the vector configuration generation unit generates vsetvl or vsetvli instructions, and dynamically determines the vector length based on the remaining iterations of the loop in the eBPF source code and the hardware configuration of the processor vector registers, in order to control the parallelism of each vectorization execution and maximize the utilization of the computing resources of the RISC-V vector hardware.

[0039] For example, when the preset parallelizability conditions are met, the instruction classification and parallel translation unit adopts a classification parallel translation mechanism to identify and process eBPF instructions within the loop region of the eBPF source code, including: Based on instruction function type, the eBPF instructions in the loop region of the eBPF source code are finely classified and processed to extract the parallelizable logic instructions and remove the non-parallelizable auxiliary control instructions to avoid unnecessary translation overhead. For parallelizable logic instructions, a parallelization translation strategy adapted to the RISC-V RVV architecture is matched to achieve precise adaptation of "one strategy per type". The extracted parallelizable logic instructions are vectorized and translated to generate corresponding RVV vector machine code, maximizing the release of vector hardware computing power; Among them, parallelizable logic instructions include at least arithmetic logic instructions, comparison instructions, data move instructions, and memory load / store instructions verified by eBPF.

[0040] S103, in response to the hardware environment and data volume meeting the conditions for parallelization, executes RVV vector machine code to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code.

[0041] In one feasible implementation, a dynamic scheduler monitors the hardware environment status and the amount of data to be processed in real time related to the execution of the eBPF program. The dynamic scheduler can be attached to a kernel event trigger point in kernel mode or to the eBPF program in user mode. Hardware environment status includes whether the RISC-V processor supports RVV vector extensions, the current CPU load level, and whether vector register resources are sufficient. Data volume includes the total number of eBPF loop iterations and the size of a single batch of data.

[0042] In one feasible implementation, the parallelizability condition, also known as the RVV vector execution condition, includes support for RVV expansion and CPU load within a reasonable threshold, the number of loop iterations ≥ the minimum vectorization threshold, and the single batch data size adapting to the vector processing granularity. If the relevant hardware environment and data volume meet the parallelizability condition, the dynamic scheduler triggers the loading and execution of the RVV vector machine code to perform parallel computation on multiple iteration operations within the loop region. During execution, relying on the strip-mining loop control mechanism and dynamic VL (Vector Length) configuration, the vectorization compilation and parallel computation of the eBPF loop are completed, ultimately outputting computation results that are strictly consistent with the scalar execution semantics, achieving efficient parallel processing of the eBPF loop.

[0043] S104, in response to the hardware environment or data volume not meeting the conditions for parallelization, executes scalar backoff code to perform sequential scalar processing on multiple iterative operations within the loop region.

[0044] In one feasible implementation, a dynamic scheduler monitors the hardware environment status and the amount of data to be processed in real time related to the execution of the eBPF program. If the hardware environment does not meet the RVV vector execution conditions (RVV extension is not supported, CPU load is too high, or vector register resources are insufficient) or the data volume does not meet the parallelization conditions (number of loop iterations < minimum vectorization threshold, single batch data size cannot adapt to vector processing granularity), or an abnormal scenario occurs during runtime, the dynamic scheduler seamlessly switches to the scalar execution path, triggers the loading and execution of standard eBPF scalar backoff codes, completes compilation and serial computation according to the native eBPF scalar execution semantics, performs serial scalar processing on multiple iterations within the loop region, and finally outputs computation results that are strictly equivalent to those of the vector execution path, ensuring the stable operation and functional integrity of the eBPF program.

[0045] In summary, the RISC-V-oriented eBPF loop vectorization compilation method provided in this application uses annotations generated by the LLVM compilation environment for bytecode parsing. It does not bypass the original eBPF security verification logic. Memory access and instruction execution of the vector machine code both follow the eBPF memory model and security constraints, without introducing new security risks such as out-of-bounds errors or illegal calls, thus ensuring the security of kernel-mode execution. By generating RVV vector machine code and performing parallel computation when conditions are met, it achieves "single instruction multiple data" parallel processing, transforming the "temporal serial" nature of eBPF loops into the "spatial parallel" nature of RVV vectors. For data-intensive logic such as packet traversal, traffic statistics, memory page monitoring, and malicious feature matching, it can significantly improve processing throughput, reduce task response latency and CPU utilization, and effectively solve the scalar execution performance bottleneck in high-bandwidth, high-concurrency scenarios. The RVV vector execution mode reduces a large number of repetitive loop control instructions and memory read / write instructions, alleviating register overflow issues caused by the scarcity of eBPF scalar register resources, reducing I-Cache pressure and branch prediction failure rate. Compared to pure scalar execution, it reduces CPU computing power and power consumption under the same task completion conditions, improving energy efficiency. Simultaneously, it generates RVV vector machine code and scalar backoff code, forming a dual execution path of "parallel priority, scalar fallback," ensuring seamless switching to scalar backoff code execution even in scenarios where the hardware environment does not support RVV, the data volume does not reach the minimum vectorization threshold, vectorization verification fails, or runtime exceptions occur. The entire process does not disrupt the original program semantics of eBPF, guarantees strict consistency of computation results, avoids business interruptions or functional abnormalities, and improves the robustness and availability of eBPF programs.

[0046] Figure 2 This is a flowchart illustrating another RISC-V-oriented eBPF loop vectorization compilation method provided in an embodiment of this application.

[0047] like Figure 2 As shown, this RISC-V-oriented eBPF loop vectorization compilation method includes, but is not limited to, the following steps: S201, Load the eBPF source code to be compiled into the LLVM compilation environment to generate the LLVM intermediate representation.

[0048] In one feasible implementation, the eBPF source code to be vectorized and optimized is directly loaded into a pre-configured LLVM compilation environment that is compatible with the eBPF compilation specification (without modifying the eBPF source code or the LLVM core compilation configuration). Lexical analysis, syntax analysis, and semantic verification are then performed on the eBPF source code sequentially, converting the eBPF instruction set specification-compliant source code into an LLVM standard intermediate representation (IR, used to transfer program information between the compiler front-end and back-end; front-ends include Clang, Rustc, etc., and back-ends include x86 and ARM code generators). It should be noted that the intermediate representation fully preserves the loop structure, memory access logic, register operation semantics, and side-effect-free instruction characteristics of the eBPF program, and is compatible with subsequent LLVM static analysis and optimization toolchains.

[0049] S202 performs static analysis on the LLVM intermediate representation, identifies cyclic regions that meet the vectorization conditions, and adds vectorized metadata annotations to the cyclic regions.

[0050] In one feasible implementation, loop structure analysis is performed on the LLVM intermediate representation to identify the basic loop blocks, loop entry / exit instructions, loop induction variables (core variables used for counting and loop exit judgment), and single back-edge jump structures in the LLVM intermediate representation, so as to clarify the overall framework and instruction boundaries of the eBPF loop.

[0051] In some embodiments, the initial values, update compensation, and exit conditions of the loop induction variable are extracted. Through semantic analysis and constant propagation calculations, it is verified whether the loop satisfies the bounded loop requirement of eBPF (i.e., the loop iteration count does not have an infinite possibility). A clear upper limit is determined through static analysis or eBPF verifier validation. For loops that satisfy the eBPF bounded loop requirement, the maximum number of loop iterations, the minimum number of loop iterations, and the actual effective iteration interval are determined. The iteration count information is used as the basic constraint for data dependency analysis, access pattern recognition, and vectorized annotation generation.

[0052] In one feasible implementation, the memory access pattern recognition unit of the LLVM compilation environment performs line-by-line traversal and deep semantic parsing on the memory access instructions of the loop that meet the bounded loop requirements of eBPF, extracting the components of each memory access instruction, including the access base address, offset, index variable, element width, and address update logic. The base address is limited to a fixed scalar address that can be subsequently verified by the eBPF verifier, and the index variable is associated with the loop induction variable. Then, through address format matching and logical deduction, the access pattern is determined in sequence to identify whether the memory access instruction belongs to at least one of the unit-stride sequential access pattern, strided access pattern, and gather / scatter indirect access pattern.

[0053] In some embodiments, if the memory address meets the standard format of "base address + loop induction variable × element width", and the address is continuously increasing / decreasing with loop iteration without gaps, it is identified as a unit-stride sequential access mode.

[0054] In some embodiments, if the memory address meets the canonical format of "base address + loop induction variable × fixed step size × element width", and the step size is a constant scalar that is not 1, and the address is distributed at fixed intervals with the loop iteration, then the strided straddling access pattern is identified.

[0055] In some embodiments, if the memory address meets the standard format of "base address + index vector [circular inductive variable] × element width", and the value of the index vector is a discrete value that is not continuous and not at fixed intervals, and the address access has no fixed pattern, then the gather / scatter indirect access pattern is identified.

[0056] In one feasible implementation, the data flow analysis unit of the LLVM compilation environment is used to perform data flow analysis on the bounded loops of eBPF that have already undergone memory access pattern analysis. By constructing a dependency graph of operands and result values ​​for each instruction in the loop, the variable definition and usage information for each instruction is extracted. The initialization, update, reference, and output paths of variables within the loop body are clarified, and the existence of variable dependencies between adjacent and non-adjacent iterations is analyzed. Through techniques such as constant propagation, variable alias resolution, and iteration interval deduction, "real data dependencies" and "pseudo-dependencies / eliminable dependencies" are distinguished. Real data dependencies refer to dependencies that cannot be eliminated by compiler optimization and directly affect the correctness of the parallel execution results of the loop. Loops with detected cross-iteration real data dependencies (i.e., the first loop) are directly excluded from the list of vectorizable loop candidates, retaining only loops without cross-iteration real data dependencies that meet the conditions for parallel execution.

[0057] In some embodiments, the existence of variable dependencies between adjacent iterations and non-adjacent iterations includes: read-after-write (RAW) dependency, where a variable defined in a previous iteration is read and used in a subsequent iteration; write-after-read (WAR) dependency, where a variable read in a previous iteration is redefined in a subsequent iteration; and write-after-write (WAW) dependency, where a variable defined in a previous iteration is redefined and overridden in a subsequent iteration.

[0058] In one feasible implementation, the alias analysis unit of the LLVM compilation environment is used to perform refined alias analysis on bounded loops of eBPF that have completed data flow analysis (without cross-iteration real data dependencies). Through methods such as variable address tracking, pointer resolution, and eBPF map object association verification, it is determined whether there are alias ambiguities in the memory access instructions within the loop (i.e., whether different instructions point to the same memory address and may cause access conflicts), and loops with alias ambiguities that cannot be resolved and affect the correctness of parallel execution are eliminated.

[0059] In one feasible implementation, the side effect filtering unit of the LLVM compilation environment traverses all instruction sequences within the loop body, identifies and filters out the second loop, so as to obtain the target loop that meets the vectorization conditions, and obtains the loop region based on the target loop.

[0060] In some embodiments, the second loop includes eBPF Helper function calls, atomic operations, and eBPF map updates. eBPF Helper function calls have kernel-mode semantics and cannot be parallelized; atomic operations include atomic instructions such as atomic loading, atomic storing, and atomic insertion / removal, which rely on exclusive memory access and cannot support vector parallel processing; eBPF map updates perform write operations such as insertion, modification, and deletion on the eBPF map table, which involve shared resource access and have semantic constraints, making parallel optimization impossible.

[0061] In one feasible implementation, adding vectorized metadata annotations to the circular region includes: determining the data format for carrying RVV vectorized metadata according to the LLVM metadata specification, wherein the data format is used to carry semantic layer configuration information and semantic layer mask control parameters; determining the one-to-one mapping relationship between the eBPF virtual registers and each Lane in the RVV vector registers according to the preset register mapping constraints in the data format, so as to realize the conversion from eBPF serial semantics to RVV parallel semantics; and constructing standardized metadata nodes that can be mounted to the circular region based on the mapping relationship and in combination with semantic layer configuration information and semantic layer mask control parameters, so as to complete the vectorized metadata annotation of the circular region.

[0062] S203, embeds the annotation into a custom ELF extension segment that does not participate in the eBPF bytecode to obtain the annotated eBPF bytecode, wherein the eBPF bytecode is obtained based on the eBPF source code.

[0063] In one feasible implementation, lexical, syntactic analysis, and semantic transformation are completed through the front-end compilation chain of the LLVM compilation environment. After optimization by the eBPF back-end compilation, pure scalar eBPF bytecode conforming to the eBPF instruction set specification is generated. A custom ELF extension segment, independent of the native eBPF executable instruction stream, is created (this extension segment is not included in the executable instruction verification scope of the eBPF kernel verifier, does not participate in the loading, parsing, and native execution process of eBPF bytecode, and only serves as a metadata storage carrier). The previously generated vectorized annotations (including core metadata such as loop iteration intervals, memory access patterns, and vectorization thresholds) are written into this custom ELF extension segment according to a preset structured format (such as fixed field length, key-value pair mapping, and binary serialization format). The custom ELF extension segment storing vectorized annotations is integrated with the native eBPF bytecode to form a composite eBPF bytecode that combines executable eBPF instructions with vectorized metadata annotations. This annotated eBPF bytecode retains the executableness and kernel compatibility of the native eBPF bytecode, while also carrying the key annotation information required for subsequent vectorization processing through the custom ELF extension segment, providing data support for the parsing and vector compilation of the kernel-mode JIT enhancement module.

[0064] S204, parse the annotated eBPF bytecode to generate RVV vector machine code and scalar backoff code that is semantically equivalent to eBPF scalars.

[0065] In one feasible implementation, the syntax compliance of eBPF instructions and their corresponding operands in the annotated eBPF bytecode is checked, and the execution semantics of the eBPF instructions are extracted. The compliance of RVV vectorized metadata in the annotated eBPF bytecode is checked, and configuration parameters and constraints related to vector compilation are extracted. Based on the execution semantics and configuration parameters and constraints, RVV vector machine code conforming to the RISC-V vector extension native vector execution model is generated; wherein, if the vectorization conditions are not met, scalar fallback code equivalent to eBPF scalar semantics is generated using the native scalar execution semantics of eBPF.

[0066] For further details on step S204, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0067] S205, in response to the hardware environment and data volume meeting the conditions for parallelization, the RVV vector machine code is executed to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code.

[0068] In one feasible implementation, if the hardware environment and data volume meet preset parallelizability conditions, a classification-based parallel translation mechanism is used to identify and extract parallelizable logic instructions within the loop region. This mechanism categorizes instructions within the loop region based on their function type and matches a corresponding parallelization translation strategy to each type of instruction. Parallelizable logic instructions include arithmetic logic instructions, comparison instructions, data movement instructions, and memory load / store instructions verified by eBPF. Based on these parallelizable logic instructions, RVV vector machine code is triggered and executed to perform parallel computation on multiple iterative operations within the loop region.

[0069] For further details on step S205, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0070] S206, in response to the hardware environment or data volume not meeting the conditions for parallelization, executes scalar backoff code to perform sequential scalar processing on multiple iterative operations within the loop region.

[0071] In one feasible implementation, if the relevant hardware environment and data volume do not meet the preset parallelizability conditions, a scalar rollback processing mechanism is used to identify and extract all scalar logic instructions within the loop region. This mechanism adapts all instructions within the loop region based on the eBPF scalar execution specification and matches corresponding scalar translation and execution strategies for different types of scalar instructions. The scalar logic instructions include parallelizable logic instructions and non-parallelizable instructions excluded from the loop region. Based on all scalar logic instructions, scalar rollback codes are triggered and executed to perform sequential scalar processing on multiple iterative operations within the loop region.

[0072] For further details on step S206, please refer to the relevant descriptions in the above embodiments; they will not be repeated here.

[0073] In summary, the RISC-V-oriented eBPF loop vectorization compilation method provided in this application uses annotations generated by the LLVM compilation environment for bytecode parsing. It does not bypass the original eBPF security verification logic. Memory access and instruction execution of the vector machine code both follow the eBPF memory model and security constraints, without introducing new security risks such as out-of-bounds errors or illegal calls, thus ensuring the security of kernel-mode execution. By generating RVV vector machine code and performing parallel computation when conditions are met, it achieves "single instruction multiple data" parallel processing, transforming the "temporal serial" nature of eBPF loops into the "spatial parallel" nature of RVV vectors. For data-intensive logic such as packet traversal, traffic statistics, memory page monitoring, and malicious feature matching, it can significantly improve processing throughput, reduce task response latency and CPU utilization, and effectively solve the scalar execution performance bottleneck in high-bandwidth, high-concurrency scenarios. The RVV vector execution mode reduces a large number of repetitive loop control instructions and memory read / write instructions, alleviating register overflow issues caused by the scarcity of eBPF scalar register resources, reducing I-Cache pressure and branch prediction failure rate. Compared to pure scalar execution, it reduces CPU computing power and power consumption under the same task completion conditions, improving energy efficiency. Simultaneously, it generates RVV vector machine code and scalar backoff code, forming a dual execution path of "parallel priority, scalar fallback," ensuring seamless switching to scalar backoff code execution even in scenarios where the hardware environment does not support RVV, the data volume does not reach the minimum vectorization threshold, vectorization verification fails, or runtime exceptions occur. The entire process does not disrupt the original program semantics of eBPF, guarantees strict consistency of computation results, avoids business interruptions or functional abnormalities, and improves the robustness and availability of eBPF programs.

[0074] Corresponding to the aforementioned RISC-V-oriented eBPF loop vectorization compilation method, this application also provides a RISC-V-oriented eBPF loop vectorization compilation apparatus. Since the RISC-V-oriented eBPF loop vectorization compilation apparatus corresponds to the aforementioned RISC-V-oriented eBPF loop vectorization compilation method, details not disclosed in the embodiments of the RISC-V-oriented eBPF loop vectorization compilation apparatus can be found in the embodiments of the aforementioned RISC-V-oriented eBPF loop vectorization compilation method, and will not be repeated here.

[0075] Figure 3 This is a schematic diagram of the structure of an eBPF loop vectorization compiler for RISC-V provided in an embodiment of this application.

[0076] like Figure 3 As shown, the eBPF circular vectorization compiler 300 for RISC-V includes: Loading module 301 is used to load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode; The generation module 302 is used to parse the annotated eBPF bytecode to generate RVV vector machine code and scalar backoff code that is equivalent to eBPF scalar semantics. The first compilation module 303 is used to execute RVV vector machine code in response to the hardware environment and data volume meeting the parallelization conditions, so as to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code. The second compilation module 304 is used to execute scalar backoff codes in response to hardware environment or data volume not meeting the conditions for parallelization, so as to perform sequential scalar processing on multiple iterative operations in the loop region.

[0077] The methods and apparatus provided in the embodiments of this application have been described above. To achieve the functions of the methods provided in the embodiments of this application, the methods and apparatus can be further refined using electronic devices.

[0078] Figure 4 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Figure 4 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0079] like Figure 4 As shown, the electronic device 400 includes a processor 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 402 or a program loaded from memory 406 into a random access memory (RAM) 403. The RAM 403 also stores various programs and data required for the operation of the electronic device 400. The processor 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0080] The following components are connected to I / O interface 405: memory 406 including hard disks, etc.; and communication section 407 including network interface cards such as LAN (Local Area Network) cards, modems, etc., which performs communication processing via a network such as the Internet; and driver 408 is also connected to I / O interface 405 as needed.

[0081] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 407. When the computer program is executed by processor 401, it performs the functions defined in the methods of this application.

[0082] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory including instructions, which can be executed by a processor 401 of an electronic device 400 to perform the above-described method. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0083] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0084] In this embodiment of the disclosure, a computer program product is also provided, including a computer program that, when executed by a processor, implements the methods disclosed in the above embodiments.

[0085] For cases where the corresponding electronic device can be a chip or a chip system, please refer to [reference needed]. Figure 5 The diagram shows the result of the chip. Figure 5The chip shown includes one or more interface circuits 502 and one or more processors 501; the interface circuits 502 are used to receive signals from the memory of the electronic device and send signals to the processors 501. The signals include computer instructions stored in the memory 503. When the processors 501 execute the computer instructions, the electronic device performs the steps of the RISC-V-oriented eBPF cyclic vectorization compilation method proposed in the embodiments of this application.

[0086] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0087] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A RISC-V-oriented eBPF loop vectorization compilation method, characterized in that, include: Load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode; The annotated eBPF bytecode is parsed to generate RVV vector machine code and scalar backoff code that is semantically equivalent to eBPF scalars. In response to the hardware environment and data volume meeting the conditions for parallelization, the RVV vector machine code is executed to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code. In response to hardware conditions or data volume not meeting the conditions for parallelization, the scalar backoff code is executed to perform sequential scalar processing on multiple iterative operations within the loop region.

2. The method according to claim 1, characterized in that, The process of loading the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode includes: Load the eBPF source code to be compiled into the LLVM compilation environment to generate the LLVM intermediate representation; Static analysis is performed on the LLVM intermediate representation to identify cyclic regions that meet the vectorization conditions, and vectorized metadata annotations are added to the cyclic regions. The annotations are embedded into a custom ELF extension segment that does not participate in the eBPF bytecode to obtain an annotated eBPF bytecode, wherein the eBPF bytecode is obtained based on the eBPF source code.

3. The method according to claim 2, characterized in that, The step of performing static analysis on the LLVM intermediate representation to identify cyclic regions that meet the vectorization conditions includes: Perform loop structure analysis on the intermediate representation of LLVM to determine the number of loop iterations that satisfy the bounded loop requirement of eBPF; Analyze the memory access instructions of loops that satisfy the bounded loop requirements of eBPF to identify whether the memory access instructions belong to at least one of the unit-stride sequential access mode, strided access mode, and gather / scatter indirect access mode. Perform data flow analysis on the loops that complete the memory access pattern analysis to exclude the first loop that has cross-iteration real data dependencies. Alias ​​analysis is performed on the loops that complete the data flow analysis to filter out the second loops that contain eBPF Helper function calls, atomic operations, and eBPF map updates, so as to identify the target loops that meet the vectorization conditions, and obtain the loop region based on the target loops.

4. The method according to claim 2, characterized in that, The annotation for adding vectorized metadata to the cyclic region includes: The data format for carrying RVV vectorized metadata is determined according to the LLVM metadata specification, wherein the data format is used to carry semantic layer configuration information and semantic layer mask control parameters; Based on the preset register mapping constraints in the data format, the one-to-one mapping relationship between the eBPF virtual register and each Lane in the RVV vector register is determined to realize the conversion from eBPF serial semantics to RVV parallel semantics. Based on the mapping relationship, combined with the semantic layer configuration information and semantic layer mask control parameters, a standardized metadata node that can be mounted to the cyclic region is constructed to complete the vectorized metadata annotation of the cyclic region.

5. The method according to claim 1, characterized in that, The step of parsing the annotated eBPF bytecode to generate RVV vector machine code and scalar fallback code equivalent to eBPF scalar semantics includes: Syntax compliance checks are performed on the eBPF instructions and their corresponding operands in the annotated eBPF bytecode, and the execution semantics of the eBPF instructions are extracted. Perform compliance verification on the RVV vectorized metadata in the annotated eBPF bytecode, and extract the configuration parameters and constraints related to vector compilation; Based on the execution semantics and the configuration parameters and constraints, RVV vector machine code conforming to the RISC-V vector extension native vector execution model is generated; If the vectorization condition is not met, the native scalar of eBPF is used to generate a scalar backoff code that is semantically equivalent to the eBPF scalar.

6. The method according to any one of claims 1-5, characterized in that, The step of responding to the hardware environment and data volume meeting the parallelizability conditions, executing the RVV vector machine code to perform parallel computation on multiple iterative operations within the loop region, including: If the hardware environment and data volume meet the preset parallelization conditions, a classification parallel translation mechanism is used to identify and extract parallelizable logic instructions within the loop region. The classification parallel translation mechanism performs classification processing on instructions in the loop region based on instruction function type, and matches a corresponding parallelization translation strategy for each type of instruction. The parallelizable logic instructions include arithmetic logic instructions, comparison instructions, data move instructions, and memory load / store instructions verified by eBPF. The RVV vector machine code is triggered and executed based on the parallelizable logic instructions to perform parallel computation on multiple iterative operations within the loop region.

7. The method according to any one of claims 1-5, characterized in that, The step of executing the scalar backtracking code in response to hardware environment or data volume not meeting parallelization conditions to perform sequential scalar processing on multiple iterative operations within the loop region includes: If the relevant hardware environment and data volume do not meet the preset parallelizability conditions, a scalar rollback processing mechanism is used to identify and extract all scalar logic instructions within the loop region. The scalar rollback processing mechanism adapts all instructions within the loop region based on the eBPF scalar execution specification and matches corresponding scalar translation and execution strategies for different types of scalar instructions. The scalar logic instructions include parallelizable logic instructions and non-parallelizable instructions excluded from the loop region. The scalar backoff code is triggered and executed based on all the scalar logic instructions to perform sequential scalar processing on multiple iterative operations within the loop region.

8. An eBPF loop vectorization compiler for RISC-V, characterized in that, include: A loading module, which is used to load the eBPF source code to be compiled into the LLVM compilation environment to generate annotated eBPF bytecode; A generation module is used to parse the annotated eBPF bytecode to generate RVV vector machine code and scalar backoff code that is equivalent to eBPF scalar semantics. The first compilation module is used to execute the RVV vector machine code in response to the hardware environment and data volume meeting the parallelization conditions, so as to perform parallel computation on multiple iterative operations within the loop region, wherein the loop region is based on the eBPF source code. The second compilation module is used to execute the scalar backoff code in response to the hardware environment or the amount of data not meeting the conditions for parallelization, so as to perform sequential scalar processing on multiple iterative operations in the loop region.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method according to any one of claims 1 to 7.

10. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1 to 7.

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