Chip read-write test and control system supporting multiple protocols and based on ZYNQ

Abstract

The invention relates to a chip read-write test and control system supporting multiple protocols, and belongs to the field of integrated circuit chip control and safe burning. According to the system, a command of an upper computer is analyzed through an end operation system and then written into an instruction decoding IP core of a PL end, the instruction decoding IP core of the PL end performs secondary analysis on the written command, and control waveforms of corresponding chips are output on pins of a chip base through a special time sequence output IP core, a time sequence output IP core and a time sequence output IP core of the PL end; a dynamic encryption strategy is introduced into a firmware program of an operation system of the terminal, and when the firmware program is updated each time, a program mirror image is encrypted by using an encryption key derived at one time; and the IP core of the PL end can be updated in a user-defined manner, so that a communication protocol and a chip read-write time sequence of the end are expanded. According to the separated architecture, the expandability and the maintenance convenience are improved, and the system and the method are suitable for high-requirement application scenes such as chip verification, batch burning and safety testing.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit chip control and secure programming, and relates to a chip read / write test and control system based on ZYNQ that supports multiple protocols. Background Technology

[0002] With the rapid development of electronic technology, chips are increasingly widely used in modern industry, consumer electronics, automobile manufacturing, communication equipment, and other fields. The realization of their core functions depends on writing specific programs, data, or configuration files into the chip's internal storage area. This process directly affects the correctness and reliability of the chip's functions. During chip manufacturing and testing, the equipment's ability to operate different protocols, the accuracy of timing control, and the efficiency and success rate of read and write operations directly affect the overall quality and capacity of the production line.

[0003] Traditional control devices are mostly based on microcontroller or DSP architectures. These architectures suffer from performance bottlenecks when handling complex protocols, especially when supporting multi-protocol and multi-channel tasks, where their computing power and resource scheduling capabilities are insufficient. In recent years, with the development of embedded technology, the ZYNQ platform, as a heterogeneous architecture integrating an ARM processor (PS) and FPGA programmable logic (PL), has provided new ideas for the design of chip read / write control devices. The ARM side can efficiently complete task management, protocol parsing, data interaction, and complex timing generation, while the FPGA side can utilize hardware logic to generate timing signals. Therefore, developing a read / write test and control system based on the ZYNQ platform that supports multiple chips not only meets the diverse operational needs of different chip timings but also has significant research value and practical significance.

[0004] Most current control devices employ fixed timing logic, designed for specific protocols, making it difficult to adapt to the protocol requirements of new chips. For some dedicated protocols (such as the timing protocols of OTP chips), the timing logic needs to be redeveloped, resulting in a long development cycle and poor scalability. In designs based on the ZYNQ platform, fully utilizing the heterogeneous architecture advantages of ARM and FPGA remains a challenge. In existing research, the task division between FPGA and ARM is often unclear, leading to low data interaction efficiency and difficulty in meeting the requirements of high-performance, multi-tasking programming. Multi-channel read / write devices often face problems such as signal conflicts and uneven task allocation in practical applications, resulting in decreased programming efficiency or increased failure rates. In addition, the electrical characteristics of different channels (such as voltage level requirements) also increase the complexity of hardware design. In the design of multi-protocol timing controllers, how to rationally allocate and manage limited system resources (such as logic units, I / O pins, memory, etc.) to simultaneously meet the needs of multiple protocols and multiple channels is an unsolved problem. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a chip read / write test and control system based on ZYNQ that supports multiple protocols. Specifically, it is a chip read / write test and control system based on the ZYNQ heterogeneous computing platform, integrating multi-protocol control, data encryption, and batch scheduling capabilities. This system is widely applicable to the efficient and secure data writing, reading, and verification operations of chips with multiple communication protocols such as IIC, SPI, and OTP. It falls within the category of high-performance control system technology that crosses embedded system design and trusted electronics testing, improving upon the problems of poor versatility, low architecture development efficiency, and high expansion difficulty of traditional chip controllers.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A multi-protocol-supporting ZYNQ-based chip read / write test and control system includes a host computer, a chip base, and a PS terminal and a PL terminal. The PS terminal runs the FreeRTOS system and parses the commands from the host computer, writing them into the instruction decoding IP core of the PL terminal. The instruction decoding IP core of the PL terminal performs secondary parsing of the written commands and outputs the corresponding chip control waveforms on the pins of the chip base through the special timing output IP core, IIC timing output IP core, and SPI timing output IP core of the PL terminal. The firmware program running the FreeRTOS system on the PS side introduces a dynamic encryption strategy based on DES. Each time the firmware program is updated, a one-time derived encryption key is used to encrypt the program image. The IP core on the PL side can be customized and updated, thereby expanding the communication protocol and chip read / write timing on the PS side.

[0007] Furthermore, when the PS is running the FreeRTOS system, it simultaneously starts multiple task queues, parses the commands transmitted by the host computer via UART, executes the corresponding API functions, and writes the command data into the registers of the instruction decoding IP core on the PL side. The API functions parse the instructions transmitted from the serial port and change the data of the corresponding channel control bit address, thereby realizing the control of the PL side.

[0008] Furthermore, the PS end is equipped with a task scheduling application and an instruction transceiver application. The instruction transceiver application establishes a communication link with the host computer via USB or UART, receives and parses the instructions sent by the host computer, writes the parsed operation type, target channel, and parameters into a preset task queue, and triggers the task scheduling application after parsing is completed. The task scheduling application calls the corresponding API function according to the instruction priority and system resource status in the task queue, and configures and controls the instruction decoding IP core and various timing output IP cores on the PL end through the AXI bus, thereby completing operations such as reading, writing, erasing, and verification of different chips. The operator sends commands to the instruction transceiver application through the host computer to achieve unified management and control of the entire ZYNQ-based chip read / write test and control system.

[0009] Furthermore, the special timing IP core on the PL side is used to generate the operating timing of the OTP chip, and the chip frequency is changed by adjusting the method of writing data; The PL's IIC timing output IP core and SPI timing output IP core are used to generate read and write control timings for flash memory supporting the SPI protocol and EEPROM supporting the IIC protocol. The IIC timing output IP core uses Xilinx's AXI Quad SPI peripheral IP core, which calls functions on the PS side to drive the peripheral IP to generate read, write, and erase timings for the flash memory. The SPI timing output IP core uses ZYNQ's hardware IIC to drive GPIO to implement control timings for the output chip. After the data is written, the IP core sends a read timing signal to read the data from the chip, compares it with the written data, and completes the detection step.

[0010] Furthermore, the special timing IP core at the PL end includes a frequency measurement module, a voltage control module, and a read / write timing output module. When the system is powered on, the voltage control module adjusts the pin voltage output to the OTP chip to the first voltage. Under the first voltage, the chip emits a frequency. The frequency measurement module measures the chip's reference frequency and transmits the frequency value to the PS end via the AXI bus. The reference frequency is substituted into the formula to calculate the chip's control word. After the calculation is completed, the voltage control module continuously changes the output level of the voltage pin, switching between the first and second voltages, until the read / write timing output module writes the entire control word into the chip. The voltage control module then adjusts the chip's pin voltage to the first voltage, controlling the chip to emit the frequency to be measured. The frequency measurement module automatically calculates the part-in-a-million error value and transmits the error value to the PS end.

[0011] Furthermore, the frequency metering module uses an equal-precision measurement method to detect the frequency value emitted by the chip, and within the time specified by the gate signal, it measures the frequency of the signal under test. and reference signal Perform the count and obtain the count value. and The resulting count is proportional to the frequency of the signal being counted. The frequency of the signal under test can be calculated using the following formula. :

[0012] Error frequency The calculation is as follows:

[0013] The relative error is:

[0014] To calculate and write the control word to the chip, the chip's reference frequency value must first be measured. The formula is as follows:

[0015]

[0016] The chip's DSM_VALUE is calculated based on the reference frequency value, and the target frequency is finally obtained by writing DSM_VALUE to the chip. .

[0017] Furthermore, the firmware program running the FreeRTOS system on the PS side utilizes the multi-boot feature of Xilinx FPGA, which allows the FPGA to load multiple bitstreams from different addresses of external Flash. The flash is configured with a Lock program responsible for encryption operations, a main program responsible for decryption operations, and a space for storing ciphertext. The Lock program in Multi-boot uses the device DNA as plaintext and performs DES encryption with a user-defined key, then writes the encrypted ciphertext into flash. The main program then performs a symmetric mirroring operation, reads the ciphertext from flash, performs DES decryption with a user-defined key, and then restores it to plaintext. The device's DNA is unique to the main program; the program can only be successfully loaded if the program and the FPGA chip match.

[0018] Furthermore, in the encryption process, when the system is powered on, the FPGA loads the main program from the Flash. If the main program is successfully loaded, the ciphertext data at the specified location is read from the Flash, and the ciphertext is decrypted using the decryption operation module integrated in the system using DES. After decryption, the obtained plaintext data is compared with the preset content. If the comparison is successful, it means that the data is valid, and the program starts running. If the main program fails to load, the system loads a Lock program that has been pre-written into Flash. The Lock program is responsible for reading the current ZYNQ device DNA, combining it with the DNA, encrypting the application content through the encryption operation module, and finally writing the encrypted data to the specified location in Flash.

[0019] Furthermore, the IP core has a protocol extension interface, which supports module-level loading and replacement of protocol descriptions based on Verilog language, making it easy for users to dynamically add or modify protocol logic according to different chip characteristics or new protocol requirements.

[0020] Furthermore, the system adopts a main card and daughter card separable architecture, and sets up separate chip adapters for supported protocols. The adapter of the OTP chip is equipped with a level conversion circuit, and its output voltage is controlled by the voltage control module of the PL end.

[0021] The beneficial effects of this invention are as follows: Read / write control of different chips involves various protocols, which differ in timing requirements and data transmission methods. This invention enables the control and testing of multiple chips, supporting efficient and accurate read / write operations for various chip types. By establishing clear protocol access specifications and timing configuration methods, the system can flexibly adapt to the timing requirements of different chips. Simultaneously, a scalable system architecture is constructed, and flexible hardware and software interfaces are designed to support the access of new chip protocols, providing strong support for future protocol expansion and timing operations for more chip types. This improves upon the problems of poor versatility, low architecture development efficiency, and high expansion difficulty of traditional chip controllers.

[0022] Furthermore, the system innovatively introduces a dynamic encryption method combining DES with Device ID. After each program upgrade, the administrator can change the encryption key. Users can only successfully start the system with the new key. Moreover, after the update, the image will strongly bind the encryption key to Device DNA, so that the encrypted image can only run on specific chips, preventing the image from being copied to other devices and fundamentally eliminating the illegal copying and distribution of firmware.

[0023] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the structure of a chip read / write test and control system based on ZYNQ according to an embodiment of the present invention; Figure 2 This is an overall flowchart illustrating the functional implementation in an embodiment of the present invention; Figure 3 This is a schematic diagram of the encryption and decryption section in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the algorithm execution for encryption and decryption in the system according to an embodiment of the present invention. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0028] Please see Figures 1-4 This is a ZYNQ-based chip read / write test and control system that supports multiple protocols.

[0029] This embodiment first provides a ZYNQ-based chip read / write test and control system that supports multiple protocols, such as... Figure 1As shown, it includes a host computer, a chip base, and a PS terminal and a PL terminal. The PS terminal runs the FreeRTOS system and parses the commands from the host computer and writes them into the instruction decoding IP core of the PL terminal. The instruction decoding IP core of the PL terminal performs secondary parsing on the written commands and outputs the corresponding chip control waveforms on the pins of the chip base through the special timing output IP core, IIC timing output IP core and SPI timing output IP core of the PL terminal. The firmware program running the FreeRTOS system on the PS side introduces a dynamic encryption strategy based on DES. Each time the firmware program is updated, a one-time derived encryption key is used to encrypt the program image. The IP core on the PL side can be customized and updated, thereby expanding the communication protocol and chip read / write timing on the PS side.

[0030] After the system is powered on, the ZYNQ processor system (referred to as the PS side) starts running the FreeRTOS system, starts multiple task queues, monitors the commands transmitted from the host computer via UART, parses the commands, executes the corresponding API functions, and finally writes the command data into the register of the instruction decoding IP core.

[0031] ZYNQ's programmable logic side (PL side) instruction decoding IP core performs secondary parsing on the commands transmitted from the PS side, enabling control of special timing output IP cores, IIC timing output IP cores, and SPI timing output IP cores, and finally outputs the corresponding chip's control waveform on the pins.

[0032] A dynamic encryption strategy based on DES is introduced into the firmware program running on ZYNQ. Each time the firmware is updated, a one-time derived encryption key is used to encrypt the program image. In this embodiment, the operating system can run up to 8 tasks simultaneously and control 8 chips. The API functions parse the instructions transmitted from the serial port and modify the data at the corresponding channel control bit address to control the PL terminal.

[0033] This system can expand new communication protocols and chip read / write timings by updating the custom IP core on the PL side. It supports multiple communication protocols such as IIC, SPI, and OTP. Furthermore, by configuring registers and timing templates, it can achieve rapid switching and fine timing control of various chip read / write protocols.

[0034] More specifically, the PS terminal is equipped with a task scheduling application and an instruction transceiver application. The instruction transceiver application establishes a communication link with the host computer via USB or UART, receives and parses the instructions sent by the host computer, writes the parsed operation type, target channel, and parameters into a preset task queue, and triggers the task scheduling application after parsing is completed. The task scheduling application calls the corresponding API function according to the instruction priority and system resource status in the task queue, and configures and controls the instruction decoding IP core and timing output IP cores on the PL terminal through the AXI bus, thereby completing operations such as reading, writing, erasing, and verification of different chips. The operator sends commands to the instruction transceiver application through the host computer to achieve unified management and control of the entire ZYNQ-based chip read / write test and control system.

[0035] The instruction decoding IP core at the PL end parses the data in the instruction register and sends it to the timing IP core corresponding to the instruction. The control IP core outputs different timing signals to the chip pins to complete the corresponding operations on the chip.

[0036] The special timing IP core on the PL side is used to generate the operation timing of the OTP chip. This chip is a crystal oscillator chip, and its frequency can be changed by adjusting the data written. The IP core consists of a frequency measurement module, a voltage control module, and a read / write timing output module. When the chip is successfully written with data, the program will automatically calculate the ppm error and send the detection result to the host computer via the serial port.

[0037] The frequency metering module uses an equal-precision measurement method to detect the frequency value emitted by the chip. Within the specified time of the gate signal, it measures the signal under test. and reference signal Perform the count and obtain the count value. and Since the counting time is consistent, the counting result is proportional to the frequency of the signal being counted. The frequency value of the signal under test can be calculated using the following formula. :

[0038] However, due to the uncertainty of the relationship between the actual gate signal and the reference clock, the reference clock counter may still exhibit a technical deviation of one unit, thus affecting the error frequency. The calculation is as follows:

[0039] Therefore, the relative error is:

[0040] It can be seen that the relative error is only related to Related to this, Ns = actual gate width t * reference clock frequency The value is a fixed value independent of the frequency of the signal under test; this enables equal-precision measurement of signals under test at different frequencies, and the larger the gate width and the higher the reference clock frequency, the smaller the error. For signals in the 50MHz-100MHz range, the measurement error of the frequency metering module is only about 2ppm.

[0041] The calculation of the control word written to the chip first requires measuring the chip's reference frequency value Fref. Based on the reference frequency value, the chip's DSM_VALUE is calculated. Writing DSM_VALUE to the chip ultimately yields the target frequency Ftarget, as shown in the following formula:

[0042]

[0043] The PL's IIC timing output IP core and SPI timing output IP core are used to generate read / write control timings for flash memory supporting the SPI protocol and EEPROM supporting the IIC protocol. For flash chips, Xilinx's AXI Quad SPI peripheral IP core is used, with functions called on the PS side to drive the peripheral IP to generate read, write, and erase timings for the flash. For EEPROM chips, ZYNQ's hardware IIC is used to drive GPIO to implement control timings for the output chip. After data is written, the IP core issues a read timing signal to read the data from the chip, compares it with the written data, and completes the detection step.

[0044] The system uses Device ID combined with DES encryption, allowing for multiple changes to the programming key without requiring an external battery to ensure key persistence. This is a customizable encryption method suitable for mass production. The Device ID is a unique identifier for each FPGA chip. DES encryption is performed on the 64-bit Device ID and a 56-bit custom key to generate ciphertext, which is then downloaded to flash memory, completing the program encryption. Because the custom key can be changed, it can be modified with each program update to prevent program cracking. Furthermore, the system strongly binds the encryption key to the Device ID, ensuring that the encrypted image can only run on specific chips, making it a more flexible encryption method.

[0045] The IP core has a protocol extension interface, which supports module-level loading and replacement of protocol descriptions based on Verilog language. This allows users to dynamically add or modify protocol logic according to different chip characteristics or new protocol requirements without changing the main control program, significantly improving the system's adaptability and upgradeability.

[0046] The system adopts a detachable main card and daughter card architecture, offering excellent scalability. Each supported protocol has its own dedicated chip adapter, allowing connection of up to eight chip adapters and accommodating 8-16 chips. The OTP chip adapter incorporates a level conversion circuit, with its output voltage controlled by a voltage control module on the PL side.

[0047] like Figure 1 A block diagram of a chip read / write test and control system based on ZYNQ is presented, demonstrating the functions implemented by the ZYNQ's PS and PL terminals in the system, as well as the communication methods of each module. Figure 1 The instruction decoding IP core parses the data from the instruction register and sends it to the corresponding timing IP core. Its instruction structure is: prefix code + command code + channel number + checksum. The prefix code is a fixed value used to identify different chip models. The command code is the control operation for the chip. The channel number selects a specific channel for output control timing; 0 indicates the channel is not selected, and 1 indicates it is selected. The checksum is calculated using a checksum method based on the preceding command parts.

[0048] Figure 1 The special timing output IP core in the system allows the voltage control module to adjust the pin voltage of the OTP chip to 3.3V after the system powers on. At 3.3V, the chip emits a frequency. At this time, the frequency measurement module measures the chip's reference frequency and transmits the frequency value to the PS terminal via the AXI bus. The reference frequency is then substituted into the formula to calculate the chip's control word. After the calculation is completed, the voltage control module continuously changes the output level of the voltage pin, switching between 3.3V and 6.5V, until the read / write timing output module writes the entire control word into the chip. The voltage control module then adjusts the chip's pin voltage to 3.3V, controlling the chip to emit the frequency to be measured. The frequency measurement module automatically calculates the error ppm value and transmits the error value to the PS terminal.

[0049] Figure 1 The IIC timing output IP core and SPI timing output IP core are used to generate read / write control timings for flash memory supporting the SPI protocol and EEPROM supporting the IIC protocol. For flash chips, Xilinx's AXI Quad SPI peripheral IP core is used, with functions called on the PS side to drive the peripheral IP to generate read, write, and erase timings for the flash. For EEPROM chips, ZYNQ's hardware IIC is used to drive GPIO to implement control timings for the EEPROM. After data is written, the IP core issues a read timing signal to read the data from the chip, compares it with the written data to check for correctness, and completes the detection step.

[0050] Figure 2The overall workflow of the entire system is presented. First, the user transmits commands to the PS terminal via serial port through the host computer. After the commands are parsed on the PS terminal, multiple operation tasks are started on the FreeRTOS system to execute the corresponding programs. Then, the commands are transmitted to the PL terminal, and the control IP core issues the control timing sequence of the corresponding chip, which is input into the chip from the pins of the chip adapter. For program encryption, the multi-boot feature of Xilinx FPGAs needs to be utilized. This mechanism allows the FPGA to load multiple bitstreams from different addresses in external Flash. Therefore, two copies of the program exist in the Flash: one is the Lock program responsible for encryption operations, and the other is the main program containing decryption operations. In addition, a space needs to be designated in the Flash to store the ciphertext. For example... Figure 3 As shown, the Lock program in Multi-boot uses the DNA as plaintext and performs DES encryption with a user-defined key, then writes the encrypted ciphertext into flash memory. The main program performs a symmetric mirroring operation, reading the ciphertext from flash memory and decrypting it using the user-defined key, then restoring it to plaintext. Because of the uniqueness of the Device DNA, the main program is also unique; only when the program and the FPGA chip match can the program be successfully loaded.

[0051] Figure 4 The entire encryption process is described: First, the system is powered on, and the FPGA loads the main program (application program) from the Flash memory. If the main program loads successfully, the ciphertext data at the specified location is read from the Flash memory, and the ciphertext is decrypted using the decryption module integrated into the system (usually combined with Device DNA to generate the key). After decryption, the obtained plaintext data is compared with the preset content. If the comparison is successful, it means that the data is valid, and the program starts running. If the main program fails to load: the system will load a Lock program that has been written to Flash beforehand. The Lock program is responsible for reading the Device DNA (i.e., the chip's unique ID) of the current ZYNQ device, combining it with the DNA, encrypting the application content through the encryption operation module, and finally writing the encrypted data to the specified location in Flash.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A chip read / write test and control system based on ZYNQ that supports multiple protocols, characterized in that: The system includes a host computer, a chip base, a PS terminal, and a PL terminal. The PS terminal runs the FreeRTOS system and parses the commands from the host computer, then writes them into the instruction decoding IP core of the PL terminal. The instruction decoding IP core of the PL terminal performs secondary parsing of the written commands and outputs the corresponding chip control waveforms on the pins of the chip base through the special timing output IP core, IIC timing output IP core, and SPI timing output IP core of the PL terminal. The firmware program running the FreeRTOS system on the PS side introduces a dynamic encryption strategy based on DES. Each time the firmware program is updated, a one-time derived encryption key is used to encrypt the program image. The IP core on the PL side can be customized and updated, thereby expanding the communication protocol and chip read / write timing on the PS side.

2. The ZYNQ-based chip read / write test and control system supporting multiple protocols as described in claim 1, characterized in that: When the PS terminal is running the FreeRTOS system, it simultaneously starts multiple task queues, parses the commands transmitted by the host computer via UART, executes the corresponding API functions of the commands, and writes the command data into the register of the instruction decoding IP core of the PL terminal. API functions parse the instructions transmitted from the serial port and modify the data of the corresponding channel control bit address, thereby enabling control of the PL terminal.

3. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 2, characterized in that: The PS terminal is equipped with a task scheduling application and an instruction transceiver application. The instruction transceiver application establishes a communication link with the host computer via USB or UART, receives and parses the instructions sent by the host computer, writes the parsed operation type, target channel and parameters into a preset task queue, and triggers the task scheduling application after parsing is completed. The task scheduling application calls the corresponding API functions based on the instruction priority and system resource status in the task queue. It configures and controls the PL-side instruction decoding IP core and each timing output IP core through the AXI bus, thereby completing the read, write, erase, and verification operations on different chips. The operator sends commands to the instruction transceiver application through the host computer to achieve unified management and control of the entire ZYNQ-based chip read and write test and control system.

4. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 1, characterized in that: The special timing IP core on the PL side is used to generate the operating timing of the OTP chip, and the chip frequency is changed by adjusting the method of writing data; The PL's IIC timing output IP core and SPI timing output IP core are used to generate read and write control timings for flash memory supporting the SPI protocol and EEPROM supporting the IIC protocol. The IIC timing output IP core uses Xilinx's AXI Quad SPI peripheral IP core, which calls functions on the PS side to drive the peripheral IP to generate read, write, and erase timings for the flash memory. The SPI timing output IP core uses ZYNQ's hardware IIC to drive GPIO to implement control timings for the output chip. After the data is written, the IP core sends a read timing signal to read the data from the chip, compares it with the written data, and completes the detection step.

5. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 4, characterized in that: The special timing IP core at the PL end includes a frequency measurement module, a voltage control module, and a read / write timing output module. When the system is powered on, the voltage control module adjusts the pin voltage output to the OTP chip to the first voltage. Under the first voltage, the chip emits a frequency. The frequency measurement module measures the chip's reference frequency and transmits the frequency value to the PS end via the AXI bus. The reference frequency is substituted into the formula to calculate the chip's control word. After the calculation is completed, the voltage control module continuously changes the output level of the voltage pin, switching between the first and second voltages, until the read / write timing output module writes the entire control word into the chip. The voltage control module then adjusts the chip's pin voltage to the first voltage, controlling the chip to emit the frequency to be measured. The frequency measurement module automatically calculates the part-in-a-million error value and transmits the error value to the PS end.

6. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 5, characterized in that: The frequency metering module uses an equal-precision measurement method to detect the frequency value emitted by the chip. Within the specified time of the gate signal, it measures the signal under test. and reference signal Perform the count and obtain the count value. and The resulting count is proportional to the frequency of the signal being counted. The frequency of the signal under test can be calculated using the following formula. : Error frequency The calculation is as follows: The relative error is: To calculate and write the control word to the chip, the chip's reference frequency value must first be measured. The formula is as follows: The chip's DSM_VALUE is calculated based on the reference frequency value, and the target frequency is finally obtained by writing DSM_VALUE to the chip. .

7. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 1, characterized in that: The firmware program running the FreeRTOS system on the PS side utilizes the multi-boot feature of Xilinx FPGA, which allows the FPGA to load multiple bitstreams from different addresses in the external Flash. The Flash is configured with a Lock program responsible for encryption operations, a main program responsible for decryption operations, and a space to store the ciphertext. The Lock program in Multi-boot uses the device DNA as plaintext and performs DES encryption with a user-defined key, then writes the encrypted ciphertext into flash. The main program then performs a symmetrical mirroring operation, reads the ciphertext from the flash memory, performs DES decryption using a user-defined key, and then restores it to plaintext. The device's DNA is unique to the main program; the program can only be successfully loaded if the program and the FPGA chip match.

8. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 7, characterized in that: In the encryption process, the system is powered on, and the FPGA loads the main program from the Flash. If the main program is successfully loaded, the ciphertext data at the specified location is read from the Flash, and the ciphertext is decrypted using the decryption operation module integrated in the system using DES. After decryption, the obtained plaintext data is compared with the preset content. If the comparison is successful, it means that the data is valid, and the program starts running. If the main program fails to load, the system loads a Lock program that has been pre-written into Flash. The Lock program is responsible for reading the current ZYNQ device DNA, combining it with the DNA, encrypting the application content through the encryption operation module, and finally writing the encrypted data to the specified location in Flash.

9. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 1, characterized in that: The IP core has a protocol extension interface that supports module-level loading and replacement of protocol descriptions based on the Verilog language, making it easy for users to dynamically add or modify protocol logic according to different chip characteristics or new protocol requirements.

10. A chip read / write test and control system based on ZYNQ supporting multiple protocols as described in claim 1, characterized in that: The system adopts a main card and daughter card separable architecture, and sets up separate chip adapters for supported protocols. The adapter of the OTP chip is equipped with a level conversion circuit, and its output voltage is controlled by the voltage control module of the PL end.

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