Cache fault processing method and device, processor, electronic equipment and storage medium

Abstract

The invention provides a cache fault processing method and device, a processor, electronic equipment and a storage medium, and relates to the technical field of caches. The method is applied to a processor, and a Cache in the processor comprises a plurality of main cache lines and a plurality of standby cache lines. State storage units are arranged at the heads of the main cache lines and the standby cache lines; a status bit is stored in the status storage unit, and the status bit is used for representing whether the cache line is in use or not; the method comprises the following steps: determining a fault type under the condition that any primary cache line is detected to have a fault; under the condition that the fault type is an uncorrectable error or under the condition that the fault type is a correctable error and the fault frequency reaches a preset threshold value, determining a target cache line from available standby cache lines; setting the status bit of the fault cache line to be unused; and setting the status bit of the target cache line to be in use and deleting the target cache line from the available standby cache lines. The reliability of the processor is improved.

Description

Technical Field

[0001] This application relates to the field of caching technology, and in particular to a cache fault handling method, apparatus, processor, electronic device and storage medium. Background Technology

[0002] The cache is located within the processor and consists of static random-access memory (SRAM). It has a relatively small capacity but its access speed is faster than main memory, approaching the speed of the processor. Currently, caches can fail during use. For example, a cache line is the basic unit in the cache; a failed cache line can affect the reliability of the processor.

[0003] In related technologies, when one or more cache lines fail, the faulty cache lines can be isolated. However, as the number of faulty cache lines increases, the number of available cache lines in the cache decreases, impacting the processor's storage resources. Summary of the Invention

[0004] This application provides a cache fault handling method, apparatus, processor, electronic device, and storage medium to solve the problem in the related art where cache line faults affect the processor's storage resources.

[0005] In a first aspect, this application provides a cache fault handling method applied to a processor, the processor including a high-speed cache memory (Cache), and the Cache including multiple primary cache lines and multiple spare cache lines; each of the primary cache lines and each of the spare cache lines has a status storage unit at its header; the status storage unit stores a status bit, the status bit being used to indicate whether the cache line is in use;

[0006] The method includes:

[0007] If a failure is detected in any primary cache line, determine the type of failure;

[0008] In the case where the fault type is an uncorrectable error, or in the case where the fault type is a correctable error and the number of faults reaches a preset threshold, the target cache line is determined from the available spare cache lines;

[0009] Set the status bit of the faulty cache line to unused to isolate the faulty cache line;

[0010] Set the status bit of the target cache line to "in use" and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

[0011] In one alternative implementation, determining the target cache line from the available alternative cache lines includes:

[0012] Read the standby resource table to see if there is an identifier for a usable standby cache line;

[0013] If there is an identifier for an available standby cache line in the standby resource table, then the target cache line is determined from the standby resource table;

[0014] or,

[0015] If there are no available backup cache rows in the backup resource table, then the exception will be handled according to the preset exception handling strategy.

[0016] In one alternative implementation, determining the target cache line from the spare resource table includes:

[0017] When the address mapping method of the cache is direct mapping or fully associative mapping, the standby cache line pointed to by the identifier of any standby cache line in the standby resource table is determined as the target cache line;

[0018] When the address mapping method of the cache is group-associative mapping, the spare cache line belonging to the same path as the faulty cache line is queried from the spare resource table, and the spare cache line is determined as the target cache line.

[0019] In one alternative implementation, when the fault type is a correctable error, the method further includes:

[0020] The data stored in the fault cache line is remapped to the target cache line.

[0021] In one alternative implementation, when the fault type is an uncorrectable error, the method further includes:

[0022] When the address mapping method of the Cache is set to group-associative mapping, the status bits of the primary cache lines that belong to the same path as the faulty cache line in the Cache are all set to unused.

[0023] In one alternative implementation, determining the fault type upon detecting a fault in any primary cache line includes:

[0024] If a fault is detected in any primary cache line, the latest recorded fault information is read from the register;

[0025] The fault information is parsed to obtain the fault type.

[0026] Secondly, this application provides a cache failure handling device, which is disposed in a processor. The processor further includes a cache, and the cache includes multiple primary cache lines and multiple backup cache lines. Each primary cache line and each backup cache line has a status storage unit at its header. The status storage unit stores a status bit, which is used to indicate whether the cache line is in use.

[0027] The cache fault handling device includes a fault reading circuit and a fault handling circuit, wherein the fault handling circuit is connected to the fault reading circuit;

[0028] The fault reading circuit is used to determine the fault type when a fault is detected in any primary cache line;

[0029] The fault handling circuit is used to determine the target cache line from the available spare cache lines when the fault type is an uncorrectable error, or when the fault type is a correctable error and the number of faults reaches a preset threshold.

[0030] The fault handling circuit is further configured to set the status bit of the faulty cache line to unused to isolate the faulty cache line; set the status bit of the target cache line to used, and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

[0031] Thirdly, this application provides a processor, the processor including a cache and a cache fault handling device as described in the second aspect; the cache includes a plurality of primary cache lines and a plurality of backup cache lines; each of the primary cache lines and each of the backup cache lines has a status storage unit in its header; the status storage unit stores status bits, the status bits being used to indicate whether the cache line is in use.

[0032] Fourthly, this application provides an electronic device, including: a processor and a memory communicatively connected to the processor;

[0033] The memory stores computer-executed instructions;

[0034] The processor executes computer execution instructions stored in the memory to implement the cache fault handling method as described in any of the first aspects.

[0035] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the cache fault handling method described in any of the first aspects.

[0036] Sixthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the cache fault handling method described in any of the first aspects.

[0037] The cache failure handling method, apparatus, processor, electronic device, and storage medium provided in this application add multiple spare cache lines to the cache, and each primary cache line and each spare cache line have a status storage unit in the header to store status bits, thereby recording whether the cache line is in use. By setting the status bit of the faulty cache line to unused when a primary cache line failure is detected, the faulty cache line is isolated. By determining the target cache line from the available spare cache lines and setting the status bit of the target cache line to used, the faulty cache line is replaced with a spare cache line, which can effectively isolate the faulty cache line, improve the reliability of the processor, and even if some primary cache lines fail, the spare cache lines can be used for data storage, ensuring that the processor has sufficient storage resources. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] Figure 1 This is a schematic diagram of the structure of a processor provided in this application;

[0040] Figure 2 This is a flowchart illustrating a cache fault handling method provided in this application;

[0041] Figure 3 This is a flowchart illustrating another cache fault handling method provided in this application;

[0042] Figure 4 This is a flowchart illustrating another cache fault handling method provided in this application;

[0043] Figure 5 This is a schematic diagram of the structure of a cache fault handling device provided in this application;

[0044] Figure 6 This is a schematic diagram of another cache fault handling device provided in this application;

[0045] Figure 7 This is a schematic diagram of a cache fault handling process provided in this application;

[0046] Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application.

[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] The cache is located in the processor and consists of static random-access memory (SRAM). It has a relatively small capacity but a faster access speed than main memory, approaching the speed of the processor.

[0050] The basic structure of a cache:

[0051] Block: The smallest unit of storage in the cache, often also called a cache line.

[0052] Set: The cache is divided into multiple sets, each containing a number of blocks.

[0053] Way: The number of blocks in each group is called the way.

[0054] There are several address mapping methods for caches, such as set-associative mapping, direct mapping, and fully associative mapping. Taking set-associative mapping as an example, when accessing the cache, the address information is segmented, and the SET index, TAG, and OFFSET are extracted from the physical address. The SET index is used to find the corresponding cache set. In the found cache set, the TAG field of each cache line is compared to find the matching cache line. The OFFSET is used to locate the specific bytes within the cache line for data read and write.

[0055] Currently, cache failures can occur during use. Upon detecting a cache line failure, fault information is recorded in a fault log register (located inside the processor). This fault information includes the fault location and fault type. The fault location refers to the position of the faulty cache line; the fault type is either an uncorrectable error or a correctable error. For uncorrectable errors, the processor crashes and restarts. For correctable errors, automatic correction and recording are performed. It is evident that a cache line failure impacts processor reliability. Related technologies can isolate faulty cache lines when one or more fail. However, as the number of faulty cache lines increases, the number of available cache lines decreases, impacting the processor's storage resources.

[0056] Based on this, this application proposes a cache fault handling method, apparatus, processor, electronic device and storage medium, aiming to solve the above-mentioned technical problems.

[0057] Figure 1 This is a schematic diagram of the structure of a processor provided in this application. Figure 1 As shown, the processor 10 includes a processor core 11 and a cache 12. The processor core 11 is connected to the cache 12. The cache 12 includes multiple primary cache lines and multiple spare cache lines. Each primary cache line and each spare cache line has a status storage unit at its header. The status storage unit stores status bits, which are used to indicate whether the cache line is in use.

[0058] In one application scenario, processor core 11 is used to isolate and replace faulty cache lines when a fault is detected in any cache line in Cache 12.

[0059] In another application scenario, continuing as... Figure 1 As shown, the processor 10 also includes a cache fault handling device 13, which is connected to the processor core 11 and the cache 12 respectively. The cache fault handling device 13 is used to isolate and replace the faulty cache line when a fault is detected in any cache line in the cache 12.

[0060] In yet another application scenario, continuing as... Figure 1As shown, the processor 10 also includes a management microcontroller 14, which is connected to the processor core 11 and the cache 12. The management microcontroller 14 is used to isolate and replace the faulty cache line when a fault is detected in any cache line in the cache 12. Exemplarily, the management microcontroller 14 is a high-reliability management microcontroller such as a system control processor (SCP) or a system management unit (SMU).

[0061] It should be noted that the processor core 11 or the management microcontroller 14 implements the cache fault handling method provided in this application by executing program code; while the cache fault handling device 13 implements cache fault handling through hardware circuit logic.

[0062] For example, the processor 10 may be a processor such as a central processing unit (CPU), a data processing unit (DPU), or a graphics processing unit (GPU).

[0063] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0064] Figure 2 This is a flowchart illustrating a cache fault handling method provided in this application. The method is applied to a processor, which includes a cache, and the cache includes multiple primary cache lines and multiple spare cache lines. Each primary cache line and each spare cache line has a status storage unit at its header. The status storage unit stores status bits indicating whether the cache line is in use. For example, the status bit is 1 or 0, where 1 indicates use and 0 indicates unused (i.e., idle). Exemplarily, the status storage unit can be any of an electrically erasable programmable read-only memory (E2PROM), random-access memory (RAM), flash memory, or a fuse. E2PROM, flash memory, and fuses all support the function of continuing to function after a power outage and restart, and are therefore preferred.

[0065] For example, the execution subject of this method is Figure 1 The processor core 11 or management microcontroller 14 shown is illustrated. Figure 2 As shown, the cache failure handling method provided in this embodiment includes the following steps:

[0066] Step S101: If a fault is detected in any primary cache line, determine the fault type.

[0067] For example, an interrupt event is triggered when any primary cache line fails, so as to execute the cache fault handling method provided in this application. Alternatively, once any primary cache line fails, fault information is recorded in a register. Correspondingly, the register can be polled to see if new fault information is added. If new fault information is added, the cache fault handling method provided in this application is executed.

[0068] The fault type is either an uncorrectable error or a correctable error.

[0069] Step S102: If the fault type is an uncorrectable error, or if the fault type is a correctable error and the number of faults reaches a preset threshold, determine the target cache line from the available backup cache lines.

[0070] If any primary cache line encounters an uncorrectable error or the number of correctable errors reaches a preset threshold, it indicates that the primary cache line is faulty and unusable. Continued use of such a line could potentially impact processor operation. In this case, the primary cache line can be isolated and replaced to ensure processor reliability. For ease of description, this primary cache line will be referred to as the faulty cache line in the following text.

[0071] The preset threshold can be set according to actual needs, and this embodiment does not limit it. For example, the preset threshold can be 5, 10, or 20.

[0072] In this embodiment, the cache also includes standby cache lines, so a target cache line can be determined from the available standby cache lines, which is a standby cache line used to replace the faulty cache line.

[0073] Step S103: Set the status bit of the fault cache line to unused to isolate the fault cache line.

[0074] In this embodiment, the status bit of each primary cache line is set to "in use" by default, while the status bit of each standby cache line is set to "idle" by default. When any primary cache line fails, the status bit of the failed cache line is set to "unused," thereby isolating the failed cache line.

[0075] Step S104: Set the status bit of the target cache line to "in use" and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

[0076] The replacement of faulty cache lines is achieved by setting the status bit of the target cache line to "in use" and removing the identifier of the target cache line from the standby resource table.

[0077] In this embodiment, multiple spare cache lines are added to the cache, and each primary cache line and each spare cache line has a status storage unit at the header to store status bits, thereby recording whether the cache line is in use. By setting the status bit of the faulty cache line to unused when a primary cache line failure is detected, the faulty cache line is isolated. By determining the target cache line from the available spare cache lines and setting the status bit of the target cache line to used, the faulty cache line is replaced by a spare cache line, which can effectively isolate the faulty cache line, improve the reliability of the processor, and ensure that the processor has sufficient storage resources even if some primary cache lines fail. This method can handle uncorrectable errors and repeated correctable errors, enhance the fault tolerance of the processor, and enable the processor to make corresponding handling in the face of different types of cache failures. By isolating and replacing faulty cache lines in a timely manner, crashes or performance degradation caused by cache failures are avoided, thereby extending the service life of the device.

[0078] In some embodiments, step S101 is implemented by: reading the latest recorded fault information from the register when a fault is detected in any primary cache line; and parsing the fault information to obtain the fault type.

[0079] When a fault occurs in the primary cache line, fault information is recorded in a register. This fault information includes the fault type. Therefore, by reading the latest recorded fault information and parsing it, the fault type can be obtained. The register is located in the processor and is connected to the processor core and the management microcontroller.

[0080] In some embodiments, the standby resource table stores the identifiers and addresses of available standby cache lines. Accordingly, the implementation of determining the target cache line from the available standby cache lines in step S102 includes: reading the identifier of whether an available standby cache line exists in the standby resource table; correspondingly, there are the following two cases:

[0081] In the first case, if there is an identifier for an available alternative cache line in the alternative resource table, then the target cache line is determined from the alternative resource table.

[0082] If the standby resource table contains an identifier for a usable standby cache line, it indicates that a usable standby cache line exists in the cache, and the target cache line can be determined from the standby resource table. This embodiment, by reading the standby resource table, can quickly locate usable standby cache lines, reducing search time and improving fault handling efficiency. Furthermore, the use of the standby resource table ensures orderly management of standby cache lines, avoiding confusion during fault handling and thus improving stability.

[0083] In the second scenario, if there are no available backup cache rows in the backup resource table, the exception will be handled according to the preset exception handling strategy.

[0084] Among them, the preset exception handling strategy can be the handling strategy in related technologies when a cache line fails, such as processor crash and restart.

[0085] In one optional implementation of this embodiment, the method of determining the target cache line from the standby resource table includes the following two cases:

[0086] In the first scenario, if the cache address mapping method is direct mapping or fully associative mapping, the standby cache line pointed to by the identifier of any standby cache line in the standby resource table is determined as the target cache line. In the second scenario, if the cache address mapping method is set-associative mapping, a standby cache line belonging to the same way as the failed cache line is retrieved from the standby resource table, and that standby cache line is determined as the target cache line.

[0087] Specifically, upon detecting a fault in any primary cache line, the latest recorded fault information is read from the register; this fault information is parsed to obtain the fault address, which indicates the location of the faulty cache line. This fault address includes the SET index, TAG, and OFFSET. Based on this fault address, the backup cache line belonging to the same path as the faulty cache line can be determined.

[0088] This method employs different processing strategies based on different address mapping methods in the cache (direct mapping, fully associative mapping, and set-associative mapping), exhibiting strong adaptability and meeting the needs of various cache structures. The first scenario directly selects any spare cache line from the spare resource table as the target cache line, resulting in fast fault handling. The second scenario, by selecting a spare cache line belonging to the same path as the faulty cache line, ensures that the replaced cache line maintains consistency with the original structure, avoiding complex address remapping operations during subsequent cache accesses.

[0089] Figure 3 This is a flowchart illustrating another cache fault handling method provided in this application, such as... Figure 3As shown, this embodiment describes a cache fault handling method for cases where the fault type is an uncorrectable error. The cache fault handling method provided in this embodiment includes the following steps:

[0090] Step S201: If a fault is detected in any primary cache line, determine the fault type.

[0091] Step S202: In the case of an uncorrectable error, read the identifier in the standby resource table to see if there is a usable standby cache line.

[0092] In this embodiment, if there is an identifier for a usable standby cache line in the standby resource table, then steps S203-S204 are executed; if there is no identifier for a usable standby cache line in the standby resource table, then step S205 is executed.

[0093] Step S203: If there is an identifier for an available standby cache line in the standby resource table, then determine the target cache line from the standby resource table.

[0094] Step S204: Isolate the faulty cache line and replace it with the target cache line.

[0095] In this embodiment, the implementation of steps S201-S204 is the same as in the above embodiment, and will not be repeated here.

[0096] Step S205: If there is no identifier for a usable backup cache line in the backup resource table, then perform exception handling according to the preset exception handling strategy.

[0097] Among them, the preset exception handling strategy can be the handling strategy in related technologies when a cache line fails, such as processor crash and restart.

[0098] In some embodiments, when the fault type is an uncorrectable error and there is no identifier for a usable alternative cache line in the alternative resource table, the method provided in this application further includes the following step S206:

[0099] Step S206: When the address mapping method of the Cache is set to group-associative mapping, set the status bits of the primary cache lines in the Cache that belong to the same path as the faulty cache line to unused.

[0100] By setting the status bits of all primary cache lines on the same path to unused, faulty cache lines can be effectively isolated, preventing uncorrectable data errors from propagating to other cache lines, thereby protecting data integrity and consistency. In the event of spare cache line exhaustion, disabling primary cache lines on the same path can prevent processor instability or crashes caused by the inability to replace faulty cache lines, ensuring continuous processor operation.

[0101] Figure 4 This is a flowchart illustrating another cache fault handling method provided in this application, such as... Figure 4 As shown, this embodiment describes a cache fault handling method for cases where the fault type is a correctable error. The cache fault handling method provided in this embodiment includes the following steps:

[0102] Step S301: If a fault is detected in any primary cache line, determine the fault type.

[0103] Step S302: If the fault type is a correctable error and the number of faults reaches a preset threshold, read the identifier of whether there is a usable backup cache line in the backup resource table.

[0104] In this embodiment, if there is an identifier for a usable standby cache line in the standby resource table, then steps S303-S305 are executed; if there is no identifier for a usable standby cache line in the standby resource table, then step S306 is executed.

[0105] Optionally, considering that the preset threshold is a fixed value set by technicians based on experience and may not be accurate enough, the current processing procedure can also report the fault information to the AI ​​management center when the fault type is a correctable error. The AI ​​management center uses this fault information to determine whether to handle the faulty cache line. The AI ​​management center can be located on the local device or on other devices. Accordingly, a fault handling request can be sent to other devices, carrying the fault information, so that other devices can use the AI ​​management center to make decisions on whether to handle the faulty cache line. This fault information includes not only the fault location and fault type, but also the number of correctable errors.

[0106] For example, the decision logic of the AI ​​management center can be as follows: determine whether to handle the faulty cache line based on the fault information, obtain a decision result, and return the decision result to the current processing program. This decision result indicates whether to handle the faulty cache line. If the decision result is to handle the faulty cache line, then the identifier of whether a usable backup cache line exists in the backup resource table is read; if the decision result is not to handle the faulty cache line, then no processing is required, i.e., no further operation is performed. Specifically, after receiving a fault handling request, the AI ​​management center determines the probability that a correctable error will evolve into an uncorrectable error based on the fault information carried in the fault handling request; if the probability is higher than a threshold, the decision result is determined to handle the faulty cache line; if the probability is not higher than the threshold, the decision result is determined not to handle the faulty cache line. This threshold can be set according to actual needs, and this embodiment does not limit it; for example, the threshold can be 50%, 60%, 70%, etc. The AI ​​management center pre-analyzes and extracts fault characteristic information of correctable and uncorrectable errors based on massive amounts of fault handling data, thereby learning the possibility of correctable errors evolving into uncorrectable errors.

[0107] Step S303: If there is an identifier for an available standby cache line in the standby resource table, then determine the target cache line from the standby resource table.

[0108] Step S304: Isolate the faulty cache line and replace it with the target cache line.

[0109] In this embodiment, the implementation of steps S301-S304 is the same as in the above embodiment, and will not be repeated here.

[0110] In some embodiments, when the fault type is a correctable error, after replacing the fault cache line with the target cache line, the following step S305 is further included.

[0111] Step S305: Remap the data stored in the fault cache line to the target cache line.

[0112] By remapping data in a faulty cache line to a target cache line, data integrity and consistency can be guaranteed without loss during replacement. In the event of a correctable error in a faulty cache line, data remapping can effectively recover the data, preventing data corruption from impacting processor operation and improving processor reliability.

[0113] Step S306: If there is no identifier for a usable backup cache line in the backup resource table, then perform exception handling according to the preset exception handling strategy.

[0114] In this embodiment, the implementation of step S306 is the same as that of step S205, and will not be described again here.

[0115] The above Figures 2-4 This application provides an embodiment of cache fault handling implemented in software for a processor core or management microcontroller. It also provides a cache fault handling apparatus, such as... Figure 1 As shown, the cache fault handling device 13 is installed in the processor 10 and can implement cache fault handling in hardware circuit logic.

[0116] Figure 5 This is a schematic diagram of a cache fault handling device provided in this application. In this embodiment, the cache fault handling device 13 is disposed in a processor, and the processor also includes a cache, which includes multiple primary cache lines and multiple spare cache lines. Each primary cache line and each spare cache line has a status storage unit at its header. The status storage unit stores status bits, which are used to indicate whether the cache line is in use. For example, the status bit is 1 or 0, where 1 indicates that it is in use and 0 indicates that it is not in use, i.e., idle. Exemplarily, the status storage unit can be an E2PROM or RAM. E2PROM supports the function of continuing to be effective after power failure and restart, so E2PROM is preferred.

[0117] like Figure 5 As shown, the cache fault handling device 13 includes a fault reading circuit 131 and a fault handling circuit 132, and the fault handling circuit 132 is connected to the fault reading circuit 131.

[0118] The fault reading circuit 131 is used to determine the fault type when a fault is detected in any primary cache line;

[0119] The fault handling circuit 132 is used to determine the target cache line from the available spare cache lines when the fault type is an uncorrectable error, or when the fault type is a correctable error and the number of faults reaches a preset threshold.

[0120] The fault handling circuit 132 is also used to set the status bit of the faulty cache line to unused to isolate the faulty cache line; set the status bit of the target cache line to used, and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

[0121] The fault reading circuit 131 and the fault processing circuit 132 can be implemented by logic circuits.

[0122] In some embodiments, Figure 6 This is a schematic diagram of another cache fault handling device provided in this application, as shown below. Figure 6As shown, the processor 10 also includes a register 15, and the fault reading circuit 131 is connected to the register; the cache fault processing device 13 also includes a fault parsing circuit 133, which is connected to the fault reading circuit 131 and the fault processing circuit 132 respectively.

[0123] Register 15 is used to store fault information; correspondingly, fault reading circuit 131 is specifically used to read the latest recorded fault information from register 15 when a fault is detected in any primary cache line; fault parsing circuit 132 is used to parse the fault information to obtain the fault type.

[0124] Specifically, the fault analysis circuit 132 includes an information acquisition interface, a fault analysis unit, and an analysis output interface, which are connected in sequence. The information acquisition interface is used to receive fault information sent by the fault reading circuit 131, and the fault analysis unit is used to analyze the fault information according to preset fault characteristics. After the analysis is completed, the fault type is obtained, and the fault type is output to the fault processing circuit 132 through the analysis output interface.

[0125] Once a fault occurs in the primary cache line, the fault information is recorded in register 15. The fault information includes the fault type. Therefore, by reading the latest recorded fault information and parsing it, the fault type can be obtained.

[0126] In some embodiments, such as Figure 6 As shown, the cache fault handling device 13 also includes a fault detection circuit 134; the fault detection circuit 134 is connected to the register 15 and the fault reading circuit 131 respectively; the fault detection circuit 134 is also connected to the processor core 11.

[0127] The processor core 11 is used to trigger an interrupt signal when a fault occurs in any main cache line; the fault detection circuit 134 is used to send a read signal to the fault read circuit 131 when it detects the interrupt signal triggered by the processor core 11; or, the fault detection circuit 134 is used to periodically detect whether new fault information has been added to the register 15, and when it detects that new fault information has been added to the register 15, it sends a read signal to the fault read circuit 131; accordingly, the fault read circuit 131 is specifically used to read the latest recorded fault information from the register 15 when it receives the read signal.

[0128] Specifically, the fault reading circuit 131 includes a notification interface, a register reading interface, and a fault information recording unit, which are connected sequentially. The notification interface receives a reading signal from the fault detection circuit 134, the register reading interface reads the latest recorded fault information from register 15, and the fault information recording unit records the read fault information and sends it to the fault analysis circuit 132.

[0129] Specifically, the fault detection circuit 134 includes a detection interface, a detection processing unit, and a notification interface, which are connected sequentially. The detection interface is used to receive interrupt signals, and the detection processing unit is used to send a read signal to the fault reading circuit 134 via the notification interface when an interrupt signal is received.

[0130] Alternatively, the fault detection circuit 134 may also include an internal timer. Accordingly, the detection interface is used to periodically detect whether new fault information has been added to the register 15 according to the periodic signal output by the internal timer. The detection processing unit is used to send a read signal to the fault reading circuit 134 through the notification interface when new fault information is detected in the register 15.

[0131] In some embodiments, such as Figure 6 As shown, the cache fault handling device 13 also includes a storage unit 135, which is connected to the fault handling circuit 132. Exemplarily, the storage unit 135 can be any type of memory.

[0132] Storage unit 135 is used to store a spare resource table; the spare resource table stores the identifiers and addresses of available spare cache lines. Accordingly, fault handling circuit 132 is specifically used to read from storage unit 135 whether there is an identifier of an available spare cache line in the spare resource table; if there is an identifier of an available spare cache line in the spare resource table, the target cache line is determined from the spare resource table.

[0133] If the standby resource table contains an identifier for a usable standby cache line, it indicates that a usable standby cache line exists in the cache, and the target cache line can be determined from the standby resource table. This embodiment, by reading the standby resource table, can quickly locate usable standby cache lines, reducing search time and improving fault handling efficiency. Furthermore, the use of the standby resource table ensures orderly management of standby cache lines, avoiding confusion during fault handling and thus improving stability.

[0134] In some embodiments, the fault handling circuit 132 is specifically used for:

[0135] When the address mapping method of the cache is direct mapping or fully associative mapping, the standby cache line pointed to by the identifier of any standby cache line in the standby resource table is determined as the target cache line;

[0136] When the address mapping method of the cache is set-associative mapping, the standby cache line belonging to the same path as the faulty cache line is queried from the standby resource table, and the standby cache line is determined as the target cache line.

[0137] Specifically, the fault reading circuit 131 reads the latest recorded fault information from register 15; the fault parsing circuit 133 parses the fault information to obtain the fault address; the fault address is used to indicate the location of the fault cache line, and the fault address includes SET index, TAG, and OFFSET. Thus, the fault handling circuit 132 can determine the spare cache line belonging to the same path as the fault cache line based on the fault address.

[0138] This embodiment employs different processing strategies based on different address mapping methods of the cache (direct mapping, fully associative mapping, and set-associative mapping), demonstrating strong adaptability and the ability to meet the needs of various cache structures. The first scenario directly selects any spare cache line from the spare resource table as the target cache line, resulting in fast fault handling. The second scenario selects a spare cache line belonging to the same path as the faulty cache line, ensuring that the replaced cache line maintains consistency with the original structure and avoiding complex address remapping operations during subsequent cache accesses.

[0139] In some embodiments, after replacing the fault cache line with the target cache line, the fault handling circuit 132 is further configured to: remap the data stored in the fault cache line to the target cache line if the fault type is a correctable error.

[0140] By remapping data in a faulty cache line to a target cache line, data integrity and consistency can be guaranteed without loss during replacement. In the event of a correctable error in a faulty cache line, data remapping can effectively recover the data, preventing data corruption from impacting processor operation and improving processor reliability.

[0141] In some embodiments, after isolating and replacing the faulty cache line, the fault handling circuit 132 is further configured to: report processing information to the processor core 11; the processing information includes the identifier of the faulty cache line and the identifier of the target cache line.

[0142] Reporting processing information to processor core 11 makes the cache fault handling process more transparent, facilitating monitoring and management. The processing information includes identifiers for the faulty cache line and the target cache line, which helps in tracing and analyzing faults, identifying their causes, developing corresponding improvement measures, and enhancing reliability.

[0143] In some embodiments, the fault handling circuit 132 is further configured to: if there is no available spare cache line in the spare resource table, report a fault handling instruction to the processor core 11 so that the processor core 11 performs exception handling according to a preset exception handling strategy. Accordingly, the processor core 11 is configured to receive the fault handling instruction reported by the cache fault handling device 13 and perform exception handling according to the preset exception handling strategy; the fault handling instruction is reported by the fault handling circuit 132 in the cache fault handling device 13 when it detects that any primary cache line has failed and there is no available spare cache line.

[0144] Among them, the preset exception handling strategy can be the handling strategy in related technologies when a cache line fails, such as processor crash and restart.

[0145] In some embodiments, the fault handling circuit 132 is further configured to: if there is no available spare cache line in the spare resource table, then in the case of an uncorrectable error and the address mapping method of the Cache is group-associative mapping, set the status bits of all primary cache lines belonging to the same path in the Cache to unused.

[0146] By setting the status bits of all primary cache lines on the same path to unused, faulty cache lines can be effectively isolated, preventing uncorrectable data errors from propagating to other cache lines, thereby protecting data integrity and consistency. In the event of spare cache line exhaustion, disabling primary cache lines on the same path can prevent processor instability or crashes caused by the inability to replace faulty cache lines, ensuring continuous processor operation.

[0147] Figure 7 This is a schematic diagram of a cache fault handling process provided in this application. See [link / reference]. Figure 7Cache 12 uses set-associative address mapping. Cache 12 includes multiple primary cache lines and multiple spare cache lines; for example, SET0-SET3 are primary cache lines, and SET16384-SET16385 are spare cache lines. Each cache line has a status storage unit at its header, storing status bits represented by 0 or 1 (1 indicates use, 0 indicates unused, i.e., idle). The cache line located at "SET0, WAY32" is a faulty cache line with a status bit of 0, and has been replaced by a spare cache line located at "SET16385, WAY32" with a status bit of 1. The cache fault handling device 13 stores a spare resource table in its storage unit 135 and can read fault information from register 15 to handle faulty cache lines in Cache 12. When accessing Cache12, the access address includes SET index, TAG, and OFFSET. SET index is used to find the corresponding Cache set (SET0). In the found Cache set, the TAG field of each cache line is compared to find the matching cache line. OFFSET is used to locate the specific bytes inside the cache line for data reading and writing.

[0148] This application also provides an electronic device. Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application. For example... Figure 8 As shown, the electronic device 40 includes a processor 401 and a memory 402 communicatively connected to the processor 401.

[0149] The memory 402 stores computer-executable instructions; the processor 401 executes the computer-executable instructions stored in the memory 402 to implement the cache fault handling method provided in this application.

[0150] In this embodiment, the memory 402 and the processor 401 are connected via a bus. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, a Double Data Rate (DDR) memory bus, a Serializer / DeSerializer (SerDes) bus, etc. The bus can be categorized as an address bus, a data bus, a control bus, etc.

[0151] The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein. The various components are interconnected via different buses and can be mounted on a common motherboard, packaged within a chip, or otherwise installed as needed.

[0152] In an exemplary embodiment, a computer-readable storage medium is also provided, which stores computer-executable instructions that, when executed by a processor, are used to implement the cache fault handling method provided in this application.

[0153] In an exemplary embodiment, a computer program product is also provided, including a computer program, which, when executed by a processor, is used to implement the cache fault handling method provided in this application.

[0154] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0155] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A cache fault handling method, characterized in that, The processor includes a cache memory, and the cache includes multiple primary cache lines and multiple backup cache lines; each primary cache line and each backup cache line has a state storage unit at its header. The state storage unit stores a state bit, which is used to indicate whether the cache line is in use; The method includes: If a failure is detected in any primary cache line, determine the type of failure; In the case where the fault type is an uncorrectable error, or in the case where the fault type is a correctable error and the number of faults reaches a preset threshold, the target cache line is determined from the available spare cache lines; Set the status bit of the faulty cache line to unused to isolate the faulty cache line; Set the status bit of the target cache line to "in use" and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

2. The method according to claim 1, characterized in that, Determining the target cache line from the available alternative cache lines includes: Read the standby resource table to see if there is an identifier for a usable standby cache line; If there is an identifier for an available standby cache line in the standby resource table, then the target cache line is determined from the standby resource table; or, If there are no available backup cache rows in the backup resource table, then the exception will be handled according to the preset exception handling strategy.

3. The method according to claim 2, characterized in that, Determining the target cache line from the spare resource table includes: When the address mapping method of the cache is direct mapping or fully associative mapping, the standby cache line pointed to by the identifier of any standby cache line in the standby resource table is determined as the target cache line; When the address mapping method of the cache is group-associative mapping, the spare cache line belonging to the same path as the faulty cache line is queried from the spare resource table, and the spare cache line is determined as the target cache line.

4. The method according to claim 1, characterized in that, In the case where the fault type is a correctable error, the following is also included: The data stored in the fault cache line is remapped to the target cache line.

5. The method according to claim 1, characterized in that, In the case where the fault type is an uncorrectable error, the following is also included: When the address mapping method of the Cache is set to group-associative mapping, the status bits of the primary cache lines that belong to the same path as the faulty cache line in the Cache are all set to unused.

6. The method according to claim 1, characterized in that, The step of determining the fault type when a fault is detected in any primary cache line includes: If a fault is detected in any primary cache line, the latest recorded fault information is read from the register; The fault information is parsed to obtain the fault type.

7. A cache fault handling device, characterized in that, The cache fault handling device is disposed in the processor, the processor further includes a cache, and the cache includes multiple primary cache lines and multiple backup cache lines, and each of the primary cache lines and each of the backup cache lines is provided with a state storage unit at the head. The state storage unit stores a state bit, which is used to indicate whether the cache line is in use; The cache fault handling device includes a fault reading circuit and a fault handling circuit, wherein the fault handling circuit is connected to the fault reading circuit; The fault reading circuit is used to determine the fault type when a fault is detected in any primary cache line; The fault handling circuit is used to determine the target cache line from the available backup cache lines when the fault type is an uncorrectable error, or when the fault type is a correctable error and the number of faults reaches a preset threshold. The fault handling circuit is further configured to set the status bit of the faulty cache line to unused to isolate the faulty cache line; set the status bit of the target cache line to used, and delete the target cache line from the available spare cache lines to replace the faulty cache line with the target cache line.

8. A processor, characterized in that, The processor includes a cache and a cache fault handling device as described in claim 7; the cache includes multiple primary cache lines and multiple backup cache lines; each primary cache line and each backup cache line has a status storage unit at its header; the status storage unit stores status bits, which are used to indicate whether the cache line is in use.

9. An electronic device, characterized in that, include: A processor and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

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