Time sequence verification method and device of three-dimensional integrated circuit and electronic equipment

Abstract

The embodiment of the invention discloses a time sequence verification method and device of a three-dimensional integrated circuit and electronic equipment. According to the embodiment of the invention, after a data transmitting end and a data receiving end of each to-be-tested circuit in a three-dimensional integrated circuit set are determined as data transmission modules, an actual test result of each data transmission module is obtained, and a transmitting jitter parameter and a receiving jitter parameter of each data transmission module are determined according to each actual test result; and generating a simulation test result of the three-dimensional integrated circuit set according to the transmitting jitter parameter and the receiving jitter parameter, and determining a time sequence table of the three-dimensional integrated circuit set according to the test result. According to the embodiment of the invention, the process corner combination of each module is estimated according to the real test result of part of the integrated circuits in the three-dimensional integrated circuit set, and then the test of the three-dimensional integrated circuit set is realized according to the simulation test result similar to the real test result, so that the test of the three-dimensional integrated circuit can be realized with relatively high accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a timing verification method, apparatus, and electronic device for three-dimensional integrated circuits. Background Technology

[0002] Timing margin analysis is one of the core technologies in the chip design, verification, and testing phases. Its purpose is to evaluate whether the internal signal transmission timing of the chip meets the design requirements. Timing margin analysis is usually implemented using techniques such as Statistical Margin Verification (SMV). However, 3D integrated circuits (3DICs) lack 2D Shmoo circuit design, making it difficult to obtain timing tables through conventional timing margin analysis techniques. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a timing verification method, apparatus, and electronic device for three-dimensional integrated circuits, which estimates the process corner combination of each module through the actual test results of some integrated circuits in a three-dimensional integrated circuit assembly, and then performs testing of the three-dimensional integrated circuit assembly based on simulation test results that are close to the actual test results, thereby achieving testing of three-dimensional integrated circuits with high accuracy.

[0004] In a first aspect, embodiments of the present invention provide a timing verification method for a three-dimensional integrated circuit, the method comprising: The data transmission module of each circuit under test in the integrated circuit set is determined. The data transmission module includes a data transmitter and a data receiver. Each circuit under test is a three-dimensional integrated circuit with the same hardware structure. Each of the data transmission modules is tested, and the actual test results of each data transmission module are obtained. The actual test results are used to characterize whether the number of bit errors of each data transmission module meets the preset bit error count condition when transmitting data at each data transmission rate. The transmit jitter parameters and receive jitter parameters of each data transmission module are determined based on the actual test results. The transmit jitter parameters include at least one of the jitter mean and jitter standard deviation of the data transmitter at each process angle. The receive jitter parameters include at least one of the jitter mean and jitter standard deviation of the data receiver at each process angle. The simulation test results of the integrated circuit set are generated based on the transmit jitter parameters and receive jitter parameters. The simulation test results are used to characterize whether the data transmitter and data receiver of each integrated circuit in the integrated circuit set meet the timing constraints when transmitting data at each data transmission rate. The timing table of the integrated circuit assembly is determined based on the simulation test results. The timing table includes the data transmission pass rate of the data transmitter and the data receiver of each process corner combination at each data transmission rate.

[0005] Optionally, determining the transmit jitter parameters and receive jitter parameters of each data transmission module based on the actual test results includes: Obtain the probability distribution of the process corner combinations corresponding to the integrated circuit set; Based on the probability distribution, the transmit jitter parameter and the receive jitter parameter are determined by maximizing the likelihood of each actual test result.

[0006] Optionally, generating the simulation test results of the integrated circuit assembly based on the transmit jitter parameters and receive jitter parameters includes: Test data for each integrated circuit is generated based on a preset statistical algorithm, the transmit jitter parameters, and the receive jitter parameters. The test data includes the process corner combination of the data transmitter and the data receiver, the transmit jitter value of the data transmitter, and the receive jitter value of the data receiver. The simulation test results are determined based on the test data and the bit period corresponding to each data transmission rate.

[0007] Optionally, the bit period is the reciprocal of the data transmission rate; Determining the simulation test results based on the bit periods corresponding to each of the test data and each of the data transmission rates includes: The system delay of the corresponding data transmitter and data receiver is determined based on the test data. The simulation test results are determined based on the system delay and each bit period.

[0008] Optionally, determining the timing table of the integrated circuit assembly based on the simulation test results includes: The simulation test results are divided into multiple test result groups according to the process angle combination and the data transmission rate; The pass rate corresponding to each test result group is determined based on the number of successful simulation test results in each test result group and the total number of simulation test results; The timing table is determined based on the respective pass rates.

[0009] Optionally, the transmit jitter parameters and the receive jitter parameters follow a normal distribution.

[0010] Secondly, embodiments of the present invention provide a timing verification apparatus for a three-dimensional integrated circuit, the apparatus comprising: A transmission module determination unit is used to determine the data transmission module of each circuit under test in the integrated circuit set. The data transmission module includes a data transmitter and a data receiver. Each circuit under test is a three-dimensional integrated circuit with the same hardware structure. The first test unit is used to test each of the data transmission modules and obtain the actual test results of each of the data transmission modules. The actual test results are used to characterize whether the number of bit errors of each of the data transmission modules meets the preset bit error number condition when transmitting data at each data transmission rate. The parameter determination unit is used to determine the transmit jitter parameters and receive jitter parameters of each of the data transmission modules based on the actual test results. The transmit jitter parameters include at least one of the jitter mean and jitter standard deviation of the data transmitter at each process angle. The receive jitter parameters include at least one of the jitter mean and jitter standard deviation of the data receiver at each process angle. The second test unit is used to generate simulation test results of the integrated circuit set based on the transmit jitter parameters and receive jitter parameters. The simulation test results are used to characterize whether the data transmitter and data receiver of each integrated circuit in the integrated circuit set meet the timing constraints when transmitting data at each data transmission rate. The result determination unit is used to determine the timing table of the integrated circuit assembly based on the simulation test results. The timing table includes the data transmission rate of the data transmitter and the data receiver of each process corner combination at each data transmission rate.

[0011] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of the first aspects.

[0012] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any one of the first aspects.

[0013] Fifthly, embodiments of the present invention provide a computer program product, the computer program product including a computer program / instruction, which, when executed by a processor, implements the method as described in any one of the first aspects.

[0014] In this embodiment of the invention, after identifying the data transmitter and data receiver of each circuit under test in a three-dimensional integrated circuit assembly as data transmission modules, the actual test results of each data transmission module are obtained. Based on these actual test results, the transmit jitter parameters and receive jitter parameters of each data transmission module are determined. Then, simulation test results of the three-dimensional integrated circuit assembly are generated based on these parameters, thereby determining the timing table of the three-dimensional integrated circuit assembly. This embodiment of the invention estimates the process corner combinations of each module using the actual test results of some integrated circuits in the three-dimensional integrated circuit assembly, and then performs testing of the three-dimensional integrated circuit assembly based on simulation test results that are close to the actual test results. Therefore, it can achieve three-dimensional integrated circuit testing with high accuracy. Attached Figure Description

[0015] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the actual test results of the data transmission module in an embodiment of the present invention; Figure 3 This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of test data from the data transmission module of an embodiment of the present invention; Figure 5 This is a schematic diagram of the simulation test results of the data transmission module according to an embodiment of the present invention; Figure 6 This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the actual test results of the data transmission module in an embodiment of the present invention; Figure 8 This is a schematic diagram of a timing verification device for a three-dimensional integrated circuit according to an embodiment of the present invention; Figure 9 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0016] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0017] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0018] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0019] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0021] 3D integrated circuits are integrated circuits implemented based on 3D Interconnect for Integration and Optimization (3D Interconnect for Integration and Optimization) technology. This technology utilizes vertical interconnect technologies such as through-silicon vias (TSVs) and microbumps to stack logic chips, memory chips, and RF chips in layers, forming a three-dimensional structure. It supports the mixed stacking of chips with different process nodes, materials, and functions, while shortening the vertical interconnect path to the micrometer level. Therefore, compared to traditional planar packaging, 3D Interconnect for Integration and Optimization technology can effectively reduce chip package area, improve chip stacking flexibility, reduce signal latency, increase bandwidth, reduce signal transmission loss, and reduce chip power consumption.

[0022] However, 3D integrated circuit design lacks timing test circuits (Shmoo circuits). Therefore, during chip testing, only Boolean results (i.e., pass / fail binary test results) can be obtained for the 3D integrated circuit, and the continuous distribution of parameters such as delay and jitter cannot be obtained. System margin verification relies on the continuous distribution of parameters such as delay and jitter of the 3D integrated circuit to quantify its timing margin. Therefore, under these circumstances, it is difficult to generate a timing table for the 3D integrated circuit as a timing margin analysis result through system margin verification.

[0023] To address the aforementioned issues, this invention proposes a timing verification method, apparatus, and electronic device for three-dimensional integrated circuits. This method estimates the process corner combinations of each module based on actual test results of some integrated circuits within a three-dimensional integrated circuit assembly. Then, it performs testing on the three-dimensional integrated circuit assembly based on simulation test results that closely approximate the actual test results, thereby achieving high accuracy in testing the three-dimensional integrated circuits.

[0024] The following describes the method through examples. Figure 1 This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention. Figure 1 As shown, the method in this embodiment may include the following steps: Step S100: Determine the data transmission module of each circuit to be tested in the integrated circuit set.

[0025] In the actual manufacturing process of 3D integrated circuits, 3D integrated circuits in the same batch often have the same hardware structure. However, due to factors such as fluctuations in manufacturing processes, there may be certain non-structural differences between 3D integrated circuits, such as differences in transistor parameters and interconnect delays. Therefore, in this embodiment, 3D integrated circuits in the same batch can be defined as an integrated circuit set, or multiple 3D integrated circuits with the same hardware structure can be defined as an integrated circuit set according to actual settings. This embodiment does not impose any restrictions on this.

[0026] The integrated circuit set can include a large number of three-dimensional integrated circuits. Therefore, in the actual testing process, a certain number of three-dimensional integrated circuits can be randomly selected from the integrated circuit set as the circuit to be tested, or all integrated circuits in the integrated circuit set can be determined as the circuit to be tested. Generally, the more circuits to be tested, the higher the accuracy of the test results, but the lower the test efficiency. Therefore, in this embodiment, the number of circuits to be tested can be set according to actual needs, and this embodiment does not impose any restrictions on this.

[0027] The structure of 3D integrated circuits is complex. When testing 3D integrated circuits, different data transmitters (TX) and data receivers (RX) will produce different simulation test results. Therefore, it is necessary to determine the data transmitter and data receiver as data transmission modules in the 3D integrated circuit. The data transmitter and data receiver can be determined according to the actual hardware structure of the 3D integrated circuit, and this embodiment does not impose any restrictions on this.

[0028] Step S200: Test each data transmission module and obtain the actual test results of each data transmission module.

[0029] In this step, the data transmission modules can be tested by the data transmitter sending predefined test sequences to the data receiver at various data transmission rates, yielding Boolean results for each module. The predefined test sequences are known data sequences, specifically pseudo-random binary sequences (PRBS), incrementing sequences (such as 0x0001 / 0x0002), etc. Specifically, the data receiver can integrate a bit error detector, which stores the predefined test sequences. Therefore, after receiving the data sequence from the data transmitter, the data receiver provides it to the bit error detector, which then compares the predefined test sequences with the received data sequence. For each mismatched bit detected, the bit error count is incremented.

[0030] After testing each data transmission module, the number of bit errors for each module at each data transmission rate can be determined by reading the bit error counter. It can then be determined whether the number of bit errors for each module at each data transmission rate meets the preset bit error count condition. For any given data transmission module, if the number of bit errors meets the bit error count condition, the actual test result for that module at the corresponding data transmission rate is considered passed; otherwise, it is considered a failure.

[0031] In this embodiment, the error rate condition can be set according to actual needs, for example, the error rate can be set to be less than or equal to a preset threshold. Furthermore, the preset threshold can be determined based on the product of the test duration of the data transmission module or the amount of data transmitted by the data transmitter and a preset ratio.

[0032] Figure 2 This is a schematic diagram illustrating the actual test results of the data transmission module according to an embodiment of the present invention. For example... Figure 2As shown, the row header of List 20 indicates the data transmission rate of the data transmission module, in Gbps (bit rate), including 1.00, 1.20, 1.40, 1.60, 1.80, 2.00, 2.20, 2.40, 2.60, 2.80, 3.00, and 3.20. The list header of List 20 indicates the module identifier of the data transmission module, namely module 201-module 212. The values ​​are Boolean results when the data transmission module transmits data at different data transmission rates. Taking the Boolean results of some data transmission modules as an example, module 201 has a pass Boolean result at data transmission rates of 1.00Gbps and 1.20Gbps, but a failure Boolean result when transmitting data at data transmission rates of 1.40Gbps and higher. Module 204 has a pass Boolean result when transmitting data at data transmission rates from 1.00Gbps to 3.20Gbps.

[0033] The higher the data transmission rate, the higher the probability of bit errors generated by the data transmission module. In other words, for any data transmission module, if the number of bit errors when outputting data at any data transmission rate does not meet the preset bit error count condition, then the number of bit errors when transmitting data at other data transmission rates higher than that rate will also fail to meet the preset bit error count condition. Therefore, optionally, to improve the testing efficiency of the data transmission module, if the actual test result of any data transmission module at any data transmission rate is determined to be a failure, then the actual test results of the data transmission module at other data transmission rates higher than that rate can be directly determined to be failures.

[0034] For example, if the actual test result of the data transmission module S1 at a bit rate of 1.40G is determined to be a failure, the actual test result of the data transmission module S1 at other data transmission rates higher than 1.40G, such as 1.60G or 1.80G, can be directly determined to be a failure.

[0035] Step S300: Determine the transmit jitter parameters and receive jitter parameters of each data transmission module based on the actual test results.

[0036] Timing jitter at the data transmitter and receiver of the data transmission module is a direct factor determining the Boolean result. The timing jitter at the data transmitter is determined by its process corner, and the timing jitter at the data receiver is also determined by its process corner. Therefore, in this step, the transmit jitter parameters and receive jitter parameters of each data transmission module can be determined based on the actual test results of each module. In this embodiment, the transmit jitter parameters of the data transmission module include at least one of the mean jitter and standard deviation of the jitter at each process corner, and the receive jitter parameters include at least one of the mean jitter and standard deviation of the jitter at each process corner.

[0037] The manufacturing process of 3D integrated circuits is complex, making it difficult to directly measure the process corners of the data transmitter and receiver using methods such as wafer testing. However, it is possible to determine the possible combinations of process corners for the data transmitter and receiver, as well as the probability distribution of each combination. In one possible scenario, both the process corners of the data transmitter and receiver can be of three types: SS (Slow-Slow), FF (Fast-Fast), and TT (Typical-Typical). Therefore, the combinations of process corners for the data transmitter and receiver can include nine possible combinations: data transmitter and data receiver are both SS, data transmitter and data receiver are both TT, data transmitter and data receiver are both FF, data transmitter and data receiver are both FF, data transmitter and data receiver are both SS, data transmitter and data receiver are both TT, data transmitter and data receiver are both SS, data transmitter and data receiver are both FF, data transmitter and data receiver are both TT, data transmitter and data receiver are both SS, and data transmitter and data receiver are both TT.

[0038] In practical applications, the transmit jitter parameters and receive jitter parameters of the data transmission module each follow independent normal distributions. Therefore, the transmit and receive jitter parameters of each data transmission module can be determined by maximizing the likelihood estimation of each actual test result based on the probability distribution (i.e., prior probability) of the combination of process corners at the data transmitter and receiver. Specifically, the probability distribution function of the transmit jitter parameter can be expressed by the following formula: ; in, This represents the jitter value at the data transmitter of the i-th data transmission module. This represents the average jitter value at the data transmitter of the data transmission module at process angle c. This represents the standard deviation of jitter at the data transmitter of the data transmission module under process angle c.

[0039] The probability distribution function of the received jitter parameter can be expressed by the following formula: ; in, This represents the jitter value at the data receiver of the i-th data transmission module. This indicates that the data receiving end of the data transmission module is at the process corner. The average jitter below, This indicates that the data receiving end of the data transmission module is at the process corner. The standard deviation of the jitter.

[0040] The Boolean result of the data transmission module can also indicate whether the system latency of the data transmission module is less than the bit period corresponding to the data transmission rate. If so, the Boolean result is "pass"; otherwise, it is "fail." This constrains the actual jitter of the data transmission module within a specific latency range. This latency range is the range between the bit period corresponding to the minimum data transmission rate where the Boolean result is "fail" and the bit period corresponding to the maximum data transmission rate where the Boolean result is "pass." The bit period corresponding to the data transmission rate can be determined based on the reciprocal of the data transmission rate.

[0041] by Figure 2 Taking the schematic diagram as an example, the Boolean result of module 202 indicates that the data transmission rate is between 1.00Gbps and 3.00Gbps when the data transmission rate is passed, and the Boolean result indicates that the data transmission rate is failed, which is 3.20Gbps. Here, 3.00Gbps is the maximum data transmission rate when the Boolean result of module 202 is passed, and 3.20Gbps is the minimum data transmission rate when the Boolean result of module 202 is failed. Therefore, the actual jitter of module 202 is constrained to be between the bit period corresponding to 3.20Gbps and the bit period corresponding to 3.20Gbps.

[0042] Therefore, optionally, when maximizing the likelihood estimation of each actual test result, the delay interval corresponding to each data transmission module can be determined based on the actual test results of each data transmission module. Then, a log-likelihood function can be established based on the probability distribution of the delay interval of each data transmission module and the combination of process angles at the data transmitter and receiver. Specifically, the log-likelihood function can be expressed by the following formula: ; in, This indicates the transmit jitter parameters and receive jitter parameters of the data transmission module. This represents the total number of actual test results. This indicates the process angle at the data transmitting end. Indicates the process angle at the data receiving end. Indicates possible combinations of process angles, This represents the probability distribution of the process angle combinations at the data transmitter and data receiver. Indicates the combination of process corners and parameters Below, the system latency of the data transmission module Falling into the delay interval The probability of.

[0043] The actual process corner combinations for data transmission modules are difficult to determine directly. Therefore, the mean and standard deviation of each data transmission module can be estimated using the Expectation-Maximization (EM) algorithm. The EM algorithm alternates between the expectation step (E-step) and the maximization step (M-step) until the log-likelihood function converges. The expectation step is used to calculate the mean and standard deviation of each data transmission module at the current parameter estimate. Belongs to a certain process angle combination The posterior probability can be normalized to make the sum of the probabilities of all process corner combinations equal to 1 when calculating the posterior probability. The posterior probability can be expressed by the following formula: ; in, Indicates a specific combination of process angles and current parameter estimation Below, the system latency of the data transmission module falls within the latency range. The probability of.

[0044] Maximize the step to find new To maximize the log-likelihood of the expected complete data. In calculating the new... In such cases, a numerical optimizer can be used, such as the Limited-memory-BFGS-Bound-constrained optimization algorithm (L-BFGS-B), which achieves this by minimizing the expected value of the negative log-likelihood function.

[0045] Among them, parameter estimation This can be expressed by the following formula: ; in, Indicates the current parameter estimation Below, the expected value of the log-likelihood function.

[0046] Step S400: Generate simulation test results of the integrated circuit assembly based on the transmit jitter parameters and receive jitter parameters.

[0047] After determining the transmit and receive jitter parameters of the data transmission module, the test results of the integrated circuit assembly can be simulated based on these parameters to determine whether the data transmitters and receivers of each integrated circuit meet timing constraints at various data transmission rates. Optionally, to improve the accuracy of the data transmission pass rate of the data transmitters and receivers at various data transmission rates for each process corner combination in the timing table, the number of simulated test results can be much larger than the number of actual test results; for example, the number of simulated test results can be 100 times the number of actual test results.

[0048] Figure 3 This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention. Figure 3 As shown, in an optional implementation of this embodiment, step S400 may include the following steps: Step S410: Generate test data for each integrated circuit based on a preset statistical algorithm, transmit jitter parameters, and receive jitter parameters.

[0049] In this step, test data for each integrated circuit can be generated based on preset statistical algorithms, such as Monte Carlo simulation algorithm and semi-analytical method (SMV, Statistical Moment-based Variability Analysis), including the process corner combination of the data transmitter and data receiver, the transmit jitter value of the data transmitter, and the receive jitter value of the data receiver.

[0050] Optionally, in order to make the simulated test data closer to the real test data, this step can also combine the probability distribution of the process corner combinations corresponding to the integrated circuit set to generate the test data of each integrated circuit, so that the process corner combinations of each integrated circuit conform to the probability distribution of the process corner combinations corresponding to the integrated circuit set.

[0051] Figure 4 This is a schematic diagram of test data from the data transmission module of an embodiment of the present invention. For example... Figure 4 As shown, the row headers of List 40 represent the process angles of the data transmitter and receiver of the data transmission module, the transmit jitter value of the data transmitter, and the receive jitter value of the data receiver, respectively; the column headers represent the module identifiers of the data transmission modules, namely modules 401-407. Taking the test data of some data transmission modules as an example, the process angle combination of module 401 is SS for the transmitter and TT for the receiver, with a transmit jitter value of 251 and a receive jitter value of 250; the process angle combination of module 402 is SS for the transmitter and FF for the receiver, with a transmit jitter value of 238 and a receive jitter value of 199.

[0052] Step S420: Determine the simulation test results based on each test data and the bit period corresponding to each data transmission rate.

[0053] After determining the test data for each integrated circuit, the system delay of each integrated circuit can be determined based on the test data. The system delay is the sum of the transmit jitter and receive jitter values ​​of each integrated circuit.

[0054] In this optional implementation, whether the data transmitter and receiver of each integrated circuit meet the timing constraints when transmitting data at each data transmission rate can be specifically expressed as: whether the system delay of the data transmission module of each integrated circuit is less than the bit period corresponding to each data transmission rate. For any integrated circuit, if the system delay of its data transmission module is less than the bit period corresponding to any data transmission rate, it indicates that the data transmitter and receiver meet the timing constraints when transmitting data at that data transmission rate, and therefore the simulation test result can be determined as passed; otherwise, the simulation test result can be determined as failed.

[0055] Figure 5 This is a schematic diagram illustrating the simulation test results of the data transmission module according to an embodiment of the present invention. Figure 5 As shown, the row headers of List 50 represent the transmit jitter value of the data transmitter, the receive jitter value of the data receiver, the system delay of the data transmission module, and the data transmission rate (in Gbps); the column headers represent the module identifiers of the data transmission modules, namely modules 401-407. Taking the test data of some data transmission modules as an example, the transmit jitter value of module 401 is 251, the receive jitter value is 250, and the system delay is the sum of the transmit and receive jitter values, which is 501. The Boolean result is "pass" at data transmission rates of 1.00Gbps and 1.20Gbps, and "fail" at data transmission rates of 2.20Gbps and 3.20Gbps. The transmit jitter value of module 402 is 238, the receive jitter value is 199, and the system delay is the sum of the transmit and receive jitter values, which is 437. The Boolean result is "pass" at data transmission rates from 1.00Gbps to 2.20Gbps, and "fail" at data transmission rate of 3.20Gbps.

[0056] Step S500: Determine the timing table of the integrated circuit assembly based on the simulation test results.

[0057] After obtaining the simulation test results of each integrated circuit, the simulation test results can be classified and statistically analyzed to generate a timing table of the integrated circuit set.

[0058] Figure 6This is a flowchart of a timing verification method for a three-dimensional integrated circuit according to an embodiment of the present invention. Figure 6 As shown, in an optional implementation of this embodiment, step S500 may include the following steps: Step S510: Divide each simulation test result into multiple test result groups according to the process corner combination and data transmission rate.

[0059] To evaluate the system performance of integrated circuits with the same process corner combination, simulation test results of integrated circuits with the same process corner combination transmitting data at the same data transmission rate can be grouped into a test result group, thus obtaining multiple test result groups. For example, if a test result group includes test results T1-T1000, then the process corner combinations of the data transmission modules corresponding to test results T1-T1000 are all the same, such as the data transmitter being SS and the data receiver being FF, and the data transmission rate corresponding to test results T1-T1000 is also the same, such as 1.80Gbps.

[0060] Step S520: Determine the pass rate based on the number of passing simulation test results in each test result group and the total number of simulation test results.

[0061] After determining multiple test result groups, the number of simulated test results that passed (i.e., the number of passes) in each test result group and the total number of simulated test results in each test result group can be counted separately. Then, the pass rate corresponding to the test result group can be determined based on the ratio of the number of simulated test results that passed to the total number of simulated test results in the same test result group.

[0062] Step S530: Determine the timing table based on each pass rate.

[0063] After determining the pass rate for each test result group, a timing table for the integrated circuit assembly can be generated based on the pass rate for each test result group. The timing margin and mass production yield of the integrated circuit assembly can then be verified using the timing table corresponding to the integrated circuit assembly.

[0064] Figure 7 This is a schematic diagram illustrating the actual test results of the data transmission module according to an embodiment of the present invention. For example... Figure 7As shown, the row header of List 70 indicates the data transmission rate of the data transmission module, in Gbps (bit rate), including 1.00, 1.20, 1.40, 1.60, 1.80, 2.00, 2.20, and 2.40; the list header of List 70 indicates the process corner combination of the data transmission module, namely the combination of TX=FF and RX=FF, TX=FF and RX=TT, TX=FF and RX=SS, TX=TT and RX=FF, TX=TT and RX=TT, TX=TT and RX=SS, TX=SS and RX=FF, TX=SS and RX=TT, and TX=SS and RX=SS; the value is the throughput of the data transmission module for each process corner combination when transmitting data at different data transmission rates. Taking the throughput of data transmission modules with certain process corner combinations as an example, the throughput of data transmission modules with process corner combinations of TX as FF and RX as FF is 100% when the data transmission rate is between 1.00Gbps and 2.20Gbps, and 77.78% when the data transmission rate is 2.40Gbps; the throughput of data transmission modules with TX as FF and RX as SS is 100% when the data transmission rate is between 1.00Gbps and 1.80Gbps, and 0% when the data transmission rate is between 2.00Gbps and 2.40Gbps.

[0065] In this embodiment of the invention, the transmit jitter parameters and receive jitter parameters of the data transmission module are generated based on real test results, thus effectively improving the testing accuracy of 3D integrated circuits. Furthermore, when generating simulation test results based on the transmit and receive jitter parameters of the data transmission module, it is possible to simulate the real test results generated by the data transmission module during actual data transmission without performing a large number of repetitive tests, thereby effectively improving the testing efficiency of 3D integrated circuits.

[0066] In this embodiment of the invention, after identifying the data transmitter and data receiver of each circuit under test in a three-dimensional integrated circuit assembly as data transmission modules, the actual test results of each data transmission module are obtained. Based on these actual test results, the transmit jitter parameters and receive jitter parameters of each data transmission module are determined. Then, simulation test results of the three-dimensional integrated circuit assembly are generated based on these parameters, thereby determining the timing table of the three-dimensional integrated circuit assembly. This embodiment of the invention estimates the process corner combinations of each module using the actual test results of some integrated circuits in the three-dimensional integrated circuit assembly, and then performs testing of the three-dimensional integrated circuit assembly based on simulation test results that are close to the actual test results. Therefore, it can achieve high accuracy in testing three-dimensional integrated circuits.

[0067] Figure 8 This is a schematic diagram of a timing verification device for a three-dimensional integrated circuit according to an embodiment of the present invention. Figure 8 As shown, the timing verification device for the three-dimensional integrated circuit in this embodiment includes a transmission module determination unit 801, a first test unit 802, a parameter determination unit 803, a second test unit 804, and a result determination unit 805.

[0068] The transmission module determination unit 801 is used to determine the data transmission module of each circuit under test in the integrated circuit set. The data transmission module includes a data transmitter and a data receiver, and each circuit under test is a three-dimensional integrated circuit with the same hardware structure. The first test unit 802 is used to test each data transmission module and obtain the actual test results of each data transmission module. The actual test results are used to characterize whether the number of bit errors of each data transmission module during data transmission at each data transmission rate meets the preset bit error rate condition. The parameter determination unit 803 is used to determine the transmit jitter parameters and receive jitter parameters of each data transmission module based on the actual test results. The transmit jitter parameters include the jitter of the data transmitter at each process corner. The receiving jitter parameter includes at least one of the jitter mean and jitter standard deviation of the data receiving end at each process corner; the second test unit 804 is used to generate simulation test results of the integrated circuit set based on the transmitting jitter parameter and the receiving jitter parameter, the simulation test results being used to characterize whether the data transmitting end and the data receiving end of each integrated circuit in the integrated circuit set meet timing constraints when transmitting data at each of the data transmission rates; the result determination unit 805 is used to determine the timing table of the integrated circuit set based on the simulation test results, the timing table including the pass rate of data transmission between the data transmitting end and the data receiving end at each of the process corner combinations at each of the data transmission rates.

[0069] Furthermore, the parameter determination unit 803 includes a probability determination subunit and a parameter determination subunit.

[0070] The probability determination subunit is used to obtain the probability distribution of the process corner combination corresponding to the integrated circuit set; the parameter determination subunit is used to perform maximum likelihood estimation on each of the actual test results according to the probability distribution to determine the transmit jitter parameter and the receive jitter parameter.

[0071] Furthermore, the second test unit 804 includes a data generation subunit and a result determination subunit.

[0072] The data generation subunit is used to generate test data for each of the integrated circuits based on a preset statistical algorithm, the transmit jitter parameters, and the receive jitter parameters. The test data includes the process corner combination of the data transmitter and the data receiver, the transmit jitter value of the data transmitter, and the receive jitter value of the data receiver. The result determination subunit is used to determine the simulation test result based on each of the test data and the bit period corresponding to each of the data transmission rates.

[0073] Furthermore, the bit period is the reciprocal of the data transmission rate; The result determination subunit includes a delay determination module and a result determination module.

[0074] The delay determination module is used to determine the system delay of the corresponding data transmitter and data receiver based on each of the test data; the result determination module is used to determine the simulation test result based on the system delay and each of the bit periods.

[0075] Furthermore, the result determination unit 805 includes a grouping determination subunit, a pass rate determination subunit, and a timing table determination subunit.

[0076] The grouping determination subunit is used to divide each of the simulation test results into multiple test result groups according to the process angle combination and the data transmission rate; The pass rate determination subunit is used to determine the pass rate corresponding to each test result group based on the number of passed simulation test results in each test result group and the total number of simulation test results; The timing table determination subunit is used to determine the timing table based on each of the said pass rates.

[0077] Furthermore, the transmit jitter parameters and the receive jitter parameters follow a normal distribution.

[0078] In this embodiment of the invention, after identifying the data transmitter and data receiver of each circuit under test in a three-dimensional integrated circuit assembly as data transmission modules, the actual test results of each data transmission module are obtained. Based on these actual test results, the transmit jitter parameters and receive jitter parameters of each data transmission module are determined. Then, simulation test results of the three-dimensional integrated circuit assembly are generated based on these parameters, thereby determining the timing table of the three-dimensional integrated circuit assembly. This embodiment of the invention estimates the process corner combinations of each module using the actual test results of some integrated circuits in the three-dimensional integrated circuit assembly, and then performs testing of the three-dimensional integrated circuit assembly based on simulation test results that are close to the actual test results. Therefore, it can achieve high accuracy in testing three-dimensional integrated circuits.

[0079] Figure 9This is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 9 includes a server, a terminal, etc. Figure 9 As shown, the electronic device 9 includes at least one processor 901; a memory 902 communicatively connected to at least one processor 901; and a communication component 903 communicatively connected to a scanning device, wherein the communication component 903 receives and transmits data under the control of the processor 901; wherein the memory 902 stores instructions executable by at least one processor 901, the instructions being executed by at least one processor 901 to implement the timing verification method of the above-mentioned three-dimensional integrated circuit.

[0080] Specifically, the electronic device includes: one or more processors 901 and a memory 902. Figure 9 Taking a processor 901 as an example, the processor 901 and the memory 902 can be connected via a bus or other means. Figure 9 Taking a bus connection as an example, memory 902, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Processor 901 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in memory 902, thereby realizing the timing verification method of the aforementioned three-dimensional integrated circuit.

[0081] Memory 902 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, memory 902 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 902 may optionally include memory remotely located relative to processor 901, and these remote memories may be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0082] One or more modules are stored in memory 902, and when executed by one or more processors 901, they perform the timing verification method for the three-dimensional integrated circuit in any of the above method embodiments.

[0083] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0084] In this embodiment of the invention, after identifying the data transmitter and data receiver of each circuit under test in a three-dimensional integrated circuit assembly as data transmission modules, the actual test results of each data transmission module are obtained. Based on these actual test results, the transmit jitter parameters and receive jitter parameters of each data transmission module are determined. Then, simulation test results of the three-dimensional integrated circuit assembly are generated based on these parameters, thereby determining the timing table of the three-dimensional integrated circuit assembly. This embodiment of the invention estimates the process corner combinations of each module using the actual test results of some integrated circuits in the three-dimensional integrated circuit assembly, and then performs testing of the three-dimensional integrated circuit assembly based on simulation test results that are close to the actual test results. Therefore, it can achieve high accuracy in testing three-dimensional integrated circuits.

[0085] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0086] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0087] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A timing verification method for a three-dimensional integrated circuit, characterized in that, The method includes: The data transmission module of each circuit under test in the integrated circuit set is determined. The data transmission module includes a data transmitter and a data receiver. Each circuit under test is a three-dimensional integrated circuit with the same hardware structure. Each of the data transmission modules is tested, and the actual test results of each data transmission module are obtained. The actual test results are used to characterize whether the number of bit errors of each data transmission module meets the preset bit error count condition when transmitting data at each data transmission rate. The transmit jitter parameters and receive jitter parameters of each data transmission module are determined based on the actual test results. The transmit jitter parameters include at least one of the jitter mean and jitter standard deviation of the data transmitter at each process angle. The receive jitter parameters include at least one of the jitter mean and jitter standard deviation of the data receiver at each process angle. The simulation test results of the integrated circuit set are generated based on the transmit jitter parameters and receive jitter parameters. The simulation test results are used to characterize whether the data transmitter and data receiver of each integrated circuit in the integrated circuit set meet the timing constraints when transmitting data at each data transmission rate. The timing table of the integrated circuit assembly is determined based on the simulation test results. The timing table includes the data transmission pass rate of the data transmitter and the data receiver of each process corner combination at each data transmission rate.

2. The method according to claim 1, characterized in that, The determination of the transmit jitter parameters and receive jitter parameters of each data transmission module based on the actual test results includes: Obtain the probability distribution of the process corner combinations corresponding to the integrated circuit set; Based on the probability distribution, the transmit jitter parameter and the receive jitter parameter are determined by maximizing the likelihood of each actual test result.

3. The method according to claim 1, characterized in that, The simulation test results generated based on the transmit jitter parameters and receive jitter parameters for the integrated circuit assembly include: Test data for each integrated circuit is generated based on a preset statistical algorithm, the transmit jitter parameters, and the receive jitter parameters. The test data includes the process corner combination of the data transmitter and the data receiver, the transmit jitter value of the data transmitter, and the receive jitter value of the data receiver. The simulation test results are determined based on the test data and the bit period corresponding to each data transmission rate.

4. The method according to claim 3, characterized in that, The bit period is the reciprocal of the data transmission rate; Determining the simulation test results based on the bit periods corresponding to each of the test data and each of the data transmission rates includes: The system delay of the corresponding data transmitter and data receiver is determined based on the test data. The simulation test results are determined based on the system delay and each bit period.

5. The method according to claim 1, characterized in that, The step of determining the timing table of the integrated circuit assembly based on the simulation test results includes: The simulation test results are divided into multiple test result groups according to the process angle combination and the data transmission rate; The pass rate corresponding to each test result group is determined based on the number of successful simulation test results in each test result group and the total number of simulation test results; The timing table is determined based on the respective pass rates.

6. The method according to claim 1, characterized in that, The transmit jitter parameters and the receive jitter parameters follow a normal distribution.

7. A timing verification device for a three-dimensional integrated circuit, characterized in that, The device includes: A transmission module determination unit is used to determine the data transmission module of each circuit under test in the integrated circuit set. The data transmission module includes a data transmitter and a data receiver. Each circuit under test is a three-dimensional integrated circuit with the same hardware structure. The first test unit is used to test each of the data transmission modules and obtain the actual test results of each of the data transmission modules. The actual test results are used to characterize whether the number of bit errors of each of the data transmission modules meets the preset bit error number condition when transmitting data at each data transmission rate. The parameter determination unit is used to determine the transmit jitter parameters and receive jitter parameters of each of the data transmission modules based on the actual test results. The transmit jitter parameters include at least one of the jitter mean and jitter standard deviation of the data transmitter at each process angle. The receive jitter parameters include at least one of the jitter mean and jitter standard deviation of the data receiver at each process angle. The second test unit is used to generate simulation test results of the integrated circuit set based on the transmit jitter parameters and receive jitter parameters. The simulation test results are used to characterize whether the data transmitter and data receiver of each integrated circuit in the integrated circuit set meet the timing constraints when transmitting data at each data transmission rate. The result determination unit is used to determine the timing table of the integrated circuit assembly based on the simulation test results. The timing table includes the data transmission rate of the data transmitter and the data receiver of each process corner combination at each data transmission rate.

8. An electronic device comprising a memory and a processor, characterized in that, The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the method as described in any one of claims 1-6.

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