Display panel, method for performing pattern test on display panel, and electronic device

Abstract

The invention relates to a display panel, a method for performing a pattern test on the display panel, and an electronic device. The display panel includes: a plurality of data lines; a plurality of pixels connected to the plurality of data lines; a light emission test circuit providing an emission data voltage to the plurality of pixels through the plurality of data lines; and a pattern test circuit that supplies a non-emission data voltage to a portion of the plurality of pixels through the plurality of data lines after the emission data voltage is supplied to the plurality of pixels such that the plurality of pixels display a pattern image.

Description

Technical Field

[0001] The embodiments relate to a display panel including a pattern testing circuit and a pattern testing method using the display panel with the pattern testing circuit. Background Technology

[0002] The display device may include a display panel containing multiple pixels, a data driver that provides data signals to the pixels, a gate driver that provides gate signals to the pixels, and a controller that controls the data driver and the gate driver.

[0003] When manufacturing a display device, in order to detect defects in the display panel, light emission tests, open-circuit and short-circuit tests, etc., can be performed on the display panel in the unit state before the data driver is connected to the display panel. However, tests (e.g., pattern tests) for detecting image adhesion defects, etc., that appear after the patterned image is displayed on the display panel can be performed in the module state after the data driver is connected to the display panel. Summary of the Invention

[0004] Some implementations provide a display panel in which a pattern test is performed on the display panel in a cell state.

[0005] Some implementations provide a method for performing pattern testing on a display panel in a cell state.

[0006] According to an embodiment, the display panel may include: a plurality of data lines; a plurality of pixels connected to the plurality of data lines; a light emission test circuit that provides emission data voltage to the plurality of pixels through the plurality of data lines; and a pattern test circuit that provides non-emission data voltage to a portion of the plurality of pixels through the plurality of data lines after the emission data voltage is provided to the plurality of pixels, so that the plurality of pixels display a pattern image.

[0007] In one implementation, the light emission test circuit can provide emission data voltage to a plurality of pixels arranged in the pixel row during a first cycle of the horizontal time allocated to the pixel row, and the pattern test circuit can provide non-emission data voltage to a portion of the plurality of pixels arranged in the pixel row during a second cycle after the first cycle of the horizontal time.

[0008] In one embodiment, the light emission test circuit may include: a transmit data voltage line for transmitting transmit data voltage; and a plurality of light emission test transistors for connecting the transmit data voltage line to the plurality of data lines in response to a light emission test signal.

[0009] In one embodiment, the plurality of pixels may include red pixels arranged in a first pixel column, green pixels arranged in a second pixel column, and blue pixels arranged in a third pixel column. The light emission test circuit may include: a red emission data voltage line for transmitting red emission data voltage to the red pixels; a green emission data voltage line for transmitting green emission data voltage to the green pixels; a blue emission data voltage line for transmitting blue emission data voltage to the blue pixels; a first light emission test transistor for connecting the red emission data voltage line to the data line arranged in the first pixel column among the plurality of data lines in response to a light emission test signal; a second light emission test transistor for connecting the green emission data voltage line to the data line arranged in the second pixel column among the plurality of data lines in response to a light emission test signal; and a third light emission test transistor for connecting the blue emission data voltage line to the data line arranged in the third pixel column among the plurality of data lines in response to a light emission test signal.

[0010] In an implementation, the plurality of pixels may include: red pixels, green pixels, blue pixels, and green pixels arranged in a first pixel row and respectively arranged in a first pixel column, a second pixel column, a third pixel column, and a fourth pixel column; and blue pixels, green pixels, red pixels, and green pixels arranged in a second pixel row adjacent to the first pixel row and respectively arranged in a first pixel column, a second pixel column, a third pixel column, and a fourth pixel column. The light emission test circuit may include: a red emission data voltage line for transmitting red emission data voltage; a green emission data voltage line for transmitting green emission data voltage; a blue emission data voltage line for transmitting blue emission data voltage; a first-first light emission test transistor for connecting the red emission data voltage line to a data line arranged in a first pixel column among a plurality of data lines in response to a first light emission test signal; a first-second light emission test transistor for connecting the blue emission data voltage line to a data line arranged in the first pixel column among a plurality of data lines in response to a second light emission test signal; a second light emission test transistor for connecting the green emission data voltage line to a data line arranged in a second pixel column among a plurality of data lines in response to a third light emission test signal; a third-first light emission test transistor for connecting the blue emission data voltage line to a data line arranged in a third pixel column among a plurality of data lines in response to the first light emission test signal; a third-second light emission test transistor for connecting the red emission data voltage line to a data line arranged in a third pixel column among a plurality of data lines in response to the second light emission test signal; and a fourth light emission test transistor for connecting the green emission data voltage line to a data line arranged in a fourth pixel column among a plurality of data lines in response to the third light emission test signal.

[0011] In this implementation, the light emission test circuit can receive a first light emission test signal and a third light emission test signal within a first horizontal time period for the first pixel row, and can receive a second light emission test signal and a third light emission test signal within a second horizontal time period for the second pixel row.

[0012] In one embodiment, the pattern test circuit may include: a non-emitting data voltage line for transmitting a non-emitting data voltage; a plurality of first pattern test transistors for connecting the non-emitting data voltage line to a portion of the plurality of data lines in response to a first pattern test signal; and a plurality of second pattern test transistors for connecting the non-emitting data voltage line to the remainder of the plurality of data lines in response to a second pattern test signal.

[0013] In one implementation, the light emission test circuit can receive the light emission test signal in a first cycle of each horizontal time period, and the pattern test circuit can receive one of the first pattern test signal and the second pattern test signal in a second cycle after the first cycle of each horizontal time period.

[0014] In an implementation, the plurality of data lines may include: a first data line to a Mth data line, respectively arranged in the first pixel column to the Mth pixel column; a (M+1)th data line to a 2Mth data line, respectively arranged in the (M+1)th pixel column to the 2Mth pixel column; a (2M+1)th data line to a 3Mth data line, respectively arranged in the (2M+1)th pixel column to the 3Mth pixel column; and a (3M+1)th data line to a 4Mth data line, respectively arranged in the (3M+1)th pixel column to the 4Mth pixel column. M may be an integer greater than 0. The pattern test circuit may include: a non-emitting data voltage line for transmitting a non-emitting data voltage; a plurality of first pattern test transistors for connecting the non-emitting data voltage line to the first data line to the Mth data line and the (2M+1)th data line to the 3Mth data line in response to a first pattern test signal; and a plurality of second pattern test transistors for connecting the non-emitting data voltage line to the (M+1)th data line to the 2Mth data line and the (3M+1)th data line to the 4Mth data line in response to a second pattern test signal.

[0015] In this implementation, the light emission test circuit can receive a light emission test signal during a first cycle within each of the following: a first horizontal time allocated to the first pixel row to the Nth pixel row; a (N+1) horizontal time allocated to the (N+1)th pixel row to the 2Nth pixel row; a (2N+1) horizontal time allocated to the (3N+1)th pixel row to the 3Nth pixel row; and a (3N+1) horizontal time allocated to the (4N)th pixel row. N can be an integer greater than 0. The pattern test circuit can receive a second pattern test signal during a second cycle following the first cycle within each of the first horizontal time to the Nth horizontal time and the (2N+1)th horizontal time to the 3Nth horizontal time; and can receive a first pattern test signal during a second cycle following the first cycle within each of the (N+1)th horizontal time to the 2Nth horizontal time and the (3N+1)th horizontal time to the 4Nth horizontal time. The pattern image can be a chess pattern image.

[0016] In this implementation, the light emission test circuit can receive a light emission test signal during a first cycle within each of the following: a first horizontal time allocated to the first pixel row to the Nth pixel row; a (N+1) horizontal time allocated to the (N+1)th pixel row to the 2Nth pixel row; a (2N+1) horizontal time allocated to the (3N+1)th pixel row to the 3Nth pixel row; and a (3N+1) horizontal time allocated to the (4N)th pixel row. N can be an integer greater than 0. The pattern test circuit can receive a first pattern test signal during a second cycle following the first cycle within each of the first horizontal time to the Nth horizontal time and the (2N+1)th horizontal time to the 3Nth horizontal time; and can receive a second pattern test signal during the second cycle following the first cycle within each of the (N+1)th horizontal time to the 2Nth horizontal time and the (3N+1)th horizontal time to the 4Nth horizontal time. The pattern image can be a chess pattern image.

[0017] In one implementation, the plurality of data lines may include first data lines to Lth data lines arranged in the first pixel column to the Lth pixel column. L may be an integer greater than 0. The pattern test circuit may include: a non-emitting data voltage line for transmitting a non-emitting data voltage; a plurality of first pattern test transistors for connecting the non-emitting data voltage line to the (K+1)th to (LK)th data lines in response to a first pattern test signal; and a plurality of second pattern test transistors for connecting the non-emitting data voltage line to the first data lines to the Kth data lines and the (L-K+1)th to Lth data lines in response to a second pattern test signal. K may be an integer greater than 0 and less than L / 2.

[0018] In this implementation, the display panel may include a first pixel row to a P-th pixel row. P may be an integer greater than 0. The light emission test circuit may receive a light emission test signal during a first cycle within each of the first to P-th horizontal times allocated to the first to P-th pixel rows. The pattern test circuit may not receive either the first pattern test signal or the second pattern test signal during each of the first to Q-th horizontal times and the (P-Q+1)-th to P-th horizontal times within the first to P-th horizontal times, and may receive the first pattern test signal during a second cycle after the first cycle within each of the (Q+1)-th to (PQ)-th horizontal times within the first to P-th horizontal times. The pattern image may be an outer-line image. Q may be an integer greater than 0 and less than P / 2.

[0019] In this implementation, the display panel may include a first pixel row to a P-th pixel row. P may be an integer greater than 0. The light emission test circuit may receive a light emission test signal during a first cycle within each of the first to P-th horizontal times allocated to the first to P-th pixel rows. The pattern test circuit may receive both a first pattern test signal and a second pattern test signal during each of the first to Q-th horizontal times and the (P-Q+1)-th to P-th horizontal times within the first to P-th horizontal times, and may receive a second pattern test signal during a second cycle after the first cycle within each of the (Q+1)-th to (PQ)-th horizontal times within the first to P-th horizontal times. The pattern image may be a central region image. Q may be an integer greater than 0 and less than P / 2.

[0020] In one implementation, the plurality of data lines may include first data lines to Lth data lines respectively arranged in the first pixel column to the Lth pixel column. L may be an integer greater than 0. The pattern test circuit may include: a non-emitting data voltage line for transmitting a non-emitting data voltage; a plurality of first pattern test transistors for connecting the non-emitting data voltage line to the first data line to the (L / 2)th data line among the first data lines to the Lth data line in response to a first pattern test signal; and a plurality of second pattern test transistors for connecting the non-emitting data voltage line to the (L / 2+1)th data line to the Lth data line among the first data lines to the Lth data line in response to a second pattern test signal.

[0021] In this implementation, the light emission test circuit receives the light emission test signal during the first cycle of each horizontal time period. The pattern test circuit receives the first pattern test signal during the second cycle following the first cycle of each horizontal time period. The pattern image may be a right-side region image.

[0022] In this implementation, the light emission test circuit receives the light emission test signal during the first cycle of each horizontal time period. The pattern test circuit receives the second pattern test signal during the second cycle following the first cycle of each horizontal time period. The pattern image may be a left region image.

[0023] In this embodiment, the display panel may further include an open-circuit / short-circuit test circuit that alternately provides a first open-circuit / short-circuit test voltage and a second open-circuit / short-circuit test voltage to a plurality of data lines. The non-transmit data voltage may be the first open-circuit / short-circuit test voltage of the open-circuit / short-circuit test circuit.

[0024] According to an embodiment, a method for performing pattern testing on a display panel may include: measuring the initial brightness of the display panel; displaying a pattern image by the multiple pixels of the display panel for a period of time by providing emission data voltage to a plurality of pixels using a light emission test circuit of the display panel and providing non-emission data voltage to a portion of the plurality of pixels that have received the emission data voltage using a pattern test circuit of the display panel; measuring the final brightness of the display panel; and detecting whether the display panel has defects based on the brightness difference between the initial brightness and the final brightness.

[0025] In one implementation, pattern testing can be performed in the cell state before the data driver is connected to the display panel.

[0026] According to one embodiment, the electronic device may include a processor that provides image data and a display device that displays an image based on the image data. The display device may include a display panel.

[0027] As described above, in the display panel according to the embodiment and the method for performing pattern testing on the display panel, the light emission test circuit can provide emission data voltages to multiple pixels, and the pattern test circuit can provide non-emission data voltages to a portion of the multiple pixels. Therefore, the display panel according to the embodiment can display a pattern image in a cell state, and thus pattern testing can be performed on the display panel in the cell state. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a schematic diagram showing a display panel according to an embodiment.

[0030] Figure 2 This is a schematic diagram of the equivalent circuit of a pixel included in a display panel according to an embodiment.

[0031] Figure 3 This is a schematic diagram of the equivalent circuit of a pixel included in a display panel according to an embodiment.

[0032] Figure 4 This is a schematic diagram showing a display panel according to an embodiment.

[0033] Figure 5 This is a schematic diagram showing a display panel according to an embodiment.

[0034] Figure 6 This is a schematic diagram illustrating a pattern test circuit included in a display panel according to an embodiment.

[0035] Figure 7 This is a schematic timing diagram illustrating the operation of a pattern test circuit included in a display panel, according to an embodiment.

[0036] Figure 8 This is a schematic diagram showing a display panel according to an embodiment.

[0037] Figure 9 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0038] Figure 10 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0039] Figure 11 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0040] Figure 12 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0041] Figure 13 This is a schematic diagram showing a display panel according to an embodiment.

[0042] Figure 14 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0043] Figure 15 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0044] Figure 16 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0045] Figure 17 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0046] Figure 18 This is a schematic diagram showing a display panel according to an embodiment.

[0047] Figure 19 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0048] Figure 20 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0049] Figure 21 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0050] Figure 22 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0051] Figure 23 This is a schematic diagram showing a display panel according to an embodiment.

[0052] Figure 24 This is a schematic timing diagram illustrating the operation of a display panel according to an embodiment.

[0053] Figure 25 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0054] Figure 26 This is a flowchart illustrating a method for performing a pattern test on a display panel according to an embodiment.

[0055] Figure 27 This is a schematic block diagram illustrating a display device according to an embodiment.

[0056] Figure 28This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment. Detailed Implementation

[0057] In the following, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0058] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals, reference marks, and / or reference characters denote the same elements.

[0059] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, directly connected to, or directly attached to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly" on, directly connected to, or directly attached to another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary component. Furthermore, when a component is referred to as being "in contact" or "contacted" with another component, the component can be in "electrical contact" or "physical contact" with the other component, or in "indirect contact" or "direct contact" with the other component.

[0060] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0061] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”), etc., may be used herein to describe the relationship between one element and another (or multiple elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0062] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0063] In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood to be equivalent to "and / or".

[0064] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the values ​​and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0065] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0066] Figure 1 This is a schematic diagram showing a display panel according to an embodiment. Figure 2 This is a schematic diagram of the equivalent circuit of a pixel included in a display panel according to an embodiment. Figure 3 This is a schematic diagram of the equivalent circuit of a pixel included in a display panel according to an embodiment. Figure 4 This is a schematic diagram showing a display panel according to an embodiment. Figure 5 This is a schematic diagram showing a display panel according to an embodiment. Figure 6 This is a schematic diagram illustrating a pattern test circuit included in a display panel according to an embodiment, and Figure 7 This is a schematic timing diagram illustrating the operation of a pattern test circuit included in a display panel, according to an embodiment.

[0067] refer to Figure 1 According to embodiments, the display panel 100 may include a plurality of data lines DL, a plurality of pixels PX connected to the data lines DL, a light emission test circuit 120 that provides an emission data voltage VEM to the pixels PX via the data lines DL, and a pattern test circuit 160 that provides a non-emission data voltage VNEM to a portion of the pixels PX via the data lines DL. In some embodiments, the display panel 100 may further include an open-circuit short-circuit test circuit 140 that provides a first open-circuit short-circuit test voltage VOST1 or a second open-circuit short-circuit test voltage VOST2 to the data lines DL. In some embodiments, the display panel 100 may further include a plurality of gate lines GL and a gate driver 180 that provides gate signals to the pixels PX via the gate lines GL. In some embodiments, although not explicitly stated... Figure 1 As shown, the display panel 100 may also include a crack detection circuit, a single-chip test circuit, etc. Furthermore, in some embodiments, in the unit state before the display panel 100 is connected to the data driver 190, light emission tests, open / short circuit tests, pattern tests, etc., can be performed on the display panel 100.

[0068] Pixels PX can be connected to data lines DL and gate lines GL. In some embodiments, each pixel PX may include at least two transistors, at least one capacitor, and a light-emitting element. According to embodiments, the light-emitting element may be an organic light-emitting diode (“OLED”), a micro light-emitting diode, a nano light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0069] For example, such as Figure 2 As shown, each pixel PXa can receive a write signal GW as a gate signal, and pixel PXa can include a second transistor PXT2a that transmits the voltage of a data line DL in response to the write signal GW, a capacitor CST that stores the voltage transmitted by the second transistor PXT2a, a first transistor PXT1a that generates a drive current based on the voltage stored in the capacitor CST, and a light-emitting element EL that emits light based on the drive current flowing from the line transmitting a first power supply voltage ELVDD (e.g., a high power supply voltage) to the line transmitting a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0070] In another embodiment, such as Figure 3 As shown, each pixel PXb can receive a write signal GW, a compensation signal GC, an initialization signal GI, a bypass signal GB, and an transmit signal EM as a gate signal, and the pixel PXb can include a capacitor CST, a first transistor PXT1b, a second transistor PXT2b, a third transistor PXT3b, a fourth transistor PXT4b, a fifth transistor PXT5b, a sixth transistor PXT6b, a seventh transistor PXT7b, an eighth transistor PXT8b, and a light-emitting element EL.

[0071] The capacitor CST can store the voltage transmitted from the data line DL via the second transistor PXT2b and the first transistor PXT1b (which is diode-connected via the third transistor PXT3b). The first transistor PXT1b can generate a drive current based on the voltage stored in the capacitor CST. The second transistor PXT2b can transmit the voltage of the data line DL to the first terminal (e.g., the source) of the first transistor PXT1b in response to the write signal GW. The third transistor PXT3b can connect the diode of the first transistor PXT1b in response to the compensation signal GC. The fourth transistor PXT4b can apply the initialization voltage VINT to the capacitor CST and the gate of the first transistor PXT1b in response to the initialization signal GI. The fifth transistor PXT5b and the sixth transistor PXT6b can form a path of drive current from the line transmitting the first power supply voltage ELVDD to the line transmitting the second power supply voltage ELVSS in response to the transmit signal EM. The seventh transistor PXT7b can apply the anode initialization voltage AINT to the anode of the light-emitting element EL in response to the bypass signal GB. The eighth transistor PXT8b can apply a bias voltage VOBS to the first terminal (e.g., the source) of the first transistor PXT1b in response to the bypass signal GB. The light-emitting element EL can emit light based on the drive current generated by the first transistor PXT1b.

[0072] although Figure 2 An embodiment in which pixel PXa has a 2T1C structure is shown, and Figure 3 An embodiment in which pixel PXb has an 8T1C structure is shown, but the pixel PX of the display panel 100 is not limited to... Figure 2 and Figure 3 The implementation method.

[0073] In some implementations, such as Figure 4As shown, the display panel 100a may have an RGB bar structure, in which red pixels RPX, green pixels GPX, and blue pixels BPX are arranged in three adjacent pixel columns (e.g., a first pixel column PC1, a second pixel column PC2, and a third pixel column PC3). In the display panel 100a, a red pixel RPX, a green pixel GPX, and a blue pixel BPX may form a unit pixel UPX or a pixel group. For example, the display panel 100a may include a red pixel RPX connected to a first data line DL1 in the first pixel column PC1, a green pixel GPX connected to a second data line DL2 in the second pixel column PC2, a blue pixel BPX connected to a third data line DL3 in the third pixel column PC3, a red pixel RPX connected to a fourth data line DL4 in the fourth pixel column PC4, a green pixel GPX connected to a fifth data line DL5 in the fifth pixel column PC5, and a blue pixel BPX connected to a sixth data line DL6 in the sixth pixel column PC6.

[0074] In other implementations, such as Figure 5As shown, the display panel 100b may have an RGBG pixel arrangement structure, in which red pixels (RPX), green pixels (GPX), blue pixels (BPX), and green pixels (GPX) are arranged repeatedly along the pixel row direction. In the display panel 100b, a red pixel (RPX), a blue pixel (BPX), and a green pixel (GPX) can form a unit pixel or a pixel group. For example, a red pixel (RPX) and a green pixel (GPX) can form a first unit pixel (UPX1), and a blue pixel (BPX) and a green pixel (GPX) can form a second unit pixel (UPX2). Furthermore, for example, the red pixel RPX and blue pixel BPX connected to the first data line DL1 can be repeatedly arranged in the first pixel column PC1; the green pixel GPX connected to the second data line DL2 can be repeatedly arranged in the second pixel column PC2; the blue pixel BPX and red pixel RPX connected to the third data line DL3 can be repeatedly arranged in the third pixel column PC3; the green pixel GPX connected to the fourth data line DL4 can be repeatedly arranged in the fourth pixel column PC4; the red pixel RPX and blue pixel BPX connected to the fifth data line DL5 can be repeatedly arranged in the fifth pixel column PC5; the green pixel GPX connected to the sixth data line DL6 can be repeatedly arranged in the sixth pixel column PC6; the blue pixel BPX and red pixel RPX connected to the seventh data line DL7 can be repeatedly arranged in the seventh pixel column PC7; and the green pixel GPX connected to the eighth data line DL8 can be repeatedly arranged in the eighth pixel column PC8. Furthermore, for example, red pixel RPX, green pixel GPX, blue pixel BPX, and green pixel GPX can be repeatedly arranged in each of the odd-numbered pixel rows PR1 and PR3, and blue pixel BPX, green pixel GPX, red pixel RPX, and green pixel GPX can be repeatedly arranged in each of the even-numbered pixel rows PR2 and PR4.

[0075] although Figure 4 An embodiment in which the display panel 100a has an RGB bar structure is shown, and Figure 5 An embodiment in which the display panel 100b has an RGBG pixel arrangement structure is shown, but the display panel 100b according to the embodiment is not limited to... Figure 4 and Figure 5 The implementation method.

[0076] The luminescence test circuit 120 can perform a luminescence test, which detects defects in the display panel 100 by allowing the pixel PX to emit light through the data line DL in response to the luminescence test signal SLT, providing an emission data voltage VEM to the pixel PX. In some embodiments, the emission data voltage VEM can be (but is not limited to) a data voltage corresponding to the maximum gray level (e.g., 255 gray levels). In some embodiments, the luminescence test can be performed on the display panel 100 in a cell state before the display panel 100 is connected to the data driver 190. In other embodiments, the luminescence test can be further performed on the display panel 100 in a module state after the display panel 100 is connected to the data driver 190. Furthermore, the luminescence test circuit 120 and the pattern test circuit 160 can be used to perform a pattern test on the display panel 100 in the cell state by allowing the pixel PX to display a pattern image (e.g., a predetermined pattern image). In some embodiments, the luminescence test circuit 120 may include an emission data voltage line for transmitting the emission data voltage VEM and a plurality of luminescence test transistors that connect the emission data voltage line to the data line DL in response to the luminescence test signal SLT.

[0077] For example, such as Figure 4As shown, in an embodiment where the display panel 100a has an RGB bar structure, the light emission test circuit 120a may include a red emission data voltage line VEML_R that transmits the red emission data voltage VEM_R to the red pixel RPX, a green emission data voltage line VEML_G that transmits the green emission data voltage VEM_G to the green pixel GPX, a blue emission data voltage line VEML_B that transmits the blue emission data voltage VEM_B to the blue pixel BPX, and a red emission data voltage line VEML_R connected to the first pixel column PC1 and the fourth pixel column PC1 in response to the light emission test signal SLT. The first light-emitting test transistor LTT1 of the first data line DL1 and the fourth data line DL4 in pixel column PC4, the second light-emitting test transistor LTT2 that connects the green emission data voltage line VEML_G to the second data line DL2 and the fifth data line DL5 arranged in the second pixel column PC2 and the fifth pixel column PC5 in response to the light-emitting test signal SLT, and the third light-emitting test transistor LTT3 that connects the blue emission data voltage line VEML_B to the third data line DL3 and the sixth data line DL6 arranged in the third pixel column PC3 and the sixth pixel column PC6 in response to the light-emitting test signal SLT. To perform a light emission test or pattern test, the light emission test circuit 120a can receive a light emission test signal SLT within the horizontal time allocated to each pixel row. The first light emission test transistor LTT1, in response to the light emission test signal SLT, provides a red emission data voltage VEM_R to the red pixel RPX via the first data line DL1 and the fourth data line DL4. The second light emission test transistor LTT2, in response to the light emission test signal SLT, provides a green emission data voltage VEM_G to the green pixel GPX via the second data line DL2 and the fifth data line DL5. Furthermore, the third light emission test transistor LTT3, in response to the light emission test signal SLT, provides a blue emission data voltage VEM_B to the blue pixel BPX via the third data line DL3 and the sixth data line DL6. Therefore, the red pixel RPX can emit light based on the red emission data voltage VEM_R, the green pixel GPX can emit light based on the green emission data voltage VEM_G, and the blue pixel BPX can emit light based on the blue emission data voltage VEM_B.

[0078] In another embodiment, such as Figure 5As shown, in an embodiment where the display panel 100b has an RGBG pixel arrangement structure, the light emission test circuit 120b may include a red emission data voltage line VEML_R that transmits the red emission data voltage VEM_R to the red pixel RPX, a green emission data voltage line VEML_G that transmits the green emission data voltage VEM_G to the green pixel GPX, a blue emission data voltage line VEML_B that transmits the blue emission data voltage VEM_B to the blue pixel BPX, a first-first light emission test transistor LTT1-1 that connects the red emission data voltage line VEML_R to the first data line DL1 and the fifth data line DL5 arranged in the first pixel column PC1 and the fifth pixel column PC5 in response to a first light emission test signal SLT1, a first-second light emission test transistor LTT1-2 that connects the blue emission data voltage line VEML_B to the first data line DL1 and the fifth data line DL5 arranged in the first pixel column PC1 and the fifth pixel column PC5 in response to a second light emission test signal SLT2, and a second light emission test transistor LTT1-2 that connects the blue emission data voltage line VEML_B to the first data line DL1 and the fifth data line DL5 arranged in the first pixel column PC1 and the fifth pixel column PC5 in response to a second light emission test signal SLT2, and a third-second ... line VEML_ The three-light emission test signal SLT3 connects the green emission data voltage line VEML_G to the second data line DL2 and the sixth data line DL6 arranged in the second pixel column PC2 and the sixth pixel column PC6, respectively. The third-first light emission test transistor LTT3-1 connects the blue emission data voltage line VEML_B to the third data line DL3 and the seventh data line DL7 arranged in the third pixel column PC3 and the seventh pixel column PC7, respectively. The third-second light emission test transistor LTT3-2 connects the red emission data voltage line VEML_R to the third data line DL3 and the seventh data line DL7 arranged in the third pixel column PC3 and the seventh pixel column PC7, respectively. The fourth light emission test transistor LTT4 connects the green emission data voltage line VEML_G to the fourth data line DL4 and the eighth data line DL8 arranged in the fourth pixel column PC4 and the eighth pixel column PC8, respectively, in response to the third light emission test signal SLT3.To perform a light emission test or pattern test, the light emission test circuit 120b can receive a first light emission test signal SLT1 and a third light emission test signal SLT3 within the horizontal time allocated to each odd-numbered pixel row PR1 and PR3. The first-first light emission test transistor LTT1-1 can, in response to the first light emission test signal SLT1, provide a red emission data voltage VEM_R to the red pixel RPX arranged in the odd-numbered pixel rows PR1 and PR3 via the first data line DL1 and the fifth data line DL5. The third-first light emission test transistor LTT3-1 can, in response to the first light emission test signal SLT1, provide a blue emission data voltage VEM_B to the blue pixel BPX arranged in the odd-numbered pixel rows PR1 and PR3 via the third data line DL3 and the seventh data line DL7. Furthermore, the second light emission test transistor LTT2 and the fourth light emission test transistor LTT4 can, in response to the third light emission test signal SLT3, provide a green emission data voltage VEM_G to the green pixel GPX via the second data line DL2, the fourth data line DL4, the sixth data line DL6, and the eighth data line DL8. Furthermore, the light emission test circuit 120b can receive the second light emission test signal SLT2 and the third light emission test signal SLT3 during the horizontal time allocated to each even-numbered pixel row PR2 and PR4. The first-second light emission test transistor LTT1-2 can provide the blue emission data voltage VEM_B to the blue pixel BPX arranged in the even-numbered pixel row PR2 and PR4 through the first data line DL1 and the fifth data line DL5 in response to the second light emission test signal SLT2. The third-second light emission test transistor LTT3-2 can provide the red emission data voltage VEM_R to the red pixel RPX arranged in the even-numbered pixel row PR2 and PR4 through the third data line DL3 and the seventh data line DL7 in response to the second light emission test signal SLT2. In addition, the second light emission test transistor LTT2 and the fourth light emission test transistor LTT4 provide the green emission data voltage VEM_G to the green pixel GPX through the second data line DL2, the fourth data line DL4, the sixth data line DL6 and the eighth data line DL8 in response to the third light emission test signal SLT3. Therefore, the red pixel RPX can emit light based on the red emission data voltage VEM_R, the green pixel GPX can emit light based on the green emission data voltage VEM_G, and the blue pixel BPX can emit light based on the blue emission data voltage VEM_B.

[0079] The open-circuit and short-circuit test circuit 140 can perform an open-circuit and short-circuit test to detect open-circuit defects in each data line DL and short-circuit defects between data lines DL by alternately providing a first open-circuit and short-circuit test voltage VOST1 and a second open-circuit and short-circuit test voltage VOST2 to the data lines DL in response to the open-circuit and short-circuit test signal SOST. In some embodiments, the open-circuit and short-circuit test can be performed on the display panel 100 in a cell state before the display panel 100 is connected to the data driver 190. In other embodiments, the open-circuit and short-circuit test can be performed on the display panel 100 in a module state after the display panel 100 is connected to the data driver 190. In some embodiments, the first open-circuit and short-circuit test voltage VOST1 can be (but is not limited to) a black data voltage (e.g., a data voltage corresponding to 0 gray level), and the second open-circuit and short-circuit test voltage VOST2 can be (but is not limited to) a white data voltage (e.g., a data voltage corresponding to 255 gray level). The first open-circuit short-circuit test voltage VOST1 may correspond to the non-emit data voltage VNEM, and the second open-circuit short-circuit test voltage VOST2 may correspond to the transmit data voltage VEM. In some embodiments, the pattern test circuit 160 may receive the first open-circuit short-circuit test voltage VOST1 from the open-circuit short-circuit test circuit 140 as the non-emit data voltage VNEM. In other embodiments, the first open-circuit short-circuit test voltage VOST1 may be (but is not limited to) a white data voltage, and the second open-circuit short-circuit test voltage VOST2 may be (but is not limited to) a black data voltage. In some embodiments, the open-circuit short-circuit test circuit 140 may provide one of the first open-circuit short-circuit test voltage VOST1 and the second open-circuit short-circuit test voltage VOST2 to each unit pixel UPX, such that the first open-circuit short-circuit test voltage VOST1 and the second open-circuit short-circuit test voltage VOST2 are alternately provided to the corresponding unit pixels along the pixel row direction.

[0080] For example, such as Figure 4As shown, in an embodiment where the display panel 100a has an RGB strip structure, the open / short circuit 140a may include a first open / short circuit test voltage line VOSTL1 that transmits a first open / short circuit test voltage VOST1, a second open / short circuit test voltage line VOSTL2 that transmits a second open / short circuit test voltage VOST2, a first open / short circuit test transistor OSTT1 that connects the first open / short circuit test voltage line VOSTL1 to the first data line DL1, the second data line DL2, and the third data line DL3 arranged in the first pixel column PC1, the second pixel column PC2, and the third pixel column PC3 in response to the open / short circuit test signal SOST, and a second open / short circuit test transistor OSTT2 that connects the second open / short circuit test voltage line VOSTL2 to the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 arranged in the fourth pixel column PC4, the fifth pixel column PC5, and the sixth pixel column PC6 in response to the open / short circuit test signal SOST. Therefore, when performing open-circuit and short-circuit tests, the open-circuit and short-circuit test circuit 140a can alternately provide a first open-circuit and short-circuit test voltage VOST1 and a second open-circuit and short-circuit test voltage VOST2 to each group of the three data lines. In some embodiments, the first open-circuit and short-circuit test voltage VOST1 of the first open-circuit and short-circuit test voltage line VOST1 can be provided to the pattern test circuit 160 as a non-transmit data voltage VNEM.

[0081] In another embodiment, such as Figure 5As shown, in an embodiment where the display panel 100b has an RGBG pixel arrangement structure, the open / short circuit 140b may include a first open / short circuit test voltage line VOSTL1 for transmitting a first open / short circuit test voltage VOST1, a second open / short circuit test voltage line VOSTL2 for transmitting a second open / short circuit test voltage VOST2, a first open / short circuit test transistor OSTT1 that connects the first open / short circuit test voltage line VOSTL1 to the first data line DL1, second data line DL2, fifth data line DL5, and sixth data line DL6 arranged in the first pixel column PC1, second pixel column PC2, fifth pixel column PC5, and sixth pixel column PC6 in response to the open / short circuit test signal SOST, and a second open / short circuit test transistor OSTT2 that connects the second open / short circuit test voltage line VOSTL2 to the third data line DL3, fourth data line DL4, seventh data line DL7, and eighth data line DL8 arranged in the third pixel column PC3, fourth pixel column PC4, seventh pixel column PC7, and eighth pixel column PC8 in response to the open / short circuit test signal SOST. Therefore, when performing open-circuit and short-circuit tests, the open-circuit and short-circuit test circuit 140b can alternately provide a first open-circuit and short-circuit test voltage VOST1 and a second open-circuit and short-circuit test voltage VOST2 to each group of the two data lines. In some embodiments, the first open-circuit and short-circuit test voltage VOST1 of the first open-circuit and short-circuit test voltage line VOST1 can be provided to the pattern test circuit 160 as a non-transmit data voltage VNEM.

[0082] The pattern test circuit 160 may, in response to a first pattern test signal SPT1 and / or a second pattern test signal SPT2, provide a non-emitting data voltage VNEM to a portion of the pixel PX via the data line DL. In some embodiments, the non-emitting data voltage VNEM may be (but is not limited to) a data voltage corresponding to the minimum gray level (e.g., gray level 0). Furthermore, in some embodiments, the pattern test circuit 160 may receive (but is not limited to) a first open-circuit short-circuit test voltage VOST1 from the open-circuit short-circuit test circuit 140 as the non-emitting data voltage VNEM.

[0083] The light emission test circuit 120 and the pattern test circuit 160 can be used to perform pattern testing in the cell state before the display panel 100 is connected to the data driver 190. To perform the pattern test, the initial brightness of the display panel 100 can be measured, and the pixels PX can display a pattern image for a specific time period (e.g., approximately 10 minutes to approximately 1 hour). According to embodiments, the pattern image can be (but is not limited to)... Figure 10 and Figure 12 The chess pattern image shown Figure 15 The outer line image shown Figure 17 The central region image shown Figure 20 The right region image shown Figure 22 The left region image shown or Figure 25 The image shown is a combination of a chess pattern image and an outer line image. To enable pixel PX to display the pattern image, the light emission test circuit 120 can provide an emission data voltage VEM to pixel PX, and the pattern test circuit 160 can provide a non-emission data voltage VNEM to a portion of pixel PX after the emission data voltage VEM is provided to pixel PX. For example, the light emission test circuit 120 can provide the emission data voltage VEM to all pixel PXs arranged in the pixel row during a first cycle of the horizontal time allocated to the pixel row, and the pattern test circuit 160 can provide the non-emission data voltage VNEM to a portion of the pixel PXs arranged in the pixel row during a second cycle after the first cycle of the horizontal time. Therefore, the portion of pixel PX to which the non-emission data voltage VNEM is provided may not emit light, and the remaining portion of pixel PX not to which the non-emission data voltage VNEM is provided may emit light, and thus pixel PX can display the pattern image. After pixel PX displays the pattern image, the final brightness of the display panel 100 can be measured. The pattern test can detect defects in the display panel 100 based on the brightness difference between the initial brightness and the final brightness.

[0084] In some embodiments, the pattern test circuit 160 may include a non-emitting data voltage line VNEML that transmits a non-emitting data voltage VNEM, a plurality of first pattern test transistors PTT1 that connect the non-emitting data voltage line VNEML to a portion of the data line DL in response to a first pattern test signal SPT1, and a plurality of second pattern test transistors PTT2 that connect the non-emitting data voltage line VNEML to the remaining portion of the data line DL in response to a second pattern test signal SPT2. For example, as Figure 6 As shown, the non-emitting data voltage line VNEML can receive the first open-circuit short-circuit test voltage VOST1 from the open-circuit short-circuit test circuit 140 as the non-emitting data voltage VNEM. The first pattern test transistor PTT1 can connect the non-emitting data voltage line VNEML to the first data lines DL1 to DLM arranged in the first pixel column PC1 to the Mth pixel column PCM in response to the first pattern test signal SPT1, where M can be an integer greater than 0. Furthermore, the second pattern test transistor PTT2 can connect the non-emitting data voltage line VNEML to the (M+1)th data line DLM+1 to the 2Mth data line DL2M arranged in the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M in response to the second pattern test signal SPT2.

[0085] The light emission test circuit 120 can receive the light emission test signal SLT in the first cycle of each horizontal time period, and the pattern test circuit 160 can receive one of the first pattern test signal SPT1 and the second pattern test signal SPT2 in the second cycle after the first cycle of the horizontal time period. For example, as Figure 6 and Figure 7 As shown, the frame period FP may include a first horizontal time HT1 to the Nth horizontal time HTN (where N may be an integer greater than 0) allocated to the first pixel row PR1 to the Nth pixel row PRN of the display panel 100, and a (N+1)th horizontal time HTN+1 to the 2Nth horizontal time HT2N allocated to the (N+1)th pixel row PRN+1 to the 2Nth pixel row PR2N of the display panel 100. The gate driver 180 may sequentially apply a first write signal GW1 to the Nth write signal GWN to the first pixel row PR1 to the Nth pixel row PRN during the first horizontal time HT1 to the Nth horizontal time HTN, and may sequentially apply a (N+1)th write signal GWN+1 to the 2Nth write signal GW2N to the (N+1)th pixel row PRN+1 to the 2Nth pixel row PR2N during the (N+1)th horizontal time HTN+1 to the 2Nth horizontal time HT2N. The light emission test circuit 120 can receive a light emission test signal SLT with a conduction level (e.g., low level) in the first period P1 within each of the first horizontal time HT1 to the second horizontal time HT2N, and can sequentially provide the transmit data voltage VEM to all pixels PX in the first pixel row PR1 to the second pixel row PR2N row by row.

[0086] In the second period P2 following the first period P1 within each of the first level time HT1 to the Nth level time HTN, the pattern test circuit 160 may not receive the first pattern test signal SPT1 with an on-level (e.g., low level), but may instead receive the second pattern test signal SPT2 with an on-level. Therefore, in the first level time HT1 to the Nth level time HTN, the second pattern test transistor PTT2 of the pattern test circuit 160 may provide a non-emit data voltage VNEM to the pixels PX arranged in the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M in response to the second pattern test signal SPT2, and the pixels PX arranged in the first pixel column PC1 to the Mth pixel column PCM may not receive the non-emit data voltage VNEM. Therefore, the first display area DR1, which includes pixels PX arranged in the first pixel row PR1 to the Nth pixel row PRN and the first pixel column PC1 to the Mth pixel column PCM, can emit light, and the second display area DR2, which includes pixels PX arranged in the first pixel row PR1 to the Nth pixel row PRN and the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M, can not emit light.

[0087] In the second period P2 following the first period P1 within each of the (N+1) level time HTN+1 to the 2N level time HT2N, the pattern test circuit 160 may not receive the second pattern test signal SPT2 with a conduction level, but may instead receive the first pattern test signal SPT1 with a conduction level. Therefore, in the (N+1) level time HTN+1 to the 2N level time HT2N, the first pattern test transistor PTT1 of the pattern test circuit 160 may provide a non-emit data voltage VNEM to the pixels PX arranged in the first pixel column PC1 to the M pixel column PCM in response to the first pattern test signal SPT1, and the pixels PX arranged in the (M+1) pixel column PCM+1 to the 2M pixel column PC2M may not receive the non-emit data voltage VNEM. Therefore, the third display area DR3, which includes pixels PX arranged in the (N+1)th pixel row PRN+1 to the 2Nth pixel row PR2N and the first pixel column PC1 to the Mth pixel column PCM, may not emit light, while the fourth display area DR4, which includes pixels PX arranged in the (N+1)th pixel row PRN+1 to the 2Nth pixel row PR2N and the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M, may emit light. In this way, the display panel 100 according to the embodiment can display a pattern image in a cell state before the display panel 100 is connected to the data driver 190, and a pattern test can be performed on the display panel 100 in the cell state.

[0088] In conventional display devices, the display panel requires a data driver to display patterned images. Therefore, in conventional display devices, pattern testing can be performed in a module state after the data driver is connected to the display panel. However, in the display panel 100 according to the embodiment, the light-emitting test circuit 120 can provide an emission data voltage VEM to the pixel PX, and the pattern testing circuit 160 can provide a non-emission data voltage VNEM to a portion of the pixel PX. Therefore, the display panel 100 according to the embodiment can display patterned images in a unit state, and thus pattern testing can be performed on the display panel 100 in the unit state. Therefore, since pattern testing can be performed at an early stage in the manufacturing process of the display device, defects and faults in the display panel 100 can be detected quickly and accurately.

[0089] Figure 8 This is a schematic diagram showing a display panel according to an embodiment. Figure 9 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment. Figure 10 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment. Figure 11This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment, and Figure 12 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0090] refer to Figure 8 The display panel 200 according to the embodiments may include a plurality of data lines DL1 to DL4M, a plurality of pixels PX, a light emission test circuit 220, and a pattern test circuit 260. In some embodiments, although not in Figure 8 As shown in the figure, the display panel 200 may also include open circuit and short circuit test circuits, crack detection circuits, single-chip test circuits, etc.

[0091] Data lines DL1 to DL4M may include the first data line DL1 to the Mth data line DLM arranged in the first pixel column PC1 to the Mth pixel column PCM, the (M+1)th data line DLM+1 to the 2Mth data line DL2M arranged in the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M, the (2M+1)th data line DL2M+1 to the 3Mth data line DL3M arranged in the (2M+1)th pixel column PC2M+1 to the 3Mth pixel column PC3M, and the (3M+1)th data line DL3M+1 to the 4Mth data line DL4M arranged in the (3M+1)th pixel column PC3M+1 to the 4Mth pixel column PC4M, wherein M may be an integer greater than 0.

[0092] The pattern test circuit 260 may include a non-emitting data voltage line VNEML that transmits a non-emitting data voltage VNEM, a plurality of first pattern test transistors PTT1 that connect the non-emitting data voltage line VNEML to the first data lines DL1 to the Mth data line DLM and the (2M+1)th data line DL2M+1 to the 3rd data line DL3M in response to a first pattern test signal SPT1, and a plurality of second pattern test transistors PTT2 that connect the non-emitting data voltage line VNEML to the (M+1)th data line DLM+1 to the 2nd data line DL2M and the (3M+1)th data line DL3M+1 to the 4th data line DL4M in response to a second pattern test signal SPT2.

[0093] like Figure 9 and Figure 11As shown, the light emission test circuit 220 can receive a light emission test signal SLT with a conduction level (e.g., low level) in a first cycle within each of the following: the first horizontal time HT1 to the Nth horizontal time HTN allocated to the first pixel row PR1 to the Nth pixel row PRN; the (N+1) horizontal time HTN+1 to the 2Nth horizontal time HT2N allocated to the (N+1)th pixel row PRN+1 to the 2Nth pixel row PR2N; the (2N+1) horizontal time HT2N+1 to the 3Nth horizontal time HT3N allocated to the (2N+1)th pixel row PR2N+1 to the 3Nth pixel row PR3N; and the (3N+1) horizontal time HT3N+1 to the 4Nth horizontal time HT4N allocated to the (3N+1)th pixel row PR3N+1 to the 4Nth pixel row PR4N (where N is an integer greater than 0). Therefore, the light emission test circuit 220 can provide the emission data voltage VEM to all pixels PX arranged in the first pixel row PR1 to the fourth pixel row PR4N during the first horizontal time HT1 to the fourth horizontal time HT4N.

[0094] In some implementations, such as Figure 9As shown, in the second period following the first period within each of the first horizontal time HT1 to the Nth horizontal time HTN and the (2N+1)th horizontal time HT2N+1 to the 3Nth horizontal time HT3N, the pattern test circuit 260 may receive a second pattern test signal SPT2 with a conduction level, and may not receive a first pattern test signal SPT1 with a conduction level. Therefore, the pattern test circuit 260 may only provide the non-transmit data voltage VNEM to the pixels PX arranged in the first pixel rows PR1 to the Nth pixel rows PRN and the (2N+1)th pixel rows PR2N+1 to the 3Nth pixel rows PR3N, arranged in the (M+1)th pixel column PCM+1 to the 2Mth pixel column PC2M and the (3M+1)th pixel column PC3M+1 to the 4Mth pixel column PC4M. Furthermore, in the second cycle following the first cycle within each of the (N+1) level time HTN+1 to the 2N level time HT2N and the (3N+1) level time HT3N+1 to the 4N level time HT4N, the pattern test circuit 260 may receive a first pattern test signal SPT1 with a conduction level, and may not receive a second pattern test signal SPT2 with a conduction level. Therefore, the pattern test circuit 260 may only provide a non-emit data voltage VNEM to pixels PX arranged in the first pixel column PC1 to the M pixel column PCM and the (2M+1) pixel column PC2M+1 to the 3M pixel column PC3M within the pixel rows PX arranged in the (N+1) pixel rows PRN+1 to the 2N pixel rows PR2N and the (3N+1) pixel rows PR3N+1 to the 4N pixel rows PR4N. Therefore, the display panel 200 may respond to... Figure 9 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 10 The chess pattern image 300 shown is shown.

[0095] In other implementations, such as Figure 11As shown, in the second period following the first period within each of the first horizontal time HT1 to the Nth horizontal time HTN and the (2N+1)th horizontal time HT2N+1 to the 3Nth horizontal time HT3N, the pattern test circuit 260 may receive a first pattern test signal SPT1 with a conduction level, and may not receive a second pattern test signal SPT2 with a conduction level. Therefore, the pattern test circuit 260 may only provide the non-transmit data voltage VNEM to the pixels PX arranged in the first pixel rows PR1 to the Nth pixel rows PRN and the (2N+1)th pixel rows PR2N+1 to the 3Nth pixel rows PR3N, and the pixels PX arranged in the first pixel columns PC1 to the Mth pixel columns PCM and the (2M+1)th pixel columns PC2M+1 to the 3Mth pixel columns PC3M. Furthermore, in the second cycle following the first cycle within each of the (N+1) level time HTN+1 to the 2N level time HT2N and the (3N+1) level time HT3N+1 to the 4N level time HT4N, the pattern test circuit 260 may receive a second pattern test signal SPT2 with a conduction level, and may not receive a first pattern test signal SPT1 with a conduction level. Therefore, the pattern test circuit 260 may only provide a non-emit data voltage VNEM to pixels PX arranged in the (N+1) pixel rows PRN+1 to 2N pixel rows PR2N and the (3N+1) pixel rows PR3N+1 to 4N pixel rows PR4N, arranged in the (M+1) pixel columns PCM+1 to 2M pixel columns PC2M and the (3M+1) pixel columns PC3M+1 to 4M pixel columns PC4M. Therefore, the display panel 200 may respond to... Figure 11 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 12 Image 350 of the chess pattern shown.

[0096] As described above, in the display panel 200 according to the embodiment, the light emission test circuit 220 can provide an emission data voltage VEM to the pixel PX, and the pattern test circuit 260 can provide a non-emission data voltage VNEM to a portion of the pixel PX. Therefore, the display panel 200 according to the embodiment can display chess pattern images 300 and 350 in a cell state, and thus a pattern test can be performed on the display panel 200 in the cell state.

[0097] Figure 13 This is a schematic diagram showing a display panel according to an embodiment. Figure 14 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment. Figure 15 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment. Figure 16 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment, and Figure 17 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0098] refer to Figure 13 According to an embodiment, the display panel 400 may include first data lines DL1 to Lth data lines DLL (where L can be an integer greater than 0) arranged in first pixel columns PC1 to Lth pixel columns PCL, a plurality of pixels PX, a light emission test circuit 420, and a pattern test circuit 460. In some embodiments, although not in Figure 13 As shown in the figure, the display panel 400 may also include open circuit and short circuit test circuits, crack detection circuits, single-chip test circuits, etc.

[0099] The pattern test circuit 460 may include a non-emission data voltage line VNEML that transmits the non-emission data voltage VNEM, and in response to a first pattern test signal SPT1, connects the non-emission data voltage line VNEML to the (K+1) data line DLK+1, the (K+2) data line DLK+2, the (LK-1) data line DLL-K-1, and the (LK) data line DLL-K-1 arranged in the (K+1) pixel column PCK+1, the (K+2) pixel column PCK+2, the (LK-1) pixel column PCL-K-1, and the (LK) pixel column PCL-K. The data line DLL-K is connected to a plurality of first pattern test transistors PTT1 and a non-emit data voltage line VNEML in response to a second pattern test signal SPT2. The non-emit data voltage line VNEML is connected to a plurality of second pattern test transistors PTT2 arranged in the first pixel column PC1 to the Kth pixel column PCK and the (L-K+1)th data line DLL-K+1 to the Lth data line DLL arranged in the (L-K+1)th pixel column PCL-K+1 to the Lth pixel column PCL, wherein K can be an integer greater than 0 and less than L / 2.

[0100] The display panel 400 may include a first pixel row PR1, ..., a Q-th pixel row PRQ, a (Q+1)-th pixel row PRQ+1, a (Q+2)-th pixel row PRQ+2, ..., a (PQ-1)-th pixel row PRP-Q-1, a (PQ)-th pixel row PRP-Q, a (P-Q+1)-th pixel row PRP-Q+1, ..., a P-th pixel row PRP, where P can be an integer greater than 0. For example... Figure 14 and Figure 16As shown, the light emission test circuit 420 can receive a light emission test signal SLT with a conduction level (e.g., low level) during a first cycle within each of the following levels assigned to the first pixel row PR1 to the P-th pixel row PRP: first horizontal time HT1, ..., Q-th horizontal time HTQ, (Q+1)-th horizontal time HTQ+1, (Q+2)-th horizontal time HTQ+2, ..., (PQ-1)-th horizontal time HTP-Q-1, (PQ)-th horizontal time HTP-Q+1, ..., P-th horizontal time HTP. Therefore, the light emission test circuit 420 can provide the transmit data voltage VEM to all pixels PX.

[0101] In some implementations, such as Figure 14 As shown, in each of the first level times HT1, ..., Q level times HTQ and (P-Q+1) level times HTP-Q+1, ..., P level times HTP (where Q is an integer greater than 0 and less than P / 2), the pattern test circuit 460 may not receive either the first pattern test signal SPT1 or the second pattern test signal SPT2, which have a conduction level. Therefore, the non-transmit data voltage VNEM may not be provided to the pixels PX arranged in the first pixel rows PR1, ..., Q pixel rows PRQ and (P-Q+1) pixel rows PRP-Q+1, ..., P pixel rows PRP. Furthermore, in the second period following the first period within each of the (Q+1) level time HTQ+1, (Q+2) level time HTQ+2, ..., (PQ-1) level time HTP-Q-1 and (PQ) level time HTP-Q in the first level time HT1 to the P level time HTP, the pattern test circuit 460 may receive the first pattern test signal SPT1 with a conduction level, and may not receive the second pattern test signal SPT2 with a conduction level. Therefore, the pattern test circuit 460 can provide a non-emit data voltage VNEM only to the pixels PX arranged in the (Q+1) pixel row PRQ+1, the (Q+2) pixel row PRQ+2, ..., the (PQ-1) pixel row PRP-Q-1 and the (PQ) pixel row PRP-Q, and the pixels PX arranged in the (K+1) pixel column PCK+1, the (K+2) pixel column PCK+2, ..., the (LK-1) pixel column PCL-K-1 and the (LK) pixel column PCL-K. The display panel 400 can respond to Figure 14 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 15 The outer line image 500 shown is shown.

[0102] In other implementations, such as Figure 16 As shown, in the second cycle following the first cycle within each of the first horizontal time HT1, ..., the Q-th horizontal time HTQ and the (P-Q+1)-th horizontal time HTP-Q+1, ..., the P-th horizontal time HTP, the pattern test circuit 460 can receive both the first pattern test signal SPT1 and the second pattern test signal SPT2, which have a conduction level. Therefore, the non-transmit data voltage VNEM can be provided to all pixels PX arranged in the first pixel row PR1, ..., the Q-th pixel row PRQ and the (P-Q+1)-th pixel row PRP-Q+1, ..., the P-th pixel row PRP. Furthermore, in the second cycle following the first cycle within each of the (Q+1) level times HTQ+1, (Q+2) level times HTQ+2, ..., (PQ-1) level times HTP-Q-1 and (PQ) level times HTP-Q in the first level time HT1 to the P level time HTP, the pattern test circuit 460 may receive a second pattern test signal SPT2 with a conduction level, and may not receive a first pattern test signal SPT1 with a conduction level. Therefore, the pattern test circuit 460 may only provide the non-transmit data voltage VNEM to the pixels PX arranged in the first pixel columns PC1 to K pixel columns PCK and the (L-K+1) pixel columns PCL-K+1 to L pixel columns PCL in the (Q+1) pixel row PRQ+1, the (Q+2) pixel row PRQ+2, ..., the (PQ-1) pixel row PRP-Q-1 and the (PQ) pixel row PRP-Q. Therefore, the display panel 400 can respond to Figure 16 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 17 Image 550 of the central region shown.

[0103] As described above, in the display panel 400 according to the embodiment, the light emission test circuit 420 can provide the emitted data voltage VEM to the pixel PX, and the pattern test circuit 460 can provide the non-emitted data voltage VNEM to a portion of the pixel PX. Therefore, the display panel 400 according to the embodiment can display an outer line image 500 or a central area image 550 in a cell state, and thus a pattern test can be performed on the display panel 400 in the cell state.

[0104] Figure 18 This is a schematic diagram showing a display panel according to an embodiment. Figure 19 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment. Figure 20 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment. Figure 21 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment, and Figure 22 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0105] refer to Figure 18 According to an embodiment, the display panel 600 may include first data lines DL1 to Lth data lines DLL arranged in first pixel columns PC1 to Lth pixel columns PCL, a plurality of pixels PX, a light emission test circuit 620, and a pattern test circuit 660. In some embodiments, although not in Figure 18 As shown in the figure, the display panel 600 may also include open-circuit and short-circuit test circuits, crack detection circuits, single-chip test circuits, etc.

[0106] The pattern test circuit 660 may include a non-emission data voltage line VNEML that transmits the non-emission data voltage VNEM, a plurality of first pattern test transistors PTT1 that connect the non-emission data voltage line VNEML to the first data lines DL1 to DLL / 2 arranged in the first pixel column PC1 to the (L / 2) pixel column PCL / 2 in response to a first pattern test signal SPT1, and a plurality of second pattern test transistors PTT2 that connect the non-emission data voltage line VNEML to the (L / 2+1) data lines DLL / 2+1 to the L data line DLL arranged in the (L / 2+1) pixel column PCL / 2+1 to the L pixel column PCL in response to a second pattern test signal SPT2.

[0107] Display panel 600 may include first pixel row PR1 to P-th pixel row PRP. For example... Figure 19 and Figure 21 As shown, the light emission test circuit 620 can receive a light emission test signal SLT with a conduction level (e.g., low level) during a first cycle within each of the first horizontal time HT1 to the P-th horizontal time HTP allocated to the first pixel row PR1 to the P-th pixel row PRP. Therefore, the light emission test circuit 620 can provide the transmit data voltage VEM to all pixels PX.

[0108] In some implementations, such as Figure 19 As shown, in the second period following the first period within each of the first horizontal time HT1 to the Pth horizontal time HTP, the pattern test circuit 660 can receive a first pattern test signal SPT1 with a conduction level, and can not receive a second pattern test signal SPT2 with a conduction level. Therefore, the pattern test circuit 660 can provide a non-emit data voltage VNEM only to pixels PX arranged in the first pixel column PC1 to the (L / 2)th pixel column PCL / 2. Therefore, the display panel 600 can respond to... Figure 19 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 20 The right region image 700 is shown.

[0109] In other implementations, such as Figure 21 As shown, in the second period following the first period within each of the first horizontal time HT1 to the Pth horizontal time HTP, the pattern test circuit 660 can receive a second pattern test signal SPT2 with a conduction level, and can not receive the first pattern test signal SPT1 with a conduction level. Therefore, the pattern test circuit 660 can provide a non-emission data voltage VNEM only to pixels PX arranged in the (L / 2+1)th pixel column PCL / 2+1 to the Lth pixel column PCL. Therefore, the display panel 600 can respond to... Figure 21 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state. Figure 22 The left region image 750 is shown.

[0110] As described above, in the display panel 600 according to the embodiment, the light emission test circuit 620 can provide the emitted data voltage VEM to the pixel PX, and the pattern test circuit 660 can provide the non-emitted data voltage VNEM to a portion of the pixel PX. Therefore, the display panel 600 according to the embodiment can display the right region image 700 or the left region image 750 in a cell state, and thus a pattern test can be performed on the display panel 600 in the cell state.

[0111] Figure 23 This is a schematic diagram showing a display panel according to an embodiment. Figure 24 This is a schematic timing diagram illustrating the operation of the display panel according to an embodiment, and Figure 25 This is a schematic diagram illustrating a patterned image displayed on a display panel according to an embodiment.

[0112] refer to Figure 23 According to an embodiment, the display panel 800 may include first data lines DL1 to Lth data lines DLL arranged in first pixel columns PC1 to Lth pixel columns PCL, a plurality of pixels PX, a light emission test circuit 820, and a pattern test circuit 860. In some embodiments, although not in Figure 23 As shown in the figure, the display panel 800 may also include open circuit and short circuit test circuits, crack detection circuits, single-chip test circuits, etc.

[0113] The pattern test circuit 860 may include a non-emission data voltage line VNEML that transmits the non-emission data voltage VNEM, a second data line DL2 to the (M+1)th data line arranged in the second pixel column PC2 to the (M+1)th pixel column, and a plurality of data lines DL2M+2 to the (3M+1)th data lines arranged in the (2M+2)th pixel column PC2M+2 to the (3M+1)th pixel column. The first pattern test transistor PTT1 and, in response to the second pattern test signal SPT2, a plurality of second pattern test transistors PTT2 connect the non-emitting data voltage line VNEML to the (M+2) data lines DLM+2 to (2M+1) in the (M+2) pixel column PCM+2 to the (2M+1) pixel column and the (3M+2) data line DL3M+2 to (L-1) in the (3M+2) pixel column PC3M+2 to the (L-1) pixel column. Therefore, the pattern test circuit 860 may not include a pattern test transistor that connects the non-emitting data voltage line VNEML to the first data line DL1 and the Lth data line DLL arranged in the first pixel column PC1 and the Lth pixel column PCL.

[0114] The display panel 800 may include a first pixel row PR1, a second pixel row PR2, ..., a (N+2)th pixel row PRN+2, ..., a (2N+2)th pixel row PR2N+2, ..., a (3N+2)th pixel row PR3N+2, ..., and a Pth pixel row PRP. For example... Figure 24As shown, the light emission test circuit 820 can receive a light emission test signal SLT with a conduction level (e.g., low level) during the first cycle of each of the first horizontal time HT1, second horizontal time HT2, ..., (N+2)th horizontal time HTN+2, ..., (2N+2)th horizontal time HT2N+2, ..., (3N+2)th horizontal time HT3N+2, ..., and Pth horizontal time HTP assigned to the first pixel row PR1 to the P-th pixel row PRP. Therefore, the light emission test circuit 820 can provide the transmit data voltage VEM to all pixels PX. Furthermore, the pattern test circuit 860 can receive a first pattern test signal SPT1 with a conduction level in the second cycle after the first cycle within each of the second horizontal time HT2 to the (N+1)th horizontal time and the (2N+2)th horizontal time HT2N+2 to the (3N+1)th horizontal time; it can receive a second pattern test signal SPT2 with a conduction level in the second cycle after the first cycle within each of the (N+2)th horizontal time HTN+2 to the (2N+1)th horizontal time and the (3N+2)th horizontal time HT3N+2 to the (P-1)th horizontal time; and it can not receive either the first pattern test signal SPT1 or the second pattern test signal SPT2 during the first horizontal time HT1 and the P-th horizontal time HTP. Therefore, the display panel 800 can respond to... Figure 24 The light emission test signal SLT, the first pattern test signal SPT1, and the second pattern test signal SPT2 shown in the diagram are displayed in the cell state as follows: Figure 25 Image 890, which is a combination of a chess pattern image and an outer line image, is shown.

[0115] Figure 26 This is a flowchart illustrating a method for performing a pattern test on a display panel according to an embodiment.

[0116] refer to Figure 1 and Figure 26 In the pattern testing method for display panel 100 according to an embodiment, the initial brightness of display panel 100 can be measured (S910). In some embodiments, the initial brightness of display panel 100 can be measured when all pixels PX of display panel 100 emit light based on emission data voltage VEM.

[0117] The light emission test circuit 120 can provide the emitted data voltage VEM to a plurality of pixels PX, and the pattern test circuit 160 can provide the non-emitted data voltage VNEM to a portion of the pixels PX that have received the emitted data voltage VEM. Therefore, the pixels PX can display a pattern image for a specific time period (e.g., approximately 10 minutes to approximately 1 hour) (S930). According to the embodiment, the pattern image can be (but is not limited to)... Figure 10 and Figure 12 The chess pattern image shown Figure 15 The outer line image shown Figure 17 The central region image shown Figure 20 The right region image shown Figure 22 The left region image shown or Figure 25 The image shown is a combination of a chess pattern and an outer line image.

[0118] After a period of time, the final brightness of the display panel 100 can be measured (S950). In some embodiments, the final brightness of the display panel 100 can be measured when all pixels PX of the display panel 100 emit light based on the emission data voltage VEM.

[0119] Whether the display panel 100 is defective can be determined based on the brightness difference between the initial brightness and the final brightness (S970). For example, if the brightness difference between the initial brightness and the final brightness is greater than or equal to a reference brightness difference, it can be determined that the display panel 100 is defective. In some embodiments, this can be performed in the unit state before the data driver 190 is connected to the display panel 100. Figure 26 The pattern testing method shown. Furthermore, in some embodiments, during the execution... Figure 26 Before or after the pattern testing method shown, the display panel 100 in the unit state can be further subjected to light emission testing, open circuit and short circuit testing, etc. Furthermore, during the execution... Figure 26 After the pattern testing method shown, the display panel 100 can be connected to the data drive 190.

[0120] Figure 27 This is a schematic block diagram illustrating a display device according to an embodiment.

[0121] refer to Figure 27 The display device 1000 may include a display panel 1010 containing a plurality of pixels PX, a data driver 1030 that provides a data signal DS to the pixels PX, a gate driver 1050 that provides a gate signal GS to the pixels PX, and a controller 1070 that controls the data driver 1030 and the gate driver 1050.

[0122] The display panel 1010 may include pixels (PX), a light emission test circuit 1012, and a pattern test circuit 1014. During the manufacture of the display device 1000, the light emission test circuit 1012 and the pattern test circuit 1014 can be used to perform light emission tests and / or pattern tests. After the manufacture of the display device 1000, the light emission test circuit 1012 and the pattern test circuit 1014 may not be operated. According to an embodiment, the display panel 1010 may be... Figure 1 Display panel 100 Figure 8 Display panel 200 Figure 13 Display panel 400, Figure 18 Display panel 600, Figure 23 A display panel 800 or similar display panel. In some embodiments, although not in Figure 27 As shown in the figure, the display panel 1010 may also include open circuit and short circuit test circuits, crack detection circuits, single-chip test circuits, etc.

[0123] Data driver 1030 can provide data signal DS to pixel PX based on output image data ODAT and data control signal DCTRL received from controller 1070. In some embodiments, data control signal DCTRL may include (but is not limited to) output data enable signal, level start signal, and load signal. In some embodiments, data driver 1030 and controller 1070 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, data driver 1030 and controller 1070 may be implemented as separate integrated circuits.

[0124] The gate driver 1050 can provide a gate signal GS to the pixel PX based on a gate control signal GCTRL received from the controller 1070. In some embodiments, the gate control signal GCTRL may include (but is not limited to) a start signal and a clock signal. Furthermore, in some embodiments, such as Figure 27 As shown, the gate driver 1050 may be integrated or formed in the display panel 1010. In other embodiments, the gate driver 1050 may be implemented using one or more integrated circuits.

[0125] Controller 1070 (e.g., a timing controller) can receive input image data IDAT and control signal CTRL from an external processor (e.g., an application processor (“AP”), a graphics processing unit (“GPU”), or a graphics card). In some implementations, the control signal CTRL may include (but is not limited to) a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 1070 can generate output image data ODAT, a data control signal DCTRL, and a gate control signal GCTRL based on the input image data IDAT and the control signal CTRL. Controller 1070 can control data driver 1030 by providing output image data ODAT and data control signal DCTRL to data driver 1030, and can control gate driver 1050 by providing gate control signal GCTRL to gate driver 1050.

[0126] Figure 28This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0127] refer to Figure 28 Electronic device 1100 may include processor 1110, memory device 1120, storage device 1130, input / output (“I / O”) device 1140, power supply 1150, and display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0128] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be connected to other components via address buses, control buses, data buses, etc. In some embodiments, processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0129] Memory device 1120 may store data for the operation of electronic device 1100. For example, memory device 1120 may include at least one non-volatile memory device (such as erasable programmable read-only memory (“EPROM”) device, electrically erasable programmable read-only memory (“EEPROM”) device, flash memory device, phase-change random access memory (“PRAM”) device, resistive random access memory (“RRAM”) device, nanofloating gate memory (“NFGM”) device, polymer random access memory (“PoRAM”) device, magnetic random access memory (“MRAM”) device, ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as dynamic random access memory (“DRAM”) device, static random access memory (“SRAM”) device, mobile dynamic random access memory (“Mobile DRAM”) device, etc.).

[0130] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be input devices such as a keyboard, keypad, mouse, touchscreen, etc., and output devices such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0131] In the manufacturing process of display device 1160, the light emission test circuit of the display panel can provide emission data voltage to multiple pixels, and the pattern test circuit of the display panel can provide non-emission data voltage to a portion of the pixels. Therefore, the display panel included in display device 1160 according to the embodiment can display a pattern image in a cell state, and thus a pattern test can be performed on the display panel in the cell state.

[0132] This disclosure can be applied to any electronic device 1100, including display device 1160. For example, this disclosure can be applied to mobile phones, smartphones, virtual reality (“VR”) devices, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0133] The above description is an example of the technical features of this disclosure, and those skilled in the art will be able to make various modifications and variations. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0134] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirit within the equivalent scope is included within the scope of this disclosure.

Claims

1. A display panel comprising: a plurality of data lines; a plurality of pixels connected to the plurality of data lines; an emission test circuit that supplies emission data voltages to the plurality of pixels through the plurality of data lines; and a pattern test circuit that supplies non-emission data voltages to a portion of the plurality of pixels through the plurality of data lines after the emission data voltages are supplied to the plurality of pixels, so that the plurality of pixels display a pattern image. 2.The display panel according to claim 1, wherein the emission test circuit supplies the emission data voltages to the plurality of pixels arranged in a pixel row in a first period within a horizontal time allocated to the pixel row, and the pattern test circuit supplies the non-emission data voltages to a portion of the plurality of pixels arranged in the pixel row in a second period after the first period within the horizontal time. the emission test circuit comprises:

3. The display panel of claim 1, wherein, an emission data voltage line that transmits the emission data voltages; and a plurality of emission test transistors that connect the emission data voltage line to the plurality of data lines in response to an emission test signal. 4.The display panel according to claim 1, wherein the plurality of pixels include red pixels arranged in a first pixel column, green pixels arranged in a second pixel column, and blue pixels arranged in a third pixel column, and the emission test circuit comprises: a red emission data voltage line that transmits red emission data voltages to the red pixels; a green emission data voltage line that transmits green emission data voltages to the green pixels; a blue emission data voltage line that transmits blue emission data voltages to the blue pixels; a first emission test transistor that connects the red emission data voltage line to a data line arranged in the first pixel column among the plurality of data lines in response to an emission test signal; a second emission test transistor that connects the green emission data voltage line to a data line arranged in the second pixel column among the plurality of data lines in response to the emission test signal; and a third emission test transistor that connects the blue emission data voltage line to a data line arranged in the third pixel column among the plurality of data lines in response to the emission test signal. 5.The display panel according to claim 1, wherein the plurality of pixels include: red pixels, green pixels, blue pixels, and green pixels arranged in a first pixel row and arranged in a first pixel column, a second pixel column, a third pixel column, and a fourth pixel column, respectively; and blue pixels, green pixels, red pixels, and green pixels arranged in a second pixel row adjacent to the first pixel row and arranged in the first pixel column, the second pixel column, the third pixel column, and the fourth pixel column, respectively, and the emission test circuit comprises: a red emission data voltage line that transmits red emission data voltages; a green emission data voltage line that transmits green emission data voltages; a blue emission data voltage line that transmits blue emission data voltages; ​ a first-first emission test transistor connecting the red emission data voltage line to a data line arranged in the first pixel column among the plurality of data lines in response to a first emission test signal; a first-second emission test transistor connecting the blue emission data voltage line to the data line arranged in the first pixel column among the plurality of data lines in response to a second emission test signal; a second emission test transistor connecting the green emission data voltage line to a data line arranged in the second pixel column among the plurality of data lines in response to a third emission test signal; a third-first emission test transistor connecting the blue emission data voltage line to a data line arranged in the third pixel column among the plurality of data lines in response to the first emission test signal; a third-second emission test transistor connecting the red emission data voltage line to the data line arranged in the third pixel column among the plurality of data lines in response to the second emission test signal; and a fourth emission test transistor connecting the green emission data voltage line to a data line arranged in the fourth pixel column among the plurality of data lines in response to the third emission test signal.

6. The display panel of claim 5, wherein, the emission test circuit receives the first emission test signal and the third emission test signal in a first horizontal time for the first pixel row, and receives the second emission test signal and the third emission test signal in a second horizontal time for the second pixel row.

7. The display panel of claim 1, wherein, the pattern test circuit includes: a non-emission data voltage line conveying the non-emission data voltage; a plurality of first pattern test transistors connecting the non-emission data voltage line to a portion of the plurality of data lines in response to a first pattern test signal; and a plurality of second pattern test transistors connecting the non-emission data voltage line to a remaining portion of the plurality of data lines in response to a second pattern test signal.

8. The display panel of claim 7, wherein the emission test circuit receives an emission test signal in a first period of each horizontal time, and the pattern test circuit receives one of the first pattern test signal and the second pattern test signal in a second period after the first period of the each horizontal time.

9. The display panel of claim 1, wherein the plurality of data lines include: first data lines to Mth data lines arranged in first pixel columns to Mth pixel columns, respectively; (M+1)th data lines to 2Mth data lines arranged in (M+1)th pixel columns to 2Mth pixel columns, respectively; (2M+1)th data lines to 3Mth data lines arranged in (2M+1)th pixel columns to 3Mth pixel columns, respectively; and (3M+1)th data lines to 4Mth data lines arranged in (3M+1)th pixel columns to 4Mth pixel columns, respectively, M is an integer greater than 0, and the pattern test circuit includes: a non-emission data voltage line conveying the non-emission data voltage; a plurality of first pattern test transistors connecting the non-emission data voltage line to the first data line to the Mth data line and the (2M+1)th data line to the 3Mth data line in response to a first pattern test signal; and a plurality of second pattern test transistors connecting the non-emission data voltage line to the (M+1)th data line to the 2Mth data line and the (3M+1)th data line to the 4Mth data line in response to a second pattern test signal.

10. The display panel according to claim 9, wherein the light emission test circuit receives a light emission test signal in a first period within each of a first horizontal time to an Nth horizontal time allocated to a first pixel row to an Nth pixel row, an (N+1)th horizontal time to a 2Nth horizontal time allocated to an (N+1)th pixel row to a 2Nth pixel row, a (2N+1)th horizontal time to a 3Nth horizontal time allocated to a (2N+1)th pixel row to a 3Nth pixel row, and an (3N+1)th horizontal time to a 4Nth horizontal time allocated to an (3N+1)th pixel row to a 4Nth pixel row, N is an integer greater than 0, the pattern test circuit receives the second pattern test signal in a second period after the first period within each of the first horizontal time to the Nth horizontal time and the (2N+1)th horizontal time to the 3Nth horizontal time, and receives the first pattern test signal in a second period after the first period within each of the (N+1)th horizontal time to the 2Nth horizontal time and the (3N+1)th horizontal time to the 4Nth horizontal time, and the pattern image is a chess pattern image.

11. The display panel according to claim 9, wherein the light emission test circuit receives a light emission test signal in a first period within each of a first horizontal time to an Nth horizontal time allocated to a first pixel row to an Nth pixel row, an (N+1)th horizontal time to a 2Nth horizontal time allocated to an (N+1)th pixel row to a 2Nth pixel row, a (2N+1)th horizontal time to a 3Nth horizontal time allocated to a (2N+1)th pixel row to a 3Nth pixel row, and an (3N+1)th horizontal time to a 4Nth horizontal time allocated to an (3N+1)th pixel row to a 4Nth pixel row, N is an integer greater than 0, the pattern test circuit receives the first pattern test signal in a second period after the first period within each of the first horizontal time to the Nth horizontal time and the (2N+1)th horizontal time to the 3Nth horizontal time, and receives the second pattern test signal in a second period after the first period within each of the (N+1)th horizontal time to the 2Nth horizontal time and the (3N+1)th horizontal time to the 4Nth horizontal time, and the pattern image is a chess pattern image.

12. The display panel according to claim 1, wherein the plurality of data lines include first to Lth data lines arranged in first to Lth pixel columns, L is an integer greater than 0, the pattern test circuit includes: a non-emission data voltage line that transmits the non-emission data voltage; a plurality of first pattern test transistors that connect the non-emission data voltage line to (K+1)th to (L-K)th data lines among the first to Lth data lines in response to a first pattern test signal; and a plurality of second pattern test transistors that connect the non-emission data voltage line to the first to Kth data lines and (L-K+1)th to Lth data lines among the first to Lth data lines in response to a second pattern test signal, and K is an integer greater than 0 and smaller than L / 2.

13. The display panel according to claim 12, wherein the display panel includes first to Pth pixel rows, P is an integer greater than 0, the light emission test circuit receives a light emission test signal in a first period within each of first to Pth horizontal times allocated to the first to Pth pixel rows, the pattern test circuit does not receive any one of the first pattern test signal and the second pattern test signal in each of the first to Qth horizontal times and (P-Q+1)th to Pth horizontal times among the first to Pth horizontal times, and receives the first pattern test signal in a second period after the first period within each of (Q+1)th to (P-Q)th horizontal times among the first to Pth horizontal times, Q is an integer greater than 0 and smaller than P / 2, and the pattern image is an outer line image.

14. The display panel according to claim 12, wherein the display panel includes first to Pth pixel rows, P is an integer greater than 0, the light emission test circuit receives a light emission test signal in a first period within each of first to Pth horizontal times allocated to the first to Pth pixel rows, the pattern test circuit receives both the first pattern test signal and the second pattern test signal in each of the first to Qth horizontal times and (P-Q+1)th to Pth horizontal times among the first to Pth horizontal times, and receives the second pattern test signal in a second period after the first period within each of (Q+1)th to (P-Q)th horizontal times among the first to Pth horizontal times, Q is an integer greater than 0 and smaller than P / 2, and the pattern image is a central region image.

15. The display panel according to claim 1, wherein the plurality of data lines include first to Lth data lines arranged in first to Lth pixel columns, respectively, L is an integer greater than 0, and the pattern test circuit includes: a non-emission data voltage line that transmits the non-emission data voltage; a non-emission data voltage line that carries the non-emission data voltage; a plurality of first pattern test transistors that connect the non-emission data voltage line to the first to (L / 2)th data lines among the first data line to the Lth data line in response to a first pattern test signal; and a plurality of second pattern test transistors that connect the non-emission data voltage line to the (L / 2+1)th to Lth data lines among the first data line to the Lth data line in response to a second pattern test signal.

16. The display panel of claim 15, wherein the light emission test circuit receives a light emission test signal in a first period in each horizontal time, the pattern test circuit receives the first pattern test signal in a second period after the first period in the each horizontal time, and the pattern image is a right area image.

17. The display panel of claim 15, wherein the light emission test circuit receives a light emission test signal in a first period in each horizontal time, the pattern test circuit receives the second pattern test signal in a second period after the first period in the each horizontal time, and the pattern image is a left area image.

18. The display panel of claim 1, further comprising: an open / short test circuit that alternately provides a first open / short test voltage and a second open / short test voltage to the plurality of data lines, wherein the non-emission data voltage is the first open / short test voltage of the open / short test circuit.

19. A method of performing a pattern test on a display panel, the method comprising: measuring an initial luminance of the display panel; displaying a pattern image by the plurality of pixels of the display panel for a period of time by providing an emission data voltage to the plurality of pixels using a light emission test circuit of the display panel and providing a non-emission data voltage to a portion of the plurality of pixels that have received the emission data voltage using a pattern test circuit of the display panel; measuring a final luminance of the display panel; and detecting whether the display panel is defective based on a luminance difference between the initial luminance and the final luminance.

20. An electronic device comprising: a processor that provides image data; and a display device that displays an image based on the image data, wherein the display device includes the display panel of claim 1. ​

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