Pixel, display device, and electronic apparatus

Abstract

The invention relates to a pixel, a display device and an electronic device. The pixel includes: a first transistor connected between a first power voltage terminal and a first node, and turned on and off by a first light emission control signal; a driving transistor connected in series with the first transistor and the light emitting element, and turned on and off by a signal applied to a gate terminal of the driving transistor; a second transistor connected between the data line and a second node connected to the gate terminal of the driving transistor, and turned on and off by the scan signal; a first capacitor connected between the first power voltage terminal and the first node; and a second capacitor connected between the first node and the second node.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0108062, filed on August 13, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] One or more embodiments relate to a pixel, a display apparatus including the pixel, and an electronic device including the pixel. BACKGROUND

[0004] A pixel emits light based on a data voltage, and includes a transistor (e.g., a thin film transistor (TFT)) that controls driving of the pixel. A display apparatus can display an image in a sequential emission method in which pixels sequentially emit light in order or in a simultaneous emission method in which all pixels simultaneously emit light after data writing is sequentially completed. SUMMARY

[0005] One or more embodiments include a pixel, and a display apparatus including the pixel. The problems to be solved by the disclosure are not limited to the problems mentioned above, and other problems and advantages of the disclosure not mentioned can be understood from the following description, and will be more clearly understood by embodiments of the disclosure. Also, it will be appreciated that the problems and advantages to be solved by the disclosure can be achieved by the means indicated in the claims and combinations thereof.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or can be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a pixel includes a first transistor connected between a first power voltage terminal and a first node, and the first transistor is turned on and off by a first light emission control signal; a driving transistor connected in series with the first transistor and a light emitting element, and the driving transistor is turned on and off by a signal applied to a gate terminal of the driving transistor; a second transistor connected between a data line and a second node connected to the gate terminal of the driving transistor, and the second transistor is turned on and off by a scan signal; a first capacitor connected between the first power voltage terminal and the first node; and a second capacitor connected between the first node and the second node.

[0008] In an embodiment, the pixel can further include a third transistor connected to the second node and a node between the driving transistor and the light emitting element; and a fourth transistor connected between the second node and an initialization voltage terminal, and the fourth transistor is turned on and off by an initialization scan signal.

[0009] In an embodiment, the third transistor can be turned on and off by an initialization scan signal or a compensation scan signal.

[0010] In an embodiment, the pixel can further include a fifth transistor connected between the first node and the driving transistor, and the fifth transistor can be turned on and off by a second light emission control signal.

[0011] In an embodiment, the pixel can further include a sixth transistor connected to an anode initialization voltage terminal and a node between the driving transistor and the light emitting element, and the sixth transistor can be turned on and off by a bypass scan signal, and a seventh transistor connected to an on-bias voltage terminal and the first node, and the seventh transistor can be turned on and off by the bypass scan signal.

[0012] In an embodiment, in the first period, the third transistor and the fourth transistor can be turned on, an initialization voltage can be supplied to the second node from the initialization voltage terminal, and a voltage obtained by adding a threshold voltage of the driving transistor to the initialization voltage can be applied to the first node.

[0013] In an embodiment, in the second period, the second transistor can be turned on, a data voltage can be supplied to the second node, and a voltage proportional to an amount of change in a voltage of the second node can be additionally applied to the first node.

[0014] In an embodiment, in the third period, the first transistor can be turned on, a first power voltage can be supplied to the first node, and a voltage proportional to an amount of change in a voltage of the first node can be additionally applied to the second node.

[0015] According to one or more embodiments, a display apparatus includes a display unit including a plurality of pixels, wherein each of the plurality of pixels is connected to a respective scan line among a plurality of scan lines, a respective light emission control line among a plurality of light emission control lines, and a respective data line among a plurality of data lines; a scan driver configured to supply a scan signal to each of the plurality of pixels through the respective scan line among the plurality of scan lines; a light emission control driver configured to supply a light emission control signal to each of the plurality of pixels through the respective light emission control line among the plurality of light emission control lines; a data driver configured to supply a data voltage to each of the plurality of pixels through the respective data line among the plurality of data lines; and a power supply unit configured to supply a first power voltage to each of the plurality of pixels, wherein each of the plurality of pixels includes a first transistor connected between a first power voltage terminal and a first node and turned on and off by a first light emission control signal included in the light emission control signal, a driving transistor connected in series to the first transistor and a light emitting element and turned on and off by a signal applied to a gate terminal of the driving transistor, a second transistor connected between a data line and a second node connected to the gate terminal of the driving transistor and turned on and off by the scan signal, a first capacitor connected between the first power voltage terminal and the first node, and a second capacitor connected between the first node and the second node.

[0016] In an embodiment, the power supply unit can be configured to supply an initialization voltage to each of the plurality of pixels, the scan driver can be configured to supply an initialization scan signal to each of the plurality of pixels, and each of the plurality of pixels can further include a third transistor connected to the second node and a node between the driving transistor and the light emitting element, and a fourth transistor connected between the second node and an initialization voltage terminal and turned on and off by the initialization scan signal.

[0017] In an embodiment, the scan driver can be further configured to supply a compensation scan signal to each of the plurality of pixels, and the third transistor can be turned on and off by the initialization scan signal or the compensation scan signal.

[0018] In an embodiment, the light emission control signal can further include a second light emission control signal, and each of the plurality of pixels can further include a fifth transistor connected between the first node and the driving transistor and turned on and off by the second light emission control signal.

[0019] In an embodiment, the power supply unit can further be configured to supply an anode initialization voltage and a turn-on bias voltage to each of the plurality of pixels, the scan driver can further be configured to supply a bypass scan signal to each of the plurality of pixels, and each of the plurality of pixels can further include: a sixth transistor connected to the anode initialization voltage terminal and a node between the driving transistor and the light emitting element, and the sixth transistor turned on and off by the bypass scan signal; and a seventh transistor connected to the turn-on bias voltage terminal and the first node, and the seventh transistor turned on and off by the bypass scan signal.

[0020] In an embodiment, in the first period, the third transistor and the fourth transistor can be turned on, an initialization voltage can be supplied to the second node, and a voltage obtained by adding a threshold voltage of the driving transistor to the initialization voltage can be applied to the first node.

[0021] In an embodiment, in the second period, the second transistor can be turned on, a data voltage can be supplied to the second node, and a voltage proportional to an amount of change in a voltage of the second node can be additionally applied to the first node.

[0022] In an embodiment, in the third period, the first transistor can be turned on, a first power voltage can be supplied to the first node, and a voltage proportional to an amount of change in a voltage of the first node can be additionally applied to the second node.

[0023] According to one or more embodiments, an electronic device includes a display apparatus that displays an image, and a processor that controls the display apparatus. The display apparatus includes a plurality of pixels, wherein each of the plurality of pixels is connected to a respective scan line among a plurality of scan lines, a respective light emission control line among a plurality of light emission control lines, and a respective data line among a plurality of data lines, wherein each of the plurality of pixels includes a first transistor connected between a first power voltage terminal and a first node, and the first transistor turned on and off by a first light emission control signal included in a light emission control signal, a driving transistor connected in series with the first transistor and a light emitting element, and the driving transistor turned on and off by a signal applied to a gate terminal of the driving transistor, a second transistor connected between the data line and a second node connected to the gate terminal of the driving transistor, and the second transistor turned on and off by a scan signal, a first capacitor connected between the first power voltage terminal and the first node, and a second capacitor connected between the first node and the second node.

[0024] In the electronic device, each of the plurality of pixels can further include a third transistor connected to the second node and a node between the driving transistor and the light emitting element, and a fourth transistor connected between the second node and an initialization voltage terminal, and the fourth transistor turned on and off by an initialization scan signal.

[0025] In the electronic device, each of the plurality of pixels can further include a fifth transistor connected between the first node and the driving transistor, and the fifth transistor is turned on and off by the second light emission control signal.

[0026] In the electronic device, each of the plurality of pixels can further include a sixth transistor connected to the anode initialization voltage terminal and a node between the driving transistor and the light emitting element, and the sixth transistor is turned on and off by the bypass scan signal; and a seventh transistor connected to the turn-on bias voltage terminal and the first node, and the seventh transistor is turned on and off by the bypass scan signal.

[0027] Further aspects, features, and advantages of aspects other than those described above will become apparent from the following drawings, claims, and detailed description of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment;

[0030] Figure 2 is a circuit diagram illustrating a structure of a pixel in the related art;

[0031] Figure 3 is a circuit diagram illustrating a structure of a pixel according to an embodiment;

[0032] Figure 4 is a timing chart of signals for driving a pixel of Figure 3 ;

[0033] Figure 5 is a circuit diagram for describing an operation of elements of a pixel of Figure 3 in an initialization period;

[0034] Figure 6 is a circuit diagram for describing an operation of elements of a pixel of Figure 3 in a data write period;

[0035] Figure 7 is a circuit diagram for describing an operation of elements of a pixel of Figure 3 in an anode initialization period;

[0036] Figure 8 is a circuit diagram for describing an operation of elements of a pixel of Figure 3 in an emission period;

[0037] Figure 9 is a circuit diagram showing a structure of a pixel according to another embodiment;

[0038] Figure 10 is a circuit diagram showing a structure of a pixel according to another embodiment;

[0039] Figure 11 is a circuit diagram showing a structure of a pixel according to another embodiment;

[0040] Figure 12 is a timing chart of signals for driving a pixel of Figure 11 ;

[0041] Figure 13 is a circuit diagram showing a structure of a pixel according to another embodiment;

[0042] Figure 14 is a timing chart of signals for driving a pixel of Figure 13 ;

[0043] Figure 15 is a circuit diagram showing a structure of a pixel according to another embodiment;

[0044] Figure 16 is a timing chart of signals for driving a pixel of Figure 15 ; and

[0045] Figure 17 is a block diagram showing an electronic device according to an embodiment. DETAILED DESCRIPTION

[0046] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0047] Because the present disclosure allows various changes and numerous embodiments, a specific embodiment will be shown in the drawings and described in detail in the written description. The effects and features of the present disclosure and the method of achieving the effects and features of the present disclosure will be apparent by referring to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0048] In the following embodiments, although terms such as "first", "second", etc. can be used to describe various elements, the elements are not necessarily limited to the above terms.

[0049] In the following embodiments, unless there is a clear different meaning in the context, an expression used in the singular includes an expression in the plural.

[0050] In the following embodiments, it should be understood that terms such as "include" and "have" are intended to indicate that there is existence of the features or elements disclosed in the present disclosure, and are not intended to exclude the possibility of one or more other features or elements being present or being additionally added.

[0051] It will be understood that when a unit, region, or element is referred to as being formed on another unit, region, or element, it can be directly or indirectly formed on the other unit, region, or element. That is, for example, there can be an intervening unit, region, or element.

[0052] In the following embodiments, unless the context clearly indicates otherwise, terms such as "connected" or "coupled" do not necessarily mean that two members are directly connected or directly coupled and / or fixedly connected or fixedly coupled, and do not exclude the possibility of another member interposed therebetween.

[0053] For ease of explanation, the size and thickness of elements (or components) in the drawings can be exaggerated. In other words, since the size and thickness of components shown in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0054] The present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. Like reference numerals can indicate like elements throughout the drawings and description, and a description thereof will not be repeated.

[0055] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment.

[0056] Referring to Figure 1 The display apparatus according to an embodiment can include a display unit 10 including a plurality of pixels PX11 to PXnm, a scan driver 20, a data driver 30, a light emission control driver 40, a power supply unit 50, and a controller 60.

[0057] In an embodiment, each of the plurality of pixels PX11 to PXnm can be connected to a corresponding one or more scan lines among the plurality of scan lines S1 to Sn, a corresponding one or more light emission control lines among the plurality of light emission control lines EM1 to EMn, and a corresponding one or more data lines among the plurality of data lines D1 to Dm, wherein the scan lines S1 to Sn, the light emission control lines EM1 to EMn, and the data lines D1 to Dm are connected to the display unit 10.

[0058] In an embodiment, although not directly shown in the display unit 10, Figure 1 In an embodiment, although not directly shown in the display unit 10, each of the plurality of pixels PX11 to PXnm can be connected to a power supply line connected to the display unit 10 to receive power (such as the first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage Vint) for operation of the pixel.

[0059] In an embodiment, the display unit 10 can include a plurality of pixels PX11, …, PX1m, …, PXn1, …, and PXnm arranged in a specific form (for example, in a matrix form).

[0060] In an embodiment, each of the plurality of pixels PX11 to PXnm can emit light having a specific brightness by a driving current supplied to the light emitting element according to a corresponding data voltage transmitted through the plurality of data lines D1 to Dm.

[0061] The display unit 10 can be referred to as a display panel. In the present disclosure, the display panel can be implemented as one of a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), an addressable mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD), and can also be implemented as other types of flat panel displays or flexible displays.

[0062] In an embodiment, the scan driver 20 can generate a scan signal corresponding to each pixel and transmit the scan signal corresponding to each pixel through a corresponding scan line among the plurality of scan lines S1 to Sn. That is, the scan driver 20 can transmit a scan signal to each of the plurality of pixels through a corresponding scan line among the plurality of scan lines S1 to Sn. For example, the scan driver 20 can receive a scan driving control signal SCS from the controller 60 to generate a plurality of scan signals, and can sequentially supply the generated scan signals to the plurality of scan lines S1 to Sn connected to a plurality of rows.

[0063] Although Figure 1Although not shown, in an embodiment, the scan driver 20 can generate and supply one or more types of scan signals. As a specific example, the scan driver 20 can generate and supply required scan signals, such as a first scan signal GW (see Figure 3 ), a second scan signal GI (or an initialization scan signal) (see Figure 3 ), a third scan signal GB (or a bypass scan signal) (see Figure 3 ), and a fourth scan signal GC (or a compensation scan signal) (see Figure 3 ), depending on the implementation or emission control method of the pixels. Accordingly, the plurality of scan lines S1 to Sn can include one or more types of scan lines, so that a scan line can be configured for each scan signal. Specifically, the first scan signal GW can be applied to each of the plurality of pixels PX11 to PXnm through a corresponding one of a plurality of first scan lines (not shown), the second scan signal GI can be applied to each of the plurality of pixels PX11 to PXnm through a corresponding one of a plurality of second scan lines (not shown), the third scan signal GB can be applied to each of the plurality of pixels PX11 to PXnm through a corresponding one of a plurality of third scan lines (not shown), and the fourth scan signal GC can be applied to each of the plurality of pixels PX11 to PXnm through a corresponding one of a plurality of fourth scan lines (not shown).

[0064] In an embodiment, the data driver 30 can transmit a data signal to each pixel through a corresponding one of a plurality of data lines D1 to Dm. For example, the data driver 30 can receive a data driving control signal DCS from the controller 60 and supply data signals corresponding to the plurality of data lines D1 to Dm connected to the plurality of pixels PX11 to PXnm included in each row, respectively.

[0065] In an embodiment, the light emission control driver 40 can be connected to a plurality of light emission control lines EM1 to EMn connected to the display unit 10 including the plurality of pixels PX11 to PXnm arranged in a matrix form. That is, the plurality of light emission control lines EM1 to EMn extending in the row direction of each of the plurality of pixels PX11 to PXnm and almost in parallel to each other can connect the plurality of pixels PX11 to PXnm and the light emission control driver 40 to each other.

[0066] In this embodiment, the light emission control driver 40 can generate a light emission control signal corresponding to each pixel and transmit the light emission control signal corresponding to each pixel through a plurality of light emission control lines EM1 to EMn. In response to the control of the light emission control signal, each pixel receiving the light emission control signal can be controlled to emit light according to the image data signal. That is, the operation of the light emission control transistor included in each pixel can be controlled in response to the light emission control signal transmitted through the corresponding light emission control line, and therefore, the light-emitting element connected to the light emission control transistor can emit light with a brightness corresponding to the driving current of the data signal or may not emit light with a brightness corresponding to the driving current of the data signal.

[0067] In this embodiment, two light emission control signals can be supplied to each pixel. That is, the emission of a pixel can be controlled based on two types of light emission control signals.

[0068] In this embodiment, the power supply unit 50 may supply a first power voltage ELVDD, a second power voltage ELVSS, an initialization voltage Vint, and an anode initialization voltage VAINT (see [link to embodiment]) to each pixel of the display unit 10. Figure 3 ) or the on-bias voltage VOBS (see Figure 3 For example, the first power voltage ELVDD can be a specific high-level voltage, and the second power voltage ELVSS can be a voltage lower than the first power voltage ELVDD or ground. For example, the initialization voltage Vint can be set to a voltage value equal to or lower than the second power voltage ELVSS.

[0069] The voltage values ​​of the first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage Vint are not particularly limited, but these voltage values ​​can be set or controlled according to the power control signal PCS transmitted from the controller 60.

[0070] In an embodiment, the controller 60 can convert a plurality of image signals externally transmitted into a plurality of image data signals (or data signals) DATA, and transmit the plurality of image data signals DATA to the data driver 30. Further, the controller 60 can receive a vertical synchronization signal (not shown), a horizontal synchronization signal (not shown), and a clock signal (not shown), and can generate and transmit control signals for controlling driving of the scan driver 20, the light emission control driver 40, and the data driver 30, respectively. That is, the controller 60 can generate and transmit a scan driving control signal SCS for controlling the scan driver 20, a light emission driving control signal ECS for controlling the operation of the light emission control driver 40, and a data driving control signal DCS for controlling the data driver 30. Further, the controller 60 can generate a power control signal PCS for controlling the operation of the power supply unit 50, and transmit the generated power control signal PCS to the power supply unit 50.

[0071] In an embodiment, the display device can further include a reference voltage generator (not shown). For example, the reference voltage generator can generate a reference voltage based on a control signal received from the controller 60. The reference voltage generator can provide the reference voltage to the data driver 30. The reference voltage can have a value corresponding to each data signal DATA. The reference voltage generator can be disposed within the controller 60 or within the data driver 30.

[0072] In an embodiment, the data driver 30 can receive the data driving control signal DCS from the controller 60, and can receive the reference voltage from the reference voltage generator. The data driver 30 can convert the data signal DATA into a data voltage in an analog form by using the reference voltage. For example, the data driver 30 can output the data voltage to the data line.

[0073] Figure 2 FIG. 1 is a circuit diagram illustrating a structure of a pixel in the related art.

[0074] Referring to Figure 2 , the pixel can include a light emitting element and a pixel circuit for controlling emission or non-emission of the light emitting element. Figure 2 The pixel circuit shown in FIG. 1 can include nine transistors (i.e., a first transistor T1 to a ninth transistor T9) and two capacitors (i.e., a first capacitor C1 and a second capacitor C2). The second transistor T2 can include a first-second sub-transistor T2-1 and a second-second sub-transistor T2-2, the third transistor T3 can include a first-third sub-transistor T3-1 and a second-third sub-transistor T3-2, the fourth transistor T4 can include a first-fourth sub-transistor T4-1 and a second-fourth sub-transistor T4-2, and the fifth transistor T5 can include a first-fifth sub-transistor T5-1 and a second-fifth sub-transistor T5-2.

[0075] Reference Figure 2 The first capacitor C1 and the second capacitor C2 can be arranged between the gate terminal of the first transistor T1 and the terminal receiving the first power voltage ELVDD. The first capacitor C1 can be a storage capacitor for storing the data voltage Vdata of the pixel, and the second capacitor C2 can be a holding capacitor for helping to maintain the data and stabilize the pixel until the data switches to data for the next frame.

[0076] When viewed from the gate terminal of the first transistor T1 towards the terminal receiving the first power voltage ELVDD, the first capacitor C1 and the second capacitor C2 are connected in series. Specifically, the first capacitor C1 is positioned between the terminal receiving the first power voltage ELVDD and the first node 201, and the second capacitor C2 is positioned between the first node 201 and the second node 202. As a result, the series connection of two capacitors between the gate terminal of the first transistor T1 and the terminal receiving the first power voltage ELVDD may adversely affect the driving characteristics.

[0077] To overcome the above problems, pixels (or pixel circuits) according to various embodiments are described below.

[0078] Figure 3 This is a circuit diagram illustrating the structure of a pixel according to an embodiment.

[0079] Reference Figure 3 According to the embodiment, a pixel may include nine transistors (i.e., driving transistor Tdr plus first transistors T1 to eighth transistors T8) and two capacitors (i.e., first capacitor C1 and second capacitor C2).

[0080] Reference Figure 3 The diagram illustrates a driving transistor Tdr, which is turned on and off by a signal applied to its gate terminal and configured to control the current emitted by a light-emitting element. In one embodiment, the gate terminal of the driving transistor Tdr may be connected to the drain terminal of a second transistor T2. The second transistor T2 may be connected to a data line configured to supply a data voltage Vdata to a pixel. The source terminal of the second transistor T2 may be connected to the data line. The second transistor T2 may be turned on and off by a first scan signal GW to control the supply of the data voltage Vdata.

[0081] Reference Figure 3In an embodiment, the first transistor T1 and the fifth transistor T5 can be connected in series with the driving transistor Tdr. Specifically, a drain terminal of the fifth transistor T5 can be connected to a source terminal of the driving transistor Tdr, a drain terminal of the first transistor T1 can be connected to a source terminal of the fifth transistor T5, and the first power voltage ELVDD can be supplied to a source terminal of the first transistor T1. The first transistor T1 can be turned on and off by the first light emission control signal EM1, and the fifth transistor T5 can be turned on and off by the second light emission control signal EM2.

[0082] Referring to Figure 3 The pixel according to an embodiment can include a first capacitor C1 having a first end (or a first terminal) connected to a terminal receiving the first power voltage ELVDD and a second end (or a second terminal) connected to a source terminal of the fifth transistor T5, and a second capacitor C2 having a first end (or a first terminal) connected to the source terminal of the fifth transistor T5 and a second end (or a second terminal) connected to a gate terminal of the driving transistor Tdr.

[0083] Referring to Figure 3 In an embodiment, the third transistor T3 turned on and off by the second scan signal GI and the fourth transistor T4 turned on and off by the second scan signal GI can be connected to the gate terminal of the driving transistor Tdr. Specifically, a source terminal of the third transistor T3 can be connected to the gate terminal of the driving transistor Tdr. Specifically, a drain terminal of the fourth transistor T4 can be connected to the gate terminal of the driving transistor Tdr. The initialization voltage VINT can be supplied to a source terminal of the fourth transistor T4.

[0084] Referring to Figure 3 In an embodiment, the eighth transistor T8 turned on and off by the first light emission control signal EM1 can be connected to the driving transistor Tdr. Specifically, a source terminal of the eighth transistor T8 can be connected to a drain terminal of the driving transistor Tdr. Further, the eighth transistor T8 can be connected to the third transistor T3. Specifically, the source terminal of the eighth transistor T8 can be connected to a drain terminal of the third transistor T3.

[0085] Referring to Figure 3 In an embodiment, the sixth transistor T6 turned on and off by the third scan signal GB can be connected to the eighth transistor T8. Specifically, a drain terminal of the sixth transistor T6 can be connected to a drain terminal of the eighth transistor T8. The anode initialization voltage VAINT can be supplied to a source terminal of the sixth transistor T6.

[0086] Referring to Figure 3In an embodiment, the light emitting element can be connected to the eighth transistor T8 and the sixth transistor T6. Specifically, an anode of the light emitting element can be connected to a drain terminal of the eighth transistor T8 and a drain terminal of the sixth transistor T6. A cathode of the light emitting element can be connected to a terminal that receives the second power voltage ELVSS.

[0087] Referring to Figure 2 In an embodiment, the seventh transistor T7 turned on and off by the third scan signal GB can be connected to the driving transistor Tdr. Specifically, a drain terminal of the seventh transistor T7 can be connected to a source terminal of the driving transistor Tdr. The on bias voltage VOBS can be supplied to a source terminal of the seventh transistor T7.

[0088] Unlike the pixel of Figure 3 , a first node 301 between the first capacitor C1 and the second capacitor C2 of the pixel according to the embodiment shown in Figure 3 may be connected to a drain terminal of the first transistor T1 (the first transistor T1 is turned on and off by the first light emission control signal EM1 and is configured to supply the first power voltage ELVDD), and a second node 302 between the second capacitor C2 and a gate terminal of the driving transistor Tdr can be connected to a drain terminal of the second transistor T2 (the second transistor T2 is turned on and off by the first scan signal GW and is configured to supply the data voltage Vdata).

[0089] Advantages or effects of the pixel according to the embodiment shown in Figures 5 to 8 may become more apparent from the description of the specific operations to be made with reference to Figure 4 .

[0090] Figure 3 is a timing chart of signals for driving Figure 4 the pixel.

[0091] Referring to Figure 3 , the changes of the signals (i.e., the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal GW, the second scan signal GI, and the third scan signal GB) applied to the pixel of Figure 4 during one unit period (e.g., a single frame period) are shown.

[0092] Referring to Figure 3 and in conjunction with Figures 5 to 8, one unit period can mainly include an initialization period TT1, a data write period TT2, an anode initialization period TT3, and an emission period TT4. The initialization period TT1 can be a period in which an initialization voltage VINT is applied to a gate terminal of a driving transistor Tdr of the pixel to initialize the driving transistor Tdr. The data write period TT2 can be a period in which a data voltage Vdata is applied to the gate terminal of the driving transistor Tdr of the pixel. The anode initialization period TT3 can be a period in which an anode initialization voltage VAINT is applied to an anode of the light emitting element. Also, the anode initialization period TT3 can be a period in which an on bias voltage VOBS is applied to a source terminal of the driving transistor Tdr of the pixel. The emission period TT4 can be a period in which a driving current of the pixel is applied by the driving transistor Tdr to the light emitting element to allow the light emitting element to emit light or not to emit light.

[0093] Hereinafter, referring to Figure 3 , the operation of each period of the pixel according to the embodiment shown in Figures 5 to 8 is described. In Figure 5 , a period in which elements are electrically connected and signals are transmitted and received is indicated by a dotted line.

[0094] Figure 3 is a circuit diagram for describing the operation of elements of the pixel in the initialization period. Figure 4

[0095] Referring to the values of signals in the initialization period TT1 of Figure 3 , it is shown that the second scan signal GI applied to the gate terminal of the third transistor T3 and the gate terminal of the fourth transistor T4 of Figure 3 , and the second light emission control signal EM2 applied to the gate terminal of the fifth transistor T5 of Figure 5 have a low voltage. Accordingly, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned on.

[0096] Referring to Figure 3 , the fourth transistor T4 can be turned on so that the initialization voltage VINT supplied to the source terminal of the fourth transistor T4 can be applied to the gate terminal of the driving transistor Tdr. Accordingly, the value of the second voltage V2 applied to the second node 302 of Figure 5 may be VINT. When the initialization voltage VINT is applied to the gate terminal of the driving transistor Tdr, the driving transistor Tdr can also be turned on.

[0097] Referring to Figure 3 ​, the third transistor T3 is turned on, so that the initialization voltage VINT supplied to the source terminal of the third transistor T3 can be supplied to the drain terminal of the driving transistor Tdr. The driving transistor Tdr is turned on, and the value of the voltage of the drain terminal of the driving transistor Tdr is VINT, and thus when the value of the threshold voltage of the driving transistor Tdr is Vth, the value of the voltage of the source terminal of the driving transistor Tdr can be VINT+Vth. Thus, the first voltage V1 applied to the first node 301 can be VINT+Vth. Figure 6

[0098] In summary, after the initialization period TT1, the value of the first voltage V1 can be VINT+Vth, and the value of the second voltage V2 can be VINT. Thus, the value of the voltage stored in the second capacitor C2 can be Vth.

[0099] Figure 3 is a circuit diagram for describing the operation of the elements of the pixel of Figure 4 in the data write period.

[0100] Referring to the values of the signals in the data write period TT2 of Figure 6 , it is shown that the first scan signal GW applied to the gate terminal of the second transistor T2 has a low voltage. Thus, the second transistor T2 can be turned on.

[0101] Referring to Figure 7 , the second transistor T2 is turned on, so that the data voltage Vdata can be applied to the gate terminal of the driving transistor Tdr. Thus, the value of the second voltage V2 can be Vdata.

[0102] When the value of the second voltage V2 changes from VINT to Vdata, a voltage proportional to the amount of change of the second voltage V2 (i.e., Vdata-VINT) can be additionally applied to the first voltage V1. Specifically, the value of the first voltage V1 can change by (Vdata-VINT)×(C2 / (C1+C2)). Here, C2 / (C1+C2) can be understood to be generated by the first capacitor C1 and the second capacitor C2 explained as being connected in series.

[0103] Thus, after the data write period TT2, the first voltage V1 can be VINT+Vth+(Vdata-VINT)×(C2 / (C1+C2)), and the second voltage V2 can be Vdata.

[0104] Figure 3 is a circuit diagram for describing the operation of the elements of the pixel of Figure 4 in the anode initialization period.

[0105] Referring to Figure 7 ​The value of the signal during the anode initialization period TT3 shows that the third scan signal GB applied to the gate terminals of the sixth transistor T6 and the seventh transistor T7 has a low voltage. Therefore, the sixth transistor T6 and the seventh transistor T7 can be turned on.

[0106] Reference Figure 7 The sixth transistor T6 is turned on, allowing the anode initialization voltage VAINT to be applied to the anode of the light-emitting element.

[0107] Reference Figure 4 The seventh transistor T7 is turned on, allowing the on-bias voltage VOBS to be applied to the source terminal of the driving transistor Tdr.

[0108] In summary, during the anode initialization period TT3 (see...) Figure 8 After that, the value of the first voltage V1 can be VINT + Vth + (Vdata - VINT) × (C2 / (C1 + C2)), and the value of the second voltage V2 can be Vdata. That is to say, even after the anode initialization period TT3 has passed, both the first voltage V1 and the second voltage V2 after the data writing period TT2 are maintained.

[0109] Figure 3 It is used to describe Figure 4 The circuit diagram of the operation of the pixel element during the emission period.

[0110] Reference Figure 8 The signal values ​​during the transmission period TT4 show that the first optical emission control signal EM1 applied to the gate terminals of the first transistor T1 and the eighth transistor T8, and the second optical emission control signal EM2 applied to the gate terminal of the fifth transistor T5, have low voltages. Therefore, the first transistor T1, the fifth transistor T5, and the eighth transistor T8 can be turned on.

[0111] Reference Figure 3 When the first transistor T1 is turned on, the value of the first voltage V1 can become ELVDD. That is, during the transmission period TT4, Figure 8 The first node 301 acts as the first power voltage ELVDD, and therefore the first node 301 can not be described as a single node in the circuit.

[0112] When the first voltage V1 changes from VINT+Vth+(Vdata-VINT)×(C2 / (C1+C2)) to ELVDD, a voltage proportional to the change in the first voltage V1 can be additionally applied to the second voltage V2. Specifically, the value of the second voltage V2 can be changed to ELVDD-(VINT+Vth+(Vdata-VINT)×(C2 / (C1+C2))).

[0113] Therefore, in summary, in the emission period TT4, the value of the first voltage V1 can be ELVDD, and the value of the second voltage V2 can be Vdata+ELVDD-(VINT+Vth+(Vdata-VINT)×(C2 / (C1+C2)).

[0114] Referring to Figure 8 When the fifth transistor T5 is turned on, the first power voltage ELVDD can be applied to the source terminal of the driving transistor Tdr.

[0115] Referring to Figure 3 When the eighth transistor T8 is turned on, the current generated by the driving transistor Tdr can be supplied to the light emitting element, and the light emitting element can emit light or not emit light.

[0116] The size of the driving current (I d ) depending on the voltage size of the terminal of the driving transistor Tdr can be calculated by the following Equation 1.

[0117] [Equation 1]

[0118]

[0119] As described above, in the emission period TT4, the value of Vs is ELVDD as the value of the first voltage V1, and the value of Vg is Vdata+ELVDD-(VINT+Vth+(Vdata-VINT)×(C2 / (C1+C2)) as the value of the second voltage V2, so Vsg and (Vsg-Vth) 2 can be calculated as in the following Equation 2. Here, Vs denotes a source voltage, Vg denotes a gate voltage, Vsg denotes a source-gate voltage, μ denotes a carrier mobility, and A denotes a device constant (i.e., a width-length ratio multiplied by an oxide capacitance).

[0120] [Equation 2]

[0121]

[0122] That is, according to Equation 2, in calculating (Vsg-Vth) 2 in the pixel according to the embodiment, Vth is eliminated, so that Vth compensation can be performed.

[0123] As described above, according to the pixel of the embodiment, when the value of the first voltage V1 becomes ELVDD, the gate terminal of the driving transistor Tdr is directly connected to the terminal receiving the first power voltage ELVDD as direct current (DC) power through a capacitor (i.e., the second capacitor C2), and thus reduces the factors that may affect the gate terminal of the driving transistor Tdr, and accordingly, the gate terminal of the driving transistor Tdr can be designed to be robust.

[0124] The following describes the basis based on Figure 9 Various embodiments of the pixels in the embodiments.

[0125] Figure 9 This is a circuit diagram illustrating the structure of a pixel according to another embodiment.

[0126] Figure 3 The first node 901 and the second node 902 can correspond to Figure 3 The first node is 301 and the second node is 302.

[0127] Although Figure 4 The first node 301 of the pixel shown is in the emission period TT4 (see...) Figure 9 The first node 301 is connected to a terminal that receives the first power voltage ELVDD, but in various embodiments, the first node 301 may be designed to receive another DC power.

[0128] Reference Figure 9 ,according to Figure 3 The pixels of the embodiment and according to Figure 9 The difference between the pixels in the embodiment is that the first terminal of the first capacitor C1 is connected to the terminal that receives the conduction bias voltage VOBS, instead of the terminal that receives the first power voltage ELVDD.

[0129] Specifically, according to Figure 3 In the pixel of the embodiment, the first terminal of the first capacitor C1 can be connected to the terminal receiving the conduction bias voltage VOBS, and the second terminal of the first capacitor C1 can be connected to the drain terminal of the first transistor T1 and the source terminal of the fifth transistor T5 as a first node 901. (This is in accordance with...) Figure 9 Similar to the pixels in the embodiment, the first end of the second capacitor C2 can be connected to the first node 901, and the second end of the second capacitor C2 can be connected to the gate terminal of the driving transistor Tdr, the drain terminal of the second transistor T2, the source terminal of the third transistor T3, and the drain terminal of the fourth transistor T4 as the second node 902.

[0130] Apart from Figure 2In addition to the embodiments shown, in the pixels of this disclosure, the first node 901 may be designed to be connected to a terminal that receives DC power (such as a terminal that receives the initialization voltage VINT, a terminal that receives the anode initialization voltage VAINT, and a terminal that receives the reference voltage VREF (see [reference]). Figure 10 The first capacitor C1 is located between the first node 901 and the terminal receiving DC power.

[0131] Figure 10 This is a circuit diagram illustrating the structure of a pixel according to another embodiment.

[0132] Figure 3 The first node 1001 and the second node 1002 can correspond to Figure 10 The first node is 301 and the second node is 302.

[0133] In this embodiment, the first node 1001 can be connected to different DC lines (e.g., terminals receiving DC power) via multiple capacitors. Specifically, refer to... Figure 11 The first node 1001 can be connected to both a first capacitor C1 having a terminal connected to a terminal that receives a first power voltage ELVDD and a third capacitor C3 having a terminal connected to a terminal that receives a conduction bias voltage VOBS.

[0134] Figure 11 This is a circuit diagram illustrating the structure of a pixel according to another embodiment.

[0135] Figure 3 The first node 1101 and the second node 1102 can correspond to Figure 3 The first node is 301 and the second node is 302.

[0136] In the embodiments, it is also possible to operate without a conduction bias voltage VOBS (see [link to embodiment]). Figure 3 ) and / or the third scan signal GB (see Figure 11 Drive pixels in the case of ). See reference Figure 3 There are no transistors, such as those turned on and off by the on-bias voltage VOBS (e.g., Figure 3 The seventh transistor (T7) is a transistor. Furthermore... Figure 11 The sixth transistor T6 is turned on and off by the third scan signal GB, while... Figure 12 In one embodiment, the sixth transistor T6 can be designed to be turned on and off by the second scan signal GI.

[0137] Figure 11 It is used for driving Figure 12 The timing diagram of the signal of the pixel.

[0138] Reference Figure 11, the changes of the signals (i.e., the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal GW, and the second scan signal GI) applied to the pixel of Figure 11 during one unit period (e.g., a single frame period) are shown.

[0139] In the embodiment of Figure 3 , because the third scan signal GB is not applied (see Figure 12 ), the anode initialization of the light emitting element can be controlled by the second scan signal GI, and specifically, in Figures 3 to 8 , the anode initialization can be performed in a period in which the second scan signal GI has a low voltage.

[0140] The remaining operations for the present embodiment can be analogous to the operations described above with reference to Figure 13 .

[0141] Figure 13 is a circuit diagram showing a structure of a pixel according to another embodiment.

[0142] Figure 3 The first node 1301 and the second node 1302 of Figure 3 may correspond to the first node 301 and the second node 302 of .

[0143] In the embodiment, unlike the embodiment of Figure 14 in which the third transistor T3 is turned on and off by the second scan signal GI, the third transistor T3 can be turned on and off by the fourth scan signal GC.

[0144] Figure 13 is a timing chart of the signals for driving the pixel of Figure 14 .

[0145] Referring to Figure 13 , the changes of the signals (i.e., the first light emission control signal EM1, the second light emission control signal EM2, the first scan signal GW, the second scan signal GI, the third scan signal GB, and the fourth scan signal GC) applied to the pixel of Figure 14 during one unit period (e.g., a single frame period) are shown.

[0146] Referring to Figure 14 , except that there is the fourth scan signal GC in addition to the second scan signal GI, the period in which the fourth scan signal GC has a low voltage is also the same as the period in which the second scan signal GI has a low voltage, and thus the operations in Figures 3 to 8 may be applied in the same manner as the operations described above with reference to Figure 15 .

[0147] Figure 15is a circuit diagram showing a structure of a pixel according to another embodiment.

[0148] Figure 3 The first node 1501 and the second node 1502 of the pixel 1500 can correspond to Figure 3 the first node 301 and the second node 302 of the pixel 300.

[0149] In an embodiment, the first light emission control signal EM1 (see Figure 3 ) and the second light emission control signal EM2 (see Figure 3 ) can be the same light emission control signal (e.g., a light emission control signal EM). Unlike the pixel 300 of the embodiment of the pixel 300 including the fifth transistor T5 turned on and off by the second light emission control signal EM2, in the pixel according to the embodiment of the pixel 1500, the second light emission control signal EM2 is not applied, and a transistor (such as the fifth transistor T5) turned on and off by the second light emission control signal EM2 is not included. Figure 15 Figure 3 Figure 15

[0150] In an embodiment, the pixel can include the first transistor T1 and the tenth transistor T10 turned on and off by the light emission control signal EM.

[0151] In an embodiment, the source terminal of the first transistor T1 can be connected to a terminal receiving the first power voltage ELVDD, and the drain terminal of the first transistor T1 can be connected to the source terminal of the driving transistor Tdr.

[0152] In an embodiment, the source terminal of the tenth transistor T10 can be connected to a terminal receiving the first power voltage ELVDD, and the drain terminal of the tenth transistor T10 can be connected to the first node 1501 between the first capacitor C1 and the second capacitor C2.

[0153] In an embodiment, the source terminal of the ninth transistor T9 turned on and off by the second scan signal GI can be connected to the first node 1501, and the drain terminal of the ninth transistor T9 can be connected to the source terminal of the driving transistor Tdr.

[0154] As for the remaining transistors, Figure 3 the driving transistor Tdr, the second transistor T2, the third transistor T3, and the fourth transistor T4 of the pixel 1500 can correspond to Figure 15 the driving transistor Tdr, the second transistor T2, the third transistor T3, and the fourth transistor T4 of the pixel 300, respectively. Figure 3 the eighth transistor T8, the sixth transistor T6, and the seventh transistor T7 of the pixel 1500 can correspond to Figure 16 the eighth transistor T8, the sixth transistor T6, and the seventh transistor T7 of the pixel 300, respectively. ​​​

[0155] Figure 15 is a timing chart of signals for driving Figure 16 a pixel.

[0156] Referring to Figure 15 , changes in signals (i.e., a light emission control signal EM, a first scan signal GW, a second scan signal GI, and a third scan signal GB) applied to a pixel of Figure 16 during one unit period (e.g., a single frame period) are shown.

[0157] Referring to Figure 3 , there are differences in that only the light emission control signal EM exists, instead of the second light emission control signal EM2 (see Figures 3 to 8 ). Except for these differences, the operations described above with reference to Figure 3 can be similarly applied to the operation of the pixel within a single unit period.

[0158] Although each of the transistors included in the pixel according to various embodiments has been described as a single-gate transistor as described above, each of the transistors included in the pixel according to various embodiments can be a double-gate transistor having two gate terminals. For example, the second transistor T2 (see Figure 3 ), the third transistor T3 (see Figure 3 ), and / or the fourth transistor T4 (see Figure 3 ) can be a double-gate transistor.

[0159] Each of the transistors included in the pixel according to various embodiments as described above can be a four-terminal transistor.

[0160] Some of the transistors included in the pixel according to various embodiments as described above can be oxide transistors. For example, the second transistor T2 and the eighth transistor T8 (see Figure 17 ) can be transistors using an oxide semiconductor.

[0161] The pixel according to various embodiments as described above can be designed such that the first node becomes DC power (e.g., a first power voltage ELVDD) in an emission period, and the gate terminal of the driving transistor receives the DC power only through one capacitor, without being affected by the series connection of the capacitors, thereby eliminating the risk of image quality degradation while ensuring a high-speed driving timing.

[0162] The transistor included in the pixel according to various embodiments as described above has been described based on a P-type metal oxide semiconductor field effect transistor (MOSFET), but a design changing the transistor from a P-type MOSFET to an N-type MOSFET is also included in various embodiments described in the disclosure, and a person skilled in the art will easily understand such a design change.

[0163] Figure 17 is a block diagram illustrating an electronic device according to an embodiment. Figure 1 An electronic device 1000 including a display module 1100, a processor 1200, a memory 1300, and a power module 1400 is depicted. The electronic device 1000 can further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, and a universal serial bus (USB) device, etc., or communicating with other systems.

[0164] The processor 1200 can perform a specific computation or task. According to an embodiment, the processor 1200 can be a microprocessor or a central processing unit (CPU), etc. The processor 1200 can be connected to other components through an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1200 can also be connected to an extension bus such as a peripheral component interconnect (PCI) bus. The processor 1200 can control the display module 1100.

[0165] The processor 1200 can control the display module 1100. In an embodiment, the processor 1200 can distribute image data and controller signals provided to the controller 60 of the display module 1100 to the display module 1100. ​

[0166] The memory 1300 can store data required for the operation of the electronic device 1000. For example, the memory 1300 can include a non-volatile storage device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM); and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory, or a mobile DRAM.

[0167] Each of the above-described embodiments can be independently implemented, but the structure of each embodiment can be applied in conjunction with other embodiments.

[0168] ​It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached drawings, it will be evident for those skilled in the art that various changes and modifications in form and details can be made therein without departing from the spirit and scope of the appended claims.

[0169] The specific implementations described in the embodiments are examples and do not limit the scope of the embodiments. Furthermore, if there is no specific mention of a specific term such as "essential", "important", etc., it can not be an essential component of the application of the present disclosure.

[0170] The display device and the pixel disclosed herein can be used in various products such as portable electronic devices including a mobile phone, a smart phone, a tablet PC, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC), and a television (TV), a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device, etc. According to an embodiment, the display device and the pixel of the present disclosure can also be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD). According to an embodiment, the display device and the pixel of the present disclosure can also be used in a dashboard of a car, a center panel or a central information display (CID) of a dashboard of a car, an in-dash display of a car that replaces a side mirror, and a display screen of a car that is arranged at the rear side of a front seat to be used as an entertainment device for rear seat passengers.

[0171] The use of the term "and / or" (and / or similar references such as "at least one of", "one, and / or the other of", and "one or the other of") for an item can refer to the item being selected from the group consisting of three possibilities. Further, when ranges are described in the embodiments, (unless there is a contrary statement) the disclosure includes application of the individual values within that range and is the same as describing each individual value that makes up the range in the detailed description. Finally, unless it is expressly stated to the contrary, or there is a contrary statement of sequence of operation of the acts constituting a method according to the embodiments, acts described in an embodiment can be performed in any order appropriate to the application. Embodiments are not necessarily limited to the order of acts described in the above description. The use of all examples or illustrative terms in the embodiments is merely to illustrate the embodiments and the scope of the embodiments is not limited to the examples or illustrative terms unless limited by the claims. Furthermore, those skilled in the art will recognize that various modifications, combinations, and changes in the details can be made therein without departing from the spirit and scope of the appended claims, within the scope of the appended claims or the scope of equivalents of the appended claims.

Claims

1. A pixel, wherein, The pixel includes: a first transistor connected between a first power voltage terminal and a first node, and turned on and off by a first light emission control signal; a drive transistor connected in series with the first transistor and a light emitting element, and turned on and off by a signal applied to a gate terminal of the drive transistor; a second transistor connected between a data line and a second node connected to the gate terminal of the drive transistor, and turned on and off by a scan signal; a first capacitor connected between the first power voltage terminal and the first node; and a second capacitor connected between the first node and the second node.

2. The pixel of claim 1, wherein, The pixel further includes: a third transistor connected to the second node and a node between the drive transistor and the light emitting element; and a fourth transistor connected between the second node and an initialization voltage terminal, and turned on and off by an initialization scan signal.

3. The pixel of claim 2, wherein, The third transistor is turned on and off by the initialization scan signal or a compensation scan signal.

4. The pixel of claim 1, wherein, The pixel further includes a fifth transistor connected between the first node and the drive transistor, and turned on and off by a second light emission control signal.

5. The pixel of claim 1, wherein, The pixel further includes: a sixth transistor connected to an anode initialization voltage terminal and a node between the drive transistor and the light emitting element, and turned on and off by a bypass scan signal; and a seventh transistor connected to an on-bias voltage terminal and the first node, and turned on and off by the bypass scan signal.

6. The pixel of claim 2, wherein, In a first period, the third transistor and the fourth transistor are turned on, and an initialization voltage is supplied from the initialization voltage terminal to the second node, and a voltage obtained by adding a threshold voltage of the drive transistor to the initialization voltage is applied to the first node.

7. The pixel of claim 6, wherein, In a second period, the second transistor is turned on, and a data voltage is supplied to the second node, and a voltage proportional to an amount of change in voltage of the second node is additionally applied to the first node.

8. The pixel of claim 6, wherein, In a third period, the first transistor is turned on, and a first power voltage is supplied to the first node, and a voltage proportional to an amount of change in voltage of the first node is additionally applied to the second node.

9. A display device, wherein, The display device includes: a display unit including a plurality of pixels, wherein each of the plurality of pixels is connected to a respective scan line among a plurality of scan lines, a respective light emission control line among a plurality of light emission control lines, and a respective data line among a plurality of data lines; a scan driver configured to supply a scan signal to each of the plurality of pixels through a respective scan line among the plurality of scan lines; a light emission control driver configured to supply a light emission control signal to each of the plurality of pixels through a respective light emission control line among the plurality of light emission control lines; a data driver configured to supply a data voltage to each of the plurality of pixels through a corresponding data line among the plurality of data lines; and a power supply unit configured to supply a first power voltage to each of the plurality of pixels, wherein each of the plurality of pixels includes: a first transistor connected between a first power voltage terminal and a first node, and turned on and off by a first light emission control signal included in the light emission control signal; a driving transistor connected in series with the first transistor and a light emitting element, and turned on and off by a signal applied to a gate terminal of the driving transistor; a second transistor connected between the data line and a second node connected to the gate terminal of the driving transistor, and turned on and off by the scan signal; a first capacitor connected between the first power voltage terminal and the first node; and a second capacitor connected between the first node and the second node.

10. The display device of claim 9, wherein, the power supply unit is configured to supply an initialization voltage to each of the plurality of pixels, the scan driver is configured to supply an initialization scan signal to each of the plurality of pixels, and each of the plurality of pixels further includes: a third transistor connected to the second node and a node between the driving transistor and the light emitting element; and a fourth transistor connected between the second node and an initialization voltage terminal, and turned on and off by the initialization scan signal.

11. The display device of claim 10, wherein, the scan driver is further configured to supply a compensation scan signal to each of the plurality of pixels, and the third transistor is turned on and off by the initialization scan signal or the compensation scan signal.

12. The display device of claim 9, wherein, the light emission control signal further includes a second light emission control signal, and each of the plurality of pixels further includes: a fifth transistor connected between the first node and the driving transistor, and turned on and off by the second light emission control signal.

13. The display device of claim 9, wherein, the power supply unit is further configured to supply an anode initialization voltage and an on bias voltage to each of the plurality of pixels, the scan driver is further configured to supply a bypass scan signal to each of the plurality of pixels, and each of the plurality of pixels further includes: a sixth transistor connected to an anode initialization voltage terminal and a node between the driving transistor and the light emitting element, and turned on and off by the bypass scan signal; and a seventh transistor connected to an on bias voltage terminal and the first node, and turned on and off by the bypass scan signal.

14. The display device of claim 10, wherein, in a first period, the third transistor and the fourth transistor are turned on, and the initialization voltage is supplied to the second node, and a voltage obtained by adding a threshold voltage of the driving transistor to the initialization voltage is applied to the first node.

15. The display device of claim 14, wherein, In the second period, the second transistor is turned on, and the data voltage is supplied to the second node, and a voltage proportional to the amount of change in the voltage of the second node is additionally applied to the first node.

16. The display device of claim 14, wherein, In the third period, the first transistor is turned on, and the first power voltage is supplied to the first node, and a voltage proportional to the amount of change in the voltage of the first node is additionally applied to the second node.

17. An electronic device, comprising: The electronic device includes: a display device that displays an image; and a processor that controls the display device, wherein the display device includes a plurality of pixels, wherein each of the plurality of pixels is connected to a respective scan line among a plurality of scan lines, a respective light emission control line among a plurality of light emission control lines, and a respective data line among a plurality of data lines, wherein each of the plurality of pixels includes: a first transistor connected between a first power voltage terminal and a first node, and turned on and off by a first light emission control signal included in a light emission control signal; a driving transistor connected in series with the first transistor and a light emitting element, and turned on and off by a signal applied to a gate terminal of the driving transistor; a second transistor connected between the data line and a second node connected to the gate terminal of the driving transistor, and turned on and off by a scan signal; a first capacitor connected between the first power voltage terminal and the first node; and a second capacitor connected between the first node and the second node.

18. The electronic device of claim 17, wherein, Each of the plurality of pixels further includes: a third transistor connected to the second node and a node between the driving transistor and the light emitting element; and a fourth transistor connected between the second node and an initialization voltage terminal, and turned on and off by an initialization scan signal.

19. The electronic device of claim 17, wherein, Each of the plurality of pixels further includes a fifth transistor connected between the first node and the driving transistor, and turned on and off by a second light emission control signal.

20. The electronic device of claim 17, wherein, Each of the plurality of pixels further includes: a sixth transistor connected to an anode initialization voltage terminal and a node between the driving transistor and the light emitting element, and turned on and off by a bypass scan signal; and a seventh transistor connected to a turn-on bias voltage terminal and the first node, and turned on and off by the bypass scan signal. a seventh transistor connected to a turn-on bias voltage terminal and the first node, and turned on and off by the bypass scan signal.

Images