A driving and biasing circuit for a pixel array

Abstract

The application discloses a driving and biasing circuit of a pixel array, the pixel array is divided into M*N same square sub-arrays, each pixel in each sub-array is provided with a driving branch, the driving branch comprises a current mirror PMOS tube MP0 and a switch PMOS tube MP1, the gate of the current mirror PMOS tube MP0 is connected with a bias voltage VBP, the gate of the switch PMOS tube MP1 is connected with a switch SW signal output by a data latch and switch control circuit, and the drain of the switch PMOS tube MP1 is connected with a pixel; the biasing branch comprises a first-stage current mirror array and a second-stage current mirror array connected, the first-stage current mirror array is used for copying a reference current IREF into M*N parts and outputting an IBIAS current; one second-stage current mirror array is arranged in each sub-array and is used for receiving the IBIAS current and outputting a bias voltage VBP, and the bias voltage VBP is connected with the driving branch in each sub-array.

Description

Technical Field

[0001] This invention relates to the field of OLED microdisplay driving control technology, and in particular to a driving and biasing circuit for a pixel array. Background Technology

[0002] Micro-LED display technology, with its superior performance, possesses a significant competitive advantage in the high-end display market and is ushering in unprecedented development opportunities. The biggest advantage of Micro-LED displays lies in their ability to achieve extremely high brightness, making them promising for applications in micro-projection and smart lighting. However, high brightness implies high power consumption and high current density, which places higher demands on the design of display driver chips.

[0003] The photoelectric characteristics of Micro-LEDs significantly limit their driving methods. The external quantum efficiency and emission wavelength of Micro-LEDs vary with current. Especially at lower currents, the external quantum efficiency drops sharply, and the wavelength shift between red and green Micro-LEDs is noticeable. Furthermore, compared to OLEDs and other light-emitting devices, Micro-LEDs have a steeper current-voltage characteristic, making it difficult to precisely control brightness using voltage. This means that PAM (Pulse Amplitude Modulation) technology, which controls grayscale by controlling the current flowing through the light-emitting device, is not well-suited for driving Micro-LED displays. However, under larger, constant currents, PWM (Pulse Width Modulation) technology, which controls grayscale by controlling the emission time, is a viable solution. This constant high-current PWM driving method allows both the energy conversion efficiency and emission wavelength of the Micro-LED to remain at their optimal levels.

[0004] Because of the parasitic resistance between the power supply line and the common cathode line of the Micro-LED (usually a negative voltage power supply line), a significant voltage drop often occurs in high-current applications. In a basic PWM drive structure with only one switching MOSFET, this power supply voltage drop directly affects the voltage difference between the positive and negative terminals of the Micro-LED, causing severe display unevenness. Current solutions typically involve adding a current mirror MOSFET between the switching MOSFET and the power supply line to minimize the impact of the common cathode negative voltage drop on the voltage difference between the positive and negative terminals of the Micro-LED. However, this method remains sensitive to anode voltage drop and introduces other factors that cause display unevenness, such as mismatch in the current mirror MOSFET. Summary of the Invention

[0005] Technical objective: To address the deficiencies in existing technologies, this invention discloses a driving and biasing circuit for a pixel array. The biasing branch is divided into two stages, which reduces the number of copies made by a single-stage current mirror. At the same time, the first-stage current mirror array is always kept on, which can improve the response speed of pixel switching and improve display uniformity.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0007] A driving and biasing circuit for a pixel array, comprising a driving branch and a biasing branch; The pixel array is divided into M×N identical square subarrays. Each pixel in each subarray has a driving branch, which includes a current mirror PMOS transistor MP0 and a switching PMOS transistor MP1. The source of the current mirror PMOS transistor MP0 is connected to the pixel area power supply VLED, and the gate of the current mirror PMOS transistor MP0 is connected to the bias voltage VBP. The bias voltage VBP is transmitted and output through the bias branch. The drain of the current mirror PMOS transistor MP0 is connected to the source of the switching PMOS transistor MP1. The gate of the switching PMOS transistor MP1 is connected to the switching signal SW output by the data latch and switching control circuit. The drain of the switching PMOS transistor MP1 is connected to the pixel and is used to control whether the pixel emits light. The bias branch includes a first-stage current mirror array and a second-stage current mirror array that are connected. The first-stage current mirror array is used to copy the reference current IREF into M×N copies and output the IBIAS current. Each subarray has a second-stage current mirror array, which is used to receive the IBIAS current and output the bias voltage VBP. The bias voltage VBP is connected to the drive branch in each subarray, thereby controlling each pixel in each subarray.

[0008] Furthermore, the first-stage current mirror array includes a reference circuit and M×N replica circuits; the reference circuit is connected to the reference current IREF, and each replica circuit has the same structure. The reference circuit and each replica circuit form a common-source common-gate current mirror. Each replica circuit replicates the reference current and controls the final IBIAS current output to be 1 to 4 times the current of IREF.

[0009] Furthermore, the reference circuit includes NMOS transistors MN3 to MN5; the drain of NMOS transistor MN4 is connected to the reference current IREF; the gate of NMOS transistor MN4 is connected to the drain of NMOS transistor MN4, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN5 is grounded; the drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is grounded, and the gate of NMOS transistor MN3 is connected to the enable signal EN.

[0010] Furthermore, the replication circuit includes: PMOS transistors MP2~MP4, NMOS transistors MN0~MN2, and NMOS transistors MN6~MN16; The gate of NMOS transistor MN6 is connected to the reference current IREF, and the drain of NMOS transistor MN6 outputs the IBIAS current; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN5 in the reference circuit, and the source of NMOS transistor MN7 is grounded. The drain of NMOS transistor MN8 outputs the IBIAS current; the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN9 is grounded; the gate of NMOS transistor MN8 is connected to the source of NMOS transistor MN0, the drain of NMOS transistor MN14, and the drain of PMOS transistor MP2; the drain of NMOS transistor MN0 is connected to the reference current IREF, and the gate of NMOS transistor MN0 is connected to the first control signal T0; the source of NMOS transistor MN14 is grounded, and the gate of NMOS transistor MN14 is connected to the first control signal T0; the source of PMOS transistor MP2 is connected to the reference current IREF, and the gate of PMOS transistor MP2 is connected to the first control signal T0. The drain of NMOS transistor MN10 outputs the IBIAS current; the source of NMOS transistor MN10 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN11 is grounded; the gate of NMOS transistor MN10 is connected to the source of NMOS transistor MN1, the drain of NMOS transistor MN15, and the drain of PMOS transistor MP3; the drain of NMOS transistor MN1 is connected to the reference current IREF, and the gate of NMOS transistor MN1 is connected to the second control signal T1; the source of NMOS transistor MN15 is grounded, and the gate of NMOS transistor MN15 is connected to the second control signal T1; the source of PMOS transistor MP3 is connected to the reference current IREF, and the gate of PMOS transistor MP3 is connected to the second control signal T1. The drain of NMOS transistor MN12 outputs the IBIAS current; the source of NMOS transistor MN12 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN13 is grounded; the gate of NMOS transistor MN12 is connected to the source of NMOS transistor MN2, the drain of NMOS transistor MN16, and the drain of PMOS transistor MP4; the drain of NMOS transistor MN2 is connected to the reference current IREF, and the gate of NMOS transistor MN2 is connected to the second control signal T1; the source of NMOS transistor MN16 is grounded, and the gate of NMOS transistor MN16 is connected to the second control signal T1; the source of PMOS transistor MP4 is connected to the reference current IREF, and the gate of PMOS transistor MP4 is connected to the second control signal T1.

[0011] Furthermore, the structure of the second-stage current mirror array includes PMOS transistors MP5~MP16 and NMOS transistors MN14~MN20; PMOS transistors MP5~MP8 are used to form a current mirror with the current mirror PMOS transistor MP0 in the driving branch of each sub-array, and PMOS transistors MP5~MP8 are reference transistors. The drain of each is connected to the IBIAS current output by the first-stage current mirror array, and the source of each is connected to the pixel area power supply VLED.

[0012] Furthermore, the gates of PMOS transistors MP5 are all connected to the first control unit, which includes NMOS transistors MN17 and PMOS transistors MP15-MP16. The gates of NMOS transistors MN17 and MP15 are connected to the enable signal EN. The source of NMOS transistor MN17 is connected to the drain of PMOS transistor MP15 and connected to the IBIAS current. The drain of NMOS transistor MN17 is connected to the source of PMOS transistor MP15 and to the gate of PMOS transistor MP5 and the source of PMOS transistor MP16. The drain of PMOS transistor MP16 is grounded, and the gate of PMOS transistor MP16 is connected to the enable signal EN. PMOS transistor MP5 remains on by default under the control of the enable signal EN, and its gate output bias voltage VBP.

[0013] Furthermore, the gates of PMOS transistors MP6 to MP8 are all connected to the second control unit; The second control unit structure corresponding to PMOS transistor MP6 includes NMOS transistor MN18, PMOS transistor MP9, and PMOS transistor MP12. The gates of NMOS transistor MN18 and PMOS transistor MP9 are connected to the first control signal T0. The source of NMOS transistor MN18 is connected to the drain of PMOS transistor MP9 and connected to the IBIAS current. The drain of NMOS transistor MN18 is connected to the source of PMOS transistor MP9 and connected to the gate of PMOS transistor MP6 and the drain of PMOS transistor MP12. The source of PMOS transistor MP12 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP12 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP7 includes NMOS transistor MN19, PMOS transistor MP10, and PMOS transistor MP13. The gates of NMOS transistor MN19 and PMOS transistor MP10 are connected to the second control signal T1. The source of NMOS transistor MN19 is connected to the drain of PMOS transistor MP10 and connected to the IBIAS current. The drain of NMOS transistor MN19 is connected to the source of PMOS transistor MP10 and connected to the gate of PMOS transistor MP7 and the drain of PMOS transistor MP13. The source of PMOS transistor MP13 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP13 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP8 includes NMOS transistor MN20, PMOS transistor MP11, and PMOS transistor MP14. The gates of NMOS transistor MN20 and PMOS transistor MP11 are connected to the second control signal T1. The source of NMOS transistor MN20 is connected to the drain of PMOS transistor MP11 and connected to the IBIAS current. The drain of NMOS transistor MN20 is connected to the source of PMOS transistor MP11 and connected to the gate of PMOS transistor MP8 and the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the pixel area power supply VLED, and the gate of PMOS transistor MP14 is connected to the second control signal T1.

[0014] Furthermore, the PMOS transistors MP5~MP8 and the current mirror PMOS transistor MP0 have the same dimensions.

[0015] Furthermore, each subarray is divided into a digital logic region and an analog current replication region; the switching PMOS transistor MP1 and the data latch and switching control circuit are located in the digital logic region, while the current mirror PMOS transistor MP0 is located in the analog current replication region; in each analog current replication region, the current mirror PMOS transistor MP0 and the replication PMOS transistors, namely PMOS transistors MP5~MP8, are centrally and symmetrically placed.

[0016] Beneficial effects: (1) In the driving and biasing circuit of a pixel array of the present invention, the addition of a current mirror PMOS structure in the driving branch makes the circuit have very low requirements for the load end. When the cathode voltage of the Micro-LED is low enough to enable the current mirror PMOS to work in the saturation region, the voltage drop of the cathode voltage and the deviation of the impedance of the Micro-LED itself will not have a significant impact on the current output of the pixel driving, which can greatly improve the display uniformity. (2) In the driving and biasing circuit of the pixel array of the present invention, the biasing branch is divided into two stages, which reduces the number of single-stage current mirror replications. At the same time, the first-stage current mirror array is always kept on, which can improve the response speed of the pixel switch and improve the display uniformity. (3) In the driving and biasing circuit of the pixel array of the present invention, the voltage drop of the power supply line gradually increases from the periphery to the center of the pixel array. The second-stage current mirror array in the biasing branch adopts a square grid partition, and the reference PMOS transistor and the replica PMOS transistor are located in the same partition small array. Compared with simple row and column partitioning, the influence of the power supply line voltage drop is greatly reduced, and the display uniformity is improved. Moreover, the current mirror PMOS transistors are not placed according to the actual position of the pixels in the square sub-array layout. Instead, all pixel circuits are scattered and arranged in partitions, which can make the current mirror PMOS transistors as concentrated as possible and the environment in which they are located relatively uniform, further improving the uniformity. At the same time, it can also improve the layout space utilization. (4) In the driving and biasing circuit of the pixel array of the present invention, the biasing branch increases the number of reference PMOS transistors and distributes them evenly, which can reduce the display unevenness caused by MOS transistor mismatch and power line voltage drop in small areas; multiple working modes are set, and the output performance can be changed by selecting the current transmission ratio and the number of MOS transistors connected in parallel in the current mirror. When connected to Micro-LEDs with different loads, it can meet the needs of more application scenarios and greatly improve the adaptability range of the driving chip; (5) Compared with PAM, the present invention adopts the PWM brightness grayscale adjustment method. The constant current is obtained by the current mirror PMOS transistor and the reference current generation and replication circuit in the driving branch, which can make the Micro-LED always maintain a constant driving current when it is lit. The switching PMOS transistor and the data latch and switching control circuit control the pixel switching time, and the energy conversion efficiency and the emission wavelength are kept in the best state. At the same time, the brightness grayscale adjustment is also more linear. (6) This invention is achieved using conventional CMOS technology. SRAM (Static Random Access Memory) can be used for storage in the pixels, the pixel arrangement is more flexible, no capacitors are required, the process is simple, the cost is low, and it is easy to implement. Attached Figure Description

[0017] Figure 1This is a schematic diagram of a pixel array driving and biasing circuit according to an embodiment of the present invention; Figure 2 This is a structural diagram of the first-stage current mirror array in the bias branch of an embodiment of the present invention; Figure 3 This is a structural diagram of the second-stage current mirror array in the bias branch of an embodiment of the present invention; Figure 4 This is one embodiment of the partitioned pixel array analog current replication region arrangement method of the present invention; Figure 5 These are schematic diagrams illustrating four different working modes in embodiments of the present invention; Figure 6 A block diagram of a pixel array driving and biasing circuit structure according to an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application. Example

[0019] As attached Figure 1 and attached Figure 6 As shown, a pixel array driving and biasing circuit of this embodiment includes a driving branch and a biasing branch. The pixel array is divided into M×N identical square subarrays. Each pixel in each subarray has a driving branch, which includes a current mirror PMOS transistor MP0 and a switching PMOS transistor MP1. The source of the current mirror PMOS transistor MP0 is connected to the pixel area power supply VLED, and the gate of the current mirror PMOS transistor MP0 is connected to the bias voltage VBP. The bias voltage VBP is transmitted and output through the reference current generation and replication circuit. The drain of the current mirror PMOS transistor MP0 is connected to the source of the switching PMOS transistor MP1. The gate of the switching PMOS transistor MP1 is connected to the switching signal SW output by the data latch and switching control circuit, and the drain of the switching PMOS transistor MP1 is connected to the pixel output terminal Micro-LED to control whether the pixel emits light.

[0020] Among them, the current mirror PMOS transistor MP0 is a low-voltage device, and its size and aspect ratio are increased as much as possible within the allowable range to achieve smaller mismatch error, stronger overcurrent capability and lower power consumption. The switching PMOS transistor MP1 is a higher-voltage device to enhance voltage withstand and reduce leakage current. At the same time, its aspect ratio is increased as much as possible within the allowable range to support larger current and reduce power loss.

[0021] This invention maintains the gate-source voltage V of each current mirror PMOS transistor. GS Consistency ensures that the current output by each pixel is consistent.

[0022] The data latch and switching control circuit, composed of SRAM and logic gates, is used to control whether the pixel emits light. This circuit is implemented using existing technology and will not be elaborated upon here. It stores the grayscale data of the pixel and turns on the PMOS transistor at set intervals, using PWM to control the grayscale of the Micro-LED output. The PMOS transistor has only two operating states: on and off. A large aspect ratio is required to reduce the voltage drop caused by the source-drain turn-on resistance, thereby reducing power consumption. Simultaneously, because the source-drain voltage difference is large in the off state, a higher voltage PMOS transistor can be used to prevent overvoltage and reduce leakage current.

[0023] The driving branch, composed of the current mirror PMOS transistor MP0 and the switching PMOS transistor MP1, ensures that the Micro-LED maintains a constant driving current when lit, keeping the energy conversion efficiency and emission wavelength at their optimal levels, and resulting in more linear brightness and grayscale adjustment. Simultaneously, the voltage drop across the cathode and the impedance deviation of the Micro-LED itself do not significantly affect the pixel drive output current, greatly improving display uniformity.

[0024] The reference current generation and replication circuit includes a reference current generation circuit and a bias branch. The reference current generation circuit generates a reference current IREF. The reference current generation circuit includes a connected bandgap reference circuit and a voltage-to-current circuit. The bandgap reference circuit generates a temperature-independent reference voltage VREF, and the voltage-to-current circuit converts the reference voltage VREF into a reference current IREF via an adjustable resistor. In this invention, the reference current generation circuit is implemented using existing technology, which will not be elaborated upon here.

[0025] The reference current can be adjusted via a variable resistor, adding another brightness adjustment method besides PWM. However, due to the characteristics of Micro-LEDs, this brightness adjustment method will cause a certain degree of shift in luminous efficiency and wavelength. The adjustment here is mainly to keep the energy conversion efficiency and emission wavelength of the Micro-LED at their optimal levels. The final reference current is then replicated throughout the pixel array via a current mirror network.

[0026] The bias branch includes a first-stage current mirror array and a second-stage current mirror array that are connected. The first-stage current mirror array is used to copy the reference current IREF into several sub-arrays, i.e., M×N parts, and output the IBIAS current. Each sub-array has a second-stage current mirror array, which is used to receive the IBIAS current and output the bias voltage VBP. The bias voltage VBP is connected to the drive branch in each sub-array, thereby controlling each pixel in each sub-array. As attached Figure 2 As shown, the first-stage current mirror array includes a reference circuit and M×N replica circuits. The reference circuit is connected to the reference current IREF. Each replica circuit has the same structure. The reference circuit and each replica circuit form a common-source common-gate current mirror. Each replica circuit replicates the reference current and controls the final IBIAS current output to be 1 to 4 times the current of IREF.

[0027] The reference circuit includes NMOS transistors MN3-MN5; NMOS transistors MN4-MN5 are reference transistors, with the drain of NMOS transistor MN4 connected to the reference current IREF. The gate of NMOS transistor MN4 is connected to the drain of NMOS transistor MN4, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN5 is grounded; the drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is grounded, and the gate of NMOS transistor MN3 is connected to the enable signal EN; the operation of the first-stage current mirror array is controlled by NMOS transistor MN3.

[0028] Each replication circuit has the same structure, including: PMOS transistors MP2~MP4, NMOS transistors MN0~MN2, and NMOS transistors MN6~MN16; NMOS transistors MN4~MN5 in the reference circuit and NMOS transistors MN6~MN13 in each replication circuit form a common-source, common-gate current mirror, wherein: The gate of NMOS transistor MN6 is connected to the reference current IREF, and the drain of NMOS transistor MN6 outputs the IBIAS current; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN7 is grounded. The drain of NMOS transistor MN8 outputs the IBIAS current; the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN9 is grounded; the gate of NMOS transistor MN8 is connected to the source of NMOS transistor MN0, the drain of NMOS transistor MN14, and the drain of PMOS transistor MP2; the drain of NMOS transistor MN0 is connected to the reference current IREF, and the gate of NMOS transistor MN0 is connected to the first control signal T0; the source of NMOS transistor MN14 is grounded, and the gate of NMOS transistor MN14 is connected to the first control signal T0; the source of PMOS transistor MP2 is connected to the reference current IREF, and the gate of PMOS transistor MP2 is connected to the first control signal T0. The drain of NMOS transistor MN10 outputs the IBIAS current; the source of NMOS transistor MN10 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN11 is grounded; the gate of NMOS transistor MN10 is connected to the source of NMOS transistor MN1, the drain of NMOS transistor MN15, and the drain of PMOS transistor MP3; the drain of NMOS transistor MN1 is connected to the reference current IREF, and the gate of NMOS transistor MN1 is connected to the second control signal T1; the source of NMOS transistor MN15 is grounded, and the gate of NMOS transistor MN15 is connected to the second control signal T1; the source of PMOS transistor MP3 is connected to the reference current IREF, and the gate of PMOS transistor MP3 is connected to the second control signal T1. The drain of NMOS transistor MN12 outputs the IBIAS current; the source of NMOS transistor MN12 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN13 is grounded; the gate of NMOS transistor MN12 is connected to the source of NMOS transistor MN2, the drain of NMOS transistor MN16, and the drain of PMOS transistor MP4; the drain of NMOS transistor MN2 is connected to the reference current IREF, and the gate of NMOS transistor MN2 is connected to the second control signal T1; the source of NMOS transistor MN16 is grounded, and the gate of NMOS transistor MN16 is connected to the second control signal T1; the source of PMOS transistor MP4 is connected to the reference current IREF, and the gate of PMOS transistor MP4 is connected to the second control signal T1. In this circuit, NMOS transistors MN6-MN7, MN8-MN9, MN10-MN11, and MN12-MN13 each replicate the reference current. MN6-MN7 remains on by default, while MN8-MN9, MN10-MN11, and MN12-MN13 are selectively activated by MN0-2, MP2-4, and MP14-16 under the control of signals T0 and T1. Ultimately, the IBIAS current output is 1-4 times the IREF current. The number of output IBIAS lines matches the number of partitions in the pixel array, i.e., the number of sub-arrays. Each partition corresponds to one replication circuit, meaning one IBIAS and its corresponding MN6-13, ensuring consistent current across all IBIAS lines. During operation, the first-stage current mirror remains always on, improving the response speed of the pixel switches.

[0029] To improve uniformity and response speed when switching pixels, the current mirror array in this invention is divided into two levels, dividing the entire pixel array into M×N identical small square arrays; the first-level current mirror network copies the reference current M×N times, and the second-level current mirror network then copies it to each pixel.

[0030] As attached Figure 3 As shown, the structure of the second-stage current mirror array includes PMOS transistors MP5~MP16 and NMOS transistors MN14~MN20; PMOS transistors MP5~MP8 are used to form a current mirror with the current mirror PMOS transistor MP0 in the driving branch of each sub-array. PMOS transistors MP5~MP8 are reference transistors. The drain of each is connected to the IBIAS current output by the first-stage current mirror array, and the source is connected to the pixel area power supply VLED. The gates of PMOS transistors MP5 are all connected to the first control unit, and the gates of PMOS transistors MP6 to MP8 are all connected to the second control unit. The first control unit includes NMOS transistor MN17 and PMOS transistors MP15-MP16. The gates of NMOS transistor MN17 and PMOS transistor MP15 are connected to the enable signal EN. The source of NMOS transistor MN17 is connected to the drain of PMOS transistor MP15 and connected to the IBIAS current. The drain of NMOS transistor MN17 is connected to the source of PMOS transistor MP15 and is also connected to the gate of PMOS transistor MP5 and the source of PMOS transistor MP16. The drain of PMOS transistor MP16 is grounded, and the gate of PMOS transistor MP16 is connected to the enable signal EN. PMOS transistor MP5 remains on by default under the control of the enable signal EN, and its gate outputs a bias voltage VBP. The second control unit structure corresponding to PMOS transistor MP6 includes NMOS transistor MN18, PMOS transistor MP9, and PMOS transistor MP12. The gates of NMOS transistor MN18 and PMOS transistor MP9 are connected to the first control signal T0. The source of NMOS transistor MN18 is connected to the drain of PMOS transistor MP9 and connected to the IBIAS current. The drain of NMOS transistor MN18 is connected to the source of PMOS transistor MP9 and to the gate of PMOS transistor MP6 and the drain of PMOS transistor MP12. The source of PMOS transistor MP12 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP12 is connected to the second control signal T1.

[0031] The second control unit structure corresponding to PMOS transistor MP7 includes NMOS transistor MN19, PMOS transistor MP10, and PMOS transistor MP13. The gates of NMOS transistor MN19 and PMOS transistor MP10 are connected to the second control signal T1. The source of NMOS transistor MN19 is connected to the drain of PMOS transistor MP10 and connected to the IBIAS current. The drain of NMOS transistor MN19 is connected to the source of PMOS transistor MP10 and connected to the gate of PMOS transistor MP7 and the drain of PMOS transistor MP13. The source of PMOS transistor MP13 is connected to the pixel area power supply VLED, and the gate of PMOS transistor MP13 is connected to the second control signal T1.

[0032] The second control unit structure corresponding to PMOS transistor MP8 includes NMOS transistor MN20, PMOS transistor MP11, and PMOS transistor MP14. The gates of NMOS transistor MN20 and PMOS transistor MP11 are connected to the second control signal T1. The source of NMOS transistor MN20 is connected to the drain of PMOS transistor MP11 and connected to the IBIAS current. The drain of NMOS transistor MN20 is connected to the source of PMOS transistor MP11 and connected to the gate of PMOS transistor MP8 and the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the pixel area power supply VLED, and the gate of PMOS transistor MP14 is connected to the second control signal T1.

[0033] In this design, PMOS transistors MP5-MP8 and the current mirror PMOS transistor MP0 are the same size. PMOS transistors MP5-MP8 are used to evenly distribute the IBIAS current. PMOS transistors MP6-MP8 are selected to conduct or not under the control of NMOS transistors MN18-MN20 and PMOS transistors MP9-MP14, which are controlled by the first control signal T0 and the second control signal T1. Ultimately, the current output replicated by the current mirror PMOS transistor MP0 is 1, 1 / 2, 1 / 3, or 1 / 4 times the IBIAS current. Combined with the first and second-level current mirror arrays, the current replicated by the final pixel circuit's drive branch is always equal to the reference current IREF output by the reference current generation circuit. The design of multiple reference transistors can reduce display unevenness caused by MOS transistor mismatch and power line voltage drop in small areas. MN17 and MP15-16 can control the bias voltage VBP to be set to 0 through the enable signal EN. When the bias voltage VBP is set to 0, the entire current mirror array does not work, and the pixel output current is directly related to the load, which can save power consumption in special application scenarios.

[0034] Each subarray is divided into a digital logic region and an analog current replication region. The switching PMOS transistor MP1 and the data latch and switching control circuitry are located in the digital logic region. This region has lower requirements for matching and power supply, and is only responsible for controlling the conduction of the analog current replication region and the output Micro-LED. The current mirror PMOS transistor MP0 is located in the analog current replication region. Within each analog current replication region, there are independent reference PMOS transistors of the same size, namely MP0, and replication PMOS transistors, namely MP5~MP8, ensuring that the source-side power supply voltages of the reference and replication PMOS transistors are relatively consistent. This ensures that the source-drain voltages are as consistent as possible under the same bias voltage, resulting in consistent leakage current for each replication PMOS transistor. The current mirror PMOS transistor MP0 and replication PMOS transistors, namely MP5~MP8, can be centrally and symmetrically placed. The more concentrated the placement area, the closer it is to a square, resulting in a smaller power supply voltage drop within that area. Simultaneously, increasing the number of reference PMOS transistors can significantly reduce the impact of PMOS mismatch on pixel uniformity with only a slight increase in power consumption, and can also improve pixel response speed and crosstalk immunity. Finally, the reference PMOS transistors can be evenly distributed throughout the analog current replication region, making the average source-end voltage of each reference PMOS transistor closer to the average source-end voltage of the replicated PMOS transistors, thereby further reducing the impact of internal power supply voltage drops in each module of the small array. Since the current mirror PMOS transistors operate normally in the saturation region, their size should be increased as much as possible to reduce replication current offset caused by mismatch. Additionally, dummy transistors should be added around the perimeter to ensure that each current mirror PMOS transistor is in a relatively uniform environment.

[0035] Micro-LED displays have numerous applications, each with varying requirements and priorities regarding performance indicators such as brightness, uniformity, refresh rate, and power consumption. Multiple operating modes can be configured within the same pixel driver array and bias network. Output performance can be altered by selecting the current transfer rate and the number of MOSFETs connected in parallel in the current mirror. This allows the same driver chip to meet the needs of a wider range of applications when connected to different Micro-LED loads, significantly expanding the driver chip's adaptability.

[0036] Appendix Figure 4 This is a schematic diagram of the arrangement of the simulated current replication region in a partitioned pixel array according to an embodiment of the present invention. The arrangement here uses the second-stage current mirror in a 10×10 pixel partitioned array as an example. This current mirror should include at least MP5~MP8 and 100 MP0, totaling 104 reference and replication PMOS transistors of the same size. Here, a 5x22 column arrangement is used, totaling 110 cells. Simultaneously, the PMOS transistors in each cell are divided into two parallel PMOS transistors of half the width, totaling 110 pairs, thus achieving greater central symmetry when arranging the reference PMOS transistors. Specifically, half of each of the two central pairs of PMOS transistors is taken as MP5; half of each of the two pairs of PMOS transistors on either side of MP5 are taken as MP6; and half of each of the four corner pairs of PMOS transistors is taken as MP7 and MP8. Of the remaining 102 pairs, 100 pairs are MP0 for each pixel, and two pairs are dummy pairs. Although the voltage drop across the power supply is relatively large in the complete array, concentrating a set of reference and replicated PMOS transistors in a small area allows for a relatively consistent source-side power supply voltage. Furthermore, the even distribution of reference PMOS transistors across this small area makes the average source-side voltage of each reference PMOS transistor closer to the average source-side voltage of the replicated PMOS transistors, thereby further reducing the impact of internal power supply voltage drops within each module of the small array. This improves display uniformity.

[0037] Appendix Figure 5 These are schematic diagrams of four different working modes in embodiments of the present invention. Table 1 is a comparison of the four different working modes.

[0038] Table 1. Comparison of 4 different working modes

[0039] Four operating modes can be selected using the control signals T1 and T0 as 00, 01, 10, and 11 in the embodiment. The main difference is that the IBIAS output of the first-stage current mirror replication is a multiple of the reference current IREF. When T1 and T0 are both 00, it is the lowest power consumption single-transistor replication mode, where IBIAS equals IREF. In this mode, the power consumption of the entire bias network is the lowest. However, due to the smaller input current, data signal fluctuations have a higher impact on the output current, resulting in a slower pixel switching response. Simultaneously, since there is only one reference transistor in the second-stage current mirror array, MOSFET mismatch significantly affects replication accuracy, and the resistance to power supply voltage drop in small arrays is poor. However, due to the overall structure of the two-stage current mirror replication, and the checkerboard-patterned placement of the second-stage current mirrors, there is still no significant large-area display unevenness. This operating mode is suitable for scenarios with lower refresh rates and less stringent requirements for pixel uniformity. As the multiple of IBIAS to the reference current IREF increases, the power consumption of the bias array increases proportionally, while the performance of the pixel drive array and bias network improves. When T1 and T0 are 01 and 10 respectively, they correspond to dual-tube replication and triple-tube replication in Table 1; T1 and T0 are 11, which is the highest performance quad-tube replication mode, with IBIAS equal to 4 times IREF. In quad-tube replication mode, the display uniformity caused by MOSFET mismatch and power line voltage drop in small areas can be minimized. Large input current improves the output current's resistance to data signal fluctuations and increases response speed. The pixel drive array and bias network exhibit optimal performance. Although the bias network consumes 4 times more power than the single-tube replication mode, it provides a significant improvement in display uniformity. Furthermore, the bias network's power consumption accounts for a relatively small proportion of the total pixel drive array power consumption. Figure 4 In the embodiments, this accounts for only 1 / 100 to 1 / 25. This working mode is suitable for scenarios with high refresh rates and extremely high requirements for display uniformity.

[0040] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving and biasing circuit for a pixel array, characterized in that, Includes drive branches and bias branches; The pixel array is divided into M×N identical square subarrays. Each pixel in each subarray has a driving branch, which includes a current mirror PMOS transistor MP0 and a switching PMOS transistor MP1. The source of the current mirror PMOS transistor MP0 is connected to the pixel area power supply VLED, and the gate of the current mirror PMOS transistor MP0 is connected to the bias voltage VBP. The bias voltage VBP is transmitted and output through the reference current generation and replication circuit. The drain of the current mirror PMOS transistor MP0 is connected to the source of the switching PMOS transistor MP1. The gate of the switching PMOS transistor MP1 is connected to the switching signal SW output by the data latch and switching control circuit, and the drain of the switching PMOS transistor MP1 is connected to the output terminal Micro-LED to control whether the pixel emits light. The reference current generation and replication circuit includes a reference current generation circuit and a bias branch; The reference current generation circuit is used to generate the reference current IREF; The bias branch includes a first-stage current mirror array and a second-stage current mirror array that are connected. The first-stage current mirror array is used to copy the reference current IREF into M×N copies and output the IBIAS current. Each subarray has a second-stage current mirror array, which is used to receive the IBIAS current and output the bias voltage VBP. The bias voltage VBP is connected to the drive branch in each subarray, thereby controlling each pixel in each subarray.

2. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The first-stage current mirror array includes a reference circuit and M×N replica circuits; The reference circuit is connected to the reference current IREF. Each replica circuit has the same structure. The reference circuit and each replica circuit form a common source cascode current mirror. Each replica circuit copies the reference current and controls the final IBIAS current output to be 1 to 4 times the current of IREF.

3. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The reference circuit includes NMOS transistors MN3 to MN5; the drain of NMOS transistor MN4 is connected to the reference current IREF; the gate of NMOS transistor MN4 is connected to the drain of NMOS transistor MN4, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN5 is grounded; the drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is grounded, and the gate of NMOS transistor MN3 is connected to the enable signal EN.

4. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The replication circuit includes: PMOS transistors MP2~MP4, NMOS transistors MN0~MN2, and NMOS transistors MN6~MN16; The gate of NMOS transistor MN6 is connected to the reference current IREF, and the drain of NMOS transistor MN6 outputs the IBIAS current; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN5 in the reference circuit, and the source of NMOS transistor MN7 is grounded. The drain of NMOS transistor MN8 outputs the IBIAS current; the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN9 is grounded; the gate of NMOS transistor MN8 is connected to the source of NMOS transistor MN0, the drain of NMOS transistor MN14, and the drain of PMOS transistor MP2; the drain of NMOS transistor MN0 is connected to the reference current IREF, and the gate of NMOS transistor MN0 is connected to the first control signal T0; the source of NMOS transistor MN14 is grounded, and the gate of NMOS transistor MN14 is connected to the first control signal T0; the source of PMOS transistor MP2 is connected to the reference current IREF, and the gate of PMOS transistor MP2 is connected to the first control signal T0. The drain of NMOS transistor MN10 outputs the IBIAS current; the source of NMOS transistor MN10 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN11 is grounded; the gate of NMOS transistor MN10 is connected to the source of NMOS transistor MN1, the drain of NMOS transistor MN15, and the drain of PMOS transistor MP3; the drain of NMOS transistor MN1 is connected to the reference current IREF, and the gate of NMOS transistor MN1 is connected to the second control signal T1; the source of NMOS transistor MN15 is grounded, and the gate of NMOS transistor MN15 is connected to the second control signal T1; the source of PMOS transistor MP3 is connected to the reference current IREF, and the gate of PMOS transistor MP3 is connected to the second control signal T1. The drain of NMOS transistor MN12 outputs the IBIAS current; the source of NMOS transistor MN12 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN13 is grounded; the gate of NMOS transistor MN12 is connected to the source of NMOS transistor MN2, the drain of NMOS transistor MN16, and the drain of PMOS transistor MP4; the drain of NMOS transistor MN2 is connected to the reference current IREF, and the gate of NMOS transistor MN2 is connected to the second control signal T1; the source of NMOS transistor MN16 is grounded, and the gate of NMOS transistor MN16 is connected to the second control signal T1; the source of PMOS transistor MP4 is connected to the reference current IREF, and the gate of PMOS transistor MP4 is connected to the second control signal T1.

5. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The structure of the second-stage current mirror array includes PMOS transistors MP5~MP16 and NMOS transistors MN14~MN20. PMOS transistors MP5~MP8 are used to form a current mirror with the current mirror PMOS transistor MP0 in the driving branch of each sub-array. PMOS transistors MP5~MP8 are reference transistors. The drain of each is connected to the IBIAS current output by the first-stage current mirror array, and the source is connected to the pixel area power supply VLED.

6. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, The gates of PMOS transistors MP5 are all connected to the first control unit, which includes NMOS transistors MN17 and PMOS transistors MP15-MP16. The gates of NMOS transistors MN17 and MP15 are connected to the enable signal EN. The source of NMOS transistor MN17 is connected to the drain of PMOS transistor MP15 and connected to the IBIAS current. The drain of NMOS transistor MN17 is connected to the source of PMOS transistor MP15 and to the gate of PMOS transistor MP5 and the source of PMOS transistor MP16. The drain of PMOS transistor MP16 is grounded, and the gate of PMOS transistor MP16 is connected to the enable signal EN. PMOS transistor MP5 remains on by default under the control of the enable signal EN, and its gate output bias voltage VBP.

7. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, The gates of PMOS transistors MP6 to MP8 are all connected to the second control unit; The second control unit structure corresponding to PMOS transistor MP6 includes NMOS transistor MN18, PMOS transistor MP9, and PMOS transistor MP12. The gates of NMOS transistor MN18 and PMOS transistor MP9 are connected to the first control signal T0. The source of NMOS transistor MN18 is connected to the drain of PMOS transistor MP9 and connected to the IBIAS current. The drain of NMOS transistor MN18 is connected to the source of PMOS transistor MP9 and connected to the gate of PMOS transistor MP6 and the drain of PMOS transistor MP12. The source of PMOS transistor MP12 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP12 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP7 includes NMOS transistor MN19, PMOS transistor MP10, and PMOS transistor MP13. The gates of NMOS transistor MN19 and PMOS transistor MP10 are connected to the second control signal T1. The source of NMOS transistor MN19 is connected to the drain of PMOS transistor MP10 and connected to the IBIAS current. The drain of NMOS transistor MN19 is connected to the source of PMOS transistor MP10 and connected to the gate of PMOS transistor MP7 and the drain of PMOS transistor MP13. The source of PMOS transistor MP13 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP13 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP8 includes NMOS transistor MN20, PMOS transistor MP11, and PMOS transistor MP14. The gates of NMOS transistor MN20 and PMOS transistor MP11 are connected to the second control signal T1. The source of NMOS transistor MN20 is connected to the drain of PMOS transistor MP11 and connected to the IBIAS current. The drain of NMOS transistor MN20 is connected to the source of PMOS transistor MP11 and connected to the gate of PMOS transistor MP8 and the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the pixel area power supply VLED, and the gate of PMOS transistor MP14 is connected to the second control signal T1.

8. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, PMOS transistors MP5~MP8 and current mirror PMOS transistor MP0 have the same dimensions.

9. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, Each subarray is divided into a digital logic region and an analog current replication region; the switching PMOS transistor MP1 and the data latch and switching control circuit are located in the digital logic region, and the current mirror PMOS transistor MP0 is located in the analog current replication region; in each analog current replication region, the current mirror PMOS transistor MP0 and the replication PMOS transistors, namely PMOS transistors MP5~MP8, are centrally and symmetrically placed.

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