LPDDR chip test method and test system

Abstract

The invention provides an LPDDR chip test method and a test system, and relates to the field of storage equipment test, the method can detect address interference caused by process defects of a signal transmission path in an LPDDR chip, and accurately reflect a failure position and a specific failure access sequence through mapping of an address and storage data, and the test efficiency is improved. Therefore, accurate detection of the LPDDR chip with the access address error problem in a special scene is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage device testing, and particularly to an LPDDR chip testing method and system. BACKGROUND

[0002] An LPDDR (Low Power Double Data Rate SDRAM) chip is essentially a random access memory device, and each basic storage unit can be freely accessed through row and column addresses. In a specific scenario, an LPDDR access address specified by a SoC (System on Chip) is converted from a logical address to a physical address, and the physical address is finally transmitted to a CA Pin of the LPDDR chip. The LPDDR reads data of a corresponding storage unit and outputs the data according to the CA Pin.

[0003] It can be seen that, in the process of accessing the LPDDR by the SoC, correct and complete transmission of address signals is one of the key factors for normal operation of the entire machine. Since the address signals of the LPDDR are transmitted in parallel, each address signal is input through the CA Pin, and a row and column address decoder finally outputs target data by decoding the row and column addresses. In an actual scenario, crosstalk or ISI (Inter-Symbol Interference) between signals inevitably occurs, and therefore in some specific read and write access processes, the address signals are disturbed, and even in some parts of the signal transmission, the access address error failure problem may directly occur.

[0004] To solve the above problem, there is a lack of related testing means in the prior art to detect the LPDDR chip with an access address error problem in a special scenario. SUMMARY

[0005] Therefore, the present application aims to provide an LPDDR chip testing method and system, which can detect address interference caused by process defects of a signal transmission path in an LPDDR chip, and accurately reflect a failure position and a specific failure access sequence through mapping of addresses and storage data, so as to realize accurate detection of the LPDDR chip with an access address error problem in a special scenario.

[0006] In a first aspect, an embodiment of the present application provides an LPDDR chip testing method, which comprises: initializing a chip, and dividing a storage matrix of the chip to obtain a logical block; calculating background data of all storage units in each row of the logical block according to an address corresponding to the row, and writing the background data into all storage units in the row; selecting the current test logic block according to the preset order, and determining the reference column and the comparison column of the current test logic block; comparing the background data corresponding to the reference column with the background data corresponding to the comparison column according to the number of rows corresponding to the reference column, to obtain the test result of the current test logic block; If the test result of the current test logic block is passed, the test of the next logic block is performed according to the preset order until the test of all logic blocks is completed.

[0007] In some embodiments, the storage matrix of the chip is divided to obtain the logic block, including: determining the total number of bit positions corresponding to each row address in the storage matrix; obtaining the maximum number of bit positions that can be stored by the storage unit, and determining the number of logic blocks corresponding to the storage matrix according to the ratio of the total number of bit positions to the maximum number of bit positions; determining the division strategy corresponding to the storage matrix according to the number of logic blocks and the maximum number of bit positions, and obtaining the logic block by dividing the storage matrix according to the division strategy.

[0008] In some embodiments, the step of calculating the background data of all storage units in each row of the logic block according to the address corresponding to the row and writing the background data into all storage units in the row includes: obtaining the number of rows of the logic block and the row address corresponding to each row of storage units; performing remainder calculation on the number of rows of the logic block and the row address to obtain the background data of all storage units in each row, and writing the background data into all storage units in the corresponding row.

[0009] In some embodiments, the reference column and the comparison column of the current test logic block are determined, including: determining a single whole column randomly selected from the current test logic block as the reference column; determining the other columns except the reference column in the current test logic block as the comparison column.

[0010] In some embodiments, the reference column and the comparison column of the current test logic block are determined, including: determining the reference column according to a single storage unit randomly selected from all single whole rows in the current test logic block; determining the comparison column according to the other storage units except the single storage unit in all single whole rows in the current test logic block.

[0011] In some embodiments, the step of comparing the background data corresponding to the reference column with the background data corresponding to the comparison column according to the number of rows corresponding to the reference column to obtain the test result of the current test logic block includes: determining a single row randomly selected from the reference column as the starting row; determining the traversal order corresponding to the reference column according to the row number corresponding to the starting row in the reference column; starting from the starting row, sequentially comparing the first background data corresponding to the reference column with the second background data corresponding to the comparison column under the same row number according to the traversal order; determining the test result corresponding to the current test logic block based on the consistency comparison result of the first background data and the second background data.

[0012] In some embodiments, the step of determining the traversal order corresponding to the reference column according to the row number corresponding to the starting row in the reference column comprises: obtaining the current row number corresponding to the starting row in the reference column, and sequentially obtaining the starting row number and the ending row number of the reference column according to the row number arrangement order of the reference column; obtaining the first row number interval between the current row number and the ending row number, and determining the first traversal order according to the row number increasing order corresponding to the first row number interval; obtaining the second row number interval between the current row number and the starting row number, and determining the second traversal order according to the row number decreasing order corresponding to the second row number interval; determining the traversal order corresponding to the reference column based on the first traversal order and the second traversal order.

[0013] In some embodiments, the step of starting from the starting row, sequentially comparing the first background data corresponding to the reference column with the second background data corresponding to the comparison column under the same row number according to the traversal order comprises: obtaining the initialized flag bit; when it is detected that the flag bit is the first flag, sequentially comparing the first background data corresponding to the reference column with the second background data corresponding to the comparison column under the same row number according to the first traversal order; when it is detected that the current row number is consistent with the ending row number, stopping the traversal of the first row number interval, and setting the flag bit to the second flag; when it is detected that the flag bit is the second flag, sequentially comparing the first background data corresponding to the reference column with the second background data corresponding to the comparison column under the same row number according to the second traversal order; when it is detected that the current row number is consistent with the starting row number, stopping the traversal of the second row number interval, and setting the flag bit to the first flag.

[0014] In some embodiments, after the step of obtaining the test result of the current test logic block, the method further comprises: if the test result of the current test logic block is failure, ending the test process.

[0015] In a second aspect, the present application provides a test system, which comprises a processor and a memory, the memory storing computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the steps of the LPDDR chip test method mentioned in the first aspect.

[0016] The LPDDR chip test method and test system provided by the embodiments of the present application can detect address interference caused by process defects of signal transmission paths in the LPDDR chip, and accurately reflect the failure position and specific failure access sequence through the mapping of the address and the storage data, so that the LPDDR chip with the access address error problem in the special scenario can be accurately detected.

[0017] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the description, claims and drawings.

[0018] In order to make the above objects, features and advantages of the present application more apparent, the following will specifically describe a preferred embodiment, and combine with the accompanying drawings, and make a detailed description as follows. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1 A flowchart of an LPDDR chip test method provided by the embodiments of the present application; Figure 2The flow chart of step S101 of the LPDDR chip test method provided by the embodiment of the present application is that the memory matrix of the chip is divided to obtain the logical block; Figure 3 The flow chart of step S102 of the LPDDR chip test method provided by the embodiment of the present application is shown in the figure; Figure 4 The flow chart of step S103 of the LPDDR chip test method provided by the embodiment of the present application is that the reference column and the comparison column of the current test logical block are determined; Figure 5 The flow chart of step S103 of another LPDDR chip test method provided by the embodiment of the present application is that the reference column and the comparison column of the current test logical block are determined; Figure 6 The flow chart of step S104 of the LPDDR chip test method provided by the embodiment of the present application is shown in the figure; Figure 7 The flow chart of step S602 of the LPDDR chip test method provided by the embodiment of the present application is shown in the figure; Figure 8 The flow chart of step S603 of the LPDDR chip test method provided by the embodiment of the present application is shown in the figure; Figure 9 The structural schematic diagram of the logical block in the LPDDR chip test method provided by the embodiment of the present application is shown in the figure; Figure 10 The structural schematic diagram of the LPDDR chip test system provided by the embodiment of the present application is shown in the figure; Figure 11 The structural schematic diagram of the test system provided by the embodiment of the present application is shown in the figure.

[0021] Icon: 1010-logical block acquisition module; 1020-background data writing module; 1030-comparison initialization module; 1040-comparison test execution module; 1050-cyclic test execution module; 101-processor; 102-memory; 103-bus; 104-communication interface. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0023] For the convenience of understanding the present embodiment, first, a kind of LPDDR chip test method disclosed in the present application is introduced, as shown in Figure 1 The method comprises: Step S101: initialization chip, the storage matrix of chip is divided to obtain logic block.

[0024] First, the LPDDR chip to be tested is initialized, including chip power-on, configuration basic test parameters (such as test clock frequency, signal transmission timing, pin level standard, etc.), to ensure that the chip enters stable testable state. Then, according to the preset "row threshold", the overall storage array of the chip is logically divided to obtain several independent logic blocks: the row threshold needs to be determined in combination with the hardware specifications of the chip (such as total storage row number, single storage cell bit width, process node), the purpose is to disassemble large-scale storage array into subunit with moderate scale, to avoid problems such as signal interference superposition and low test efficiency when testing the whole array. After division, all storage cells contained in each logic block are determined, and the relative row / column address of each cell in the logic block is recorded, to establish basic positioning information for subsequent data writing and comparison.

[0025] Step S102: calculate the background data of all storage cells in the row according to the address corresponding to the logic block of each row, and write the background data into all storage cells in the row.

[0026] For each logic block, in units of rows, the background data is calculated based on the row address parameter corresponding to the row: the core calculation logic is usually the remainder operation of row address and row threshold (for example, the row address is 0x0000, the row threshold is 0xFF, and the remainder result 0x00 is the background data of the row), this calculation method can make the background data in the same logic block strongly associated with the row address, and the data rule can be traced back, if the address transmission error occurs subsequently, the background data read will deviate from the expected value, so as to locate the problem reversely. After calculation, according to the address sequence of "row by row in logic block, column by column in each row", the background data of the row is written into all storage cells in the row (i.e. all column cells in the same row store the same background data), to ensure that the data of each storage cell is strictly bound with the corresponding row address, to avoid data misplacement affecting test accuracy.

[0027] Step S103: select the current test logic block according to the preset order, and determine the reference column and comparison column of the current test logic block.

[0028] The logic block to be tested is selected according to a preset order (usually an ascending order of logic block numbers, such as starting from logic block number 0) to ensure that all logic blocks are covered and tested without any blind spots. Then, a reference column and a comparison column are determined based on the storage matrix (a two-dimensional structure of storage cells arranged in rows and columns) of the current test logic block: the reference column is a single, randomly selected column from all columns of the matrix (prioritizing columns with relatively stable signal transmission, such as those far from chip pins and with reduced external noise interference), serving as the benchmark column for data comparison; the comparison column is directly defined as all columns in the matrix except the reference column. This design maximizes coverage of potential interference scenarios (such as signal crosstalk between the reference column and adjacent columns, and inter-symbol interference within the same signal group), providing a comprehensive comparison dimension for subsequent address transmission error detection.

[0029] Step S104: Compare the background data corresponding to the reference column with the background data corresponding to the comparison column according to the row number of the reference column to obtain the test result of the current test logic block.

[0030] Following the row order corresponding to the reference column (traversing all rows of the current test logic block row by row), a background data consistency comparison is performed on the reference column and comparison column storage units of the same row: For a given row, first read the background data of that cell in the reference column as the baseline data, then sequentially read the background data of all comparison column cells in that row as the comparison data, and then determine whether the two are completely consistent. If they are consistent, it indicates that the address transmission of that row and column is normal; if they are inconsistent, they are marked as abnormal, and the row number of the abnormal row, the column number of the reference column, and the column number of the comparison column are recorded. After traversing all rows of the current logic block, the comparison results of all rows are summarized to form the test conclusion of the current test logic block.

[0031] Step S105: If the test result of the current test logic block is passed, then the test of the next logic block is performed in the preset order until all logic blocks have been tested.

[0032] If the current logic block passes the test, the system switches to the next untested logic block in a preset order, repeating steps S103-S104. If the current logic block fails the test, the system first records the block's anomaly information (such as anomaly row and column coordinates, and the number of anomalies). Then, it decides whether to continue based on the actual testing requirements (if a comprehensive analysis of chip defect distribution is needed, the remaining blocks can be tested; if only qualified chips need to be screened, the test can be paused and marked for further analysis). This process continues until all logic blocks have been tested, completing one round of core testing for the LPDDR chip. Subsequent testing can then be based on the results of all logic blocks to comprehensively determine whether the chip is qualified and to pinpoint the specific failure location.

[0033] In some embodiments, the chip's storage matrix is ​​divided into logic blocks, such as... Figure 2 As shown, it includes: Step S201: Determine the total number of bits corresponding to each row address in the storage matrix.

[0034] The total number of bits in the row address is a core parameter determined during the LPDDR chip hardware design phase, directly determining the range of the total number of rows in the storage matrix (e.g., a 16-bit row address corresponds to a total of 2 rows). 16 =65536 rows, address range 0x0000~0xFFFF). This step requires reading the complete bit length of each row address in the storage matrix through the chip datasheet or test initialization configuration. This total bit length is the key basis for subsequent splitting of logic blocks, because the storage capacity of a storage unit has an upper limit (it cannot store a row address exceeding its maximum bit length at once). The total length of the row address must be determined first in order to reasonably plan the splitting method and avoid truncation or overflow during address data storage.

[0035] Step S202: Obtain the maximum number of bits that the storage unit can store, and determine the number of logical blocks corresponding to the storage matrix based on the ratio of the total number of bits to the maximum number of bits.

[0036] First, determine the maximum number of bits that a single memory cell of the LPDDR chip can store (this is determined by the memory cell's hardware structure, such as the common 8-bit or 16-bit; this document uses 8-bit as an example). This is the upper limit of data storage for the memory cell; address data exceeding this limit cannot be completely stored by a single cell. Next, calculate the ratio of the total number of bits in the row address to the maximum number of bits in the memory cell. This ratio represents the number of logical blocks corresponding to the storage matrix. For example, if the total number of bits in the row address is 16 bits (2^16 = 65536 rows), and the maximum number of bits in the memory cell is 8 bits (2^8 = 256 rows), then the ratio is 65536 / 256 = 256, and the number of logical blocks is 256.

[0037] Step S203: Determine the partitioning strategy corresponding to the storage matrix based on the number of logical blocks and the maximum number of bits, and then partition the storage matrix according to the partitioning strategy to obtain logical blocks.

[0038] The core of this step is to split the total number of bits in the row address according to the maximum number of bits in the storage unit, forming a specific partitioning strategy, and then splitting the storage matrix into a corresponding number of logical blocks: The partitioning strategy is determined by using the maximum number of bits in a storage unit as the address segment length. The complete row address is split into multiple equal-length segments, and each segment corresponds to the internal row address of a logical block. Specifically, starting from row 0, every 8 bits of address (i.e., every 2^8 rows) constitutes a logical block.

[0039] Each logical block contains the row number corresponding to the maximum number of bits in the storage unit (e.g., 8 bits corresponds to 2 rows). 8=256 rows, and the row number threshold is 0xFF), and the in-block row addresses of all rows in the block are continuous (0x00~0xFF). After the division, the size of each logical block is uniform, which not only adapts to the storage capacity of the storage unit, but also facilitates subsequent block-by-block execution of background data writing and comparison test, avoiding cross-block signal interference.

[0040] The acquisition process of the background data is related to the row address. For all storage units of each row of the storage matrix, the corresponding row address needs to be written in order to facilitate subsequent judgment of whether the address reading is correct. Since a storage unit can store a limited number of bit positions, a storage unit cannot completely store all row address bits, and therefore needs to be split. In some embodiments, the background data of all storage units of each row is calculated according to the address corresponding to each row of the logical block, and the background data is written into all storage units of the corresponding row, as shown in step S102, which includes: Figure 3 Step S301: Obtain the number of rows of the logical block and the row address corresponding to each row of the storage unit.

[0041] The number of rows of the first logical block is essentially a preset row number threshold (2 8 =256 rows, 0xFF rows, etc.), which is determined by the storage specification (total storage row number, single logical block test efficiency requirement) of the LPDDR chip. For example, a certain chip is set to 256 rows (row number threshold = 0xFF) for a single logical block, and the total number of rows of each logical block is fixed at 256 rows.

[0042] Subsequently, the row address corresponding to each row of the storage unit is obtained, and the relative row address (rather than the global row address) in the logical block is preferentially read. The address is extracted from the address mapping table of the chip storage controller and directly corresponds to the row position in the logical block (for example, the row address of logical block 1 is 0x00~0xFF, and the row address of logical block 2 is 0x00~0xFF, and only the logical block number is used to distinguish the global position). Selecting the relative row address can simplify subsequent calculations (avoiding the redundancy of the high bits of the global address), while ensuring that the row address and the row number range of the logical block completely match (for example, the relative row address of a 256-row logical block must be between 0x00~0xFF), laying a foundation for accurate calculation of the background data.

[0043] In addition, the accuracy of the row address needs to be confirmed through the address verification mechanism of the chip. For example, after reading the row address, it is compared with the preset address range (0~row number threshold-1) of the logical block. If it exceeds the range, the address calibration is triggered to avoid the deviation of subsequent data calculation caused by address mapping errors.

[0044] Step S302: Perform modulo calculation on the number of rows of the logical block and the row address corresponding to each row of the storage unit to obtain the background data of all storage units of each row, and write the background data into all storage units of the corresponding row. ​

[0045] First, the row number threshold for dividing logical blocks is acquired in S101, and the row address determined in S201 is calculated by taking the remainder with the row number threshold. The purpose of taking the remainder is to make the background data in the same logical block fall in fixed rows, thereby ensuring data regularity. Then, the address parameters are written in the order of logical block-in-block row-in-block column, that is, all cells in a logical block are traversed first, and then the next logical block is processed. In the same logical block, the corresponding background data is written into the cells in the order of increasing row address and increasing column address in each row. For example, it can start from the 0th row, and every 8-bit address, that is, every 2^8 rows (row number threshold) is a logical block. Each row of each logical block stores the number obtained by taking the remainder of the row address with 2^8. Specifically, first, the current row address A is acquired; then, the number B is calculated by taking the remainder of A with 2^8; then, the number B is written into all columns of the A row of the storage matrix, and then the above steps are repeated to write B into the subsequent rows of the storage matrix until the 0xFFFF row is written. Specifically, as shown in the table, Figure 9 As shown in the table, the logical block 1 corresponds to the rows 0x0000~0x00FF, and the logical block 2 corresponds to the rows 0x0100~0x01FF.

[0046] In some embodiments, the reference column and the comparison column of the current test logical block are determined, as shown in the table, Figure 4 As shown in the table, Step S401: A single complete column randomly selected from the current test logical block is determined as the reference column.

[0047] In the storage matrix (composed of storage cells in the form of “row-column”) of the current test logical block, one single complete column is randomly selected from all matrix columns (that is, complete columns divided according to column addresses in the logical block), and the single complete column is determined as the reference column.

[0048] The core purpose of the random selection is to avoid the test blind area caused by the fixed reference column. If a column (such as the column with the column address of 0) is fixedly selected as the reference column for a long time, it may miss the signal interference problems (such as the noise sensitivity characteristics of the edge column) that can be detected when other columns are used as the reference. The limitation of a single column is to ensure that the reference is unique and avoid confusion in comparison logic when multiple reference columns exist (such as data conflict between different reference columns, which makes it impossible to judge normal / abnormal). The reference column will be used as the benchmark for data comparison in the future, and the background data stored in the reference column is the core basis for judging whether the transmission of other column addresses is normal (in the document, the reference column is often referred to as “AC”, which stands for Aggressor Col).

[0049] Step S402: The other columns in the current test logical block except the reference column are determined as the comparison columns.

[0050] In the current test logic block, all matrixes are removed after the reference column determined in step S401, and all the remaining whole columns are defined as comparison columns. The core logic of this design is to maximize the coverage of potential interference scenarios. The comparison column should include columns that have different interference risks with the reference column (such as signal crosstalk between adjacent columns, inter-symbol interference between columns in the same signal group, noise-sensitive columns near chip pins, etc.). There is no need for additional screening of high-risk columns. In subsequent testing, the background data stored in the comparison column will be compared with the background data of the same industry column one by one, and the address transmission error will be located through consistency judgment (in the document, the comparison column is referred to as VC, i.e. Victim Col).

[0051] In some embodiments, the reference column and the comparison column of the current test logic block are determined, as shown in Figure 5 , comprising: Step S501: determining the reference column according to a single storage unit randomly selected in all single whole rows in the current test logic block.

[0052] Different from the acquisition method in step S401, in this step, a storage unit is randomly selected from each whole row of the current test logic block, and the reference column is obtained by combining the single storage units of all columns. At this time, the reference column is not a single whole column, but a random column formed based on each single whole row.

[0053] Step S502: determining the comparison column according to other storage units except the single storage unit in all single whole rows in the current test logic block.

[0054] The determination process of the comparison column is mainly based on the single storage unit in each single whole row. The column number of the single storage unit corresponding to the reference column in each single whole row is obtained, and the other columns in the current test logic block except the column number are taken as the comparison column.

[0055] In some embodiments, the background data corresponding to the reference column is compared with the background data corresponding to the comparison column in turn according to the number of rows corresponding to the reference column, to obtain the test result of the current test logic block, as shown in Figure 6 , comprising: Step S601: determining a single row randomly selected in the reference column as a starting row.

[0056] Starting row selection: from all rows (the number of rows is consistent with the row number threshold in S101) contained in the reference column (single whole column determined in S401 and S501), a single row is randomly selected as the starting row. Random selection can avoid the test blind area caused by fixed starting row, and the in-block row address of the starting row needs to be recorded to ensure that the subsequent traversal can be traced.

[0057] Step S602: determining the traversal order corresponding to the reference column according to the row number corresponding to the starting row in the reference column.

[0058] The common traversal order is selected as follows: If the total number of rows is small, the row address increment order (starting from the next row address of the starting row, incrementing sequentially to the maximum row address, and then backfilling the row addresses before the starting row) is preferred. This order is consistent with the S102 background data writing order, which can reduce the switching frequency of the SoC address controller and reduce signal interference. If the total number of rows is large, the odd-even row separation order (first traversing the odd rows where the starting row is located, and then traversing the even rows) can be used to avoid signal crosstalk superposition caused by continuous row reading.

[0059] The already traversed row address record table is used to mark the completed traversal of the row in real time, avoiding incomplete testing caused by address repetition or omission. For example, the starting row is row address 10 (total row number 64), and in the increment order, 11-63 and 0-9 need to be traversed sequentially, and the record table needs to be updated synchronously for the traversal state of each row.

[0060] Step S603: starting from the starting row, sequentially comparing the first background data corresponding to the reference column with the second background data corresponding to the comparison column under the same row number according to the traversal order.

[0061] The traversal rule is based on the starting row of S601, and all other rows in the reference column except the starting row are traversed in the order of row address increment or row address decrement. During data comparison and result recording, for each row, the first background data corresponding to the reference column is compared with the second background data corresponding to the comparison column under the same row number for consistency. Generally, if they are consistent, it is "normal", and if they are not consistent, it is "abnormal".

[0062] Step S604: determining the test result corresponding to the current test logic block based on the consistency comparison result of the first background data and the second background data.

[0063] After obtaining the consistency comparison result of the first background data in all reference columns and the second background data corresponding to the comparison column under the same row number, the results can be merged in the order of row address to form the complete test result of the current test logic block. The test result can include: the current test logic block number, the reference column address, all comparison column addresses, the "normal / abnormal" state of each row, the specific row address and comparison column address of the abnormal row. If there is an abnormal result, the "abnormal type" (such as the data inconsistency of a certain comparison column in a certain row) needs to be marked. If all results are normal, it is determined that the current test logic block has no address error.

[0064] In some embodiments, the step S602 of determining the traversal order corresponding to the reference column according to the row number corresponding to the starting row in the reference column, as shown in Figure 7 , includes: Step S701: Obtain the current row number corresponding to the starting row in the reference column, and obtain the starting row number and the ending row number of the reference column in turn according to the row number arrangement order of the reference column.

[0065] First, the current row number corresponding to the starting row in the reference column is obtained according to the matrix column parameter corresponding to the current logical block, and then the minimum row address is set as the starting row number (usually 0, consistent with the starting value of the relative row address in the logical block) and the maximum row address is set as the ending row number (equal to the row number threshold of S101 minus 1, for example, if the threshold is 64, then the ending row number is 63) in the increasing order of the row number of the reference column.

[0066] Step S702: Obtain the first row number interval between the current row number and the ending row number, and determine the first traversal order according to the row number increasing order corresponding to the first row number interval.

[0067] This step mainly realizes splitting the first row number interval and determining the first traversal order. Specifically, the first row number interval is defined as: taking the calculation row number as the starting point and the ending row number as the ending point, the interval of "calculation row number + 1~ending row number" is determined as the first row number interval. For example, the calculation row number is 10 and the ending row number is 63, then the first interval is 11~63, which covers all the rows after the calculation row number.

[0068] The first traversal order is determined: the first traversal order is determined according to the row number increasing order (such as 11-12-…-63) in the first interval, which is consistent with the natural growth direction of the row address of the reference column, can reduce the frequency of reverse switching of the SoC address controller (such as continuous reading from low address to high address), reduce the additional interference caused by signal switching, and at the same time match the row order of the background data written in S102, improve the stability of data reading.

[0069] Step S703: Obtain the second row number interval between the current row number and the starting row number, and determine the second traversal order according to the row number decreasing order corresponding to the second row number interval.

[0070] This step mainly realizes splitting the second row number interval and determining the second traversal order. Specifically, the second row number interval is defined as: taking the starting row number as the starting point and the calculation row number as the ending point, the interval of "starting row number~calculation row number-1" is determined as the second row number interval. For example, the calculation row number is 10 and the starting row number is 0, then the second interval is 0~9, which covers all the rows before the calculation row number.

[0071] Second traversal order determination: the second traversal order is determined in descending order of row numbers in the second interval (e.g., 9-8-…-0). The reason for choosing descending order instead of ascending order is that after the first traversal order (11~63) is completed, the address controller is in a high address state, and traversing 0~9 in descending order can realize continuous switching from high address to low address, avoiding address switching delay caused by jumping from high address to low address (e.g., 63-0), and further reducing signal interference.

[0072] Step S704: determining the traversal order corresponding to the reference column based on the first traversal order and the second traversal order.

[0073] The first traversal order (e.g., 11-12-…-63) determined in S702 and the second traversal order (e.g., 9-8-…-0) determined in S703 are merged in the order of “first first, second second” to form a complete traversal order corresponding to the starting row, for example, the final traversal order is 11-12-…-63-9-8-…-0.

[0074] This merging logic can ensure that all rows in the reference column except the calculation row number (starting row) are covered without omission; the address switching always maintains a continuous direction (high address increment-high address to low address decrement), which maximizes the reduction of signal interference and meets the signal transmission characteristics of the LPDDR address controller.

[0075] In some embodiments, from the starting row, the first background data corresponding to the reference column and the second background data corresponding to the comparison column under the same row number are sequentially compared for consistency according to the traversal order, as shown in S603. Figure 8 As shown, it includes: Step S801: obtaining an initialized flag bit.

[0076] The process of initializing the flag bit can initialize a traversal phase flag bit in the test control module of the SoC. The first initialization can set it as the first flag. The core meaning of the first flag is that the current is in the traversal phase of the first row number interval, which is used to clearly define the interval range of the current data reading, avoiding confusion with the traversal logic of the second interval.

[0077] Step S802: when it is detected that the flag bit is the first flag, the first background data corresponding to the reference column and the second background data corresponding to the comparison column under the same row number are sequentially compared for consistency according to the first traversal order.

[0078] When the flag is detected as the first flag, the data is read line by line according to the first traversal order (such as 11-12-…-63) determined in S702: for the current traversal line, the row activation command is sent first to lock the row address, and then the background data of the reference column is read; subsequently, the background data of all the comparison columns under the same row number is read, and the data is temporarily stored in the SoC cache and associated with the current row address + column type after reading.

[0079] After each line of data is read, it is determined in real time whether the current traversal row address is equal to the termination row number, for example, when the termination row number is 63, it is determined whether the current row address reaches 63. The purpose of this determination is to monitor in real time whether the first interval is traversed.

[0080] Step S803: When it is detected that the current row number is consistent with the termination row number, the traversal of the first row number interval is stopped, and the flag is set to the second flag.

[0081] When it is detected that the current row number is consistent with the termination row number, it indicates that the data comparison process in the first row number interval is completed, at which time the traversal of the first row number interval is stopped, and the traversal stage flag is updated from the first flag to the second flag. The second flag represents that the current switches to the traversal stage of the second row number interval, which provides a logical basis for subsequent reading of the second interval data.

[0082] After the first row number interval is terminated, a verification process can be performed, which confirms that all rows in the first interval have been recorded by checking the list of traversed row addresses, so as to avoid missing reading of a row due to signal delay, and if there is missing reading, the missing row is read again to ensure the integrity of the data in the first interval.

[0083] Step S804: When the flag is detected as the second flag, the first background data corresponding to the reference column under the same row number is compared with the second background data corresponding to the comparison column in sequence according to the second traversal order.

[0084] When the flag is detected as the second flag, the data reading operation is repeated line by line according to the second traversal order (such as 9-8-…-0) determined in S703: lock the current traversal row address-read the reference column background data-read the comparison column background data-temporarily store and associate the address information; the overall reading logic is consistent with that of the first row number interval, but it needs to be noted that the row address is switched in reverse (such as from 9 to 8), and the SoC address controller needs to adapt to the reverse address switching to avoid signal interference.

[0085] After each line is read, it is determined in real time whether the current traversal row address is equal to the starting row number, for example, when the starting row number is 0, it is determined whether the current row address reaches 0, and whether the second interval is traversed.

[0086] Step S805: When it is detected that the current row number is consistent with the starting row number, the traversal of the second row number interval is stopped, and the flag is set to the first flag.

[0087] When the real-time judgment result is that the current line number is equal to the starting line number, it means that the traversal of all non-starting lines has been completed, and at this time, the traversal phase flag bit is reset from the second flag to the first flag, providing a comparison result of the completion of the traversal for the subsequent process.

[0088] After the traversal of the second line number interval ends, the traversed line address list can be checked to confirm that all lines in the second interval (the starting line number ~ the calculated line number - 1) have been recorded, and there are no duplicate line addresses in the list, and finally a complete non-starting line data reading list is formed to ensure that there is no missing and redundant data for subsequent comparison.

[0089] In some embodiments, after the step of obtaining the test result of the current test logic block, the method further includes: if the test result of the current test logic block is failure, ending the test process. Specifically, after obtaining the test result of the current test logic block through step S104 (comparing the reference column and the comparison column background data line by line), the determination standard of the test result being failure needs to be determined first, that is, there is at least one place in the current logic block where the background data is inconsistent (for example, the data stored in the comparison column of a certain line does not match the data in the same industry column, or there is a continuous multi-line / multi-column data deviation), which means that there is a clear defect in the address transmission path of the logic block (such as address decoding error caused by signal crosstalk, inter-symbol interference, or process problems of hardware components such as Column Decoder).

[0090] If it is determined that the test result of the current test logic block is failure, the operation of terminating the overall test process will be triggered. It needs to be pointed out that the strategy of "failure to end" is an optional test logic, and its applicable scenario needs to be determined in combination with actual needs. If it is necessary to analyze the defect distribution in depth (such as judging whether the defect exists in a single logic block or multiple logic blocks), the failure information can also be recorded and the remaining logic blocks can be tested.

[0091] As can be seen from the above LPDDR chip test method, the method can detect the address interference caused by the process defects of the signal transmission path in the LPDDR chip, and accurately reflect the failure position and specific failure access sequence through the mapping of the address and the stored data, thereby realizing the accurate detection of the LPDDR chip with access address error problem in special scenarios.

[0092] Corresponding to the above-mentioned LPDDR chip test method embodiment, the embodiment of the present application also provides an LPDDR chip test system, as shown in Figure 10 The system comprises: A logic block acquisition module 1010 is configured to initialize a chip, and divide the storage matrix of the chip to obtain logic blocks. The background data writing module 1020 is configured to calculate the background data of all memory cells in each row of the logical block according to the address corresponding to the row, and write the background data into all memory cells in the row. The comparison initialization module 1030 is configured to select the current test logical block in a preset order, and determine the reference column and the comparison column of the current test logical block. The comparison test execution module 1040 is configured to compare the background data corresponding to the reference column with the background data corresponding to the comparison column in sequence according to the number of rows corresponding to the reference column, to obtain the test result of the current test logical block. The cycle test execution module 1050 is configured to, if the test result of the current test logical block is passed, perform the test of the next logical block in the preset order until the test of all logical blocks is completed.

[0093] It can be known from the above LPDDR test system that the system can detect the address interference caused by the process defects of the signal transmission path in the LPDDR chip, and accurately reflect the failure position and specific failure access sequence through the mapping of the address and the storage data, so as to realize the accurate detection of the LPDDR chip with the access address error problem in the special scenario.

[0094] The LPDDR test system provided in the embodiments of the present application has the same implementation principle and technical effects as the foregoing LPDDR chip test method embodiments. For brief description, the parts not mentioned in the system embodiment part can be referred to the corresponding contents in the foregoing LPDDR chip test method embodiments.

[0095] The embodiment further provides a test system, and a structural schematic diagram of the test system is shown in Figure 11 The device includes a processor 101 and a memory 102; the memory 102 is configured to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the steps of the foregoing LPDDR chip test method.

[0096] Figure 11 The test system shown in the figure further includes a bus 103 and a communication interface 104, and the processor 101, the communication interface 104 and the memory 102 are connected through the bus 103.

[0097] The memory 102 can include a high-speed random access memory (RAM) and can also include a non-volatile memory, for example, at least one disk memory. The bus 103 can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 11Only one bidirectional arrow is used to represent multiple buses or multiple types of buses.

[0098] The communication interface 104 is configured to connect with at least one user terminal and other network units through a network interface, and transmit the encapsulated IPv4 packet or the IPv4 packet to the user terminal through the network interface.

[0099] The processor 101 can be an integrated circuit chip with processing capability. In implementation process, each step of the above method can be completed by integrated logic circuit or software form instruction in the processor 101. The processor 101 described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method, step and logic block in the embodiments of the present disclosure can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present disclosure can be directly embodied as a hardware code processor to execute, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage medium in the art. The storage medium is located in the memory 102, and the processor 101 reads the information in the memory 102 and combines the hardware to complete the steps of the method of the above embodiments.

[0100] The embodiment of the present application further provides a storage medium, and the storage medium stores a computer program. When the computer program is run by a processor, the steps of the LPDDR chip test method in the above embodiment are executed.

[0101] In several embodiments provided in the present application, it should be understood that the disclosed system, device, apparatus and method can be implemented in other manners. The above described system embodiments are merely illustrative. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, or a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the among different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0102] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0103] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit.

[0104] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0105] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that any skilled person in the art can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features, within the technical range disclosed by the present application. The modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for testing LPDDR chips, characterized in that, The method includes: Initialize the chip and divide the chip's storage matrix into logic blocks; Calculate the background data of all storage units in each row of the logical block based on the address corresponding to each row, and write the background data into all storage units in that row. Select the current test logic block according to a preset order, and determine the reference column and comparison column of the current test logic block; The background data corresponding to the reference column is compared with the background data corresponding to the comparison column in turn according to the row number of the reference column to obtain the test result of the current test logic block; If the test result of the current test logic block is passed, the test of the next logic block is performed in the preset order until all logic blocks have been tested.

2. The LPDDR chip testing method according to claim 1, characterized in that, The memory matrix of the chip is divided into logic blocks, including: Determine the total number of bits corresponding to each row address in the storage matrix; Obtain the maximum number of bits that the storage unit can store, and determine the number of logical blocks corresponding to the storage matrix based on the ratio of the total number of bits to the maximum number of bits; The partitioning strategy corresponding to the storage matrix is ​​determined based on the number of logical blocks and the maximum number of bits. After the storage matrix is ​​partitioned using the partitioning strategy, the logical blocks are obtained.

3. The LPDDR chip testing method according to claim 1, characterized in that, The steps of calculating the background data of all the storage cells in each row of the logical block based on the address corresponding to each row, and writing the background data into all the storage cells in the row, include: Obtain the row number of the logical block and the row address corresponding to each row of the storage unit; The background data of all storage cells in each row is obtained by taking the remainder between the row number and the row address of the logical block, and the background data is written into all storage cells of the corresponding row.

4. The LPDDR chip testing method according to claim 1, characterized in that, Determining the reference columns and comparison columns of the current test logic block includes: A single column randomly selected from the current test logic block is determined as the reference column; The columns other than the reference column in the current test logic block are determined as the comparison columns.

5. The LPDDR chip testing method according to claim 1, characterized in that, Determining the reference columns and comparison columns of the current test logic block includes: The reference column is determined based on a single storage cell randomly selected within a single row in the current test logic block; The comparison column is determined based on all storage cells in a single row within the current test logic block, excluding the single storage cell.

6. The LPDDR chip testing method according to claim 1, characterized in that, The step of comparing the background data corresponding to the reference column with the background data corresponding to the comparison column sequentially according to the row number of the reference column to obtain the test result of the current test logic block includes: A single row randomly selected from the reference column is determined as the starting row; The traversal order of the reference column is determined based on the row number corresponding to the starting row in the reference column. Starting from the initial row, in accordance with the traversal order, the first background data corresponding to the reference column is compared with the second background data corresponding to the comparison column under the same row number for consistency. The test result corresponding to the current test logic block is determined based on the consistency comparison result between the first background data and the second background data.

7. The LPDDR chip testing method according to claim 6, characterized in that, The step of determining the traversal order of the reference column based on the row number corresponding to the starting row in the reference column includes: Obtain the current row number corresponding to the starting row in the reference column, and obtain the starting row number and ending row number of the reference column in sequence according to the row number arrangement order of the reference column; Obtain the first row number interval between the current row number and the ending row number, and determine the first traversal order according to the row number increment order corresponding to the first row number interval; Obtain the second row number interval between the current row number and the starting row number, and determine the second traversal order according to the row number descending order corresponding to the second row number interval; The traversal order corresponding to the reference column is determined based on the first traversal order and the second traversal order.

8. The LPDDR chip testing method according to claim 7, characterized in that, Starting from the initial row, and following the traversal order, the steps of performing a consistency comparison between the first background data corresponding to the reference column and the second background data corresponding to the comparison column under the same row number include: Get the initialized flags; When the flag is detected as the first flag, the first background data corresponding to the reference column under the same row number is sequentially compared with the second background data corresponding to the comparison column according to the first traversal order. When the current row number is detected to be the same as the termination row number, the traversal of the first row number interval is stopped, and the flag is set to the second flag. When the flag is detected to be the second flag, the first background data corresponding to the reference column under the same row number is sequentially compared with the second background data corresponding to the comparison column according to the second traversal order. When the current row number is detected to be the same as the starting row number, the traversal of the second row number interval is stopped, and the flag is set to the first flag.

9. The LPDDR chip testing method according to claim 1, characterized in that, After obtaining the test result of the current test logic block, the method further includes: If the test result of the current test logic block is a failure, the test process ends.

10. A testing system, characterized in that, The testing system includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, and the processor executing the computer-executable instructions to implement the steps of the LPDDR chip testing method according to any one of claims 1 to 8.

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