Charging control circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronic circuits, in particular to a charging control circuit, a chip and electronic equipment. The charging control circuit comprises a first current sampling circuit, a first operational amplifier, a current mirror circuit, a first compensation voltage generation circuit, a second compensation voltage generation circuit, a reference voltage generation circuit and a voltage regulation circuit. The first current sampling circuit samples the load current of the charging output end at the current moment, and the current mirror circuit comprises a first controlled current branch and a second controlled voltage branch; the first controlled current branch and the second controlled voltage branch generate two paths of compensation current according to the first reference current respectively; the two compensation voltage generation circuits generate two paths of compensation voltages according to the compensation current; the reference voltage generation circuit generates a target reference voltage according to the two paths of compensation voltages; the voltage adjusting circuit adjusts the charging voltage output by the charging output end according to the target reference voltage so as to control the charging voltage to be stabilized at a target value, and the charging efficiency of rapid charging is guaranteed.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a charging control circuit, chip, and electronic device. Background Technology

[0002] In related technologies, with the development of electronic circuit technology, fast charging technology has gradually matured and is applied to various electronic devices and different application scenarios. In the field of fast charging technology, fast charging chips typically need to control the charging voltage at the charging output terminal to maintain a set voltage value in order to achieve fast charging of energy storage devices such as batteries. However, due to the parasitic resistance or wire bonding resistance on the charging bus itself, and the fact that the load current on the charging bus is usually large during fast charging, there is a certain voltage loss on the charging bus. This results in the charging voltage output to the battery at the charging output terminal being usually lower than the bus input voltage at the charging input terminal, thus reducing fast charging efficiency. Summary of the Invention

[0003] This application provides a charging control circuit, chip, and electronic device to solve the technical problem in the related art where the charging voltage at the charging output terminal is usually lower than the bus input voltage at the charging input terminal, resulting in reduced fast charging efficiency.

[0004] In a first aspect, this application provides a charging control circuit for controlling the charging voltage output from the charging output terminal. The charging control circuit includes: a first current sampling circuit, a first operational amplifier, a current mirror circuit, a first compensation voltage generation circuit, a second compensation voltage generation circuit, a reference voltage generation circuit, and a voltage regulation circuit. The first current sampling circuit is used to sample the load current at the current moment of the charging output terminal, and convert the load current into a corresponding first sampling voltage to be output to the positive input terminal of the first operational amplifier; the voltage value of the first sampling voltage is proportional to the current value of the load current; The current mirror circuit includes a reference current branch, a first controlled current branch, and a second controlled voltage branch; a first sampling resistor is connected in series in the reference current branch, and the high-voltage end of the first sampling resistor is connected to the negative input end of the first operational amplifier; the first operational amplifier is used to control the reference current branch to generate a first reference current; the first controlled current branch and the second controlled voltage branch are respectively used to generate a first compensation current and a second compensation current based on the first reference current; The first compensation voltage generating circuit is used to generate a first compensation voltage based on the first compensation current, and the second compensation voltage generating circuit is used to generate a second compensation voltage based on the second compensation current. The reference voltage generation circuit is used to generate a target reference voltage based on the first compensation voltage and the second compensation voltage. The voltage regulation circuit is used to adjust the charging voltage output by the charging output terminal according to the target reference voltage.

[0005] In one possible design, the current mirror circuit further includes a third controlled current branch, which is used to generate a second reference current based on the first reference current; the ratio of the second reference current to the first reference current is a preset amplification factor. The first controlled current branch and the second controlled voltage branch are respectively used to generate a first compensation current and a second compensation current based on the second reference current.

[0006] In one possible design, the reference current branch includes a first transistor and a first sampling resistor. The control terminal of the first transistor is connected to the output terminal of the first operational amplifier. The first terminal of the first transistor is used to receive a first supply voltage. The second terminal of the first transistor is connected to the first terminal of the first sampling resistor, and the second terminal of the first sampling resistor is grounded. The third controlled current branch includes a second transistor and a third transistor. The first terminal of the second transistor is connected to the first terminal of the first transistor, the control terminal of the second transistor is connected to the control terminal of the first transistor, the second terminal of the second transistor is connected to the second terminal of the third transistor, the first terminal of the third transistor is grounded, and the second terminal and the control terminal of the third transistor are shorted. The first controlled current branch includes a fourth transistor, the control electrode of the fourth transistor is connected to the control electrode of the third transistor, the first electrode of the fourth transistor is grounded, and the second electrode of the fourth transistor is used to input the first compensation current; The second controlled current branch includes a fifth transistor, the control electrode of which is connected to the control electrode of the fourth transistor, the first electrode of which is grounded, and the second electrode of which is used to input the second compensation current.

[0007] In one possible design, the ratio of the first reference current to the second reference current is 1:K; where K is a preset amplification factor, K≥1; The ratio of the current values ​​of the second reference current, the first compensation current, and the second compensation current is 1:1:1.

[0008] In one possible design, the first compensation voltage generation circuit includes a second operational amplifier, a second resistor, a third resistor, and a sixth transistor; the positive input terminal of the second operational amplifier is used to receive a first voltage, the output terminal of the second operational amplifier is connected to the control electrode of the sixth transistor, the second electrode of the sixth transistor is used to receive a second supply voltage, the first electrode of the sixth transistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the first terminal of the third resistor, and the second terminal of the third resistor is grounded; the second terminal of the second resistor is also connected to both the negative input terminal of the second operational amplifier and the second electrode of the fourth transistor; the first terminal of the second resistor is used to output the first compensation voltage. The second compensation voltage generation circuit includes a third operational amplifier, a seventh transistor, a fourth resistor, and a fifth resistor. The positive input terminal of the third operational amplifier is used to receive a second voltage. The output terminal of the third operational amplifier is connected to the control terminal of the seventh transistor. The second terminal of the seventh transistor is used to receive a third supply voltage. The first terminal of the seventh transistor is connected to the first terminal of the fourth resistor and the first terminal of the fifth resistor. The second terminal of the fourth resistor is grounded. The second terminal of the fifth resistor is connected to the second terminal of the fifth transistor. The first terminal of the fifth resistor is used to output the second compensation voltage.

[0009] In one possible design, the reference voltage generation circuit includes multiple digital-to-analog converters (DACs) connected in series, wherein the output of one DAC is connected to the input of the next DAC; wherein the input of the first DAC is used to receive the second compensation voltage, and the multiple DACs are used to sequentially convert the second compensation voltage into digital-to-analog signals, so that the last DAC outputs the target reference voltage.

[0010] In one possible design, the reference voltage generation circuit is an R2R architecture digital-to-analog converter circuit, which includes a high voltage input terminal, a low voltage input terminal, and a reference voltage output terminal. The first end of the second resistor is connected to the high-voltage input terminal of the digital-to-analog converter circuit of the R2R architecture to input a first compensation voltage to the digital-to-analog converter circuit of the R2R architecture; the first end of the fifth resistor is connected to the low-voltage input terminal of the digital-to-analog converter circuit of the R2R architecture to input a second compensation voltage to the digital-to-analog converter circuit of the R2R architecture; the reference voltage output terminal is used to output the target reference voltage.

[0011] In one possible design, the voltage regulation circuit includes a first voltage sampling circuit, a fourth operational amplifier, and a first optocoupler control loop; The sampling terminal of the first voltage sampling circuit is connected to the charging input terminal, the output terminal of the first voltage sampling circuit is connected to the positive input terminal of the fourth operational amplifier, the inverting input terminal of the fourth operational amplifier is connected to the reference voltage output terminal of the reference voltage generation circuit, the output terminal of the fourth operational amplifier is connected to the control input terminal of the first optocoupler control loop, and the control output terminal of the first optocoupler control loop is connected to the charging input terminal. The first voltage sampling circuit is used to sample the second sampling voltage corresponding to the bus input voltage on the charging input terminal, and input the second sampling voltage to the positive input terminal of the fourth operational amplifier; the inverting input terminal of the fourth operational amplifier is used to receive the target reference voltage, and the fourth operational amplifier is used to generate a voltage adjustment signal according to the second sampling voltage and the target reference voltage; the first optocoupler control loop is used to pull up or pull down the bus input voltage on the charging input terminal according to the voltage adjustment signal.

[0012] In one possible design, the voltage regulation circuit further includes an output resistor, a sixth resistor, and a first capacitor; The first end of the output resistor is connected to the output end of the fourth operational amplifier, and the second end of the output resistor is grounded; the first end of the sixth resistor is connected to the output end of the fourth operational amplifier, the second end of the sixth resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded.

[0013] Secondly, this application also provides a chip, the chip including the charging control circuit as described in any of the preceding claims.

[0014] Thirdly, this application also provides an electronic device, which includes a charging control circuit as described in any of the preceding claims.

[0015] The charging control circuit provided in the first aspect above is used to control the charging voltage output from the charging output terminal. The charging control circuit provided in this application includes: a first current sampling circuit, a first operational amplifier, a current mirror circuit, a first compensation voltage generation circuit, a second compensation voltage generation circuit, a reference voltage generation circuit, and a voltage regulation circuit. The first current sampling circuit samples the load current at the charging output terminal at the current moment and converts the load current into a corresponding first sampling voltage to be output to the positive input terminal of the first operational amplifier. The voltage value of the first sampling voltage is proportional to the current value of the load current. The current mirror circuit includes a reference current branch, a first controlled current branch, and a second controlled voltage branch. The reference current... A first sampling resistor is connected in series in the branch circuit, and the high-voltage end of the first sampling resistor is connected to the negative input terminal of the first operational amplifier. The first operational amplifier is used to control the reference current branch to generate a first reference current. A first controlled current branch and a second controlled voltage branch are used to generate a first compensation current and a second compensation current, respectively, based on the first reference current. A first compensation voltage generation circuit is used to generate a first compensation voltage based on the first compensation current, and a second compensation voltage generation circuit is used to generate a second compensation voltage based on the second compensation current. A reference voltage generation circuit is used to generate a target reference voltage based on the first compensation voltage and the second compensation voltage. A voltage adjustment circuit is used to adjust the charging voltage output at the charging output terminal based on the target reference voltage. It can be seen that in this application, the load current in the sampling circuit is used to generate a corresponding compensation voltage, and then a corresponding target reference voltage is generated based on the compensation voltage. Based on the target reference voltage, the charging voltage can be controlled to stabilize at the target value to ensure the charging efficiency of fast charging.

[0016] The beneficial effects provided by the other aspects and the various possible designs of the other aspects can be found in the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0017] Figure 1 A schematic diagram of a fast charging circuit section provided for related technologies; Figure 2 This is one of the schematic diagrams of a charging control circuit provided in related technologies; Figure 3 This is the second schematic diagram of a charging control circuit structure provided in related technologies; Figure 4 This is one of the schematic diagrams of the charging control circuit structure provided in the embodiments of this application; Figure 5 This is one of the schematic diagrams of the current mirror circuit structure provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the first compensation voltage generation circuit provided in the embodiments of this application; Figure 7 A schematic diagram of the structure of the second compensation voltage generation circuit provided in the embodiments of this application. Figure 8 This is a partial structural schematic diagram of the reference voltage generation circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of the voltage regulation circuit structure provided in an embodiment of this application. Detailed Implementation

[0018] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0021] The transistor in this application is a three-terminal transistor, with its three terminals being a control terminal, a first terminal, and a second terminal. The transistor can be a bipolar transistor (BPT) or a field-effect transistor (FET), etc. For example, when the transistor is a BPT, its control terminal is the base of the BPT, the first terminal can be the collector or emitter of the BPT, and the corresponding second terminal can be the emitter or collector of the BPT; when the transistor is a FET, its control terminal is the gate of the FET, the first terminal can be the drain or source of the FET, and the corresponding second terminal can be the source or drain of the FET.

[0022] In the field of fast charging technology, due to the parasitic resistance or wire bonding resistance on the charging bus itself, and the fact that the load current on the charging bus is usually large during fast charging, there is a certain voltage loss on the charging bus. As a result, the charging voltage output to the battery at the charging output terminal is usually lower than the bus input voltage at the charging input terminal, which leads to a reduction in fast charging efficiency. Figure 1 Please refer to the schematic diagram of the fast charging circuit for related technologies. Figure 1 As shown, in a fast charging chip, the charging output terminal is electrically connected to the battery for rapid charging. Parasitic resistance or wire resistance exists on the cable between the charging input and output terminals. This parasitic resistance or wire resistance can be equivalent to a line resistance Rcable. Under a large load current Iload, the bus input voltage BBUSP at the charging input terminal, after passing through the line resistance Rcable, is transmitted to the charging output terminal to obtain the charging voltage BBUSP_B. At this point, BBUSP_B = BBUSP - Iload * Rcable. It is evident that when the load current Iload is large, the energy loss caused by the line resistance Rcable is significant, causing the charging voltage BBUSP_B output at the charging output terminal to typically be lower than the bus input voltage VBUSP at the charging input terminal, thus reducing fast charging efficiency.

[0023] To overcome the technical deficiencies in the aforementioned related technologies, a charging control circuit is provided. Figure 2 This is one of the schematic diagrams of a charging control circuit provided in related technologies. Please refer to [link / reference]. Figure 2As shown, the charging control circuit includes a fifth operational amplifier 22, a second voltage sampling circuit 21, and a second optocoupler control loop 22. The second voltage sampling circuit 21 includes an eleventh sampling resistor R11 and a twelfth sampling resistor R12. The first terminal of the eleventh sampling resistor R11 is connected to the charging input terminal of the charging bus, and the second terminal of the eleventh sampling resistor R11 is connected to the first terminal of the twelfth sampling resistor R12. The second terminal of the twelfth sampling resistor R12 is grounded (GND). The second voltage sampling circuit 21 is used to sample the first voltage level corresponding to the bus input voltage BVBUSP at the charging input terminal. The third sampled voltage VFB3 is input to the positive input of the fifth operational amplifier 22. The negative input of the fifth operational amplifier 22 receives the third reference voltage VREDF3. The fifth operational amplifier 22 performs calculations based on the third sampled voltage VFB3 and the third reference voltage VREDF3 to output a second voltage adjustment signal Comp2. The second voltage adjustment signal Comp2 is used to control the second optocoupler control loop 22 to pull up or pull down the bus input voltage BVBUSP, thereby maintaining the bus input voltage BVBUSP at the target value. It can be seen that, based on Figure 2 The provided charging control circuit can adjust the bus input voltage BVBSP, but it cannot solve the technical problem that the charging voltage BVBSP_B at the charging output terminal is usually lower than the bus input voltage BVBSP at the charging input terminal. That is, it still cannot adjust or compensate for the charging voltage BVBSP_B at the charging output terminal to improve the charging voltage BVBSP_B at the charging output terminal.

[0024] Figure 3 This is the second schematic diagram of the charging control circuit structure provided in the related technology. Please refer to [the original text]. Figure 3As shown, the charging control circuit also includes a second current sampling circuit 31, a thirty-first transistor Q31, a thirty-first sampling resistor R31, a thirty-second transistor Q32, a thirty-third transistor Q33, and a thirty-fourth transistor Q34. The sampling terminal of the second current sampling circuit 31 is connected to the charging output terminal to sample the load current Iload on the charging bus. The output terminal of the second current sampling circuit 31 is connected to the control electrode of the thirty-first transistor Q31. The second electrode of the thirty-first transistor Q31 is used to receive the supply voltage VDD. The first electrode of the thirty-first transistor Q31 is connected to the first terminal of the thirty-first sampling resistor R31, and the second terminal of the thirty-first sampling resistor R31 is grounded to GND. The control electrode of the thirty-first transistor Q31 is connected to the control electrode of the thirty-second transistor Q32. The second electrode of the thirty-second transistor Q32 is also used to receive the supply voltage VDD. The first terminal of transistor Q32 is connected to the second terminal of transistor Q33, which is also grounded (GND). Simultaneously, the second terminal and control terminal of transistor Q33 are shorted. The control terminal of transistor Q33 is connected to the control terminal of transistor Q34, which is also grounded (GND). The second terminal of transistor Q34 is connected to the voltage divider resistor in the second voltage sampling circuit 21. The current in the branch containing transistor Q34 is the third compensation current Icomp3, which draws a portion of the current from the voltage divider resistor to adjust its voltage value. Transistor Q31, sampling resistor R31, transistor Q32, Q33, and Q34 together form a current mirror circuit to generate the corresponding third compensation current Icomp3 based on the sampled load current Iload. The amplification factor between the thirty-first transistor Q31 and the thirty-second transistor Q32 is K, and the amplification factor between the thirty-third transistor Q33 and the thirty-fourth transistor Q34 is 1:1. The voltage value at the upper end of the thirty-first resistor R31 is the third sampling voltage Vsns3.

[0025] Among them, transistors Q31 (31), Q32 (32), Q33 (33), and Q34 (34) are all NMOS (N-Metal-Oxide-Semiconductor) transistors. When transistors Q31 (31), Q32 (32), Q33 (33), and Q34 (34) are all NMOS transistors, their first electrode is the source, their second electrode is the drain, and their control electrode is the gate.

[0026] Please see Figure 3The charging control circuit shown converts the sampled load current Iload into voltage information, and after processing by several K-scale current mirrors, generates a corresponding third compensation current Icomp3. The generated third compensation current Icomp3 = K * Vsns3 / R310, where Vsns3 represents the third sampled voltage at the upper end of the thirty-first resistor R31, and R310 represents the resistance value of the thirty-first sampling resistor R31. The third compensation current Icomp3 is drawn from a node in the voltage divider resistor string of the bus input voltage BVBSP. Assuming the resistance from this node to the charging bus is R0, since the third sampled voltage VFB3 and the third reference voltage VREDF3 input to the negative input terminal of the fifth operational amplifier 22 are modulated by the compensation loop to make the voltage values ​​of the third sampled voltage VFB3 and the third reference voltage VREDF3 equal, the third compensation voltage on the bus input voltage BVBSP is Vcomp3, which is Vcomp3 = Icomp * R0 = K * Vsns31 * R0 / R310. In this way, the third compensation voltage Vcomp3 and the third sampling voltage Vsns3 have a linear correspondence. As the load current Iload increases, the third compensation voltage Vcomp also gradually increases to compensate for the bus input voltage BVBSP. This causes the charging voltage BVBSP_B at the charging output terminal to increase to the target value, thereby improving the efficiency of fast charging.

[0027] Then, when the charging control circuit provided by the relevant technology compensates the charging voltage BVBSP_B, the correspondence between the third compensation voltage Vcomp3 and the third sampling voltage Vsns3 depends on the matching of the current mirror and the matching between the resistor strings. This compensation scheme not only requires high accuracy of the current mirror parameters and resistor parameters, but also places high demands on the hardware layout of the chip. First, because the source terminals of the transistors in the K-ratio current mirror are not connected together, the mirror relationship of the current mirror circuit has a considerable systematic error. Second, the voltage divider resistor string used to sample the bus input voltage BVBSP usually includes multiple resistors, which requires matching between multiple devices in the chip. This places high demands on the layout of each device on the chip, making the hardware implementation difficult. Furthermore, since the bus input voltage BVBSP is generally high, the transistors on the branch where the third compensation current Icomp3 input node is located (such as the thirty-fourth transistor Q34) must be high-voltage transistors. High-voltage transistors are generally large and risky, which increases the size of the chip. At the same time, high-voltage transistors have poor matching, which affects the accuracy of the current mirror and thus affects the compensation accuracy of the charging voltage BVBSP_B.

[0028] To overcome the shortcomings of the aforementioned related technologies, this application provides a charging control circuit, which includes: a first current sampling circuit, a first operational amplifier, a current mirror circuit, a first compensation voltage generation circuit, a second compensation voltage generation circuit, a reference voltage generation circuit, and a voltage regulation circuit; wherein, the first current sampling circuit is used to sample the load current at the charging output terminal at the current moment, and convert the load current into a corresponding first sampling voltage to be output to the positive input terminal of the first operational amplifier, and the voltage value of the first sampling voltage is proportional to the current value of the load current; the current mirror circuit includes a reference current branch, a first controlled current branch, and a second controlled voltage branch; a voltage regulator circuit is connected in series on the reference current branch. A first sampling resistor, the high-voltage end of which is connected to the negative input terminal of a first operational amplifier; the first operational amplifier, used to control the reference current branch to generate a first reference current; a first controlled current branch and a second controlled voltage branch, used to generate a first compensation current and a second compensation current respectively based on the first reference current; a first compensation voltage generation circuit, used to generate a first compensation voltage based on the first compensation current; a second compensation voltage generation circuit, used to generate a second compensation voltage based on the second compensation current; a reference voltage generation circuit, used to generate a target reference voltage based on the first compensation voltage and the second compensation voltage; and a voltage adjustment circuit, used to adjust the charging voltage output from the charging output terminal based on the target reference voltage. According to the charging control circuit provided in this application, the load current in the oversampling circuit is used to generate a corresponding compensation voltage, and then a corresponding target reference voltage is generated based on this compensation voltage. Based on this target reference voltage, the charging voltage can be controlled to stabilize at the target value to ensure the charging efficiency of fast charging.

[0029] Figure 4 For one of the schematic diagrams of the charging control circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 4As shown, the charging control circuit provided in this embodiment includes: a first current sampling circuit 41, a first operational amplifier 42, a current mirror circuit 43, a first compensation voltage generation circuit 44, a second compensation voltage generation circuit 45, a reference voltage generation circuit 46, and a voltage regulation circuit 47; wherein, the first current sampling circuit 41 is used to sample the load current at the charging output terminal at the current moment, and convert the load current into a corresponding first sampling voltage Vsns1 to be output to the positive input terminal of the first operational amplifier 42. The voltage value Vsns1 of the first sampling voltage is proportional to the current value of the load current, that is, the voltage value of the first sampling voltage Vsns1 can reflect the magnitude of the load current on the charging bus. The negative input terminal of the first operational amplifier 42 is connected to the current mirror circuit 43. The current mirror circuit 43 is used to generate a first compensation current IcompH and a second compensation current IcompL according to a preset ratio based on the first sampling voltage Vsns1. The first compensation voltage generation circuit 44 is used to generate a first compensation voltage VREF_H based on the first compensation current IcompH. The second compensation voltage generation circuit 45 is used to generate a second compensation voltage VREF_L based on the second compensation current IcompL. The reference voltage generation circuit 46 is used to generate a target reference voltage Vref based on the first compensation voltage VREF_H and the second compensation voltage VREF_L. The voltage adjustment circuit 47 is used to adjust the charging voltage BVBUSP_B output from the charging output terminal according to the target reference voltage Vref.

[0030] The charging control circuit provided in this embodiment samples the load current in the sampling circuit and converts it into a corresponding first sampling voltage Vsns1. Then, the current mirror circuit 43 generates two compensation currents with the same current value based on the first sampling voltage Vsns1. Subsequently, the two compensation voltage generation circuits generate two compensation voltages based on the two compensation currents. Finally, the corresponding target reference voltage is generated based on the two compensation voltages, thereby realizing feedback regulation of the charging voltage. Based on the target reference voltage, the charging voltage can be controlled to stabilize at the target value to ensure the charging efficiency of fast charging.

[0031] In one embodiment of this application, the sampling terminal of the first current sampling circuit 41 is located at the charging output terminal to sample the load current Iload at the charging output terminal. Then, the sampled load current Iload can be converted into a corresponding first sampling voltage Vsns1 through a current-to-voltage conversion circuit. For example, in one embodiment, the load current Iload can be converted into the corresponding first sampling voltage Vsns1 through a resistor. When the resistance value is constant, the current value of the load current Iload is proportional to the voltage value of the first sampling voltage Vsns1. Therefore, the converted first sampling voltage Vsns1 can reflect the magnitude of the load current Iload to a certain extent.

[0032] Figure 5 For one of the schematic diagrams of the current mirror circuit structure provided in the embodiments of this application, please refer to [link / reference]. Figure 5 As shown, in one embodiment, the current mirror circuit 43 includes a reference current branch 431, a first controlled current branch 433, and a second controlled voltage branch 434; wherein, a first sampling resistor Rsns1 is connected in series on the reference current branch 431, and the high-voltage terminal of the first sampling resistor Rsns1 is connected to the negative input terminal of the first operational amplifier 42; the first operational amplifier 42 is used to control the reference current branch 431 to generate a first reference current; the first controlled current branch 433 and the second controlled voltage branch 434 are respectively used to generate a first compensation current IcompH and a second compensation current IcompL according to the first reference current.

[0033] In this embodiment, the reference current branch 431 generates a first reference current. The first controlled current branch 433 and the second controlled voltage branch 434 both form a current mirror structure with the reference current branch 431. The first reference current generated by the reference current branch 431 is then replicated to obtain a first compensation current IcompH and a second compensation current IcompL. The first compensation current IcompH and the first reference current generated by the reference current branch 431 are in a certain ratio. Similarly, the second compensation current IcompL and the first reference current generated by the reference current branch 431 are also in a certain ratio. The current amplification factor in the current mirror circuit is mainly determined by the parameters of the metal-oxide-semiconductor field-effect transistor (MOSFET). In one embodiment, the current values ​​of the first compensation current IcompH and the second compensation current IcompL can be the same; in another embodiment, the current values ​​of the first compensation current IcompH and the second compensation current IcompL can be different.

[0034] Please continue reading Figure 5 As shown, in one embodiment of this application, the current mirror circuit 43 further includes a third controlled current branch 432, which is used to generate a second reference current based on a first reference current. The first controlled current branch and the second controlled voltage branch are respectively used to generate a first compensation current and a second compensation current based on the second reference current. It is understood that, in one embodiment, the third controlled current branch 432 can amplify or reduce the first reference current generated by the reference current branch 431 to obtain the second reference current. For example, in this embodiment, the third controlled current branch 432 can amplify the first reference current generated by the reference current branch 431 by a factor of K to obtain the second reference current; in other words, the ratio of the second reference current to the first reference current is a preset multiple K.

[0035] Please continue reading Figure 5 As shown, in one embodiment of this application, the reference current branch 431 includes a first transistor Q1 and a first sampling resistor Rsns1. The control terminal of the first transistor Q1 is connected to the output terminal of the first operational amplifier 42. The first terminal of the first transistor Q1 is used to receive the first supply voltage VDD1, and the second terminal of the first transistor Q1 is connected to the first terminal of the first sampling resistor Rsns1. The second terminal of the first sampling resistor Rsns1 is grounded to GND. During operation, the first operational amplifier 42 outputs a control signal to control the first transistor Q1 to conduct, thereby generating a first reference current in the reference current branch 431. Simultaneously, the negative input terminal of the first operational amplifier 42 samples the voltage value at the upper end of the first sampling resistor Rsns1.

[0036] In this embodiment, the first transistor Q1 can be a PMOS (P-Metal-Oxide-Semiconductor) transistor; in other embodiments, the first transistor Q1 can also be an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the first transistor Q1 is a PMOS transistor, its first terminal is the source, its second terminal is the drain, and its control terminal is the gate. That is, in this embodiment, the gate of the first transistor Q1 is connected to the output terminal of the first operational amplifier 42, the source of the first transistor Q1 is used to receive the first supply voltage VDD1, the drain of the first transistor Q1 is connected to the first terminal of the first sampling resistor Rsns1, and the second terminal of the first sampling resistor Rsns1 is grounded to GND.

[0037] Please continue reading Figure 5 As shown, in one embodiment of this application, the third controlled current branch 432 includes a second transistor Q2 and a third transistor Q3. The first terminal of the second transistor Q2 is connected to the first terminal of the first transistor Q1, the control terminal of the second transistor Q2 is connected to the control terminal of the first transistor Q1, the second terminal of the second transistor Q2 is connected to the second terminal of the third transistor Q3, the first terminal of the third transistor Q3 is grounded to GND, and the second terminal and the control terminal of the third transistor Q3 are short-circuited.

[0038] In this embodiment, the second transistor Q2 can be a PMOS (P-Metal-Oxide-Semiconductor) transistor; in other embodiments, the second transistor Q2 can also be an NMOS (N-Metal-Oxide-Semiconductor) transistor; the third transistor Q3 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the second transistor Q2 is a PMOS transistor, its first electrode is the source, its second electrode is the drain, and its control electrode is the gate; when the third transistor Q3 is an NMOS transistor, its first electrode is the source, its second electrode is the drain, and its control electrode is the gate. That is, in this embodiment, the source of the second transistor Q2 is connected to the source of the first transistor Q1, the gate of the second transistor Q2 is connected to the gate of the first transistor Q1, the drain of the second transistor Q2 is connected to the drain of the third transistor Q3, the source of the third transistor Q3 is grounded (GND), and the drain and gate of the third transistor Q3 are shorted.

[0039] Please continue reading Figure 5 As shown, in one embodiment of this application, the first controlled current branch 433 includes a fourth transistor Q4. The control electrode of the fourth transistor Q4 is connected to the control electrode of the third transistor Q3. The first electrode of the fourth transistor Q4 is grounded to GND, and the second electrode of the fourth transistor Q4 is used to input the first compensation current IcompH. In this embodiment, the fourth transistor Q4 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the fourth transistor Q4 is an NMOS transistor, its first electrode is the source, its second electrode is the drain, and its control electrode is the gate. That is, in this embodiment, the gate of the fourth transistor Q4 is connected to the gate of the third transistor Q3, the source of the fourth transistor Q4 is grounded to GND, and the drain of the fourth transistor Q4 is used to input the first compensation current IcompH. It can be understood that when the fourth transistor Q4 in this embodiment is an NMOS transistor, the flow direction of the first compensation current IcompH in its branch is from the drain to the source. At this time, the first controlled current branch 433 functions similarly to a current source.

[0040] Please continue reading Figure 5As shown, in one embodiment of this application, the second controlled current branch 434 includes a fifth transistor Q5. The control electrode of the fifth transistor Q5 is connected to the control electrode of the fourth transistor Q4. The first electrode of the fifth transistor Q5 is grounded to GND, and the second electrode of the fifth transistor Q5 is used to input a second compensation current. In this embodiment, the fifth transistor Q5 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the fifth transistor Q5 is an NMOS transistor, its first electrode is the source, its second electrode is the drain, and its control electrode is the gate. That is, in this embodiment, the gate of the fifth transistor Q5 is connected to the gate of the fourth transistor Q4, the source of the fifth transistor Q5 is grounded to GND, and the drain of the fifth transistor Q5 is used to input the second compensation current IcompL. It can be understood that when the fifth transistor Q5 in this embodiment is an NMOS transistor, the flow direction of the second compensation current IcompL in its branch is from the drain to the source. At this time, the function of the second controlled current branch 434 is similar to that of a current source.

[0041] In one embodiment of this application, by setting the parameters of each transistor, the third controlled current branch 432 can amplify the first reference current generated by the reference current branch 431 by a factor of K to obtain the second reference current; that is, the ratio of the current values ​​of the first reference current and the second reference current is 1:K; where K is a preset amplification factor, K≥1.

[0042] In one embodiment of this application, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 can be selected as NMOS transistors with the same specifications or parameters, so that the first controlled current branch 433 and the second controlled current branch 434 can amplify the second reference current generated on the third controlled current branch 432 in a 1:1 ratio, that is, the ratio of the current values ​​of the second reference current, the first compensation current, and the second compensation current is 1:1:1.

[0043] Figure 6 For a schematic diagram of the first compensation voltage generation circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 6As shown, the first compensation voltage generation circuit 44 provided in this embodiment includes a second operational amplifier 441, a second resistor R2, a third resistor R3, and a sixth transistor Q6. The positive input terminal of the second operational amplifier 441 receives a first voltage, and the output terminal of the second operational amplifier 441 is connected to the control electrode of the sixth transistor Q6. The second electrode of the sixth transistor Q6 receives a second supply voltage VDD2. The first electrode of the sixth transistor Q6 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is grounded (GND). The second terminal of the second resistor R2 is also connected to the negative input terminal of the second operational amplifier 441 and the second electrode of the fourth transistor Q4. The first terminal of the second resistor R2 is used to output the first compensation voltage VREF_H.

[0044] In this embodiment, the second terminal of the second resistor R2 is connected to the second terminal of the fourth transistor Q4. At this time, the first controlled current branch 433 is equivalent to a current source, providing a downward and stable first compensation current IcompH. The negative input terminal of the second operational amplifier 441 samples the voltage at the upper end of the third resistor R3. Then, the second operational amplifier 441 compares the received first voltage with the sampled voltage value, thereby outputting a corresponding control signal to the control terminal of the sixth transistor Q6 to control the switching frequency of the sixth transistor Q6, so that the first terminal of the second resistor R2 outputs the first compensation voltage VREF_H.

[0045] In one embodiment of this application, the first voltage received by the second operational amplifier 441 can be set according to the voltage required by the high-voltage input terminal of the reference voltage generation circuit 46. For example, the voltage value of the first voltage can be set to the high-voltage input terminal voltage of the reference voltage generation circuit. Specifically, in this embodiment, the first voltage received by the non-inverting input terminal of the second operational amplifier 441 can be set to 1.2V.

[0046] In one embodiment of this application, the sixth transistor Q6 can be an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the sixth transistor Q6 is an NMOS transistor, its first terminal is the source, its second terminal is the drain, and its control terminal is the gate. That is, the output terminal of the second operational amplifier 441 is connected to the gate of the sixth transistor Q6, the drain of the sixth transistor Q6 is used to receive the second supply voltage VDD2, and the source of the sixth transistor Q6 is connected to the first terminal of the second resistor R2.

[0047] In one embodiment of this application, the first voltage received at the positive input terminal of the second operational amplifier 441 can be set to 1.2V. Using the principle of virtual short and virtual open circuits, the following relationship can be obtained: (1) In the above expression (1), VH represents the voltage value of the first compensation voltage VREF_H, R31 represents the resistance value of the third resistor R3, and R21 represents the resistance value of the second resistor R2. This represents the current value of the first compensation current IcompH.

[0048] Figure 7 For a schematic diagram of the second compensation voltage generation circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 7 As shown, the second compensation voltage generation circuit 45 provided in this embodiment includes a third operational amplifier 451, a seventh transistor Q7, a fourth resistor R4, and a fifth resistor R5. The positive input terminal of the third operational amplifier 451 is used to receive the second voltage. The output terminal of the third operational amplifier 451 is connected to the control terminal of the seventh transistor Q7. The second terminal of the seventh transistor Q7 is used to receive the third supply voltage VDD3. The first terminal of the seventh transistor Q7 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5. The second terminal of the fourth resistor R4 is grounded to GND. The second terminal of the fifth resistor R5 is connected to the second terminal of the fifth transistor Q5. The first terminal of the fifth resistor R5 is used to output the second compensation voltage VREF_L.

[0049] In this embodiment, the second terminal of the second resistor R2 and the negative input terminal of the third operational amplifier 451 are both connected to the drain of the fifth transistor Q5. At this time, the second controlled current branch 434 is equivalent to a current source, providing a downward-directed and stable second compensation current IcompL. The negative input terminal of the third operational amplifier 451 samples the voltage at the upper end of the fifth resistor R5. Then, the third operational amplifier 451 compares the received second voltage with the sampled voltage value, thereby outputting a corresponding control signal to the control terminal of the seventh transistor Q7 to control the switching frequency of the seventh transistor Q7, so that the first terminal of the fourth resistor R4 outputs the second compensation voltage VREF_L.

[0050] In one embodiment of this application, the second voltage received at the positive input terminal of the third operational amplifier 451 can be set according to the voltage required at the high-voltage input terminal of the reference voltage generation circuit 46. For example, the voltage value of the second voltage can be set to the low-voltage input terminal voltage of the reference voltage generation circuit. Specifically, in this embodiment, the second voltage received at the positive input terminal of the third operational amplifier 451 can be set to 0.2V.

[0051] In one embodiment of this application, the seventh transistor Q7 can be an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the seventh transistor Q7 is an NMOS transistor, its first terminal is the source, its second terminal is the drain, and its control terminal is the gate. That is, the output terminal of the third operational amplifier 451 is connected to the gate of the seventh transistor Q7, the drain of the seventh transistor Q7 is used to receive the third supply voltage VDD3, and the source of the seventh transistor Q7 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5.

[0052] In one embodiment of this application, the second voltage received at the positive input terminal of the third operational amplifier 451 can be set to 0.2V. Using the principle of virtual short and virtual open circuits, the following relationship can be obtained: (2) In the above expression (2), This indicates the voltage value of the second compensation voltage VREF_L. This represents the current value of the second compensation current IcompL. This indicates the resistance value of the fifth resistor, R5.

[0053] Please continue reading Figure 5 As shown, according to the current mirror circuit 43 structure provided in the embodiment of this application, the first compensation current IcompH and the second compensation current IcompL output by the current mirror circuit 43 have the same magnitude and have the relationship expressed by the following expression: IcompH1=IcompL1=K*Vsns11 / Rsns11 (3) In the above relational expression (3), IcompH1 represents the current value of the first compensation current IcompH, K represents the ratio of the second reference current to the first reference current, Vsns11 represents the voltage value of the first sampling voltage Vsns1, and Rsns11 represents the resistance value of the first sampling resistor Rsns1.

[0054] Analysis of the above relational expressions shows that if the voltage value VH of the first compensation voltage VREF_H and the voltage value of the second compensation voltage VREF_L are required... If the voltage ΔV is increased by the same amount, then the resistance values ​​of the second resistor R2 and the fifth resistor R5 must be the same, that is, the following must be satisfied. .

[0055] In one embodiment of this application, the reference voltage generation circuit includes multiple digital-to-analog converters (DACs) connected in series. The output terminal of one DAC is connected to the input terminal of the next DAC. The input terminal of the first DAC receives a second compensation voltage. The multiple DACs then sequentially convert the second compensation voltage into a digital signal. That is, the next DAC converts the voltage signal output by the previous DAC and outputs a digital voltage signal, and so on, so that the last DAC outputs the target reference voltage.

[0056] In one embodiment of this application, the reference voltage generation circuit 46 is an R2R architecture digital-to-analog converter circuit, which includes a high-voltage input terminal, a low-voltage input terminal, and a reference voltage output terminal; the first terminal of the second resistor R2 is connected to the high-voltage input terminal of the R2R architecture digital-to-analog converter circuit to input a first compensation voltage VREF_H to the R2R architecture digital-to-analog converter circuit; the first terminal of the fifth resistor R5 is connected to the low-voltage input terminal of the R2R architecture digital-to-analog converter circuit to input a second compensation voltage VREF_L to the R2R architecture digital-to-analog converter circuit; the reference voltage output terminal is used to output the target reference voltage Vref.

[0057] Figure 8 For a partial structural schematic diagram of the reference voltage generation circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 8 As shown, the reference voltage generation circuit 46 provided in this embodiment is an R2R architecture digital-to-analog converter circuit. This R2R architecture includes multiple digital-to-analog conversion units, where each digital-to-analog conversion unit comprises multiple controllable switches and resistors connected in series, such as... Figure 8 As shown, the reference voltage generation circuit 46 includes the following resistors: 80th resistor R80, 81st resistor R81, 82nd resistor R82, 83rd resistor R83, 84th resistor R84, 85th resistor R85, 86th resistor R86, 87th resistor R87, 88th resistor R88, 89th resistor R89, 90th resistor R90, 91st resistor R91, 92nd resistor R92, 93rd resistor R93, 94th resistor R94, 95th resistor R95, 96th resistor R96, 90th resistor R97, 98th resistor R98, a first controllable switch D0, a second controllable switch D1, and a third controllable switch D2. Fourth controllable switch Fifth controllable switch D k-1 The sixth controllable switch D K The seventh controllable switch k-1 Eighth controllable switch Ninth controllable switch D N-2The tenth controllable switch D N-1 Eleventh controllable switch N-2 12th controllable switch N-1 .

[0058] In this embodiment, the structure of the first digital-to-analog converter unit 461 is illustrated by way of example. The first digital-to-analog converter unit 461 includes an eighty-first resistor R81, an eighty-second resistor R82, an eighty-third resistor R83, an eighty-fourth resistor R84, a first controllable switch D0, a second controllable switch D1, and a third controllable switch. Fourth controllable switch The high-voltage input terminal of the R2R architecture digital-to-analog converter circuit is used to receive the first compensation voltage VREF_H, and the low-voltage input terminal of the R2R architecture digital-to-analog converter circuit is used to receive the second compensation voltage VREF_L. The high-voltage input terminal of the digital-to-analog converter circuit is connected to the first terminal of the first controllable switch D0 and the first terminal of the second controllable switch D1, respectively. The second terminal of the first controllable switch D0 is connected to the third controllable switch D1. The first end is connected to the third controllable switch. The second terminal is connected to the low-voltage input terminal of the digital-to-analog converter circuit, and the second terminal of the second controllable switch D1 is connected to the fourth controllable switch. The first end is connected to the fourth controllable switch. The second terminal of the first controllable switch D0 is connected to the low-voltage input terminal of the digital-to-analog converter circuit; the second terminal of the first controllable switch D0 is also connected to the first terminal of the eighty-first resistor R81, the second terminal of the eighty-first resistor R81 is connected to the first terminal of the eighty-second resistor R82, the second terminal of the eighty-second resistor R82 is connected to the first terminals of the ninety-third resistor R93 and the ninety-fourth resistor R94 respectively, the second terminal of the ninety-third resistor R93 is connected to the first terminal of the eightieth resistor R80, and the second terminal of the eightieth resistor R80 is connected to the low-voltage input terminal of the digital-to-analog converter circuit; the second terminal of the ninety-fourth resistor R94 is connected to the first terminal of the eighty-fourth resistor R84, the second terminal of the eighty-fourth resistor R84 is connected to the first terminal of the eighty-third resistor R83, and the second terminal of the eighty-third resistor R83 is connected to the second terminal of the second controllable switch D1. Among these, the first controllable switch D0, the second controllable switch D1, and the third controllable switch... Fourth controllable switch The control terminals are all used to receive corresponding switch control signals, which are used to control the first controllable switch D0, the second controllable switch D1, and the third controllable switch. Fourth controllable switch The on or off state of the first digital-to-analog converter unit 461 is controlled to operate.

[0059] In this embodiment, the Kth digital-to-analog conversion unit includes the 95th resistor R95, the 96th resistor R96, the 85th resistor R85, the 86th resistor R86, the 87th resistor R87, the 88th resistor R88, and the fifth controllable switch D. k-1 The sixth controllable switch D K The seventh controllable switch k-1 Eighth controllable switch The high-voltage input terminal of the R2R architecture digital-to-analog converter circuit is used to receive the first compensation voltage VREF_H, and the low-voltage input terminal is used to receive the second compensation voltage VREF_L; the high-voltage input terminal of the digital-to-analog converter circuit is connected to the fifth controllable switch D. k-1 The first terminal and the sixth controllable switch D K The first end is connected to the fifth controllable switch D. k-1 The second terminal and the seventh controllable switch k-1 The first end is connected to the seventh controllable switch. k-1 The second terminal is connected to the low-voltage input terminal of the digital-to-analog converter circuit, and the sixth controllable switch D... K The second terminal and the eighth controllable switch The first end is connected to the eighth controllable switch. The second terminal is connected to the low-voltage input terminal of the digital-to-analog converter circuit; the fifth controllable switch D k-1 The second terminal is also connected to the first terminal of the 85th resistor R85. The second terminal of the 85th resistor R85 is connected to the first terminal of the 86th resistor R86. The second terminal of the 86th resistor R86 is connected to the first terminals of both the 95th resistor R95 and the 96th resistor R96. The second terminal of the 95th resistor R95 is connected to the series resistor on the previous digital-to-analog converter unit. The second terminal of the 96th resistor R96 is connected to the first terminal of the 88th resistor R88. The second terminal of the 88th resistor R88 is connected to the first terminal of the 87th resistor R87. The second terminal of the 87th resistor R87 is connected to the sixth controllable switch D. K The second end is connected. Among them, the fifth controllable switch D... k-1 The sixth controllable switch D K The seventh controllable switch k-1 Eighth controllable switch The control terminals are all used to receive corresponding switch control signals, which are used to control the fifth controllable switch D. k-1 The sixth controllable switch D K The seventh controllable switch k-1 Eighth controllable switch The on or off state of the Kth digital-to-analog converter unit controls its operation.

[0060] In this embodiment, the Nth digital-to-analog converter unit is used as an example to illustrate its structure. This Nth digital-to-analog converter unit includes an 89th resistor R89, a 90th resistor R90, a 91st resistor R91, a 92nd resistor R92, a 97th resistor R97, a 98th resistor R98, and a 9th controllable switch D. N-2 The tenth controllable switch D N-1 Eleventh controllable switch N-2 12th controllable switch N-1 The high-voltage input terminal of the R2R architecture digital-to-analog converter circuit is used to receive the first compensation voltage VREF_H, and the low-voltage input terminal is used to receive the second compensation voltage VREF_L. The high-voltage input terminal of the digital-to-analog converter circuit is connected to the ninth controllable switch D. N-2 The first terminal and the tenth controllable switch D N-1 The first end is connected to the ninth controllable switch D. N-2 The second terminal and the eleventh controllable switch N-2 The first end is connected to the eleventh controllable switch. N-2 The second terminal is connected to the low-voltage input terminal of the digital-to-analog converter circuit, and the tenth controllable switch D... N-1 The second terminal and the twelfth controllable switch N-1 The first end is connected to the twelfth controllable switch. N-1 The second terminal is connected to the low-voltage input terminal of the digital-to-analog converter circuit; the ninth controllable switch D N-2 The second terminal is also connected to the first terminal of the 89th resistor R89. The second terminal of the 89th resistor R89 ​​is connected to the first terminal of the 90th resistor R90. The second terminal of the 90th resistor R90 is connected to the first terminals of the 97th resistor R97 and the 98th resistor R98, respectively. The second terminal of the 98th resistor R98 is connected to the first terminal of the 92nd resistor R92. The second terminal of the 92nd resistor R92 is connected to the first terminal of the 91st resistor R91. The second terminal of the 91st resistor R91 is connected to the 10th controllable switch D. N-1 The second end is connected. Among them, the ninth controllable switch D... N-2 The tenth controllable switch D N-1 Eleventh controllable switch N-2 12th controllable switch N-1The control terminals are all used to receive corresponding switch control signals, which are used to control the ninth controllable switch D. N-2 The tenth controllable switch D N-1 Eleventh controllable switch N-2 12th controllable switch N-1 The on or off state of the Nth digital-to-analog converter unit controls its operation.

[0061] It is understood that the working principle and workflow of the digital-to-analog converter circuit of the R2R architecture provided in this application embodiment are the same as those in the prior art, and will not be repeated here.

[0062] The above analysis shows that when the voltage value VH of the first compensation voltage VREF_H and the voltage value of the second compensation voltage VREF_L are... If the same voltage ΔV is increased, the target reference voltage Vref output by the reference voltage generation circuit 46 in this embodiment will also increase accordingly by ΔV = K * Vsns11 * R51 / Rsns11, where K represents the ratio of the second reference current to the first reference current, Vsns11 represents the voltage value of the first sampling voltage Vsns1, Rsns11 represents the resistance value of the first sampling resistor Rsns1, and R51 represents the resistance value of the fifth resistor. Then, after adjusting the target reference voltage Vref through the adjustment loop provided in this embodiment, the bus input voltage BVBUSP will also increase accordingly by ΔV * K1, where K1 is the voltage division ratio of the resistor series of the first voltage sampling circuit on the bus. This achieves the adjustment or compensation of the charging voltage BVBUSP_B at the charging output terminal, thereby increasing the charging voltage BVBUSP_B at the charging output terminal.

[0063] Figure 9 For a schematic diagram of the voltage regulation circuit structure provided in the embodiments of this application, please refer to [link / reference]. Figure 9 As shown, the voltage regulation circuit 47 provided in this embodiment includes a first voltage sampling circuit 470, a fourth operational amplifier 471, and a first optocoupler control loop 473; wherein, the sampling terminal of the first voltage sampling circuit 470 is connected to the charging input terminal, the output terminal of the first voltage sampling circuit 470 is connected to the positive input terminal of the fourth operational amplifier 471, the inverting input terminal of the fourth operational amplifier 471 is connected to the reference voltage output terminal of the reference voltage generation circuit 46, the output terminal of the fourth operational amplifier 471 is connected to the control input terminal of the first optocoupler control loop 473, and the control output terminal of the first optocoupler control loop 473 is connected to the charging input terminal.

[0064] In this embodiment, the first voltage sampling circuit 470 is used to sample the second sampling voltage Vfb corresponding to the bus input voltage on the charging input terminal, and input the second sampling voltage Vfb to the positive input terminal of the fourth operational amplifier 471; the inverting input terminal of the fourth operational amplifier 471 is used to receive the target reference voltage Vref, and the fourth operational amplifier 471 is used to generate a voltage adjustment signal Comp1 based on the second sampling voltage Vfb and the target reference voltage Vref; the first optocoupler control loop 473 is used to pull up or pull down the bus input voltage BVBUSP on the charging input terminal according to the voltage adjustment signal Comp1, so as to realize the voltage adjustment of the bus input voltage BVBUSP on the charging input terminal, thereby further realizing the adjustment of the charging voltage BVBUSP_B on the charging output terminal.

[0065] In one embodiment of this application, the first voltage sampling circuit 470 includes a seventh resistor R7 and a seventy-first resistor R71. The first end of the seventh resistor R7 is connected to the charging input terminal, and the second end of the seventh resistor R7 is connected to the first end of the seventy-first resistor R71. The second end of the seventy-first resistor R71 is grounded. Thus, the seventh resistor R7 and the seventy-first resistor R71 are connected in series to form a voltage divider circuit. Sampling the voltage at the upper end of the seventy-first resistor R71 can reflect the bus input voltage BVBUSP at the charging input terminal. In this embodiment, the resistance ratio of the seventh resistor R7 and the seventy-first resistor R71 is 9:1. The bus input voltage BVBUSP at the charging input terminal can be determined by the second sampling voltage Vfb and this voltage divider ratio.

[0066] In one embodiment of this application, please continue to refer to Figure 9 As shown, the voltage regulation circuit 47 also includes an output resistor ROUT, a sixth resistor R6, and a first capacitor C1. The first terminal of the output resistor ROUT is connected to the output terminal of the fourth operational amplifier 471, and the second terminal of the output resistor ROUT is grounded (GND). The output resistor ROUT serves to stabilize the voltage regulation signal Comp1 output by the fourth operational amplifier 471, thereby improving the stability and accuracy of the circuit regulation. The first terminal of the sixth resistor R6 is connected to the output terminal of the fourth operational amplifier 471, and the second terminal of the sixth resistor R6 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is grounded (GND). The sixth resistor R6 and the first capacitor C1 form an RC filter circuit to filter out noise or ripple signals in the voltage regulation signal Comp1 output by the fourth operational amplifier 471, further improving the stability and accuracy of the circuit regulation.

[0067] Compared with related technologies, the charging control circuit provided in this application avoids the use of high-voltage transistors, saving circuit size and simplifying circuit layout. Its basic idea is the same: a first sampling resistor Rsns1 corresponding to the load current Iload is detected. After passing through several K-scale current mirrors, two identical compensation currents are formed. However, this compensation current is no longer sent to the resistor divider string of BVBUSP, but to the reference voltage generation circuit 46. The raised voltage is no longer directly the bus input voltage BVBUSP at the charging input terminal, but rather the target reference voltage Vref output by the reference voltage generation circuit 46. This raises the second sampling voltage Vfb through loop control, indirectly compensating for the bus input voltage BVBUSP. In this application's embodiment, the charging control circuit no longer relies on the matching requirements of the NMOS current mirror with system errors and the long resistor string of BVBUSP with the first sampling resistor Rsns1. In this embodiment, in addition to ensuring the matching between the current mirrors as always, it is only necessary to pay attention to the matching between the first sampling resistor Rsns1, the fifth resistor R5, and the second resistor R2. Usually, these resistors are not very large and are easy to place together for matching in the circuit layout. More importantly, the connection point of the two compensation current branches is no longer a high-voltage node, avoiding the use of high-voltage transistors, saving hardware costs, and also saving the overall size of the circuit.

[0068] This application also provides a chip that includes the charging control circuit provided in any of the above embodiments. The working principle and technical effects of the chip can be referred to and correspond to the charging control circuits provided in the above embodiments, and will not be repeated here.

[0069] This application also provides an electronic device, which can be a power adapter or an electronic product, such as a mobile communication device (e.g., a mobile phone), a smart wearable device, a laptop computer, etc. The electronic device includes a charging control circuit as provided in any of the above embodiments. The working principle and technical effect of the electronic device can be referred to and corresponded to the charging control circuits provided in the above embodiments, and will not be described again here.

[0070] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charge control circuit for controlling a charge voltage outputted from a charge output terminal, characterized by, The charging control circuit comprises a first current sampling circuit, a first operational amplifier, a current mirror circuit, a first compensation voltage generating circuit, a second compensation voltage generating circuit, a reference voltage generating circuit and a voltage regulating circuit; The first current sampling circuit is configured to sample a load current of the charging output terminal at a current time, and convert the load current into a corresponding first sampling voltage to output to a positive input terminal of the first operational amplifier; the voltage value of the first sampling voltage is proportional to the current value of the load current; The current mirror circuit comprises a reference current branch, a first controlled current branch and a second controlled voltage branch; a first sampling resistor is connected in series to the reference current branch, and a high voltage end of the first sampling resistor is connected to a negative input terminal of the first operational amplifier; the first operational amplifier is configured to control the reference current branch to generate a first reference current; the first controlled current branch and the second controlled voltage branch are configured to generate a first compensation current and a second compensation current respectively according to the first reference current; The first compensation voltage generating circuit is configured to generate a first compensation voltage according to the first compensation current, and the second compensation voltage generating circuit is configured to generate a second compensation voltage according to the second compensation current; The reference voltage generating circuit is configured to generate a target reference voltage according to the first compensation voltage and the second compensation voltage; The voltage regulating circuit is configured to regulate a charging voltage output by the charging output terminal according to the target reference voltage.

2. The charge control circuit according to claim 1, characterized by The current mirror circuit further comprises a third controlled current branch configured to generate a second reference current according to the first reference current; a preset amplification coefficient is a ratio of the second reference current to the first reference current; The first controlled current branch and the second controlled voltage branch are configured to generate a first compensation current and a second compensation current respectively according to the second reference current.

3. The charge control circuit according to claim 2, characterized by The reference current branch comprises a first transistor and a first sampling resistor; a control electrode of the first transistor is connected to an output terminal of the first operational amplifier; a first electrode of the first transistor is configured to receive a first power supply voltage; a second electrode of the first transistor is connected to a first end of the first sampling resistor; and a second end of the first sampling resistor is grounded; The third controlled current branch comprises a second transistor and a third transistor; a first electrode of the second transistor is connected to the first electrode of the first transistor; a control electrode of the second transistor is connected to the control electrode of the first transistor; a second electrode of the second transistor is connected to a second electrode of the third transistor; a first electrode of the third transistor is grounded; and a second electrode and a control electrode of the third transistor are short-circuited; The first controlled current branch comprises a fourth transistor; a control electrode of the fourth transistor is connected to the control electrode of the third transistor; a first electrode of the fourth transistor is grounded; and a second electrode of the fourth transistor is configured to input the first compensation current; The second controlled current branch comprises a fifth transistor, a control electrode of the fifth transistor is connected with a control electrode of the fourth transistor, a first electrode of the fifth transistor is grounded, and a second electrode of the fifth transistor is used for inputting the second compensation current.

4. The charge control circuit according to claim 3, characterized by A current value ratio of the first reference current and the second reference current is 1:K; wherein K is a preset amplification coefficient, and K≥1; A current value ratio of the second reference current, the first compensation current and the second compensation current is 1:1:

1.

5. The charge control circuit according to claim 3, characterized by The first compensation voltage generation circuit comprises a second operational amplifier, a second resistor, a third resistor and a sixth transistor; a positive input end of the second operational amplifier is used for receiving a first voltage, an output end of the second operational amplifier is connected with a control electrode of the sixth transistor, a second electrode of the sixth transistor is used for receiving a second power supply voltage, a first electrode of the sixth transistor is connected with a first end of the second resistor, a second end of the second resistor is connected with a first end of the third resistor, and a second end of the third resistor is grounded; the second end of the second resistor is also connected with a negative input end of the second operational amplifier and a second electrode of the fourth transistor; and the first end of the second resistor is used for outputting the first compensation voltage. The second compensation voltage generation circuit comprises a third operational amplifier, a seventh transistor, a fourth resistor and a fifth resistor; a positive input end of the third operational amplifier is used for receiving a second voltage, an output end of the third operational amplifier is connected with a control electrode of the seventh transistor, a second electrode of the seventh transistor is used for receiving a third power supply voltage, a first electrode of the seventh transistor is connected with a first end of the fourth resistor and a first end of the fifth resistor, a second end of the fourth resistor is grounded, and a second end of the fifth resistor is connected with a second electrode of the fifth transistor; and the first end of the fifth resistor is used for outputting the second compensation voltage.

6. The charge control circuit according to claim 5, characterized by The reference voltage generation circuit comprises a plurality of digital-to-analog conversion units, the plurality of digital-to-analog conversion units are connected in series in sequence, wherein an output end of a previous digital-to-analog conversion unit is connected with an input end of a next digital-to-analog conversion unit; wherein an input end of a first digital-to-analog conversion unit is used for receiving the second compensation voltage, and the plurality of digital-to-analog conversion units are used for sequentially performing digital-to-analog conversion on the second compensation voltage, so that a last digital-to-analog conversion unit outputs the target reference voltage.

7. The charge control circuit according to claim 5, wherein The reference voltage generation circuit is a digital-to-analog conversion circuit of an R2R architecture, the digital-to-analog conversion circuit of the R2R architecture comprises a high-voltage input end, a low-voltage input end and a reference voltage output end; The first end of the second resistor is connected with the high-voltage input end of the digital-to-analog conversion circuit of the R2R architecture, so as to input the first compensation voltage to the digital-to-analog conversion circuit of the R2R architecture; the first end of the fifth resistor is connected with the low-voltage input end of the digital-to-analog conversion circuit of the R2R architecture, so as to input the second compensation voltage to the digital-to-analog conversion circuit of the R2R architecture; and the reference voltage output end is used for outputting the target reference voltage.

8. The charge control circuit according to claim 7, characterized by The voltage regulation circuit comprises a first voltage sampling circuit, a fourth operational amplifier and a first optocoupler control loop; The sampling end of the first voltage sampling circuit is connected with the charging input end, the output end of the first voltage sampling circuit is connected with the positive input end of the fourth operational amplifier, the reverse input end of the fourth operational amplifier is connected with the reference voltage output end of the reference voltage generation circuit, the output end of the fourth operational amplifier is connected with the control input end of the first optocoupler control loop, and the control output end of the first optocoupler control loop is connected with the charging input end; The first voltage sampling circuit is used for sampling a second sampling voltage corresponding to the bus input voltage on the charging input end and inputting the second sampling voltage to the positive input end of the fourth operational amplifier; the reverse input end of the fourth operational amplifier is used for receiving the target reference voltage; the fourth operational amplifier is used for generating a voltage regulation signal according to the second sampling voltage and the target reference voltage; and the first optocoupler control loop is used for pulling up or pulling down the bus input voltage on the charging input end according to the voltage regulation signal.

9. The charge control circuit according to claim 8, characterized by The voltage regulation circuit further comprises an output resistor, a sixth resistor and a first capacitor; The first end of the output resistor is connected with the output end of the fourth operational amplifier, and the second end of the output resistor is grounded; the first end of the sixth resistor is connected with the output end of the fourth operational amplifier, the second end of the sixth resistor is connected with the first end of the first capacitor, and the second end of the first capacitor is grounded.

10. A chip, characterized by The chip comprises the charging control circuit according to any one of claims 1-9.

11. An electronic device, comprising: The electronic device comprises the charging control circuit according to any one of claims 1-9.

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