Reconfigurable charge pump circuit applied to radio frequency energy acquisition system

Abstract

The invention discloses a reconfigurable charge pump circuit applied to a radio frequency energy acquisition system. The reconfigurable charge pump circuit comprises a charge pump clock generation module, a multi-stage charge pump, a field effect transistor switch module, an intermediate node voltage detection module and an output voltage stabilization module, dC voltages of the radio frequency rectifier under different input power conditions are received, the DC voltages are boosted into output signals of the multi-stage charge pump through the multi-stage charge pump, and power is supplied to subsequent loads through the output voltage stabilization module; the intermediate node voltage detection module detects the node voltage between the first two stages of charge pumps and the second two stages of charge pumps, and generates different enable signals to control the field effect transistor switch module according to whether the node voltage exceeds a threshold value or not, so that switching of the charge pumps in different working stages is realized, and reconfiguration is realized. According to the invention, stable output voltage can be obtained under the conditions of low input voltage and high input voltage, good output performance is shown, and the circuit is very suitable for the condition of input power fluctuation of a radio frequency energy acquisition system.

Description

Technical Field

[0001] This invention relates to the field of power module management technology, and in particular to a reconfigurable charge pump circuit for use in radio frequency energy harvesting systems. Background Technology

[0002] Radio frequency (RF) energy harvesting systems are widely used in the Internet of Things (IoT), especially in power-constrained environments. Passive IoT technology, which harvests energy from the surrounding environment and transmits it wirelessly via electromagnetic waves, offers advantages such as small size and long range, providing tremendous opportunities for IoT development. However, it also places higher demands on power management. Due to variations in the rectifier antenna signal strength, the energy harvested by the wireless energy harvester is unstable, resulting in a low and unstable input voltage supplied to the power management system. The most common boost and regulation methods use DC-DC converters for boosting and regulation, such as using reconfigurable switched capacitor structures to provide different conversion ratios. However, these converters are complex, difficult to control, and cannot be effectively adjusted within a dynamic input voltage range. Furthermore, a significant portion of these circuits perform poorly or even fail to operate in low-power applications.

[0003] A charge pump is a type of inductorless DC-DC converter that uses a clock circuit implemented with switched capacitors. Therefore, charge pumps are small in size, have a relatively simple structure, and are suitable for integration into chips. Summary of the Invention

[0004] In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the purpose of this invention is to provide a reconfigurable charge pump circuit for use in radio frequency energy harvesting systems.

[0005] This invention utilizes an intermediate node voltage detection module to switch the operating stages of the charge pump under different input power conditions, and finally uses an output voltage regulator module to obtain a ripple-free output voltage.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A reconfigurable charge pump circuit for use in a radio frequency energy harvesting system includes a charge pump clock generation module, a multi-stage charge pump, a field-effect transistor switching module, an intermediate node voltage detection module, and an output voltage regulator module.

[0008] DC voltage V of the receiving RF rectifier under different input power conditions RECT DC voltage V is converted through a multi-stage charge pump. RECT The voltage is boosted to the output signal V of the multi-stage charge pump. CP The output voltage regulator module supplies power to the subsequent loads.

[0009] The multi-stage charge pump includes four single-stage charge pumps, namely the first-stage charge pump and the second-stage charge pump that constitute the first two stages of the charge pump, and the third-stage charge pump and the fourth-stage charge pump that constitute the last two stages of the charge pump.

[0010] The intermediate node voltage detection module detects the node V between the first two stages of charge pumps and the last two stages of charge pumps. M Voltage, according to node V M Whether the voltage exceeds the threshold generates different enable signals to control the MOSFET switching module, enabling the charge pump to switch at different operating levels and achieving reconfigurability.

[0011] Furthermore, when the input voltage is low, the intermediate node voltage V M If the threshold is not exceeded, the intermediate node voltage detection module outputs a field-effect transistor switching module control signal, at which point the overall charge pump operates in 4 stages; when the input voltage is higher, the intermediate node V... M When the voltage exceeds the threshold, the control signal output by the intermediate node voltage detection module switches between high and low levels, and the overall charge pump operates in two stages.

[0012] Furthermore, the charge pump clock generation module includes a ring oscillator and a linear non-overlapping clock circuit;

[0013] The ring oscillator comprises an odd number of stacked inverters, each stacked inverter comprising a field-effect transistor M. 10 MOSFET M 11 MOSFET M 12 MOSFET M 13 MOSFET M 14 and field-effect transistor M 15 Field-effect transistor M 10 and field-effect transistor M 11 The source of the transistor is respectively connected to the field-effect transistor M. 12 and field-effect transistor M 13 MOSFET M 14 and field-effect transistor M 15 The drains are connected.

[0014] Furthermore, the single-stage charge pump includes field-effect transistors M1, M2, M3, and M4, capacitors C1, C2, and C3, and a dynamic body bias structure. Field-effect transistors M1 and M2 are cross-coupled. The gate of field-effect transistor M1 is connected to capacitor C2, and the gate of field-effect transistor M2 is connected to capacitor C1. Capacitors C1 and C2 are respectively connected to the CK and CKN signal terminals of a linear non-overlapping clock. The body terminals of field-effect transistors M1 and M2 are connected to the dynamic body bias structure. The dynamic body bias structure includes field-effect transistors M1, M2, M3, and M4. B1 and field-effect transistor M B2The field-effect transistor M B1 Body terminals and field-effect transistors M B2 The body terminal connection, field-effect transistor M B1 The source and field-effect transistor M B2 The source connection of the field-effect transistor M B1 Gate and field-effect transistor M B2 The drain connection of the field-effect transistor M B1 The drain and field-effect transistor M B2 The gate connection.

[0015] The field-effect transistors M3 and M4 are connected by cross-coupling, and the connection point between M3 and M4 serves as the output terminal V of a single-stage charge pump. OUT One end of capacitor C3 is connected to the ground, and the other end of capacitor C3 is grounded.

[0016] Furthermore, both the field-effect transistor M1 and the field-effect transistor M2 are disposed in a deep n-well structure.

[0017] Furthermore, the intermediate node voltage detection module includes field-effect transistors M5, M6, M7, M8, and M9, a voltage divider resistor unit, inverter D1, and inverter D2. The gates of field-effect transistors M5 and M6 are respectively connected to the enable signal SW and enable signal SW_N of the intermediate node voltage detection module. The enable signal SW and enable signal SW_N are respectively connected to the output terminals of inverter D1 and inverter D2.

[0018] The source of MOSFET M7 is connected to the drain of MOSFET M5, and the drain of MOSFET M7 is connected to the drain of MOSFET M9. It is also connected to the input of inverter D1 and the drain of MOSFET M8. The connection node voltage is V. d The voltage divider resistor unit includes two connection terminals, namely connection terminal V. r1 With connection end V r2 The connection end V r2 The connection terminal V is connected to the drain of the field-effect transistor M7. r1 The gate of MOSFET M8 is connected to the gate of MOSFET M9, and the source of MOSFET M9 is connected to the intermediate node voltage V. M The sources of field-effect transistors M5 and M6 are grounded.

[0019] Furthermore, the voltage divider resistor unit includes a voltage divider field-effect transistor MR1 and a voltage divider field-effect transistor MR2. 28 Each voltage divider field-effect transistor has its gate and drain connected, and its source and drain connected to each other. The voltage divider field-effect transistor MR... 18 and voltage divider field-effect transistor MR 19 The connection point is the connection end V. r2The field-effect transistor MR 21 and field-effect transistor MR 22 Connection terminal V r1 The field-effect transistor MR 28 The drain electrode is grounded.

[0020] Furthermore, the field-effect transistor (FET) switching module includes FET switch S1, FET switch S2, and FET switch S3.

[0021] The field-effect transistor switches S1 and S3 are connected to the dynamic body bias structure.

[0022] Furthermore, the field-effect transistors of the intermediate node voltage detection module all operate in the subthreshold region.

[0023] Furthermore, when field-effect transistors M1 and M2 need to be completely turned off with minimal cutoff current, the body terminal voltage V of the dynamic body bias structure is... B When set to ground, it is in reverse body bias mode; when MOSFETs M1 and M2 require the best conduction performance, the body terminal voltage V of the dynamic body bias structure is... B Connect to the output terminal Vout of the unipolar charge pump. At this time, it is in forward body bias mode. In this mode, the MOSFET switch has better charge transfer capability and avoids ineffective body current.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0025] (1) The reconfigurable charge pump of the present invention uses an intermediate node voltage detection module to switch the working stage. It can obtain a stable output voltage under both low and high input voltage conditions, showing good output performance. It is very suitable for the conditions of fluctuating input power in radio frequency energy harvesting systems.

[0026] (2) The single-stage charge pump module of the present invention also uses dynamic body bias technology, which effectively improves the driving capability and speeds up the stabilization time. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the present invention;

[0028] Figure 2 This is a waveform diagram showing the operation of the reconfigurable charge pump circuit of the present invention.

[0029] Figures 3(a) and 3(b) are schematic diagrams of the charge pump clock generation module of the present invention;

[0030] Figure 4 This is a schematic diagram of the circuit structure of the intermediate node voltage detection module of the present invention;

[0031] Figure 5 This is the output waveform diagram of the intermediate node voltage detection module of the present invention;

[0032] Figure 6 This is a schematic diagram of the circuit structure of a single-stage charge pump module;

[0033] Figure 7 This is a waveform diagram of the output of the single-stage charge pump of the present invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.

[0035] Example

[0036] like Figure 1 and Figure 2 As shown, a reconfigurable charge pump circuit for use in a radio frequency energy harvesting system includes a charge pump clock generation module, a multi-stage charge pump, a field-effect transistor switching module, an intermediate node voltage detection module, and an output voltage regulator module.

[0037] DC voltage V of the receiving RF rectifier under different input power conditions RECT The DC voltage V is converted by four single-stage charge pumps. RECT Boost to output signal V CP Then, the output voltage is regulated to V by the voltage regulator module. OUT This provides power to the subsequent loads.

[0038] The intermediate node voltage detection module detects the node V between the first two stages of charge pumps and the last two stages of charge pumps. M The system determines whether the voltage exceeds a threshold and then generates different enable signals to control the MOSFET switching module, enabling the charge pump to switch between different operating stages and achieving reconfigurability.

[0039] Furthermore, the charge pump clock generation module includes a ring oscillator and a linear non-overlapping clock circuit. The ring oscillator includes an odd number of stacked inverters, each of which includes a field-effect transistor M. 10 MOSFET M 11 MOSFET M 12 MOSFET M 13 MOSFET M 14 and field-effect transistor M 15 Field-effect transistor M 10 and field-effect transistor M 11 The source poles are respectively with M 12 and M 13 M 14 and M 15The drains are connected in series, providing a higher output voltage swing even with reduced supply voltage. All transistors operate in the subthreshold region, reducing leakage current and thus power consumption.

[0040] Furthermore, in this embodiment, the multi-stage charge pump includes four stages: a first-stage charge pump, a second-stage charge pump, a third-stage charge pump, and a fourth-stage charge pump. The first-stage and second-stage charge pumps constitute the first two stages of the charge pump, and the third-stage and fourth-stage charge pumps constitute the last two stages of the charge pump.

[0041] To save chip area and improve efficiency, the optimal number of charge pump stages N can be expressed as:

[0042]

[0043] Among them, V CP It is the output voltage of the charge pump, V IN It is the input voltage of the charge pump.

[0044] The capacitance C of each stage of the charge pump stage It can be represented as:

[0045]

[0046] Where f is the clock frequency at which the charge pump operates, and I LOAD This is the load current of the charge pump.

[0047] Considering factors such as efficiency and power consumption, the frequency f was ultimately chosen to be 200kHz, and the number of stages N was selected as 2 or 4 stages according to the formula. Each stage's flying capacitor is 25pF, and the load capacitor is 20pF. By utilizing different types of available capacitors to minimize the area, the proposed topology becomes a very attractive technique for reducing power loss and improving power efficiency, without sacrificing speed performance during startup.

[0048] like Figure 2 As shown: When the input voltage V RECT When the voltage is low, the intermediate node voltage VM does not exceed the threshold, and the intermediate node voltage detection module outputs the MOSFET switching module control signal. At this time, the overall charge pump operates in 4 stages. As the input voltage V... RECT Switch to a higher level when the intermediate node voltage V M If the threshold is exceeded, the control signal output by the intermediate node detection voltage module switches between high and low levels. At this time, the overall charge pump operates in two stages. After the output voltage regulator circuit LDO passes through the multi-stage charge pump, a stable, ripple-free output voltage can be obtained to power the subsequent load.

[0049] Specifically,

[0050] The single-stage charge pump includes field-effect transistors M1, M2, M3, and M4, capacitors C1, C2, and C3, and a dynamic body bias structure. Field-effect transistors M1 and M2 are cross-coupled. The gate of field-effect transistor M1 is connected to capacitor C2, and the gate of field-effect transistor M2 is connected to capacitor C1. Capacitors C1 and C2 are connected to the CK and CKN signal terminals of a linear non-overlapping clock, respectively. The body terminals of field-effect transistors M1 and M2 are connected to the dynamic body bias structure. The dynamic body bias structure includes field-effect transistors M1, M2, M3, and M4. B1 and field-effect transistor M B2 The field-effect transistor M B1 Body terminals and field-effect transistors M B2 The body terminal connection, field-effect transistor M B1 The source and field-effect transistor M B2 The source connection of the field-effect transistor M B1 Gate and field-effect transistor M B2 The drain connection of the field-effect transistor M B1 The drain and field-effect transistor M B2 The gate connection.

[0051] The field-effect transistors M3 and M4 are connected by cross-coupling, and the connection point between M3 and M4 serves as the voltage signal V. OUT The output terminal is connected to capacitor C3, and the other end of capacitor C3 is grounded.

[0052] The drains of field-effect transistors M1 and M2 are connected together to form a voltage signal V. IN The input terminal. For enhancement-mode N-type field-effect transistor devices, the effect of the body effect on the threshold voltage is calculated using the following formula:

[0053]

[0054] Where γ is the body effect coefficient, V SB V is the source-to-body voltage of the field-effect transistor. TH0 For V SB =0V threshold voltage of the MOSFET, γ is the scaling factor, Φ F This represents the surface electromotive force.

[0055] Furthermore, the field-effect transistor (FET) switching module includes FET switch S1, FET switch S2, and FET switch S3. The gate of FET switch S1 is controlled by a switching signal SW generated by the intermediate node voltage detection module. Its source is connected to the drain of FET switch S2 and is also connected to the third and fourth stage charge pumps. Its drain is connected to the drain of FET switch S3 and is also connected to the first and second stage charge pumps. The gate of FET switch S2 is controlled by a switching signal SW generated by the intermediate node voltage detection module. Its source is grounded, and its drain is connected to the source of FET switch S1 and is also connected to the third and fourth stage charge pumps. The gate of FET switch S3 is controlled by a switching signal SW_N generated by the intermediate node voltage detection module. Its source is connected to the charge pump output signal VCP and is also connected to the third and fourth stage charge pumps. Its drain is connected to the drain of FET switch S1 and is also connected to the first and second stage charge pumps.

[0056] In a multi-stage charge pump, as the input voltage increases, the body-source voltage V of MOSFET switches S1 and S2 increases. BS The voltage will become very large. Therefore, the threshold voltage of the MOSFET switch will increase, leading to reduced conduction performance. To address this issue, a dynamic body bias structure is used, which generates a higher current through the MOSFET switch to eliminate the body effect. The body terminals of MOSFET switches S1 and S2 are connected to the dynamic body bias structure; MOSFET switches S1 and S3 are both placed within a deep n-well structure.

[0057] As shown in Figures 3(a) and 3(b), the charge pump clock generation module includes an odd number of stacked inverters forming a ring oscillator. Each stacked inverter includes a field-effect transistor M. 10 MOSFET M 11 MOSFET M 12 MOSFET M 13 MOSFET M 14 and field-effect transistor M 15 Field-effect transistor M 10 and field-effect transistor M 11 The source of the transistor is respectively connected to the field-effect transistor M. 12 and field-effect transistor M 13 MOSFET M 14 and field-effect transistor M 15 The drains are connected in series. Unlike traditional inverters which consist of only a pair of field-effect transistors, the stacked inverter introduces at least two field-effect transistors in series between the output and the power supply / ground, which can significantly reduce static leakage current and thus significantly reduce static power consumption.

[0058] like Figure 4As shown, the intermediate node voltage detection module includes field-effect transistors M5, M6, M7, M8, and M9, a voltage divider resistor unit, inverter D1, and inverter D2. The gates of field-effect transistors M5 and M6 are respectively connected to the enable signal SW and enable signal SW_N of the intermediate node voltage detection module. The enable signal SW and enable signal SW_N are respectively connected to the output terminals of inverter D1 and inverter D2.

[0059] The source of MOSFET M7 is connected to the drain of MOSFET M5, and the drain of MOSFET M7 is connected to the drain of MOSFET M9. It is also connected to the input of inverter D1 and the drain of MOSFET M8. The connection node voltage is V. d The voltage divider resistor unit includes two connection terminals, namely connection terminal V. r1 With connection end V r2 The connection end V r2 The connection terminal V is connected to the drain of the field-effect transistor M7. r1 The gate of MOSFET M8 is connected to the gate of MOSFET M9, and the source of MOSFET M9 is connected to the intermediate node voltage V. M The sources of field-effect transistors M5 and M6 are grounded.

[0060] The voltage divider resistor unit includes voltage divider field-effect transistors MR1 ​​and MR2. 28 Each voltage divider field-effect transistor has its gate and drain connected, and its source and drain connected to each other. The voltage divider field-effect transistor MR... 18 and voltage divider field-effect transistor MR 19 The connection point is the connection end V. r2 The field-effect transistor MR 21 and field-effect transistor MR 22 Connection terminal V r1 The field-effect transistor MR 28 The drain electrode is grounded.

[0061] MR1-MR 28 Each has its own gate and drain connected, and its source and drain connected to each other, which can be used as a resistor to achieve a voltage divider effect.

[0062] The circuit structure and output waveform of the intermediate node voltage detection module in this invention are as follows: Figure 4 and Figure 5 As shown. This module consists of the intermediate node voltage V. M Power supply. With the intermediate node voltage V M Starting from 0V, the drain voltage V of the field-effect transistor M5 rises. d As this increases, the enable signal SW_N is low. When the intermediate node voltage V MAs the voltage continues to rise, the gate voltage V of the field-effect transistor M7... r2 This also increases the drain voltage V of the field-effect transistor M5. d Pulling down the drain voltage V of MOSFET M5 d Once the voltage drops sufficiently, the enable signals SW and SW_N switch between high and low levels. The size ratio of MOSFETs M7 and M5 determines the intermediate node voltage V. M The critical value. The field-effect transistors in the circuit all operate in the subthreshold region, with low leakage current, thus reducing power consumption. The subthreshold current I of the field-effect transistor is... sub for

[0063]

[0064] Where I0 is a proportionality constant, V GS It is the gate-source voltage of the field-effect transistor, ξ is a non-ideal constant, V T =kT / q is the thermal voltage.

[0065] The intermediate node voltage detection module has a relatively low average power consumption, with only slightly higher instantaneous power consumption during operating mode switching.

[0066] The circuit structure of the single-stage charge pump in this invention is as follows: Figure 6 As shown. Assume that after the initial transient, a stable state is reached. During the first half of the cycle, the clock signal CK is at a high level. IN When the clock signal CKN is low (0), MOSFETs M2 and M4 are turned on, while MOSFETs M1 and M3 are turned off. Capacitor C2 is charged to a lower voltage V through the conduction of MOSFET M2. IN (i.e., the voltage at point A is V) IN Meanwhile, the voltage at point B is raised to a higher voltage of 2V under the control of the clock high level. IN C1 controls the output node V through the conduction of the field-effect transistor M4. OUT Discharge. In the second half of the cycle, the clock signal CK is low (0) and the clock signal CKN is high (V). IN At this time, MOSFETs M1 and M3 are turned on, while MOSFETs M2 and M4 are turned off; capacitor C1 is charged to a lower voltage V through the conduction of MOSFET M1. IN (i.e., the voltage at point B is V) IN Meanwhile, the voltage at point A is raised to a higher voltage of 2V under the control of the clock high level. IN C2 controls the output node V through the conduction of the field-effect transistor M3. OUT Discharge. Therefore, it is possible to discharge at V. IN and V OUT A considerable voltage gain is obtained between them.

[0067] When field-effect transistors M1 and M2 need to be completely turned off with minimal cutoff current, the body bias voltage V is applied. B Set to ground, this is the reverse body bias mode; when MOSFETs M1 and M2 require the best conduction performance, the body bias voltage V... B When connected to the output, it is in forward body bias mode, which allows for better power transfer.

[0068] The output waveform of the single-stage charge pump module in this invention is as follows: Figure 7 As shown. Figure 7 The transient response capabilities of a single-stage charge pump with and without a dynamic body bias structure are demonstrated. The transient response results show that the settling time of the single-stage charge pump with the dynamic body bias structure is significantly improved compared to the single-stage charge pump without the dynamic body bias structure, indicating that the dynamic body bias structure can effectively improve the driving capability of the charge pump.

[0069] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the embodiments described above. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A reconfigurable charge pump circuit for use in a radio frequency energy harvesting system, characterized in that, It includes a charge pump clock generation module, a multi-stage charge pump, a field-effect transistor switching module, an intermediate node voltage detection module, and an output voltage regulator module; DC voltage V of the receiving RF rectifier under different input power conditions RECT DC voltage V is converted through a multi-stage charge pump. RECT Boost to output signal V CP The output voltage regulator module supplies power to the subsequent loads. The multistage charge pump includes four single-stage charge pumps; The intermediate node voltage detection module detects the node V between the first two stages of charge pumps and the last two stages of charge pumps. M Voltage, according to node V M Whether the voltage exceeds the threshold generates different enable signals to control the MOSFET switching module, enabling the charge pump to switch at different operating levels and achieving reconfigurability.

2. The reconfigurable charge pump circuit according to claim 1, characterized in that, When the intermediate node voltage V M If the threshold is not exceeded, the intermediate node voltage detection module outputs a field-effect transistor switching module control signal, at which point the overall charge pump operates in 4 stages; when the intermediate node voltage V M If the threshold is exceeded, the control signal output by the intermediate node detection voltage module switches between high and low levels, at which point the overall charge pump operates in two stages.

3. The reconfigurable charge pump circuit according to claim 2, characterized in that, The charge pump clock generation module includes a ring oscillator and a linear non-overlapping clock circuit; The ring oscillator comprises an odd number of stacked inverters, each stacked inverter comprising a field-effect transistor M. 10 MOSFET M 11 MOSFET M 12 MOSFET M 13 MOSFET M 14 and field-effect transistor M 15 Field-effect transistor M 10 and field-effect transistor M 11 The source of the transistor is respectively connected to the field-effect transistor M. 12 and field-effect transistor M 13 MOSFET M 14 and field-effect transistor M 15 The drains are connected.

4. The reconfigurable charge pump circuit according to claim 2, characterized in that, The single-stage charge pump includes field-effect transistors M1, M2, M3, and M4, capacitors C1, C2, and C3, and a dynamic body bias structure. Field-effect transistors M1 and M2 are connected by cross-coupling. The gate of field-effect transistor M1 is connected to one end of capacitor C2, and the gate of field-effect transistor M2 is connected to one end of capacitor C1. The other ends of capacitors C1 and C2 are respectively connected to the CK signal terminal and CKN signal terminal of the linear non-overlapping clock. The body terminals of field-effect transistors M1 and M2 are connected to the dynamic body bias structure. The field-effect transistors M3 and M4 are connected by cross-coupling. The connection end of the field-effect transistors M3 and M4 serves as the output end of a single-stage charge pump. The output end of the single-stage charge pump is connected to one end of capacitor C3, and the other end of capacitor C3 is grounded.

5. The reconfigurable charge pump circuit according to claim 4, characterized in that, Both the field-effect transistors M1 and M2 are housed in a deep n-well structure.

6. The reconfigurable charge pump circuit according to claim 1, characterized in that, The intermediate node voltage detection module includes field-effect transistors M5, M6, M7, M8, and M9, a voltage divider resistor unit, inverter D1, and inverter D2. The gates of field-effect transistors M5 and M6 are respectively connected to the enable signal SW and enable signal SW_N of the intermediate node voltage detection module. The enable signal SW and enable signal SW_N are respectively connected to the output terminals of inverter D1 and inverter D2. The source of MOSFET M7 is connected to the drain of MOSFET M5, and the drain of MOSFET M7 is connected to the drain of MOSFET M9. It is also connected to the input of inverter D1 and the drain of MOSFET M8. The connection node voltage is V. d The voltage divider resistor unit includes two connection terminals, namely connection terminal V. r1 With connection end V r2 The connection end V r2 The connection terminal V is connected to the drain of the field-effect transistor M7. r1 The gate of MOSFET M8 is connected to the gate of MOSFET M9, and the source of MOSFET M9 is connected to the intermediate node voltage V. M The sources of field-effect transistors M5 and M6 are grounded.

7. The reconfigurable charge pump circuit according to claim 6, characterized in that, The voltage divider resistor unit includes voltage divider field-effect transistors MR1 ​​and MR2. 28 Each voltage divider field-effect transistor has its gate and drain connected, and its source and drain connected to each other. The voltage divider field-effect transistor MR... 18 and voltage divider field-effect transistor MR 19 The connection point is the connection end V. r2 The field-effect transistor MR 21 and field-effect transistor MR 22 Connection terminal V r1 The field-effect transistor MR 28 The drain electrode is grounded.

8. The reconfigurable charge pump circuit according to claim 4, characterized in that, The field-effect transistor (FET) switching module includes FET switch S1, FET switch S2, and FET switch S3. The field-effect transistor switches S1 and S3 are connected to the dynamic body bias structure.

9. The reconfigurable charge pump circuit according to claim 6, characterized in that, The field-effect transistors of the intermediate node voltage detection module all operate in the subthreshold region.

10. The reconfigurable charge pump circuit according to claim 4, characterized in that, When the body terminal voltage of the dynamic body bias structure is set to ground, it is in reverse body bias mode. At this time, MOSFETs M1 and M2 are completely turned off with minimal cutoff current. Connecting the body terminal voltage of the dynamic body bias structure to the output of a single-stage charge pump results in a forward body bias mode, where field-effect transistors M1 and M2 exhibit good conduction performance.

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