Solid-state relay circuit with quick turn-off function

Abstract

The invention discloses a solid-state relay circuit with a quick turn-off function in the technical field of integrated circuits, which comprises a photovoltaic generation chip, a light-emitting input module and a first photocell group, and is characterized in that the photovoltaic generation chip comprises a first photocell group; the light-emitting input module comprises a first input control pin INP and a second input control pin INN, and one end of the first input control pin INP is connected with the anode of the light-emitting diode D1. According to the invention, an independent second photocell group which is not limited to two sections is provided for a depletion transistor N1, the transistor N1 can be turned off, meanwhile, a first resistor is used for rapidly discharging a parasitic capacitor which is connected in series with a first photocell and a second photocell and a grid parasitic capacitor of the MOS transistor N1, and a diode D2 and a triode Q1 are arranged, so that the voltage of the transistor N1 is reduced. And the discharge current of the PVG chip can be further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a solid-state relay circuit with a fast-off function. BACKGROUND

[0002] Compared with traditional mechanical relays, solid-state relays have the advantages of high speed, silence, low power consumption, low EMI, long service life, high reliability, etc., and are widely used in electronic engineering, semiconductor, industrial control and other fields that require precise control, energy saving and miniaturization, especially in high-frequency, high-reliability and harsh environment application scenarios.

[0003] The structural diagram of the existing solid-state relay is composed of a light-emitting diode (LED), a photovoltaic generation chip (PVG) and a power tube (MOSFET). INP and INN are input control pins, and OUT1 and OUT2 are controlled output pins. When a current signal is input from the INP to the INN port, the LED emits infrared light, the photovoltaic cell group in the PVG chip receives the infrared light and generates a voltage signal by using the photovoltaic effect, charges the gate of the MOSFET, and then turns on the MOSFET to connect the OUT1 and OUT2 ports. When the current signal input from the input control pin INP to the input control pin INN port is turned off, the LED no longer emits light, the photovoltaic cell group in the PVG chip no longer outputs a voltage signal, and the current discharge circuit in the PVG chip discharges the parasitic capacitance of the MOSFET gate, thereby turning off the MOSFET and disconnecting the connection between the OUT1 and OUT2 ports. The opening speed of the solid-state relay is determined by the current capacity of the photovoltaic cell group in the PVG chip, and the closing speed of the solid-state relay is determined by the current discharge capacity of the current discharge circuit in the PVG chip. The existing solid-state relay has the problem that the current discharge capacity of the PVG chip is limited.

[0004] In addition to the above-mentioned solid-state relay, in the solid-state relay composed of a traditional PVG chip, D1 is an LED, V1-Vn is an n-photovoltaic cell group in series, and the current discharge circuit is realized by a resistor R0. When the LED is turned off, the parasitic capacitance Cn of the photovoltaic cell group is discharged through the resistor R0, and the discharge current is I1. Similarly, the MOSFET gate parasitic capacitance Cm is discharged through the resistor R0, and the discharge current is I2, that is, the current flowing through the resistor R1 is: I=I1+I2, the total charge on the Cn and Cm capacitors can be obtained by integrating the current during the discharge process: Q=(Cn+Cm)*V0= = = ; wherein, V0 is the initial voltage difference between OUT and GND ports, i.e. the output voltage of the photovoltaic cell group V1~Vn, V(t) is the voltage difference between OUT and GND ports at t time.

[0005] The discharge time of the solid state relay is approximately: t≈2*R0*(Cn+Cm); the resistance R0 is too small to consume the current generated by the photovoltaic cell group, which affects the opening time of the solid state relay, so the resistance R0 is designed to be very large, usually more than 10M Ohm, and the sum of the capacitance values Cn and Cm is usually several tens of pF to several nF. Therefore, the turn-off time of the solid state relay composed of the traditional PVG chip is usually several hundred uS to tens of mS, that is, the current discharge capacity of the traditional PVG chip seriously affects the turn-off time of the solid state relay, which limits its high-frequency application scenarios. SUMMARY

[0006] The purpose of the present application is to provide a solid state relay circuit with fast turn-off function, which solves the problem of limited current discharge capacity in the PVG chip, so that the product can be applied to higher frequency scenarios, and has very high market value.

[0007] To achieve the above purpose, the present application provides the following technical scheme: A solid state relay circuit with fast turn-off function, comprising a photovoltaic generation chip, the photovoltaic generation chip comprising a first photovoltaic cell group, the solid state relay circuit further comprising: A light emitting input module, the light emitting input module emits infrared light to the first photovoltaic cell group, the positive and negative electrodes of the first photovoltaic cell group are connected to a power tube (MOSFET), and the first photovoltaic cell group generates a voltage signal capable of charging the gate of the power tube (MOSFET) after receiving the infrared light, thereby turning on the power tube (MOSFET); The first photovoltaic cell group, the anode of the first photovoltaic cell group is connected to the drain of a field effect transistor module and the gate of the power tube (MOSFET), the source of the field effect transistor module is connected to the first end of a first resistor R1, the anode of a second photovoltaic cell group and the source of the power tube (MOSFET), the gate of the field effect transistor module is connected to the cathode of the second photovoltaic cell group and the second end of the first resistor R1, and the voltage signal generated by the second photovoltaic cell group sets the gate-source voltage difference of the field effect transistor module below the threshold value VTH.

[0008] As a further scheme of the present application, the light-emitting input module comprises a first input control pin INP and a second input control pin INN, one end of the first input control pin INP is connected to the anode of the light-emitting diode D1, the cathode of the light-emitting diode D1 is connected to the second input control pin INN, the first input control pin INP serves as an input port of an external current signal, and the external current signal flows from the first input control pin INP to the second input control pin INN through the light-emitting diode D1.

[0009] As a further scheme of the present application, the second photocell group comprises a first photocell Va and a second photocell Vb, the anode of the first photocell Va serves as the anode of the second photocell group, the cathode of the first photocell Va is connected to the anode of the second photocell Vb, and the cathode of the second photocell Vb is connected to the second end of the first resistor R1 and the gate of the first NMOS tube N1.

[0010] As a further scheme of the present application, the power tube (MOSFET) comprises a first MOSFET tube M1 and a second MOSFET tube M2, the gate of the first MOSFET tube M1 is connected to the anode of the first photocell group and the gate of the second MOSFET tube M2, the source of the first MOSFET tube M1 is connected to the source of the second MOSFET tube M2, the drain of the first MOSFET tube M1 is the first controlled output port OUT1, and the drain of the second MOSFET tube M2 is the second controlled output port OUT2.

[0011] As a further scheme of the present application, the first MOSFET tube M1 and the second MOSFET tube M2 are both N-type power tubes.

[0012] As a further scheme of the present application, the field effect transistor module is a field effect transistor, and the field effect transistor is a first NMOS tube N1 or an N-type JFET tube, and the first NMOS tube N1 is a depletion-mode NMOS tube.

[0013] As a further scheme of the present application, the field effect transistor module comprises a field effect transistor, a bipolar NPN transistor Q1, and a PN junction diode D2, the anode of the first photocell group is connected to the collector of the bipolar NPN transistor Q1, the base of the bipolar NPN transistor Q1 is connected to the source of the field effect transistor (the first NMOS tube N1), the emitter of the bipolar NPN transistor Q1 is connected to the anode of the PN junction diode D2, and the cathode of the PN junction diode D2 is connected to the first end of the first resistor R1.

[0014] As a further scheme of the present application: the field effect transistor module comprises a field effect transistor, a second NMOS tube N2, a PN junction diode D2 and a second resistor R2, the drain of the field effect transistor is connected to the drain of the second NMOS tube N2, the source of the second NMOS tube N2 is connected to the anode of the PN junction diode D2 and the first end of the second resistor R2, and the cathode of the PN junction diode D2 and the second end of the second resistor R2 are connected.

[0015] As a further scheme of the present application: the field effect transistor module comprises a field effect transistor, a bipolar PN P transistor Q2 and a PN junction diode D2, the anode of the first photocell group is connected to the anode of the PN junction diode D2, the cathode of the PN junction diode D2 is connected to the emitter of the bipolar PN P transistor Q2 and the gate of the first MOSFET tube M1, the gate of the bipolar PN P transistor Q2 is connected to the drain of the field effect transistor, and the collector of the bipolar PN P transistor Q2 is connected to the first end of the first resistor R1.

[0016] As a further scheme of the present application: the field effect transistor module comprises a field effect transistor, a first PMOS tube P1, a PN junction diode D2 and a second resistor R2, the drain of the field effect transistor is connected to the gate of the first PMOS tube P1, the anode of the PN junction diode D2 and the first end of the second resistor R2, the source of the first PMOS tube P1 is connected to the cathode of the PN junction diode D2 and the second end of the second resistor R2, and the drain of the first PMOS tube P1 is connected to the first end of the first resistor R1.

[0017] As a further scheme of the present application: the light emitting diode D1 is an LED light emitting diode.

[0018] As a further scheme of the present application: the first photocell group comprises n diodes, the n diodes are respectively a first diode V1, a second diode V2, …, and an n-th diode Vn, and the n diodes are connected in series.

[0019] Compared with the prior art, the present application has the following beneficial effects: 1、The present application can turn off the N1 tube by providing a second photocell group for the N1 tube, which is not limited to two sections, and can further improve the discharge current of the PVG chip by setting the diode D2 and the triode Q1, further improve the discharge current of the PVG chip by the diode D2 and the PNP triode Q2, further improve the discharge current of the PVG chip by further setting the diode D2, the second resistor and the NMOS tube N2, and further strengthen the discharge current of the PVG chip by setting the diode D2, the second resistor and the PMOS tube Q2.

[0020] 2、The application can obtain higher discharge current by setting the triode and diode between the first NMOS tube and the power tube, further accelerates the discharge of the MOSFET gate parasitic capacitor, can realize the discharge time of the 10nF gate parasitic capacitor discharge less than 10uS, greatly improves the turn-off speed of the solid state relay. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is the structural diagram of the existing solid state relay; Figure 2 is the solid state relay composed of the traditional PVG chip; Figure 3 is the solid state relay circuit structural diagram of the first embodiment of the application; Figure 4 is the solid state relay circuit structural diagram of the second embodiment of the application; Figure 5 is the solid state relay circuit structural diagram of the third embodiment of the application; Figure 6 is the solid state relay circuit structural diagram of the fourth embodiment of the application; Figure 7 is the solid state relay circuit structural diagram of the fifth embodiment of the application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0023] First embodiment: Please refer to Figures 1-3In this embodiment of the invention, a solid-state relay circuit with fast turn-off function includes a photovoltaic generating chip, which includes a first photovoltaic cell group. The solid-state relay circuit also includes a light-emitting input module and the first photovoltaic cell group. The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of a light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as an input port for an external current signal, which flows from the first input control pin INP through the light-emitting diode D1 to the second input control pin INN. The light-emitting input module emits infrared light to the first photovoltaic cell group. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. After receiving the infrared light, the first photovoltaic cell group generates a voltage signal that can charge the gate of the power transistor using the photovoltaic effect, thus turning on the power transistor. The anode of the first photovoltaic cell group is connected to the drain of a field-effect transistor module and the gate of the power transistor, and the source of the field-effect transistor module is connected to a first resistor R1. The first terminal, the anode of the second photovoltaic cell, and the source of the power transistor, the power transistor includes a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to the anode of the first photovoltaic cell and the gate of the second MOSFET M2. The source of the first MOSFET M1 is connected to the source of the second MOSFET M2. The drain of the first MOSFET M1 is the first controlled output port OUT1, and the drain of the second MOSFET M2 is the second controlled output port OUT2. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell and the second terminal of the first resistor R1. The voltage signal generated by the second photovoltaic cell sets the gate-source voltage difference of the field-effect transistor module below the threshold VTH. The second photovoltaic cell includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

[0024] Preferably, both the first MOSFET M1 and the second MOSFET M2 are N-type power transistors.

[0025] In this embodiment, the field-effect transistor module is a first NMOS transistor N1, which is a depletion-type NMOS transistor.

[0026] In this embodiment, when a current signal is input from the INP to the INN port, the LED D1 emits infrared light. The first photovoltaic cell group in the PVG chip receives the infrared light and generates a voltage signal using the photovoltaic effect. Va and Vb are connected in series between the gate and source of the depletion-type NMOS transistor N1. Figure 3As shown in the figure, Va and Vb use two photovoltaic cells. In actual applications, it is not limited to two photovoltaic cells. The voltage signals generated by Va and Vb set the gate-source voltage difference of N1 below the threshold VTH, so N1 is in the off state. The photovoltaic cell group V1~Vn is connected in series to generate a voltage signal of n*Vp (Vp is the voltage value generated by each photovoltaic cell, about 0.5V~0.6V). The voltage signal generated by the photovoltaic cell group charges the gates of N-type MOSFETs M1 and M2, thereby turning on the MOSFETs and connecting the two ports OUT1 and OUT2.

[0027] When the current signal input from the INP to the INN port is turned off, LED D1 stops emitting light, the first photovoltaic cell group in the PVG chip stops outputting a voltage signal, and the parasitic capacitance Ca in the circuit (including the parasitic capacitances of the series photovoltaic cells Va and Vb and the gate parasitic capacitance of the MOSFET N1) discharges rapidly through the first resistor R1. The current flowing through N1 during the discharge of Ca is: The current I discharges the gate capacitance Cm of MOSFETs M1 and M2 and the parasitic capacitance Cn of the photovoltaic cell arrays V1~Vn.

[0028] The discharge time of the parasitic capacitance Ca is approximately: t1≈2*R1*Ca; where, Here are the process and physical parameters for the depletion-type NMOS transistor N1. VGS is the voltage difference between the gate and source of N1, and VTH is the threshold voltage of N1. Both VGS and VTH are negative values.

[0029] The value of resistor R1 is usually selected from 100K Ohm to 500K Ohm. If the value of capacitor Ca is less than 1pF, the discharge time t1 of parasitic capacitor Ca is less than 1uS.

[0030] After the parasitic capacitance Ca has discharged completely, the VGS of transistor N1 is equal to 0V, and the current flowing through N1 becomes: The width-to-length ratio W / L of N1 should be designed appropriately. It can easily reach the mA level or above.

[0031] Subsequently, the current discharge circuit in the PVG chip discharges the gate capacitance Cm of MOSFETs M1 and M2 and the parasitic capacitance Cn of the photovoltaic cell group V1~Vn with a large current I', thereby turning off the MOSFETs and disconnecting the connection between the two ports OUT1 and OUT2.

[0032] The discharge time is: t2= Cn+Cm is typically a few pF to a few nF, I' has a minimum value of 1mA, the voltage difference between OUT and GND is the output voltage of the n photovoltaic cells V1~Vn, n*Vp is 10V, then the turn-off time of the solid-state relay (less than t1+t2) is about 1uS to 100uS, that is, the turn-off time of the solid-state relay of this invention is less than one percent of the turn-off time of the traditional solid-state relay.

[0033] Second embodiment: Please see Figure 4This embodiment provides a solid-state relay circuit with fast turn-off function, including a photovoltaic generating chip, which includes a first photovoltaic cell array. The solid-state relay circuit also includes a light-emitting input module and the first photovoltaic cell array. The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of a light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as the input port for an external current signal, which flows from the first input control pin INP through the light-emitting diode D1 to the second input control pin INN. Pin INN is used by the light-emitting input module to emit infrared light to the first photovoltaic cell group. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. Upon receiving the infrared light, the first photovoltaic cell group generates a voltage signal that charges the gate of the power transistor using the photovoltaic effect, thus turning on the power transistor. The anode of the first photovoltaic cell group is connected to the drain of the field-effect transistor module and the gate of the power transistor. The source of the field-effect transistor module is connected to the first terminal of the first resistor R1, the anode of the second photovoltaic cell group, and the source of the power transistor. The power transistors include a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to the anode of the first photovoltaic cell group and the gate of the second photovoltaic cell group. The gate of the second MOSFET M2 is connected to the gate of the first MOSFET M1, and the source of the second MOSFET M2 is connected to the source of the second MOSFET M2. The drain of the first MOSFET M1 is the first controlled output port OUT1, and the drain of the second MOSFET M2 is the second controlled output port OUT2. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell and the second terminal of the first resistor R1. The field-effect transistor module includes a field-effect transistor, a bipolar NPN transistor Q1, and a PN junction diode D2. The anode of the first photovoltaic cell is connected to the collector of the bipolar NPN transistor Q1, and the base of the bipolar NPN transistor Q1 is connected to the collector of the second photovoltaic cell. The source of the field-effect transistor (first NMOS transistor N1) and the emitter of the bipolar NPN transistor Q1 are connected to the anode of the PN junction diode D2. The cathode of the PN junction diode D2 is connected to the first terminal of the first resistor R1. The voltage signal generated by the second photovoltaic cell group sets the gate-source voltage difference of the field-effect transistor module below the threshold VTH. The second photovoltaic cell group includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell group. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

[0034] In this embodiment, when a current signal is input from the INP to the INN port, the LED emits infrared light. The first photovoltaic cell group in the PVG chip receives the infrared light and generates a voltage signal using the photovoltaic effect. Va and Vb are connected in series between the gate and source of the depletion-type NMOS transistor N1.Figure 4 As shown in the circuit diagram, Va and Vb use two photovoltaic cells. In actual applications, it is not limited to two photovoltaic cells. The voltage signals generated by Va and Vb set the gate-source voltage difference of N1 below the threshold VTH, so N1 is in the off state. Since there is no base drive current, the transistor Q1 is also in the off state. The photovoltaic cell group V1~Vn is connected in series to generate a voltage signal of n*Vp (Vp is the voltage value generated by each photovoltaic cell, about 0.5V~0.6V). The voltage signal generated by the photovoltaic cell group charges the gates of N-type MOSFETs M1 and M2, thereby turning on the MOSFETs and connecting the two ports OUT1 and OUT2.

[0035] When the current signal input from the INP to the INN port is turned off, the LED stops emitting light, the photovoltaic cell in the PVG chip stops outputting a voltage signal, and the parasitic capacitance Ca in the circuit (including the parasitic capacitances of the series photovoltaic cells Va and Vb and the gate parasitic capacitance of the NMOS transistor N1) discharges rapidly through resistor R1. The current flowing through N1 during the discharge is: ; As mentioned earlier, the duration of this discharge process is less than 1µs.

[0036] After the parasitic capacitance Ca has discharged completely, VGS = 0V, and the current flowing through N1 becomes: ; Figure 4 The current I(I') flowing through N1 includes the discharge current I1 of the photovoltaic cell's parasitic capacitance and the discharge current I2 of the gate parasitic capacitance of MOSFETs M1 and M2. Because diode D2 is reverse-biased, current I2 flows to the base of transistor Q1. The collector current of transistor Q1 is: Iq = I² * β; where β is the amplification factor of the bipolar NPN transistor Q1, which is usually greater than 100.

[0037] That is, the total discharge current of the MOSFET gate parasitic capacitance is: Im = I2 * (1 + β); That is, the discharge current of the optimized and upgraded structure has increased by more than 100 times, the MOSFET gate parasitic capacitance is discharged quickly, MOSFETs M1 and M2 are turned off, and the connection between the two ports OUT1 and OUT2 is disconnected.

[0038] Optimize and upgrade the structure Figure 4 Circuit ratio Figure 3 The circuit structure has a higher discharge current, which further accelerates the discharge of the MOSFET gate parasitic capacitance. The discharge time for a 10nF gate parasitic capacitance is less than 10µs, which greatly improves the turn-off speed of the solid-state relay.

[0039] Third embodiment: Please see Figure 5 In this embodiment of the invention, a solid-state relay circuit with fast turn-off function includes a photovoltaic generating chip, which includes a first photovoltaic cell array. The solid-state relay circuit also includes a light-emitting input module and the first photovoltaic cell array. The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of a light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as the input port for an external current signal, which originates from the first input control pin INP and passes through the light-emitting diode D1. The light flows to the second input control pin INN, and the light-emitting input module emits infrared light to the first photovoltaic cell group. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. Upon receiving the infrared light, the first photovoltaic cell group generates a voltage signal that charges the gate of the power transistor using the photovoltaic effect, thus turning on the power transistor. The anode of the first photovoltaic cell group is connected to the drain of the field-effect transistor module and the gate of the power transistor. The source of the field-effect transistor module is connected to the first terminal of the first resistor R1, the anode of the second photovoltaic cell group, and the source of the power transistor. The power transistors include a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1... The source of the first MOSFET M1 is connected to the source of the second MOSFET M2, the drain of the first MOSFET M1 is the first controlled output port OUT1, and the drain of the second MOSFET M2 is the second controlled output port OUT2. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell and the second terminal of the first resistor R1. The field-effect transistor module includes a field-effect transistor, a second NMOS transistor N2, a PN junction diode D2, and a second resistor R2. The drain of the field-effect transistor is connected to the second NMOS transistor... The drain of N2 and the source of the second NMOS transistor N2 are connected to the anode of the PN junction diode D2 and the first terminal of the second resistor R2. The cathode of the PN junction diode D2 and the second terminal of the second resistor R2 are connected. The voltage signal generated by the second photovoltaic cell group sets the gate-source voltage difference of the field-effect transistor module below the threshold VTH. The second photovoltaic cell group includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell group. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

[0040] In this embodiment, the working principle is similar to that of the NPN structure circuit, but the amplified current changes from I²*(1+β) to: Im = I2 * (R2 * gm + 1); where gm is the transconductance of the second NMOS transistor N2.

[0041] Fourth embodiment: Please see Figure 6 In this embodiment of the invention, a solid-state relay circuit with fast turn-off function includes a photovoltaic generating chip, which includes a first photovoltaic cell array. The solid-state relay circuit also includes a light-emitting input module and the first photovoltaic cell array. The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of a light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as the input port for an external current signal, which flows from the first input control pin INP through the light-emitting diode D1 to the second input control pin INN. The LED input module emits infrared light to the first photovoltaic cell group via pin INN. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. Upon receiving the infrared light, the first photovoltaic cell group generates a voltage signal that charges the gate of the power transistor using the photovoltaic effect, thus turning on the power transistor. The anode of the first photovoltaic cell group is connected to the drain of the field-effect transistor module and the gate of the power transistor. The source of the field-effect transistor module is connected to the first terminal of the first resistor R1, the anode of the second photovoltaic cell group, and the source of the power transistor. The power transistors include a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to the anode of the first photovoltaic cell group and the gate of the second MOSFET M2. The gate of MOSFET M2 is connected to the source of the first MOSFET M1, and the drain of the first MOSFET M1 is connected to the first controlled output port OUT1. The drain of the second MOSFET M2 is connected to the second controlled output port OUT2. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell and the second terminal of the first resistor R1. The field-effect transistor module includes a field-effect transistor, a bipolar PNP transistor Q2, and a PN junction diode D2. The anode of the first photovoltaic cell is connected to the anode of the PN junction diode D2, and the cathode of the PN junction diode D2 is connected to the bipolar PNP transistor Q2. The emitter of the second photovoltaic cell is connected to the gate of the first MOSFET M1. The gate of the bipolar PNP transistor Q2 is connected to the drain of the field-effect transistor. The collector of the bipolar PNP transistor Q2 is connected to the first terminal of the first resistor R1. The voltage signal generated by the second photovoltaic cell sets the gate-source voltage difference of the field-effect transistor module below the threshold VTH. The second photovoltaic cell includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

[0042] In this embodiment, the working principle is similar to that of the NPN structure circuit, and the amplified current is also I²*(1+β).Figure 6 The bipolar PNP transistor Q1 in the circuit can also be replaced with a PMOS transistor, such as... Figure 7 As shown, its working principle is similar to that of the NMOS structure circuit, and the amplified current is also I2*(R2*gm+1), where gm is the transconductance of the PMOS transistor Q1.

[0043] Fifth embodiment: Please see Figure 7In this embodiment of the invention, a solid-state relay circuit with fast turn-off function includes a photovoltaic generating chip, which includes a first photovoltaic cell array. The solid-state relay circuit also includes a light-emitting input module and the first photovoltaic cell array. The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of a light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as the input port for an external current signal, which flows from the first input control pin INP through the light-emitting diode D1 to the second input control pin INN. The control pin INN allows the light-emitting input module to emit infrared light to the first photovoltaic cell group. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. Upon receiving the infrared light, the first photovoltaic cell group generates a voltage signal that charges the gate of the power transistor using the photovoltaic effect, thus turning on the power transistor. The anode of the first photovoltaic cell group is connected to the drain of the field-effect transistor module and the gate of the power transistor. The source of the field-effect transistor module is connected to the first terminal of the first resistor R1, the anode of the second photovoltaic cell group, and the source of the power transistor. The power transistors include a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to the anode of the first photovoltaic cell group. The gate of the first MOSFET M1 is connected to the gate of the second MOSFET M2, the source of the first MOSFET M1 is connected to the source of the second MOSFET M2, the drain of the first MOSFET M1 is the first controlled output port OUT1, and the drain of the second MOSFET M2 is the second controlled output port OUT2. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell and the second terminal of the first resistor R1. The field-effect transistor module includes a field-effect transistor, a first PMOS transistor P1, a PN junction diode D2, and a second resistor R2. The drain of the field-effect transistor is connected to the gate of the first PMOS transistor P1, the anode of the PN junction diode D2, and the second terminal of the first photovoltaic cell. The first terminal of the second resistor R2 is connected to the source of the first PMOS transistor P1, which is connected to the cathode of the PN junction diode D2 and the second terminal of the second resistor R2. The drain of the first PMOS transistor P1 is connected to the first terminal of the first resistor R1. The voltage signal generated by the second photovoltaic cell group sets the gate-source voltage difference of the field-effect transistor module below the threshold VTH. The second photovoltaic cell group includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell group. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

[0044] In this embodiment, by increasing the current discharge capability of the PVG chip, the turn-off time of the MOSFET is shortened, thereby achieving rapid turn-off of the solid-state relay. Figure 4 , Figure 5 , Figure 6 and Figure 7The circuit structures shown are all within the scope of protection of this invention patent. The technology proposed in this invention has the advantages of low cost and good performance, expands the application of solid-state relays, and can be well applied in higher frequency scenarios.

[0045] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A solid-state relay circuit with fast turn-off function, comprising a photovoltaic generating chip, the photovoltaic generating chip comprising a first photovoltaic cell array, characterized in that, The solid-state relay circuit also includes: The light-emitting input module emits infrared light to the first photovoltaic cell group. A power transistor is connected between the positive and negative terminals of the first photovoltaic cell group. After receiving the infrared light, the first photovoltaic cell group generates a voltage signal that can charge the gate of the power transistor using the photovoltaic effect, thereby turning on the power transistor. The first photovoltaic cell group has its anode connected to the drain of the field-effect transistor module and the gate of the power transistor. The source of the field-effect transistor module is connected to the first terminal of the first resistor R1, the anode of the second photovoltaic cell group, and the source of the power transistor. The gate of the field-effect transistor module is connected to the cathode of the second photovoltaic cell group and the second terminal of the first resistor R1. The voltage signal generated by the second photovoltaic cell group sets the gate-source voltage difference of the field-effect transistor module to below the threshold VTH.

2. The solid-state relay circuit with fast shutdown function according to claim 1, characterized in that: The light-emitting input module includes a first input control pin INP and a second input control pin INN. One end of the first input control pin INP is connected to the anode of the light-emitting diode D1, and the cathode of the light-emitting diode D1 is connected to the second input control pin INN. The first input control pin INP serves as the input port for an external current signal, which flows from the first input control pin INP through the light-emitting diode D1 to the second input control pin INN.

3. The solid-state relay circuit with fast shutdown function according to claim 2, characterized in that: The second photovoltaic cell group includes a first photovoltaic cell Va and a second photovoltaic cell Vb. The anode of the first photovoltaic cell Va serves as the anode of the second photovoltaic cell group. The cathode of the first photovoltaic cell Va is connected to the anode of the second photovoltaic cell Vb. The cathode of the second photovoltaic cell Vb is connected to the second terminal of the first resistor R1 and the gate of the first NMOS transistor N1.

4. The solid-state relay circuit with fast shutdown function according to claim 3, characterized in that: The power transistors include a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to the anode of the first photovoltaic cell and the gate of the second MOSFET M2. The source of the first MOSFET M1 is connected to the source of the second MOSFET M2. The drain of the first MOSFET M1 is the first controlled output port OUT1, and the drain of the second MOSFET M2 is the second controlled output port OUT2.

5. The solid-state relay circuit with fast turn-off function according to claim 4, characterized in that: The field-effect transistor module is a field-effect transistor, which is either a first NMOS transistor N1 or an N-type JFET transistor. The first NMOS transistor N1 is a depletion-type NMOS transistor.

6. The solid-state relay circuit with fast shutdown function according to claim 4, characterized in that: The field-effect transistor module includes a field-effect transistor, a bipolar NPN transistor Q1, and a PN junction diode D2. The anode of the first photovoltaic cell is connected to the collector of the bipolar NPN transistor Q1, the base of the bipolar NPN transistor Q1 is connected to the source of the field-effect transistor, the emitter of the bipolar NPN transistor Q1 is connected to the anode of the PN junction diode D2, and the cathode of the PN junction diode D2 is connected to the first terminal of the first resistor R1.

7. The solid-state relay circuit with fast turn-off function according to claim 4, characterized in that: The field-effect transistor module includes a field-effect transistor, a second NMOS transistor N2, a PN junction diode D2, and a second resistor R2. The drain of the field-effect transistor is connected to the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is connected to the anode of the PN junction diode D2 and the first terminal of the second resistor R2, and the cathode of the PN junction diode D2 and the second terminal of the second resistor R2 are connected.

8. The solid-state relay circuit with fast shutdown function according to claim 4, characterized in that: The field-effect transistor module includes a field-effect transistor, a bipolar PNP transistor Q2, and a PN junction diode D2. The anode of the first photovoltaic cell is connected to the anode of the PN junction diode D2. The cathode of the PN junction diode D2 is connected to the emitter of the bipolar PNP transistor Q2 and the gate of the first MOSFET M1. The gate of the bipolar PNP transistor Q2 is connected to the drain of the field-effect transistor. The collector of the bipolar PNP transistor Q2 is connected to the first terminal of the first resistor R1.

9. The solid-state relay circuit with fast turn-off function according to claim 4, characterized in that: The field-effect transistor module includes a field-effect transistor, a first PMOS transistor P1, a PN junction diode D2, and a second resistor R2. The drain of the field-effect transistor is connected to the gate of the first PMOS transistor P1, the anode of the PN junction diode D2, and the first terminal of the second resistor R2. The source of the first PMOS transistor P1 is connected to the cathode of the PN junction diode D2 and the second terminal of the second resistor R2. The drain of the first PMOS transistor P1 is connected to the first terminal of the first resistor R1.

10. The solid-state relay circuit with fast turn-off function according to claim 2, characterized in that: The light-emitting diode D1 is an LED.

Images