Pin multiplexing structure of OLT device

Abstract

The application discloses a pin multiplexing structure of an OLT device, which comprises a TIA module and a LA module; the TIA module has a burst RSSI monitoring unit, a PD unit, a TIA unit, a comparator unit and a RESET-IN / RSSI-OUT pin; the LA module has a logic switching unit, a current-to-voltage unit, a RESET-OUT / RSSI-IN pin, a system RESET port and a system RSSI port; and the RESET-OUT / RSSI-IN pin is connected with the RESET-IN / RSSI-OUT pin. Compared with the prior art, the application can effectively reduce the number of pins and reduce the packaging cost.

Description

Technical Field

[0001] This invention relates to the field of optical communication, and in particular to a pin multiplexing structure for an OLT device. Background Technology

[0002] Existing OLT (Optical Line Terminal) equipment uses burst reception at the receiver end. To meet burst timing requirements, the system needs to send a RESET signal to the TIA (Trans-Impedance Amplifier) ​​and LA (Limiting Amplifier) ​​modules to achieve circuit convergence. Therefore, both the TIA and LA modules require a RESET pin. Furthermore, if the system needs to monitor the optical power of the PD (PhotoDiode) unit in the TIA module, it needs to send an RSSI-Trigger signal to both the TIA and LA modules to enable RSSI monitoring. However, this requires adding RSSI pins to both the TIA and LA modules, increasing packaging costs.

[0003] In view of the above problems, it is necessary to study a pin reuse structure for OLT devices, aiming to solve the problems of large number of pins and high packaging cost in the existing technology. Summary of the Invention

[0004] The purpose of this invention is to provide a pin reuse structure for OLT devices, aiming to solve the problems of large number of pins and high packaging cost in the prior art.

[0005] To achieve the above objectives, the solution of the present invention is:

[0006] A pin multiplexing structure for an OLT device includes a TIA module and an LA module. The TIA module has a burst RSSI monitoring unit, a PD unit, a comparator unit, and RESET-IN / RSSI-OUT pins. The input of the burst RSSI monitoring unit is connected to the negative terminal of the PD unit, and its output is connected to the RESET-IN / RSSI-OUT pins. The burst RSSI monitoring unit generates a corresponding IRESET current signal output based on the power of the PD unit. The input of the TIA unit is connected to the positive terminal of the PD unit, and its enable terminal is connected to the output of the comparator unit. The first input of the comparator unit is connected to the RESET-IN / RSSI-OUT pin, and its second input is connected to a Vref threshold signal. The LA module has a logic switching unit, a current-to-voltage conversion unit, RESET-OUT / RSSI-IN pins, a system RESET port, and a system RSSI port. The system RESET port is used to receive the RESET signal sent by the system. The system RSSI port is used to receive the RSSI-Trigger signal sent by the system. The logic switching unit includes a first switch, a second switch, a first NOT gate, a second NOT gate, and a first AND gate. The first terminal of the first switch and the first terminal of the second switch are connected to the RESET-OUT / RSSI-IN pins. The second terminal of the first switch is connected to the output terminal of the first NOT gate. The control terminal of the first switch and the input terminal of the second NOT gate are connected to the system RESET port. The output terminal of the second NOT gate is connected to the input terminal of the first NOT gate and the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the system RSSI port. The output terminal of the first AND gate is connected to the control terminal of the second switch. The second terminal of the second switch is connected to the input terminal of the current-to-voltage unit. The current-to-voltage unit is used to convert the IRESET current signal into the VRESET voltage signal. The first NOT gate and the second NOT gate are used to convert the RESET signal into an in-phase RESET-SW signal. The RESET-OUT / RSSI-IN pin of the LA module is connected to the RESET-IN / RSSI-OUT pin of the TIA module.

[0007] The current-to-voltage unit includes a conversion resistor and an analog-to-digital converter circuit. The first end of the conversion resistor and the input end of the analog-to-digital converter circuit are connected to the input end of the current-to-voltage unit, and the second end of the conversion resistor is grounded.

[0008] The LA module also includes a current-limiting protection unit connected in parallel with the conversion resistor.

[0009] The current limiting protection unit includes a current limiting switch, a current limiting circuit, an RSSI delay circuit, and a digital logic circuit. The first terminal of the current limiting circuit is connected to the first terminal of the conversion resistor, the second terminal of the current limiting circuit is connected to the first terminal of the current limiting switch, the second terminal of the current limiting switch is connected to the second terminal of the conversion resistor, the control terminal of the current limiting switch is connected to the digital logic circuit, the digital logic circuit is connected to the system RESET port, and the digital logic circuit is connected to the system RSSI port through the RSSI delay circuit. The RSSI delay circuit is used to delay the RSSI-Trigger signal to obtain the RSSI-Trigger-Delay signal. The delay time of the RSSI delay circuit is less than the pulse width of the RSSI-Trigger-Delay signal. The digital logic circuit closes the current limiting switch when it detects the rising edge of the RSSI-Trigger-Delay signal, and opens the current limiting switch when it detects the rising edge of the RESET signal.

[0010] The current limiting circuit includes at least two current limiting diodes connected in series.

[0011] The digital logic circuit includes a RESET delay circuit, a signal compression circuit, an OR gate, and a D flip-flop. The input of the RESET delay circuit and the D pin of the D flip-flop are connected to the first input of the digital logic circuit. The input of the signal compression circuit is connected to the second input of the digital logic circuit. The outputs of the RESET delay circuit and the signal compression circuit are respectively connected to the two inputs of the OR gate. The output of the OR gate is connected to the CLK pin of the D flip-flop, and the Q pin of the D flip-flop is connected to the output of the digital logic circuit. The first input of the digital logic circuit is connected to the system RESET port to receive the RESET signal. The second input of the digital logic circuit is connected to the output of the RSSI delay circuit to receive the RSSI-Trigger-Delay signal. The output of the digital logic circuit is connected to the control terminal of the current limiting switch. The output of the word logic circuit is a CK signal to control the switching of the current limiting switch; the RESET delay circuit is used to delay the RESET signal to obtain the RESET-Delay signal. The delay time of the RESET delay circuit is less than the pulse width of the RESET signal. The signal compression circuit is used to compress the RSSI-Trigger-Delay signal to obtain the RSSI-Trigger-Delay-Rise signal. The rising edge time of the RSSI-Trigger-Delay-Rise signal is the same as the rising edge time of the RSSI-Trigger-Delay signal. The pulse width of the RSSI-Trigger-Delay-Rise signal is less than the pulse width of the RSSI-Trigger-Delay signal.

[0012] The signal compression circuit includes a signal delay circuit, an XOR gate, and a second AND gate. The input terminal of the signal delay circuit, the first input terminal of the XOR gate, and the first input terminal of the second AND gate are connected to the input terminal of the signal compression circuit. The output terminal of the signal delay circuit is connected to the second input terminal of the XOR gate, the output terminal of the XOR gate is connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the output terminal of the signal compression circuit. The signal delay circuit is used to delay the RSSI-Trigger-Delay signal, and the delay time of the signal delay circuit is less than the pulse width of the RSSI-Trigger-Delay signal.

[0013] The burst RSSI monitoring unit includes a first MOS transistor and a second MOS transistor. The drain and gate of the first MOS transistor and the gate of the second MOS transistor are connected to the input terminal of the burst RSSI monitoring unit. The source of the first MOS transistor and the source of the second MOS transistor are grounded. The drain of the second MOS transistor is connected to the output terminal of the RSSI monitoring unit.

[0014] After adopting the above scheme, the working principle of the present invention is as follows:

[0015] When the system only sends the RESET signal (i.e., the system RSSI port remains low), the second switch remains closed, and the first switch closes when the RESET signal is high. When the first switch is closed, the RESET signal is output as the RESET-SW signal formed by the second NOT gate and the first NOT gate (the RESET-SW signal is in phase with the RESET signal). This RESET-SW signal is input to the first input terminal of the comparator unit through the RESET-OUT / RSSI-IN pin and the RESET-IN / RSSI-OUT pin. When the RESET-SW signal is greater than the Vref threshold signal, the comparator unit outputs a high-level signal to the TIA unit, and the TIA unit starts working to implement the RESET function.

[0016] When the system sends a RESET signal and an RSSI-Trigger signal, the first and second switches will not close simultaneously due to the settings of the first NOT gate, the second NOT gate, and the first AND gate. Specifically, the first switch closes when the RESET signal is high. When the first switch closes, the RESET signal passes through the second NOT gate and the first NOT gate to form a high-level RESET-SW signal output (the RESET-SW signal is in phase with the RESET signal). This RESET-SW signal is input to the first input terminal of the comparator unit through the RESET-OUT / RSSI-IN and RESET-IN / RSSI-OUT pins. The comparator unit outputs a high-level signal to the TIA unit, which then performs the RESET function. The second switch closes when the RSSI-Trigger signal is high. At this time, the burst RSSI monitoring unit generates an I signal based on the power of the PD unit. RESET The current signal is input to the input terminal of the current-to-voltage unit through the RESET-OUT / RSSI-IN and RESET-IN / RSSI-OUT pins. The current-to-voltage unit converts I... RESET Current signal converted to V RESET Voltage signal to achieve RSSI function.

[0017] As can be seen from the above, the RESET-IN / RSSI-OUT pins of the TIA module and the RESET-OUT / RSSI-IN pins of the LA module of the present invention both have the effect of pin multiplexing, and both can realize the RESET-SW signal and I RESET The transmission of current signals enables time-division multiplexing of RESET and RSSI functions; moreover, compared with existing technologies, this invention can effectively reduce the number of pins and lower packaging costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the present invention.

[0019] Figure 2 This is a schematic diagram of the digital logic circuit of the present invention.

[0020] Label Explanation:

[0021] TIA Module 1,

[0022] Sudden RSSI monitoring unit 11, first MOSFET 111, second MOSFET 112,

[0023] PD unit 12, photodiode 121,

[0024] TIA Unit 13,

[0025] Comparator unit 14,

[0026] RESET-IN / RSSI-OUT pin 15

[0027] LA Module 2,

[0028] Logic switching unit 21, first switch 211, second switch 212, first NOT gate 213, second NOT gate 214, first AND gate 215,

[0029] Current-to-voltage converter 22, conversion resistor 221, analog-to-digital converter circuit 222

[0030] RESET-OUT / RSSI-IN pin 23

[0031] System RESET port 24,

[0032] System RSSI port 25,

[0033] Current limiting protection unit 26, current limiting switch 261, current limiting circuit 262, current limiting diode 2621, RSSI delay circuit 263.

[0034] Digital logic circuit 264,

[0035] RESET delay circuit 2641,

[0036] Signal compression circuit 2642, signal delay circuit 26421, XOR gate 26422, second AND gate 26423.

[0037] OR gate 2643,

[0038] D flip-flop 2644. Detailed Implementation

[0039] To further explain the technical solution of the present invention, the present invention will be described in detail below through specific embodiments.

[0040] like Figure 1 and Figure 2 As shown, this invention discloses a pin multiplexing structure for an OLT device, comprising a TIA module 1 and an LA module 2. The TIA module 1 has a burst RSSI monitoring unit 11, a PD unit 12, a TIA unit 13, a comparator unit 14, and a RESET-IN / RSSI-OUT pin 15. The input terminal of the burst RSSI monitoring unit 11 is connected to the negative terminal of the PD unit 12, and the output terminal of the burst RSSI monitoring unit 11 is connected to the RESET-IN / RSSI-OUT pin 15. The burst RSSI monitoring unit 11 is used to generate corresponding I / O signals based on the power of the PD unit 12. RESETCurrent signal output; the input terminal of TIA unit 13 is connected to the positive terminal of PD unit 12, the enable terminal of TIA unit 13 is connected to the output terminal of comparator unit 14, the first input terminal of comparator unit 14 is connected to RESET-IN / RSSI-OUT pin 15, and the second input terminal of comparator unit 14 is connected to Vref threshold signal; LA module 2 has logic switching unit 21, current to voltage unit 22, RESET-OUT / RSSI-IN pin 23, system RESET port 24 and system RSSI port 25. System RESET port 24 is used to receive RESET signal sent by the system, and system RSSI port 25 is used to receive RSSI-Trigger signal sent by the system; logic switching unit 21 includes a first switch 211, a second switch 211, a third switch 212, a fourth switch 212, a fifth switch 212, a sixth switch 212, a seventh switch 212, a seventh switch 213, a stern switch 212 ... Switch 212, first NOT gate 213, second NOT gate 214, and first AND gate 215; the first terminal of the first switch 211 and the first terminal of the second switch 212 are connected to the RESET-OUT / RSSI-IN pin 23; the second terminal of the first switch 211 is connected to the output terminal of the first NOT gate 213; the control terminal of the first switch 211 and the input terminal of the second NOT gate 214 are connected to the system RESET port 24; the output terminal of the second NOT gate 214 is connected to the input terminal of the first NOT gate 213 and the first input terminal of the first AND gate 215; the second input terminal of the first AND gate 215 is connected to the system RSSI port 25; the output terminal of the first AND gate 215 is connected to the control terminal of the second switch 212; the second terminal of the second switch 212 is connected to the input terminal of the current-to-voltage converter 22, which is used to convert I... RESET Current signal converted to V RESET The voltage signal, the first NOT gate 213 and the second NOT gate 214 are used to convert the RESET signal into an in-phase RESET-SW signal; the RESET-OUT / RSSI-IN pin 23 of the LA module 2 is connected to the RESET-IN / RSSI-OUT pin 15 of the TIA module 1.

[0041] The working principle of this invention is as follows:

[0042] When the system only sends the RESET signal (i.e., the system RSSI port 25 is kept low), the second switch 212 remains closed, and the first switch 211 closes when the RESET signal is high. When the first switch 211 is closed, the RESET signal is output as the RESET-SW signal formed by the second NOT gate 214 and the first NOT gate 213 (the RESET-SW signal is in phase with the RESET signal). This RESET-SW signal is input to the first input terminal of the comparator unit 14 through the RESET-OUT / RSSI-IN pin 23 and the RESET-IN / RSSI-OUT pin 15. When the RESET-SW signal is greater than the Vref threshold signal, the comparator unit 14 outputs a high-level signal to the TIA unit 13, and the TIA unit 13 works to realize the RESET function.

[0043] When the system sends a RESET signal and an RSSI-Trigger signal, the first switch 211 and the second switch 212 will not close simultaneously due to the settings of the first NOT gate 213, the second NOT gate 214, and the first AND gate 215. Specifically, the first switch 211 closes when the RESET signal is high. When the first switch 211 closes, the RESET signal passes through the second NOT gate 214 and the first NOT gate 213 to form a high-level RESET-SW signal output (the RESET-SW signal is in phase with the RESET signal). This RESET-SW signal is input to the first input terminal of the comparator unit 14 through the RESET-OUT / RSSI-IN pins 23 and 15. The comparator unit 14 outputs a high-level signal to the TIA unit 13, which then performs the RESET function. Meanwhile, the second switch 212 closes when the RSSI-Trigger signal is high. At this time, the burst RSSI monitoring unit 11 generates an I-value based on the power of the PD unit 12. RESET The current signal is input to the input terminal of the current-to-voltage unit 22 through RESET-OUT / RSSI-IN pin 23 and RESET-IN / RSSI-OUT pin 15. The current-to-voltage unit 22 converts I... RESET Current signal converted to V RESET Voltage signal to achieve RSSI function.

[0044] As can be seen from the above, both the RESET-IN / RSSI-OUT pin 15 of the TIA module 1 and the RESET-OUT / RSSI-IN pin 23 of the LA module 2 of the present invention have the effect of pin multiplexing, and both can realize the RESET-SW signal and I RESETThe transmission of current signals enables time-division multiplexing of RESET and RSSI functions; moreover, compared with existing technologies, this invention can effectively reduce the number of pins and lower packaging costs.

[0045] In an embodiment of the present invention, the burst RSSI monitoring unit 11 may employ a current mirror. Specifically, the burst RSSI monitoring unit 11 includes a first MOSFET 111 and a second MOSFET 112. The drain and gate of the first MOSFET 111 and the gate of the second MOSFET 112 are connected to the input terminal of the burst RSSI monitoring unit 11. The source of the first MOSFET 111 and the source of the second MOSFET 112 are grounded, and the drain of the second MOSFET 112 is connected to the output terminal of the RSSI monitoring unit. The PD unit 12 may include a photodiode 121.

[0046] In an embodiment of the present invention, the current-to-voltage unit 22 may include a conversion resistor 221 and an analog-to-digital converter circuit 222. The first end of the conversion resistor 221 and the input end of the analog-to-digital converter circuit 222 are connected to the input end of the current-to-voltage unit 22, and the second end of the conversion resistor 221 is grounded. The conversion resistor 221 is used to convert current to voltage, and the analog-to-digital converter circuit 222 is used to convert analog voltage to digital voltage. The current-to-voltage unit 22 can convert I... RESET Current signal converted to V RESET Voltage signal, V RESET The voltage signal is a digital voltage signal.

[0047] In an embodiment of the present invention, the LA module 2 may further include a current-limiting protection unit 26 connected in parallel with the conversion resistor 221, the current-limiting protection unit 26 being used to avoid I RESETExcessive current in the current signal can cause overcurrent damage to the current-to-voltage conversion unit 22 and malfunction of the comparator unit 14. Specifically, the current limiting protection unit 26 includes a current limiting switch 261, a current limiting circuit 262, an RSSI delay circuit 263, and a digital logic circuit 264. The current limiting circuit 262 may include at least two current limiting diodes 2621 connected in series. The first terminal of the current limiting circuit 262 is connected to the first terminal of the conversion resistor 221, and the second terminal of the current limiting circuit 262 is connected to the first terminal of the current limiting switch 261. The second terminal of the current limiting switch 261 is connected to the second terminal of the conversion resistor 221. The control terminal of the current limiting switch 261 is connected to the digital logic circuit 264, which is connected to the system RESET port 24. The digital logic circuit 264 is connected to the RSSI delay circuit. 263 connects to the RSSI port 25 of the system; the RSSI delay circuit 263 is used to delay the RSSI-Trigger signal to obtain the RSSI-Trigger-Delay signal. The delay time of the RSSI delay circuit is less than the pulse width of the RSSI-Trigger-Delay signal (i.e., the pulse width of the RSSI-Trigger signal). The digital logic circuit 264 closes the current limiting switch 261 when it detects the rising edge of the RSSI-Trigger-Delay signal, and the digital logic circuit 264 opens the current limiting switch 261 when it detects the rising edge of the RESET signal. Specifically, when the rising edge of the RESET signal arrives, the current limiting switch 261 closes, causing the current limiting circuit 262 to be connected in parallel with the switching resistor 221. When the RSSI-Trigger signal is high and the RESET signal is low, the second switch 212 closes, while the current limiting switch 261 remains closed, causing the current limiting circuit 262 to remain connected in parallel with the switching resistor 221. At this time, the RSSI function is working, and the voltage of the RESET-IN / RSSI-OUT pin 15 and the RESET-OUT / RSSI-IN pin 23 of the LA module 2 is limited to below the Vref threshold voltage, ensuring that the comparator unit 14 will not flip. The RSSI-Trigger signal is delayed by the RSSI delay circuit 263 to form the RSSI-Trigger-Delay signal. When the rising edge of the RSSI-Trigger-Delay signal occurs (at which time the RSSI-Trigger signal is high), the digital logic circuit 264 opens the current limiting switch 261. RESET The current signal is stable, and the current-to-voltage unit 22 converts I... RESET Current signal converted to V RESET Voltage signal, to avoid the analog-to-digital converter circuit 222 being affected by the leakage current of the current-limiting diode 2621.

[0048] In an embodiment of the present invention, the digital logic circuit 264 includes a RESET delay circuit 2641, a signal compression circuit 2642, an OR gate 2643, and a D flip-flop 2644. The input terminal of the RESET delay circuit 2641 and the D pin of the D flip-flop 2644 are connected to the first input terminal of the digital logic circuit 2644. The input terminal of the signal compression circuit 2642 is connected to the second input terminal of the digital logic circuit 2644. The output terminals of the RESET delay circuit 2641 and the signal compression circuit 2642 are respectively connected to the two input terminals of the OR gate 2643. The output terminal of the OR gate 2643 is connected to the CLK pin of the D flip-flop 2644. The Q pin of the D flip-flop 2644 is connected to the output terminal of the digital logic circuit 2644. The first input terminal of the digital logic circuit 264 is connected to the system RESET port to receive the RESET signal. The second input terminal of the digital logic circuit 264 is connected to the output terminal of the RSSI delay circuit 263 to receive the RSSI-Trigger signal. The Delay signal is connected to the control terminal of the current limiting switch 261 via the output terminal of the digital logic circuit 264. The output terminal of the digital logic circuit 264 outputs a CK signal to control the switching of the current limiting switch 261. The RESET delay circuit 2641 is used to delay the RESET signal to obtain the RESET-Delay signal. The delay time of the RESET delay circuit 2641 is less than the pulse width of the RESET signal. The signal compression circuit 2642 is used to compress the RSSI-Trigger-Delay signal to obtain the RSSI-Trigger-Delay-Rise signal. The rising edge time of the RSSI-Trigger-Delay-Rise signal is the same as the rising edge time of the RSSI-Trigger-Delay signal. The pulse width of the RSSI-Trigger-Delay-Rise signal is less than the pulse width of the RSSI-Trigger-Delay signal. Specifically, when the RSSI-Trigger-Delay signal has a rising edge, the RSSI-Trigger-Delay-Rise signal also has a rising edge. At this time, the OR gate 2643 outputs a rising edge, which triggers the D flip-flop 2644. When the RESET signal is low, the CK signal output by the D flip-flop 2644 is low, causing the current limiting switch 261 to close. When the RESET signal has a rising edge, the RSSI-Trigger-Delay signal is low, and the RSSI-Trigger-Delay-Rise signal is also low. After that, when the delay time of the RESET delay circuit 2641 is reached, the RESET-Delay signal has a rising edge, which triggers the OR gate 2643 to output a rising edge. At this time, the D flip-flop 2644 is triggered, and the RESET signal is high. The CK signal output by the D flip-flop 2644 is high, causing the current limiting switch 261 to open.

[0049] In an embodiment of the present invention, the signal compression circuit 2642 includes a signal delay circuit 26421, an XOR gate 26422, and a second AND gate 26423. The input terminal of the signal delay circuit 26421, the first input terminal of the XOR gate 26422, and the first input terminal of the second AND gate 26423 are connected to the input terminal of the signal compression circuit 2642. The output terminal of the signal delay circuit 26421 is connected to the second input terminal of the XOR gate 26422. The output terminal of the XOR gate 26422 is connected to the second input terminal of the second AND gate 26423. The output terminal of the second AND gate 26423 is connected to the output terminal of the signal compression circuit 2642. The signal delay circuit 26421 is used to delay the RSSI-Trigger-Delay signal, and the delay time of the signal delay circuit 26421 is less than the pulse width of the RSSI-Trigger-Delay signal. Specifically, when the RSSI-Trigger-Delay signal has a rising edge, the output of the signal delay circuit 26421 is still low, so the XOR gate 26422 outputs a high level, causing the second AND gate 26423 to output a high level synchronously. Subsequently, when the delay time of the signal delay circuit 26421 is reached, the output of the signal delay circuit 26421 outputs a high level, causing the XOR gate 26422 to output a low level, causing the second AND gate 26423 to output a low level. When the RSSI-Trigger-Delay signal is low, the second AND gate 26423 outputs a low level.

[0050] The above embodiments and figures are not intended to limit the product form and style of the present invention. Any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims

1. A pin reuse structure for an OLT device, characterized in that: Includes TIA and LA modules; The TIA module includes a burst RSSI monitoring unit, a PD unit, a TIA unit, a comparator unit, and RESET-IN / RSSI-OUT pins. The input of the burst RSSI monitoring unit is connected to the negative terminal of the PD unit, and the output of the burst RSSI monitoring unit is connected to the RESET-IN / RSSI-OUT pins. The burst RSSI monitoring unit is used to generate corresponding I / O signals based on the power of the PD unit. RESET Current signal output; the input terminal of the TIA unit is connected to the positive terminal of the PD unit, the enable terminal of the TIA unit is connected to the output terminal of the comparator unit, the first input terminal of the comparator unit is connected to the RESET-IN / RSSI-OUT pin, and the second input terminal of the comparator unit is connected to the Vref threshold signal. The LA module includes a logic switching unit, a current-to-voltage unit, RESET-OUT / RSSI-IN pins, a system RESET port, and a system RSSI port. The system RESET port is used to receive the RESET signal sent by the system, and the system RSSI port is used to receive the RSSI-Trigger signal sent by the system. The logic switching unit includes a first switch, a second switch, a first NOT gate, a second NOT gate, and a first AND gate. The first terminals of the first and second switches are connected to the RESET-OUT / RSSI-IN pins. The second terminal of the first switch is connected to the output of the first NOT gate. The control terminal of the first switch and the input terminal of the second NOT gate are connected to the system RESET port. The output terminal of the second NOT gate is connected to the input terminal of the first NOT gate and the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the system RSSI port. The output terminal of the first AND gate is connected to the control terminal of the second switch. The second terminal of the second switch is connected to the input terminal of the current-to-voltage unit, which is used to convert I... RESET Current signal converted to V RESET The voltage signal, the first NOT gate and the second NOT gate are used to convert the RESET signal into an in-phase RESET-SW signal; The RESET-OUT / RSSI-IN pins of the LA module are connected to the RESET-IN / RSSI-OUT pins of the TIA module.

2. The pin reuse structure of an OLT device as described in claim 1, characterized in that: The current-to-voltage unit includes a conversion resistor and an analog-to-digital converter circuit. The first end of the conversion resistor and the input end of the analog-to-digital converter circuit are connected to the input end of the current-to-voltage unit, and the second end of the conversion resistor is grounded.

3. The pin reuse structure of an OLT device as described in claim 2, characterized in that: The LA module also includes a current-limiting protection unit connected in parallel with the conversion resistor.

4. The pin reuse structure of an OLT device as described in claim 3, characterized in that: The current limiting protection unit includes a current limiting switch, a current limiting circuit, an RSSI delay circuit, and a digital logic circuit. The first end of the current limiting circuit is connected to the first end of the conversion resistor, the second end of the current limiting circuit is connected to the first end of the current limiting switch, the second end of the current limiting switch is connected to the second end of the conversion resistor, the control end of the current limiting switch is connected to the digital logic circuit, the digital logic circuit is connected to the system RESET port, and the digital logic circuit is connected to the system RSSI port through the RSSI delay circuit. The RSSI delay circuit is used to delay the RSSI-Trigger signal to obtain the RSSI-Trigger-Delay signal. The delay time of the RSSI delay circuit is less than the pulse width of the RSSI-Trigger-Delay signal. The digital logic circuit turns off the current limiting switch when it detects the rising edge of the RSSI-Trigger-Delay signal, and turns on the current limiting switch when it detects the rising edge of the RESET signal.

5. The pin reuse structure of an OLT device as described in claim 4, characterized in that: The current limiting circuit includes at least two current limiting diodes connected in series.

6. The pin reuse structure of an OLT device as described in claim 4, characterized in that: The digital logic circuit includes a RESET delay circuit, a signal compression circuit, an OR gate, and a D flip-flop; The input terminal of the RESET delay circuit and the D pin of the D flip-flop are connected to the first input terminal of the digital logic circuit. The input terminal of the signal compression circuit is connected to the second input terminal of the digital logic circuit. The output terminal of the RESET delay circuit and the output terminal of the signal compression circuit are respectively connected to the two input terminals of the OR gate. The output terminal of the OR gate is connected to the CLK pin of the D flip-flop. The Q pin of the D flip-flop is connected to the output terminal of the digital logic circuit. The first input terminal of the digital logic circuit is connected to the system RESET port to receive the RESET signal. The second input terminal of the digital logic circuit is connected to the output terminal of the RSSI delay circuit to receive the RSSI-Trigger-Delay signal. The output terminal of the digital logic circuit is connected to the control terminal of the current limiting switch. The output terminal of the digital logic circuit outputs the CK signal to control the switching of the current limiting switch. The RESET delay circuit is used to delay the RESET signal to obtain the RESET-Delay signal. The delay time of the RESET delay circuit is less than the pulse width of the RESET signal. The signal compression circuit is used to compress the RSSI-Trigger-Delay signal to obtain the RSSI-Trigger-Delay-Rise signal. The rising edge time of the RSSI-Trigger-Delay-Rise signal is the same as that of the RSSI-Trigger-Delay signal. The pulse width of the RSSI-Trigger-Delay-Rise signal is less than that of the RSSI-Trigger-Delay signal.

7. The pin reuse structure of an OLT device as described in claim 6, characterized in that: The signal compression circuit includes a signal delay circuit, an XOR gate, and a second AND gate. The input terminal of the signal delay circuit, the first input terminal of the XOR gate, and the first input terminal of the second AND gate are connected to the input terminal of the signal compression circuit. The output terminal of the signal delay circuit is connected to the second input terminal of the XOR gate, the output terminal of the XOR gate is connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the output terminal of the signal compression circuit. The signal delay circuit is used to delay the RSSI-Trigger-Delay signal, and the delay time of the signal delay circuit is less than the pulse width of the RSSI-Trigger-Delay signal.

8. The pin reuse structure of an OLT device as described in claim 1, characterized in that: The burst RSSI monitoring unit includes a first MOS transistor and a second MOS transistor. The drain and gate of the first MOS transistor and the gate of the second MOS transistor are connected to the input terminal of the burst RSSI monitoring unit. The source of the first MOS transistor and the source of the second MOS transistor are grounded. The drain of the second MOS transistor is connected to the output terminal of the RSSI monitoring unit.

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