Two-stage quantization digital reading circuit structure and detection system
By combining pixel-level and column-level ADC designs, and employing rail-to-rail amplifiers and capacitor multiplexing techniques, the problems of charge resolution and quantization speed in infrared focal plane detectors were solved, resulting in an infrared detector with high charge resolution and fast quantization.
Patent Information
- Application Number
- CN202511713629.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-02-13
AI Technical Summary
Traditional infrared focal plane detectors have low charge resolution and limited dynamic range. Two-step quantization schemes are not fast enough in high-speed applications, and matching coarse and fine quantization digital codes is difficult.
A combination of pixel-level first-order incremental sigma-delta ADC and column-level successive approximation SAR ADC is adopted. Through parallel-to-serial conversion circuit and low-voltage differential signal LVDS circuit, direct matching output of pixel-level coarse quantization and column-level fine quantization is achieved. Rail-to-rail amplifier and capacitor multiplexing technology are added to optimize quantization speed and accuracy.
It improves charge resolution, enhances dynamic range, and enables faster quantization speed and more direct digital code matching output.
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Figure CN121531245A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of infrared focal plane detector, and particularly relates to a two-stage quantization digitization readout circuit structure and a detection system. BACKGROUND
[0002] The infrared focal plane detection technology is widely applied in early warning detection, weather forecast, geothermal distribution, intelligence reconnaissance, earthquake and the like. The traditional digital pixel circuit generally adopts a digital integration technology, including a pulse frequency modulation (PFM) digital pixel, a first-order increment type sigma-delta modulator digital pixel structure and the like. Although the technology improves the charge processing capacity of the readout circuit, the charge resolution is not high due to the limitation of the minimum integration capacitor, which limits the dynamic range of the overall readout circuit.
[0003] The two-step quantization scheme of the prior art generates a residual voltage after coarse quantization, and then uses a source follower SF as a driving boost buffer stage, and then uses a column selection signal to complete fine quantization by a column ADC. However, in this mode, due to the mismatch between the quantization range of the column ADC and the residual voltage range, the high-bit digital code generated by coarse quantization cannot be directly combined with the low-bit digital code generated by fine quantization, and the overall quantization result still needs to be processed after output.
[0004] In addition, since the residual voltage range is generally significantly smaller than the range of the pixel-level voltage domain, in the case of high charge resolution requirement, the ADC used for fine quantization needs to be further improved in the number of effective bits to meet the loss of the number of effective bits caused by the overall amplification of the fine quantization digital code in the subsequent coarse and fine quantization digital code matching process, which increases the difficulty of ADC design.
[0005] In addition, in terms of speed, the ordinary two-step quantization scheme adopts a sequence working mode of coarse quantization first and then fine quantization, and the quantization time is the sum of the pixel-level coarse quantization time and the column-level fine quantization time. Compared with one-step quantization, this mode puts higher requirements on the quantization speed of the pixel level and the column level in the high-speed application environment, and cannot fully utilize the advantages of digital pixels in frame frequency. SUMMARY
[0006] The embodiment of the present application provides a two-stage quantization digitization readout circuit structure and a detection system, which realizes more direct coarse and fine quantization output digital code matching output and faster quantization speed under the premise of realizing high charge resolution.
[0007] The embodiment of the present application provides a two-stage quantization digitization readout circuit structure, which is applied to pixel-level readout of an infrared detector. The readout circuit structure includes a plurality of pixel columns, each pixel column includes a plurality of pixel units, each pixel unit contains a pixel-level ADC, and each pixel column corresponds to a column of switched capacitor amplifiers and a column-level ADC. Each column switch capacitor amplifier and column level ADC and pixel unit of each infrared detector are connected to a digital output control module, and each column switch capacitor amplifier and column level ADC are connected to a digital code register; The digital code register and the digital output control module are output through a plurality of parallel-serial conversion circuits and low-voltage differential signal (LVDS) circuits.
[0008] The embodiment of the present application also provides an infrared focal plane detection system comprising the two-stage quantization and digitization readout circuit structure as described above.
[0009] The embodiment of the present application adopts a timing design in which the pixel digitization and the column level digitization work simultaneously, and combines a first-order incremental sigma-delta ADC (IADC) integration capacitor and a common capacitor module in the column level switch capacitor amplifier, so that the residual voltage does not pass through the intermediate process of charge to voltage and then to charge in the fine quantization stage, the quantization precision is improved, and the column level digitization speed requirement is reduced. Under the premise of realizing high charge resolution, more direct coarse and fine quantization output digital code matching output and faster quantization speed are realized.
[0010] The above description is only a summary of the technical solutions of the present application. In order to enable the technical means of the present application to be more clearly understood, and to be implemented according to the content of the specification, and in order to enable the above and other purposes, features and advantages of the present application to be more apparent and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS
[0011] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not meant to limit the present application. Moreover, the same reference numerals in the attached drawings indicate the same or similar components. In the drawings: Figure 1 The overall framework of the two-stage quantization readout circuit and the main circuits at the pixel level and the column level of the embodiment of the present application are shown; Figure 2 The coarse and fine quantization timing of the two-stage quantization readout circuit of the embodiment of the present application is shown; Figure 3 The coarse quantization process timing control and the residual voltage generation process timing of the two-stage quantization readout circuit of the embodiment of the present application are shown; Figure 4 The timing control of the residual voltage transmission to the column level for fine quantization and the timing of the voltage change of the output node of the switch capacitor amplifier of the embodiment of the present application are shown; Figure 5 The row selection timing of the two-stage quantization readout circuit of the embodiment of the present application is shown; Figure 6Fig. 2 is a schematic diagram of a column selection timing sequence of a two-stage quantization readout circuit according to an embodiment of the present application; Figure 7 Fig. 3 is a schematic diagram of a data output timing sequence of a two-stage quantization readout circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0012] Exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.
[0013] The digital integration technology adopted by the existing digital pixel circuit includes pulse frequency modulation (PFM) digital pixel, first-order incremental sigma-delta modulator digital pixel structure, etc. Although these technologies improve the speed and charge processing capability of the readout circuit, they are limited by the pixel area and the minimum integration capacitor, and have the disadvantage of low charge resolution, which limits the accuracy and dynamic range of the overall readout circuit. The column-level digitization scheme adopts a column-parallel data processing mode, which cannot achieve high-speed processing at the same power consumption and quantization accuracy. Based on this, an embodiment of the present application provides a two-stage quantization digital readout circuit structure, which is applied to pixel-level readout of an infrared detector. The overall scheme of the present application includes three modules: a pixel-level first-order incremental sigma-delta modulator digital pixel structure, a rail-to-rail amplifier (rail-to-rail AMP) switched capacitor amplifier (SCA), and a column-level successive approximation (SAR) analog-to-digital converter, as well as subsequent storage circuit, parallel-to-serial conversion circuit, and low-voltage differential signal (LVDS) circuit. Specifically, as shown in Figure 1 The readout circuit structure includes a plurality of pixel columns, each pixel column includes a plurality of pixel units, each pixel unit contains a pixel-level ADC, and each pixel column corresponds to a column of switched capacitor amplifiers and a column-level ADC. In some embodiments, the pixel-level ADC adopts an m-bit first-order incremental sigma-delta structure, and oversampling and noise shaping are introduced in the first-order incremental sigma-delta structure, which can reduce the influence of capacitor noise and achieve small area implementation.
[0014] The column-level ADC adopts an n-bit successive approximation SAR ADC.
[0015] Each column of switched capacitor amplifiers and column-level ADCs and each pixel unit of the infrared detector are connected to a digital output control module, and each column of switched capacitor amplifiers and column-level ADCs are connected to a digital code register. The digital code register and the digital output control module are output through multiple sets of parallel-to-serial conversion circuits and low-voltage differential signal (LVDS) circuits.
[0016] In some embodiments, the parallel-to-serial conversion circuit is disposed after multiple sets of the column-level ADCs; The parallel-to-serial conversion circuit is used to merge the parallel results of multiple sets of pixel-level ADCs and the parallel output results of column-level ADCs, and convert them into serial outputs.
[0017] In some embodiments, such as Figure 1 As shown, the infrared detector includes C*R pixel units, C columns and R rows. The pixel-level ADC is used to complete the coarse quantization and reset of the signal within the pixel unit, the m-bit digital code result of the coarse quantization, and the remaining charge on the integrating capacitor. After pixel-level coarse quantization is completed, the remaining information is transmitted to the column switched-capacitor amplifier and column-level ADC to complete amplification and fine quantization processing.
[0018] In some embodiments, the column switched-capacitor amplifier and the column-level ADC include a capacitor-multiplexed switched-capacitor amplifier structure for transmitting the margin voltage to the SARADC for fine quantization operation after amplification.
[0019] The overall working flow of the two-stage quantization readout circuit in this application is as follows: Figure 2 As shown, the coarse quantization process and the fine quantization process adopt a ping-pong working state, that is, while performing pixel-level coarse quantization in the (i+1)th frame, column-level fine quantization is performed on the residual charge generated by the coarse quantization in the previous frame (the i-th frame).
[0020] In some embodiments, this application designs a capacitor-multiplexed switched-capacitor amplifier structure at the column level. After amplifying the margin voltage, it is transmitted to a SARADC for fine quantization. The column switched-capacitor amplifier and the column-level ADC specifically include: a comparator, an integrating capacitor C1, and an integrating capacitor C2; The comparator is connected to the margin voltage Vres, connected to the integrating capacitor C1 via switch S1, and connected to the integrating capacitor C2 via switch S2. During pixel-level quantization, the voltage change at the integration node is as follows: Figure 3 As shown, this application proposes a working mode in which the functions of the integrating capacitor and the storage capacitor are interchangeable to improve the overall quantization speed and anti-interference capability.
[0021] like Figure 3As shown, when a frame starts, the present example defines the i-th frame, after the start of the i-th frame of the infrared detector, according to the switch S1, the photocurrent is accumulated on the integration capacitor C1, at the end of each clock cycle CLK, the comparator compares the voltage at the integration node with the reference voltage. That is, the comparator is used to compare the charge accumulation result and the residual voltage Vres, in the case that the voltage of the integration result is less than the reference voltage, the comparator outputs 0, so that the column-level ADC does not work; in the case that the voltage of the integration result is greater than the residual voltage Vres, the comparator outputs an enable signal, so that the column-level ADC works, and a specified voltage value is subtracted from the voltage of the integration result to correspond to the charge decay after triggering.
[0022] During the operation of the entire comparator and DAC, the photocurrent continuously charges the integration capacitor, and the connected counter completes a count each time the comparator outputs a 1.
[0023] The pixel-level analog-to-digital converter adopts an m-bit first-order incremental sigma-delta ADC, and after 2m CLK_sd clock cycles, the pixel-level coarse quantization ends, and the pixel-level memory stores the counting result obtained by the counter, Figure 3 The intermediate signal FPsync is a pixel-level coarse quantization end control signal, and its period is equal to the frame period.
[0024] After the end of the i-th frame, according to the switches S1 and S2, the integration capacitor C1 is disconnected from the integration node and connected to the integration capacitor C2, so that in the quantization process of the i+1-th frame, the integration capacitor C2 participates in the operation of the pixel-level ADC as the integration capacitor, and in the quantization process of the i+1-th frame, the integration capacitor C1 participates in the column-level fine quantization process as the storage capacitor of the residual voltage Vres; The integration capacitor C1 and the integration capacitor C2 are alternately controlled to be connected, and so on.
[0025] In some embodiments, the column switched-capacitor amplifier and the column-level ADC further include an amplifier AMP, a switch S3, and a switch S4. One end of each of the switches S3 and S4 is connected to a reset voltage Vreset, and the other end is connected between the integration capacitor C1 and the comparator and between the integration capacitor C2 and the comparator. The other side of each of the integration capacitor C1 and the integration capacitor C2 is connected to a switch S10 through a switch S5 and a switch S6 respectively, and the switch S10 is connected to the amplifier AMP. In the pixel-level coarse quantization process, the generated residual voltage ranges from Vreset to VREF1, where VREF1 is the reference voltage of the comparator of the m-bit first-order incremental sigma-delta structure. In the case of column-level quantization, the residual voltage Vres∈[Vreset, VREF1], the residual voltage Vres is amplified by the amplifier AMP to realize rail-to-rail output, and the amplified residual voltage is finely quantized by the high-speed asynchronous SAR ADC.
[0026] The specific circuit and working timing of the storage capacitor accessing the column-level switched-capacitor amplifier are as shown in Figure 4 Figure 4 The change process of the upper plate voltage of the storage capacitor C1 as the residual charge and the output voltage of the switched-capacitor amplifier QUOTE is shown when the i+1th frame participates in the column-level fine quantization process.
[0027] In the i+1th frame, the upper plate of the residual voltage storage capacitor C1 is first disconnected from the integration node, and then the lower plate of C1 is switched from being connected to ground through a switch to being connected to the negative input terminal of the operational amplifier in the switched-capacitor amplifier through a switch.
[0028] As shown in Figure 4 , when the row selection signal arrives, the residual information of the row is finely quantized, the switch S10 is turned on, at this time the storage capacitor C1 is truly connected to the switched-capacitor amplifier module and works as a sampling capacitor.
[0029] In some embodiments, the other side of the integration capacitor C1 and the integration capacitor C2 is connected to ground through the switch S8 and the switch S9, respectively. The timing period of the switches S1, S6, and S8 is one frame period, that is, in the i frame, the switches S1, S6, and S8 are turned on; the working timing of the switches S2, S5, and S9 is opposite to that of the switches S1, S6, and S8.
[0030] When the row selection signal arrives, the switch S7 is first turned on, so that the operational amplifier forms a unit-gain buffer structure to complete the sampling stage. At this time, the charge of the negative input terminal VX node of the operational amplifier satisfies: Then S7 is turned off, and the operational amplifier is converted from the unit-gain working mode to the amplification mode. The switch S3 is turned on to connect the upper plate of the capacitor C1 to the reset voltage , and the amplification stage is completed, at this time the charge of the VX node satisfies: Due to the principle of charge conservation, , the above formula is obtained, that is: That is: By setting , and setting the size of C3, the op-amp AMP with rail-to-rail output can be realized, and the residual voltage can be amplified to full swing .
[0031] If the parasitic capacitance on the wire is considered, that is, the parasitic capacitance Cp is added in Figure 1 , the influence on the final amplification result is analyzed as follows: , repeat the above operation steps, and the following can be obtained: Let , the following can be obtained: During the charge transfer process, due to the virtual short effect of the op-amp, the parasitic capacitance of the wire basically has no effect on the amplification result.
[0032] The specific working timing and data output timing of the focal plane readout circuit of the embodiment of the present application are as follows: The circuit works under the control of the main clock MC and the frame synchronization signal FS. The period of the FS signal is a frame period. As Figure 5 shown, after the start of the ith frame, the row selection signal RSW<*> is generated by the row selection clock RSW_CLK, and under the control of the row selection signal, the residual charge temporarily stored in the last frame is finely quantized.
[0033] In some embodiments of the present application, the fine quantization of each row of pixel units of the infrared detector adopts a ping-pong working state to perform conversion and output corresponding to the conversion and output. The fine quantization of each row includes two steps: conversion and output. After the row selection signal RSW<0> arrives, the residual information of the 0th row is converted; after the row selection signal RSW<1> arrives, the conversion result of the residual information of the 0th row is output, and the residual information of the 1st row is converted; after the row selection signal RSW<2> arrives, the conversion result of the residual information of the 1st row is output, and the residual information of the 2nd row is converted; and so on.
[0034] When the Data_valid signal is high, it means that the quantization result is valid and can be output.
[0035] As Figure 6 shown, the column selection signal CSW<*> generated by the main clock MC is used to output the quantization result. The row selection signal RSW When the high level is high, the i-2th row coarse quantization result and the fine quantization result are output. Taking a pixel array scale of 640*512 as an example, in view of data output efficiency, four groups of parallel serial conversion (PISO) modules and low voltage differential output (LVDS) modules are adopted, and the quantization results of four pixels are output at the same time.
[0036] Specifically, when the RSW When the high level is present, the coarse quantization result in the i-2th row of pixels is output from the in-pixel memory to the column-level memory, wherein the in-pixel memory is m bits and the column-level memory is m+n bits.
[0037] When the column selection signal CSW When the high level is high, the column-level memory outputs (in parallel) of the i-th column to the i+3-th column of the selected row are connected to the inputs (in parallel) of four groups of PISO modules, and m+n bits of parallel data are converted into serial data, and after the parallel-to-serial conversion is completed, the serial data is output through LVDS.
[0038] As shown in Figure 7 DOP <m-1, 0> is a high m-bit parallel digital code obtained through coarse quantization, and DOC <n-1, 0> is a low n-bit parallel digital code obtained through fine quantization, in order to ensure the stability of the data, a half main clock period delay output is adopted, and when the VLOAD signal is high, the first serial output data is output on the rising edge of the high-speed clock CLKS, and the output order of the m+n bits of data is from low to high.
[0039] Finally, the infrared detector readout circuit outputs in the form of LVDS, and high-speed data readout is realized.
[0040] The circuit structure of the present application uses two steps of pixel-level coarse quantization and column-level fine quantization to complete digitization, and a rail-to-rail amplification switched-capacitor amplifier is added before column-level fine quantization, which is matched with capacitor multiplexing and timing control to realize direct matching output of two-step quantization digital codes.
[0041] The present application also provides an infrared focal plane detection system, which comprises the two-step quantization and digitization readout circuit structure as described above.
[0042] It should be noted that in the embodiments of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprises a…" does not exclude the presence of another identical element in the process, method, article or device comprising the element.
[0043] The serial numbers of the above embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.
[0044] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative but not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.
Claims
1. A two-stage quantization digital readout circuit structure, characterized in that, Pixel-level readout applied to infrared detectors, the readout circuit structure includes multiple sets of pixel columns, each set of pixel columns includes multiple pixel units, each pixel unit contains a pixel-level ADC, and each set of pixel columns corresponds to a column switched capacitor amplifier and a column-level ADC. Each column of switched-capacitor amplifiers and column-level ADCs, as well as the pixel units of each infrared detector, are connected to the digital output control module, and each column of switched-capacitor amplifiers and column-level ADCs are connected to the digital code register. The digital code register and the digital output control module are output through multiple sets of parallel-to-serial conversion circuits and low-voltage differential signal (LVDS) circuits.
2. The two-stage quantization digitization readout circuit structure as described in claim 1, characterized in that, The pixel-level ADC adopts an m-bit first-order incremental sigma-delta structure, and introduces oversampling and noise shaping into the first-order incremental sigma-delta structure. The column-level ADC uses an n-bit successive approximation SAR ADC.
3. The two-stage quantization digitization readout circuit structure as described in claim 1, characterized in that, The parallel-to-serial conversion circuit is disposed after multiple sets of the column-level ADCs; The parallel-to-serial conversion circuit is used to merge the parallel results of multiple sets of pixel-level ADCs and the parallel output results of column-level ADCs, and convert them into serial outputs.
4. The two-stage quantization digitization readout circuit structure as described in claim 2, characterized in that, The infrared detector includes C*R pixel units, C columns and R rows. The pixel-level ADC is used to complete coarse quantization and reset of the signal within the pixel unit, the m-bit digital code result of the coarse quantization, and the remaining charge on the integrating capacitor. After pixel-level coarse quantization is completed, the remaining information is transmitted to the column switched-capacitor amplifier and column-level ADC to complete amplification and fine quantization processing.
5. The two-stage quantization digital readout circuit structure as described in claim 4, characterized in that, The column-level switched-capacitor amplifier and column-level ADC include a capacitor-multiplexed switched-capacitor amplifier structure, which is used to amplify the margin voltage and then transmit it to the SARADC for fine quantization.
6. The two-stage quantization digital readout circuit structure as described in claim 4, characterized in that, The column-switched capacitor amplifier and column-level ADC specifically include: a comparator, an integrating capacitor C1, and an integrating capacitor C2; The comparator is connected to the margin voltage Vres, connected to the integrating capacitor C1 via switch S1, and connected to the integrating capacitor C2 via switch S2. After the start of the i-th frame of the infrared detector, the photocurrent is charged on the integrating capacitor C1 according to the switch S1. The comparator is used to compare the charge accumulation result with the margin voltage Vres. If the voltage of the integration result is less than the reference voltage, the comparator outputs 0, so that the column-level ADC does not work; if the voltage of the integration result is greater than the margin voltage Vres, the comparator outputs an enable signal, so that the column-level ADC works, and a specified voltage value is subtracted from the voltage of the integration result to correspond to the charge decay after triggering. After the i-th frame ends, according to the switches S1 and S2, the integrating capacitor C1 is disconnected from the integrating node and the integrating capacitor C2 is connected. In the quantization process of the i+1-th frame, the integrating capacitor C2 participates in the pixel-level ADC operation as an integrating capacitor, and in the quantization process of the i+1-th frame, the integrating capacitor C1 participates in the column-level fine quantization process as a storage capacitor for the margin voltage Vres. The connection of integrating capacitor C1 and integrating capacitor C2 is alternately controlled.
7. The two-stage quantization digital readout circuit structure as described in claim 6, characterized in that, The column switched capacitor amplifier and column-level ADC specifically include: rail-to-rail operational amplifier AMP, switch S3, and switch S4; One end of each of the switches S3 and S4 is connected to the reset voltage Vreset, and the other end is connected between the integrating capacitor C1 and the comparator, and between the integrating capacitor C2 and the comparator. The other sides of the integrating capacitors C1 and C2 are connected to switch S10 via switches S5 and S6, respectively. Switch S10 is connected to the rail-to-rail operational amplifier AMP. During pixel-level coarse quantization, the resulting margin voltage range is [Vreset, VREF1], where VREF1 is the comparator reference voltage of an m-bit first-order incremental sigma-delta structure. In the case of column-level quantization, the margin voltage Vres∈[Vreset,VREF1] is amplified and output as rail-to-rail by the rail-to-rail operational amplifier AMP. The amplified margin voltage is then finely quantized by a high-speed asynchronous SAR ADC.
8. The two-stage quantization digital readout circuit structure as described in claim 7, characterized in that, The other sides of the integrating capacitors C1 and C2 are grounded through switches S8 and S9, respectively. The timing period of switches S1, S6, and S8 is one frame period, that is, in the i-th frame, switches S1, S6, and S8 are turned on; the working timing of switches S2, S5, and S9 is opposite to the timing period of switches S1, S6, and S8.
9. The two-stage quantization digital readout circuit structure as described in claim 8, characterized in that, The pixel units of the infrared detector are finely quantized in each row using a ping-pong working state to perform corresponding conversion and output.
10. An infrared focal plane array detection system, characterized in that, Includes the two-stage quantization digital readout circuit structure as described in any one of claims 1-9.