Peripheral device power gating system and method

Abstract

The embodiment of the invention relates to a peripheral device power gating system and method. Various techniques are provided for managing power modes (e.g., also referred to as power states) in a peripheral device connected to a host device. In one example, a method includes receiving, by an intermediary device communicatively connected between a host device and a peripheral device, a notification that the host device will transition from a high power mode to a reduced power mode. The method also includes receiving, by the intermediary device from the peripheral device, context data associated with an operational state of the peripheral device. The method also includes storing, by the intermediary device, the context data and power gating, by the intermediary device, the peripheral device while the host device remains at least partially on in the reduced power mode. Additional embodiments are also provided that use the stored context data to restore the operating state of the peripheral device. Additional systems, apparatuses, and methods are also provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to power conservation for electronic devices, and more particularly to techniques for managing power modes in such devices. BACKGROUND

[0002] Power conservation is an important consideration in electronic devices. This is particularly true for mobile computing devices such as laptops, smartphones, and other devices. For example, certain techniques have been developed to permit devices to enter and exit various low power modes (e.g., also referred to as reduced power modes) under appropriate conditions.

[0003] In many cases, peripheral devices connected to host devices can only achieve limited power conservation. For example, a peripheral device can be connected to a host device through an interface that limits the low power modes in which the peripheral device can operate while the host device is at least partially on. For example, in some cases, if a host device transitions from a high power mode to a reduced power mode, a connected peripheral device can also need to transition to the same reduced power mode.

[0004] However, even when the host device is in a reduced power mode, the requirements of the interface can require the peripheral device to remain in a minimum power mode (e.g., not fully off, also referred to as power-gated), and thus continue to draw significant power from the host device. For example, the peripheral device can need to remain powered on enough to maintain the state of its local volatile memory (e.g., registers) to preserve context data to maintain its operational state for later use when the host device (and thus the peripheral device) transitions back to a high power mode.

[0005] Unfortunately, these limitations can result in the peripheral device continuing to draw significant power (e.g., about 50 mW for some peripheral devices) from the host device even when the host device is in a low power mode and the peripheral device is not in use. This is particularly problematic for peripheral devices that are continuously or permanently connected to the host device (e.g., peripheral devices provided as part of an accessory device integrated into the host device). Thus, conventional power management techniques can not fully achieve efficient power conservation in many implementations. SUMMARY

[0006] Various techniques are provided for managing power modes (e.g., also referred to as power states) of a peripheral device connected to a host device. In one embodiment, a method includes receiving, by an intermediary device communicatively connected between a host device and a peripheral device, a notification that the host device is to transition from a high power mode to a reduced power mode. The method also includes receiving, by the intermediary device from the peripheral device, context data associated with an operating state of the peripheral device. The method also includes storing, by the intermediary device, the context data. The method also includes power gating, by the intermediary device, the peripheral device while the host device remains at least partially on in the reduced power mode.

[0007] In another embodiment, a system includes an intermediary device communicatively connected between a host device and a peripheral device. The intermediary device is configured to receive a notification that the host device is to transition from a high power mode to a reduced power mode. The intermediary device is configured to receive, from the peripheral device, context data associated with an operating state of the peripheral device. The intermediary device is configured to store the context data. The intermediary device is configured to power gate the peripheral device while the host device remains at least partially on in the reduced power mode. Other embodiments are also disclosed. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of a programmable logic device (PLD) is illustrated in accordance with an embodiment of the present disclosure.

[0009] Figure 2 A system including a host device connected to a peripheral device through an intermediary device is illustrated in accordance with an embodiment of the present disclosure.

[0010] Figure 3 A circuit diagram of a transceiver of an intermediary device is illustrated in accordance with an embodiment of the present disclosure.

[0011] Figure 4 A timing diagram associated with transitioning a peripheral device from a powered on mode to a power gated mode in response to a reduced power mode initiated by a host device is illustrated in accordance with an embodiment of the present disclosure.

[0012] Figure 5 A process of transitioning a peripheral device from a powered on mode to a power gated mode in response to a reduced power mode initiated by a host device is illustrated in accordance with an embodiment of the present disclosure.

[0013] Figure 6 A timing diagram of transitioning a peripheral device from a power gated mode to a powered on mode in response to a high power mode initiated by a host device is illustrated in accordance with an embodiment of the present disclosure.

[0014] Figure 7FIG. 1 illustrates a process of transitioning a peripheral device from a power-gated mode to a powered-on mode in response to a high-power mode initiated by a host device or the peripheral device itself, according to an embodiment of the disclosure.

[0015] Embodiments of the disclosure, along with its advantages, can be best understood by reference to the following detailed description. It is to be understood that the same reference numerals can be used throughout the several figures and can refer to the same or similar elements. DETAILED DESCRIPTION

[0016] According to various embodiments disclosed herein, techniques are provided for managing power modes (e.g., also referred to as power states) in a peripheral device connected to a host device. In some embodiments, the host device can be connected to the peripheral device through an intermediary device that controls the power modes of the peripheral device. For example, the intermediary device can be an always-on intermediary device (e.g., or can include an always-on portion thereof, also referred to as an always-on island of the peripheral device), and is connected to a downstream peripheral device through a communication interface (e.g., a USB interface or other interface). The host device, the intermediary device, and / or the peripheral device can selectively operate in a plurality of different power modes.

[0017] The intermediary device can manage the operation of the peripheral device to cause the peripheral device to selectively operate in a power-gated mode, which otherwise would not be permitted by the host device. For example, in some embodiments, the host device can enter a reduced power mode (e.g., one or more components of the host device operate at a lower power level, but are not completely shut down). In a conventional system, a connected peripheral device can need to operate in a minimum power mode, such as a reduced power mode corresponding to the power mode of the host device, but not completely shut down (e.g., power-gated) so that the peripheral device retains its current state of operation.

[0018] In contrast, according to various techniques of the disclosure, the intermediary device can control the power mode of the peripheral device independent of the power mode of the host device, thereby significantly improving energy saving effects. For example, upon receiving (e.g., detecting) a notification that the host device is entering a reduced power mode, the intermediary device can store context data of the peripheral device, and power down (e.g., power-gate) the peripheral device while the intermediary device (or a portion thereof) remains powered on.

[0019] In various embodiments, the intermediary device (or the always-on portion thereof) can be implemented as a thin, low-power device that draws less power when on than the peripheral device draws in the reduced power mode of the host device. Thus, even with the addition of the intermediary device and its associated always-on power consumption, the total power consumption of the combination of the intermediary device and the peripheral device (when the host device is in the reduced power mode) will be less than without the intermediary device (e.g., the peripheral device remains at the lowest power level, such as a suspended state).

[0020] In some embodiments, the intermediary device and / or the peripheral device can be implemented by programmable logic devices (PLDs). For example, in some embodiments, the intermediary device can be implemented by a PLD with reduced power draw, such as an iCE 40 PLD, while the peripheral device can be implemented by a PLD with increased power draw, such as an NX33 PLD, both of which are available from Lattice Semiconductor Corporation of Hillsboro, Oregon.

[0021] For example, Figure 1 A block diagram illustrating an example PLD 100 that can be used to implement the intermediary device and / or the peripheral device according to embodiments of the present disclosure is shown. For example, the PLD 100 can be implemented with more or less of the various components discussed herein to implement either device as desired.

[0022] The PLD 100 (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on chip (FPSC), or other type of programmable device) generally includes various physical hardware components, such as I / O (I / O) blocks 102, logic blocks 104 (e.g., also referred to as programmable logic blocks (PLBs), programmable function units (PFUs), or programmable logic cells (PLCs)), and other components as discussed above.

[0023] The I / O blocks 102 provide I / O functionality for the PLD 100 (e.g., to support one or more I / O and / or memory interface standards), while the logic blocks 104 provide logic functionality for the PLD 100 (e.g., look-up table (LUT) logic or logic gate array-based logic). Serializer / deserializer (SERDES) blocks 150 and physical coding sublayer (PCS) blocks 152 can provide additional I / O functionality. In various embodiments, the I / O blocks 102 and the SERDES blocks 150 can route signals to or from associated external ports (e.g., physical pins) of the PLD 100. The PLD 100 can also include hard intellectual property core (IP) blocks 160 to provide additional functionality (e.g., basic predetermined functionality provided in hardware that can be configured with less programming than the logic blocks 104).

[0024] The PLD 100 can also include, as desired, memory blocks 106 (e.g., EEPROM memory blocks, RAM (e.g., static and / or dynamic) memory blocks, and / or flash memory blocks), clock-related circuitry 108 (e.g., clock sources, PLL circuitry, and / or DLL circuitry), and / or various routing resources 180 (e.g., interconnects and appropriate switching logic to provide paths for routing signals, such as clock signals, data signals, or other signals, throughout the PLD 100), as appropriate. In various embodiments, the routing resources 180 can include user-configurable routing resources and hardwired signal paths. In general, those skilled in the art will appreciate that various physical hardware components of the PLD 100 can be used to perform its intended functions for a desired application.

[0025] For example, the I / O modules 102 can be used to program the PLD 100, such as memory modules 106 (e.g., including volatile configuration memory), or transfer information (e.g., various types of data and / or control signals) to / from the PLD 100 through various external ports as understood by those skilled in the art. The I / O modules 102 can provide first programming ports (which can represent central processing unit (CPU) ports, peripheral data ports, SPI interfaces, and / or sysCONFIG programming ports) and / or second programming ports, such as Joint Test Action Group (JTAG) ports (e.g., by employing Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards). For example, the I / O blocks 102 can generally be included to receive configuration data and commands to configure the PLD 100 to its intended use and support serial or parallel device configuration and information transfer with the SERDES blocks 150, the PCS blocks 152, the hard IP blocks 160, and / or the logic blocks 104, as appropriate.

[0026] For example, in some embodiments, any of the various components discussed herein can be configured in response to a configuration engine 110 (e.g., implemented by appropriate logic, such as one or more processors, finite state machines, and / or other hardware and / or software) passing configuration data through the routing resources 180. In some embodiments, the configuration data can be stored locally on the PLD 100, e.g., in one or more memory blocks 106, and / or stored externally to the PLD 100, e.g., in the memory 134 of the external system 130.

[0027] It will be appreciated that the number and location of the various components are not limited and can depend on the desired application. For example, various components can not be necessary for a desired application or design specification (e.g., for a selected programmable device type).

[0028] Furthermore, it should be appreciated that the components are illustrated in block diagram form to emphasize functionality and that, typically, various components are distributed throughout the PLD 100, such as within and between logic blocks 104, hard IP blocks 160, and routing resources 180, to perform their conventional functions (e.g., to store configuration data used to configure the PLD 100 or to provide an interconnection structure within the PLD 100). It should also be appreciated that the various embodiments disclosed herein are not limited to programmable logic devices such as the PLD 100 and can be applied to various other types of programmable devices, as will be appreciated by those skilled in the art.

[0029] Figure 2 A host device 200 is illustrated that connects to a peripheral device 250 through an intermediary device 210, collectively providing a system 201, in accordance with embodiments of the present disclosure. In some embodiments, the host device 200, the intermediary device 210, and the peripheral device 250 are each capable of operating in a variety of different power modes. These power modes can include, for example: a high power mode in which the device operates at full power or near full power (e.g., a D0 power state); a reduced power mode in which the device operates at a lower power level than the high power mode (e.g., Dl, D2, or D3 power states and / or a suspend mode); and a powered down mode in which the device is completely shut down (e.g., power gated). While three power modes are identified herein for ease of discussion, other power modes are also contemplated.

[0030] While the system 201 is illustrated in a generalized manner herein for ease of discussion, the illustrated features can be used to implement various types of systems. In some embodiments, the intermediary device 210 and / or the peripheral device 250 can be integrated into the host device 200 to provide the system 201 within the host device 200 itself. For example, in some embodiments, the host device 200 can be a computer system such as a notebook computer system, a mobile phone, and / or other appropriate type of device, the intermediary device 210 can be integrated into the host device 200, and the peripheral device 250 can be part of an accessory device 260 that is also integrated into the host device 200.

[0031] Continuing the example, the peripheral device 250 can be part of (and / or provide support processing for) an accessory device 260 such as a camera (e.g., a computer vision chip used to detect human presence, perform facial recognition, and / or perform other operations by the host device 200), a Wi-Fi TMchip and / or other types of accessory devices that are opened and closed through the peripheral device 250. In the case of a camera, the accessory device 260 can include various components, such as an imaging device 269 that is used to capture images of the environment of the host device 200, one or more processors 261 that can be configured to execute instructions, such as software instructions for detecting human presence, performing facial recognition, and the like, that are provided in one or more memories 262 and / or stored in non-transitory form in one or more non-transitory machine-readable media 264 (e.g., a memory or other suitable storage medium internal or external to the system 201). The accessory device 260 can also include one or more input / output ports 266 and one or more other components 268 for implementing additional features, as appropriate. Other embodiments of the accessory device 260 are also contemplated.

[0032] In some embodiments, the host device 200, the intermediate device 210, and the peripheral device 250 can be connected by and communicate through a Universal Serial Bus (USB) interface. In this regard, while USB 2 will be primarily discussed and illustrated herein, the operations discussed herein can be applied to other types of USB interfaces (e.g., USB 1.x, 2.x, 3.x, 4.x, and / or other variants), Thunderbolt TM interfaces (e.g., Thunderbolt TM 1.x, 2.x, 3.x, 4.x, 5.x, and / or other variants), and / or other types of interfaces.

[0033] As shown, the host device 200 includes various components 290 (e.g., implemented together as a system on a chip (SoC), one or more discrete components, and the like), for example, including one or more processors 291 that can be configured to execute instructions (such as software instructions) that are provided in one or more memories 292 and / or stored in non-transitory form in one or more non-transitory machine-readable media 294 (e.g., a memory or other suitable storage medium internal or external to the system 201). The host device 200 also includes one or more input / output ports 296 and one or more other components 298 for implementing additional features, as appropriate.

[0034] Intermediate device 210 is connected to host device 200 (e.g., to input / output port 296) on bus 270 (e.g., a USB bus in some embodiments). Peripheral device 250 is connected to intermediate device 210 (e.g., operating as a proxy or digital interface with about 5 wires providing pass-through functionality for USB communications in some embodiments) on bus 282. Thus, in some embodiments, peripheral device 250 does not directly communicate with components 290 of host device 200, but rather communicates through intermediate device 210 (e.g., intermediate device 210 passes USB communications between bus 270 and 282, between components 290 and peripheral device 250).

[0035] As shown, intermediate device 210 and peripheral device 250 are also connected through additional bus 280. In some embodiments, bus 280 can be a single wire aggregation (SWA) bus, providing serial communications on a single wire. In some embodiments, bus 280 can be used to pass context data and / or perform additional communications discussed herein between peripheral device 250 and intermediate device 210.

[0036] As discussed, intermediate device 210 and / or peripheral device 250 can be implemented by one or more appropriate PLDs configured to implement various components and perform various operations discussed herein (e.g., by appropriate logic blocks 140 and / or other components of the PLDs).

[0037] As shown, intermediate device 210 includes finite state machine (FSM) 212, registers 214, transceiver 216, hold logic 218, SWA bus interface 220, and power control block 222.

[0038] FSM 212 (e.g., implemented by configured logic blocks 140) operates to manage storage of context data received from registers 254 of peripheral device 250 into registers 214 of intermediate device prior to power down (e.g., power gating) of peripheral device 250. For example, such context data can identify current operations of peripheral device 250 prior to power down (e.g., USB connection state, USB enumeration state, USB device address, previous USB enumeration configuration, FSM state, flags, and / or other context data associated with peripheral device 250) so that peripheral device 250 can be restored to an operational state after power down and re-powered by restoring the context data to registers 254.

[0039] FSM 212 also operates to manage reading (e.g., read back) of context data from registers 214 of intermediate device 210, and passing the context data back to peripheral device 250 after peripheral device 250 is powered on (e.g., restoring peripheral device 250 from a power down mode to a higher power mode).

[0040] Register 214 (e.g., implemented by memory block 106) stores context data received from register 254, as discussed.

[0041] Transceiver 216 (e.g., implemented by configured logic block 140 and / or I / O block 102) provides a communication interface (e.g., a USB interface, in some embodiments) to manage communications over bus 270 between intermediate device 210 and one or more components 290. Additional characteristics of transceiver 216 will be discussed in relation to Figure 3 Further discussion.

[0042] Hold logic 218 (e.g., implemented by configured logic block 140) operates to generate communications (e.g., USB NAK packets, in some embodiments) for communication with components 290 of host device 200 to temporarily interrupt (e.g., hold or stall) communications (e.g., USB communications) from host device 200 to peripheral device 250 (e.g., through intermediate device 210) when peripheral device 250 is re-powered after being power gated as discussed herein.

[0043] SWA interface 220 (e.g., implemented by configured logic block 140 and / or I / O block 102) manages context data communications and / or other communications (e.g., serial communications over a single wire) between intermediate device 210 and peripheral device 250.

[0044] Power control block 222 (e.g., implemented by configured logic block 140) operates to selectively turn on and off peripheral device 250 (e.g., through appropriate control signals communicated on SWA bus 280).

[0045] As shown, peripheral device 250 includes controller 252, register 254, processing block 256 running firmware 258, SWA bus interface 259, and fabric 263.

[0046] Processing block 256 (e.g., implemented by configured logic block 140) operates to manage reading context data from register 254 of peripheral device 250 and communicating the context data to intermediate device 210 prior to power down of peripheral device 250.

[0047] Processing block 256 also operates to manage receiving (e.g., reading back) context data from register 214 of intermediate device 210 and storing (e.g., restoring) the context data into register 254 of peripheral device 250 after peripheral device 250 is powered on (e.g., recovering peripheral device 250 from a power gated mode to a higher power mode).

[0048] The registers 254 (e.g., implemented by the memory block 106) store context data, as discussed.

[0049] The controller 252 (e.g., implemented by the configured logic block 140) operates to manage communications (e.g., USB communications) over the bus 282 between the peripheral device 250 and the intermediate device 210.

[0050] The SWA interface 259 (e.g., implemented by the configured logic block 140 and / or the I / O block 102) manages context data communications and / or other communications between the peripheral device 250 and the intermediate device 210.

[0051] The fabric 263 (e.g., implemented by the configured logic block 140 and / or the routing resources 180) operates to provide interconnections between various components of the peripheral device 250.

[0052] Figure 3 A circuit diagram of the transceiver 216 of the intermediate device 210 is illustrated, in accordance with embodiments of the present disclosure. As shown, the transceiver 216 is connected to the bus 270 (e.g., a USB bus, in this embodiment), as previously discussed. The transceiver 216 includes circuitry 300 that operates to receive analog communication signals received from the components 290 of the host device 200 on the bus 270 and convert them to corresponding digital communication signals transmitted (e.g., passed) to the peripheral device 250 on the bus 282. The circuitry 300 also operates to receive digital communication signals received from the peripheral device 250 on the bus 282 and convert them to corresponding analog communication signals transmitted (e.g., passed) to the components 290 of the host device 200 on the bus 270. Thus, the transceiver 216 can operate to route communications (e.g., USB communications) between the host device 200 and the peripheral device 250 through the intermediate device 210.

[0053] The transceiver 216 also includes a detection module 310 that can detect a notification received from the host device 200 on the bus 270, such as a communication (e.g., a USB wake-up data packet) that identifies that the host device 200 is transitioning (e.g., expected to transition) from a reduced power mode to a high power mode (e.g., wake-up). For example, the detection module 310 can provide a detected such communication to the FSM 212 and / or the retention logic 218 to trigger (e.g., through the power control block 222) the intermediate device 210 to begin powering on (e.g., restoring) the peripheral device 250 from a powered down mode.

[0054] In response, the hold logic 218 can generate a communication (e.g., a USB NAK packet in some embodiments) to temporarily interrupt communications (e.g., USB communications) from the host device 200 to the peripheral device 250, for example, at least while the intermediate device 210 is preparing to power gate the peripheral device 250, and continuing, for example, at least until the peripheral device 250 is restored to its operational state after being power gated. In this regard, the transceiver 216 further includes a response module 320 configured to transmit the generated interrupt communication to the host device 200 on the bus 270.

[0055] Operation of the host device 200, the intermediate device 210, and the peripheral device 250 will be described with respect to Figures 4-7 further discussion. Figure 4 A timing diagram 400 is illustrated and Figure 5 An associated process 500 is illustrated that identifies various operations associated with transitioning a peripheral device 250 from a powered on mode to a power gated mode in response to a reduced power mode initiated by a host device 200, in accordance with embodiments of the present disclosure.

[0056] In Figure 4 various diagrams 402-416 are illustrated that identify operational states of various devices, as well as associated signals and conditions.

[0057] FIG. 402 identifies power modes of the host device 200. As shown, the host device 200 transitions between a high power mode (e.g., S0) and a reduced power mode (e.g., Modern Connection Standby (MCS)).

[0058] FIG. 404 identifies power modes that the host device 200 intends for devices connected to the bus 270 to operate in. As shown, the host device 200 can instruct a connected device (e.g., the intermediate device 210) to transition between a high power mode (e.g., D0) and a reduced power mode (e.g., D2).

[0059] FIG. 406 identifies states of the bus 270. As shown, the bus 270 can transition between a high power mode (e.g., a connected state) in which communications are maintained and a reduced power mode (e.g., a selectively suspended state) in which communications are interrupted. For example, in embodiments in which the bus 270 is implemented as a USB bus, the host device 200 can cause the bus 270 to transition to the selectively suspended state if the host device 200 does not receive any communications on the bus 270 for a period of time (e.g., 3 milliseconds in some embodiments). Also as shown, the bus 270 can also transition to a reduced power mode (e.g., from a USB U3 suspended power mode to a USB D2 power mode).

[0060] Figure 408 identifies power modes of the peripheral device 250. As shown, the peripheral device 250 transitions between a high power mode and a power-gated (e.g., power-gated) mode. As part of this transition, context data from the registers 254 of the peripheral device 250 is stored in the registers 214 of the intermediary device 210, as discussed.

[0061] Also as shown, the peripheral device 250 can be periodically powered up from the power-gated power mode back to the high power mode for a temporary period of time and then return to the power-gated power mode. These temporary and periodic transitions can be performed (e.g., controlled by the power control block 222 of the intermediary device 210) to permit the peripheral device 250 to operate intermittently while the host device 200 is in the reduced power mode. In some embodiments, as part of these temporary and periodic transitions, context data is not restored to the registers 254.

[0062] For example, in some embodiments, the peripheral device 250 can be part of an accessory device 260 that can be used to periodically operate even while the host device 200 is in the reduced power mode. For example, the accessory device 260 can be a camera that is used to detect the presence of a human, perform facial recognition, and / or to wake up the host device 200 and transition the host device 200 from the reduced power mode back to the high power mode in response to operation of the peripheral device 250 and / or the accessory device 260 while temporarily powered up (e.g., in response to the imaging device 269 of the accessory device 260 detecting a user of the host device 200). In some embodiments, such periodic transitions can be performed at a rate of once per second (e.g., providing a frame rate of one image captured per second from the imaging device 269).

[0063] Figure 410 identifies power modes of the intermediary device 210. As shown, the intermediary device 210 transitions between a high power mode and a power-gated mode. In some embodiments, the intermediary device 210 continues to operate at high power while in the power-gated mode. In some embodiments, certain portions of the intermediary device 210 can operate in a reduced power mode during the power-gated mode, while other portions of the intermediary device 210 can operate at high power (e.g., the power control block 222) to control the power-gating of the peripheral device 250.

[0064] Figure 412 identifies a case where an image is captured by the imaging device 269 of the accessory device 260 during the temporary and periodic transitions at times 480 and 490 discussed with respect to Figure 408.

[0065] Figure 414 identifies a notification (e.g., a USB data packet) generated by the host device 200 and provided on the bus 270 to the intermediate device 210 to identify that the host device 200 is preparing to perform the power transition shown in Figure 402.

[0066] Figure 416 identifies signals received by the components 290 of the host device 200. In some embodiments, the signals of Figure 416 can trigger the host device 200 to perform the power transition shown in Figure 402. For example, in some embodiments where the host device 200 is a notebook computer, the signals of Figure 414 can transition at time 455 in response to the host device 200 entering a sleep mode and / or other events that can trigger the host device 200 to enter a reduced power mode. For example, in some embodiments, the transition shown at time 455 in Figure 416 can occur before the transition shown at time 440 in Figure 414, and can be the trigger that causes the host device 200 to generate the signals shown in Figure 414.

[0067] Timing diagram 400 will now be further described in conjunction with Figure 5 Figure 402, 406, 408, and 410.

[0068] At time 430, the host device 200 transitions the bus 270 to a reduced power mode, as discussed and shown in Figure 406. At time 440, the host device 200 notifies (e.g., signals) the intermediate device 210 that the host device 200 is preparing to transition from the high power mode to the reduced power mode, as shown in Figure 414.

[0069] During time period 450, the intermediate device 210 and the peripheral device 250 perform a process to power gate the peripheral device 250. As discussed above in Figure 5 As shown, the intermediate device 210 and the peripheral device 250 perform various operations during time period 450. In some embodiments, time period 450 constitutes a relatively short period of time (e.g., about 100 milliseconds in some embodiments) between time 440 (e.g., at which the host device 200 signals that a transition to a lower power level is anticipated) and time 460 (e.g., at which the host device 200 commands connected devices to transition to a lower power level). Thus, in some embodiments, the intermediate device 210 and the peripheral device 250 can quickly perform their various operations during time period 450 to permit the peripheral device 250 to be power gated before time 460.

[0070] For example, in block 452, the peripheral device 250 reads the context data from the register 254 (e.g., in response to a control signal provided from the FSM 212 to the processing block 256 on the bus 280) and passes the context data to the intermediate device 210 on the bus 280. In block 454, the intermediate device 210 stores the context data into the register 214.

[0071] In block 456, the intermediate device 210 isolates the peripheral device 250 from communication with the host device 200 by disabling the bus 282. For example, in some embodiments, the hold logic 218 and the transceiver 216 can operate to provide a USB NAK packet from the intermediate device 210 to the host device 200 on the bus 270, thereby interrupting communication between the host device 200 and the peripheral device 250 on the bus 282. Thus, the peripheral device 250 can safely power gate without missing communications from the host device 200.

[0072] In block 458, the intermediate device 210 powers down the peripheral device 250, while the intermediate device 210 (or at least a portion thereof, as discussed above) remains powered on, and while the host device 200 also remains in its reduced power mode. Thus, the peripheral device 250 can be completely powered down for energy conservation, even though the host device 200 remains at least partially powered on in the reduced power mode.

[0073] At time 460, the host device 200 commands the connected device (e.g., the intermediate device 210) to transition to a reduced power mode, as shown in FIG. 404. At time 470, the host device 200 transitions to its reduced power mode, as shown in FIG. 402.

[0074] At times 480 and 490, the intermediate device 210 (e.g., through the power control block 222) periodically powers on and powers down the peripheral device 250 to perform various operations, while the host device 200 remains in the reduced power mode, as discussed.

[0075] Figure 6 FIGURE illustrates a timing diagram 600 and Figure 7 FIGURE illustrates an associated process 700 that identifies various operations associated with transitioning the peripheral device 250 from a power gated mode to a powered on mode in response to a high power mode being initiated by the host device 200 or the peripheral device 250 itself, in accordance with embodiments of the present disclosure.

[0076] In Figure 6 various figures 602-616, which are Figure 4 continuations of the corresponding figures 402-416 illustrated in FIGURE 400. Thus, the time period 610 of the timing diagram 600 corresponds to the time period Figure 4 of the timing diagram 400.

[0077] Timing diagram 600 will now be further described in connection with Figure 7 process 700. During time period 610, host device 200 and bus 270 are both operating in a reduced power mode, intermediate device 210 (e.g., or a portion thereof) is operating in a high power mode, and peripheral device 250 is power gated and periodically turned on (e.g., at times 480 and 490), as previously discussed in connection with Figure 4 and Figure 5 .

[0078] In some embodiments, peripheral device 250 can be transitioned to a high power mode and have its context data restored in response to various triggering conditions. In one embodiment, the transition can be triggered at time 620 when peripheral device 250 is completely off (e.g., outside of periodic times 480 and 490). For example, in some embodiments where host device 200 is a laptop, signal 416 can transition at time 620 in response to host device 200 exiting a sleep mode and / or other events that can trigger host device 200 to transition to a high power mode.

[0079] In another embodiment, the transition can be triggered at time 615 when peripheral device 250 is temporarily turned on (e.g., during periodic times 480 or 490), as shown in the alternative dashed flow path shown in Figure 7 .

[0080] For example, as discussed, at times 480 and 490 (e.g., periodically, any desired number of times), intermediate device 210 (e.g., through power control block 222) periodically turns on and off peripheral device 250 to perform various operations as discussed, while host device 200 remains in a reduced power mode. In some embodiments, such operations can result in a trigger at time 615. For example, as discussed, peripheral device 250 can be part of accessory device 260 (such as a camera that is used to detect human presence, perform facial recognition, and / or other operations performed by host device 200). In this example, if accessory device 260 detects a triggering event (e.g., detects human presence, a facial recognition operation is successful, and / or other events), peripheral device 250 can communicate with intermediate device 210 to trigger the restoration of context data to registers 254 to continue high power operations of the peripheral device.

[0081] During time period 630, intermediate device 210 and peripheral device 250 perform a process to restore peripheral device 250. As Figure 7As shown, the intermediary device 210 and the peripheral device 250 perform various operations during a time period 630. In some embodiments, the time period 630 constitutes a relatively small time period (e.g., approximately 100 milliseconds) between the time 620 (e.g., at which the host device 200 is triggered) and the time 650 (e.g., at which the host device 200 commands the connected device to transition to a high power level). Thus, in some embodiments, the intermediary device 210 and the peripheral device 250 can quickly perform their various operations during the time period 630 to permit the peripheral device 250 to be restored prior to the time 650.

[0082] In block 632, the intermediary device 210 returns the peripheral device 250 to a high power mode, e.g., through operation of the power control block 222.

[0083] As discussed, the restoration of the peripheral device 250 can alternatively be performed in response to a triggering event at the time 615, which is caused by operation of the accessory device 260 while the peripheral device 250 is on. In this case, as shown by the alternative dashed flow, block 632 can be bypassed since the peripheral device 250 is already on. Moreover, in some embodiments, this alternative approach can provide additional time for the intermediary device 210 and the peripheral device 250 to perform their various operations during the time period 630. For example, the triggering event caused by the accessory device 260 can occur while the host device 200 itself has not yet been triggered to return to a high power mode. Thus, the risk of the peripheral device 250 not being ready when the host device 200 expects it to be is reduced.

[0084] In block 634, the intermediary device 210 reads the context data from the register 214 (e.g., in response to the control signal provided by the processing block 256 to the FSM 212 on the bus 280) and passes the context data to the peripheral device 250 on the bus 280.

[0085] In block 636, the peripheral device 250 stores the context data into the register 254. Thus, after block 636, the peripheral device 210 has been restored to its previous power-on mode with its context data being the same as it was at the time 420 of Figure 4 and Figure 5 the time 420.

[0086] Accordingly, in block 638, the intermediary device 210 stops isolating the peripheral device 250 from the host device 200 and re-enables communication between the peripheral device 250 and the host device 200 through the intermediary device 210. For example, in the case of USB communication, the intermediary device 210 can stop sending USB NAK packets to the host device 200 and instead can send appropriate data packets to indicate that the intermediary device 210 (and thus the peripheral device 250) is available for communication on the bus 270.

[0087] In Figure 7 In the alternative flow path, the intermediary device 210 can also send a trigger (e.g., a wake-up signal) to the host device 200 on the bus 270 that is now enabled to initiate a transition of the host device 200 from the reduced power mode to the high power mode.

[0088] At time 640, in response to the trigger provided at time 620 or a trigger provided from the intermediary device 210 as discussed, the host device 200 transitions to its high power mode. At time 650, the host device 200 commands the connected device (e.g., the intermediary device 210) to transition to the high power mode, as shown in diagram 604. After time 650, the host device 200, the intermediary device 210, and the peripheral device 250 can operate in the high power mode.

[0089] Where applicable, the various embodiments provided by the present disclosure can be implemented using hardware, software, firmware, or combinations thereof, where appropriate. Furthermore, where appropriate, the various hardware components and / or software components set forth herein can be combined into a composite component, where appropriate, without departing from the spirit of the present disclosure. Where appropriate, the various hardware components and / or software components set forth herein can be separated into sub-components, where appropriate, without departing from the spirit of the present disclosure. Furthermore, where appropriate, the various hardware components and / or software components set forth herein can be implemented by hardware, software, and / or firmware, where appropriate, without departing from the spirit of the present disclosure. For example, the various components of the intermediary device 210 and / or the host device 200 can be implemented with a set of one or more computers operating in cohesion, such as one or more computers of a cloud computing resource.

[0090] Software, in accordance with the present disclosure, such as program code and / or data, can be stored on one or more computer-readable media. It is also contemplated that software identified herein can be implemented using one or more computers and / or computer systems, where appropriate. Where appropriate, the various steps and / or functions described herein can be implemented by one or more computers and / or computer systems, where appropriate. The order of any steps and / or functions can be changed, combined, and / or separated into components, where appropriate, without departing from the spirit of the present disclosure.

[0091] The above-described embodiments of the application do not represent all possible implementations thereof. Instead, they are merely a possible embodiment of the application. All modifications and variations are possible which fall within the spirit and scope of the present application as defined by the appended claims. Moreover, no element and / or component in the present disclosure can be construed as critical and essential to the application unless explicitly described as such.

Claims

1. A method comprising: An intermediate device, communicatively connected between the host device and the peripheral device, receives a notification that the host device will switch from a high-power mode to a low-power mode; The intermediate device receives context data associated with the operating state of the peripheral device from the peripheral device; The context data is stored by the intermediate device; as well as While the host device remains at least partially enabled in the reduced power mode, the intermediate device performs power gating on the peripheral device.

2. The method according to claim 1, further comprising: The intermediate device receives a notification from the host device that it will switch back from the reduced power mode to the high power mode; While the host device remains in the reduced power mode, the intermediate device powers on the peripheral device; as well as The intermediate device transmits the context data to the peripheral device to allow the peripheral device to resume its operating state before the host device transitions back to the high-power mode.

3. The method according to claim 2, further comprising: When the host device is in the high-power mode, the intermediate device manages the communication between the host device and the peripheral device; When the host device is in the reduced power mode, the intermediate device disables the communication between the host device and the peripheral device through the intermediate device, so as to isolate the communication between the peripheral device and the host device. as well as After the peripheral device is restored to its operating state, the intermediate device enables the communication between the host device and the peripheral device through the intermediate device.

4. The method according to claim 3, wherein the management includes: The analog communication signals received from the host device are converted into digital communication signals and sent to the peripheral device. as well as The digital communication signals received from the peripheral device are converted into analog communication signals and sent to the host device.

5. The method according to claim 4, wherein: The intermediate device sends and receives the analog communication signals on the first USB bus, which communicatively connects the intermediate device to the host device. as well as The intermediate device sends and receives the digital communication signals on the second USB bus, which communicatively connects the intermediate device to the peripheral device.

6. The method according to claim 2, wherein: Receive a notification from the host device that the mode has switched from high power mode to low power mode; and Receive a notification from the host device that the mode has switched back to the high-power mode from the reduced-power mode.

7. The method according to claim 2, further comprising: The intermediate device periodically powers on and off the peripheral device to allow the peripheral device to operate intermittently while the host device remains in the reduced power mode.

8. The method according to claim 7, wherein: The peripheral device is part of an accessory device integrated with the host device, and the accessory device is configured to be periodically powered on and off together with the peripheral device; as well as In response to an operation performed by the accessory device when it is periodically turned on, a notification is received from the peripheral device indicating a transition from the reduced power mode back to the high power mode.

9. The method according to claim 8, wherein: The host device is a computing device; The accessory device is a camera; and The operation is performed by the camera's detection of human presence and / or the camera's successful facial recognition.

10. The method according to claim 1, wherein: The intermediate device is a first programmable logic device (PLD); The peripheral device is the second PLD; and The power drawn by the intermediate device is less than that of the peripheral device.

11. A system comprising: Intermediate devices, communicatively connected between host devices and peripheral devices, are configured to: Receive notification from the host device that it will switch from the high-power mode to the low-power mode; Receive context data associated with the operating state of the peripheral device from the peripheral device; Store the context data; as well as While the host device remains at least partially enabled in the reduced power mode, the peripheral device is power-gated.

12. The system of claim 11, wherein the intermediate device is configured to: Receive notification from the host device that it will switch back from the reduced power mode to the high power mode; While the host device remains in the reduced power mode, the peripheral device is powered on; and The context data is transmitted to the peripheral device to allow the peripheral device to resume its operating state before the host device transitions back to the high-power mode.

13. The system of claim 12, wherein the intermediate device is configured to: When the host device is in the high-power mode, the communication between the host device and the peripheral device is managed; When the host device is in the reduced power mode, communication between the host device and the peripheral device via the intermediate device is interrupted to isolate communication between the peripheral device and the host device; and After the peripheral device is restored to its operating state, communication between the host device and the peripheral device via the intermediate device is enabled.

14. The system of claim 13, wherein the intermediate device includes a transceiver configured to: Convert the analog communication signals received from the host device into digital communication signals to be sent to the peripheral device; and The digital communication signals received from the peripheral device are converted into analog communication signals and sent to the host device.

15. The system according to claim 14, wherein: The intermediate device is configured to send and receive the analog communication signals on a first USB bus, the first USB bus communicatively connecting the intermediate device to the host device; as well as The intermediate device is configured to send and receive digital communication signals on a second USB bus, which communicatively connects the intermediate device to the peripheral device.

16. The system according to claim 12, wherein: Receive a notification from the host device that the mode has switched from the high-power mode to the low-power mode; and Receive a notification from the host device that the mode has switched back to the high-power mode from the reduced-power mode.

17. The system of claim 12, wherein the intermediate device is configured to: The peripheral device is periodically powered on and off to allow it to operate intermittently while the host device remains in the reduced power mode.

18. The system according to claim 17, wherein: The peripheral device is part of an accessory device integrated with the host device and is configured to be periodically powered on and off together with the peripheral device; as well as In response to an operation performed by the accessory device when it is periodically turned on, a notification is received from the peripheral device indicating a transition from the reduced power mode back to the high power mode.

19. The system of claim 18, further comprising: The host device, wherein the host device is a computing device; Accessory device, wherein the accessory device is a camera; as well as The operation described therein is achieved by the camera detecting the presence of a human and / or by the camera's successful facial recognition.

20. The system according to claim 11, wherein: The intermediate device is a first programmable logic device (PLD); The peripheral device is the second PLD; and The power drawn by the intermediate device is less than that of the peripheral device.

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