Wiring board and method for manufacturing wiring board

Abstract

The invention provides a wiring substrate and a method for manufacturing the wiring substrate. The wiring substrate can be produced at a good yield and has a small warping degree. A wiring board according to an embodiment includes: a first substrate (10) having one surface (10F) and another surface (10S) on the opposite side to the one surface (10F), the first substrate (10) including first conductor layers (12) and first insulating layers (11) alternately laminated on both surfaces of a first core substrate (100); and a second substrate (20) including a first surface (20F) having a component mounting region (EA) and a second surface (20S) on the opposite side from the first surface (20F), the second substrate (20) including second conductor layers (22) and second insulating layers (21) alternately laminated on both surfaces of the second core substrate (200). One surface (10F) of the first substrate (10) is connected to second surfaces (20S) of a plurality of second substrates (20) having substantially the same thickness via conductor protrusions (BP).

Description

TECHNICAL FIELD

[0001] The present application relates to a wiring substrate and a manufacturing method of a wiring substrate. BACKGROUND

[0002] A semiconductor mounting member is disclosed in Patent Literature 1. The semiconductor mounting member is composed of a single first substrate and a single second substrate. The second substrate is connected to the first substrate via a bump. A semiconductor element is connected to a surface of the second substrate opposite to the first substrate.

[0003] Patent Literature 1: Japanese Patent Application Laid-Open No. 2012-160701

[0004] In the semiconductor mounting member disclosed in Patent Literature 1, one second substrate is connected to one first substrate. It is considered that in a case where the size in the planar direction of the semiconductor mounting member is relatively large, the yield in the manufacturing can be reduced, and in addition, the degree of warping of the semiconductor mounting member can be large. SUMMARY

[0005] The wiring substrate of the present application includes a first substrate having one surface and another surface opposite to the one surface, the first substrate including first conductor layers and first insulating layers alternately stacked on both surfaces of a first core substrate, and a second substrate including a first surface having a component mounting region and a second surface opposite to the first surface, the second substrate including second conductor layers and second insulating layers alternately stacked on both surfaces of a second core substrate. The one surface of the first substrate is connected to the second surfaces of a plurality of the second substrates having substantially equal thicknesses via conductor bumps.

[0006] The manufacturing method of the wiring substrate of the present application includes the steps of preparing a first substrate having one surface and another surface opposite to the one surface, the first substrate including first conductor layers and first insulating layers alternately stacked on both surfaces of a first core substrate, preparing a second substrate including a first surface having a component mounting region and a second surface opposite to the first surface, the second substrate including second conductor layers and second insulating layers alternately stacked on both surfaces of a second core substrate, and connecting the second substrate to the first substrate via conductor bumps. In the step of preparing the second substrate, a plurality of the second substrates having substantially equal thicknesses are prepared, and the second surfaces of the plurality of the second substrates are connected to the one surface of the first substrate.

[0007] According to the embodiment of the present application, it is possible to provide a wiring substrate which can be produced with a good yield and has a small degree of warping. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1is a cross-sectional view showing one example of a wiring substrate of one embodiment of the present application.

[0009] Figure 2 is Figure 1 is a plan view of the wiring substrate.

[0010] Figure 3 is a plan view showing another example of the wiring substrate of the embodiment.

[0011] Figure 4 is a plan view showing another example of the wiring substrate of the embodiment.

[0012] Figure 5 is a plan view showing another example of the wiring substrate of the embodiment.

[0013] Figure 6A is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0014] Figure 6B is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0015] Figure 6C is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0016] Figure 6D is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0017] Figure 7A is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0018] Figure 7B is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0019] Figure 7C is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0020] Figure 8A is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0021] Figure 8B is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0022] Figure 8C is a view showing one example of a manufacturing method of a wiring substrate of one embodiment of the present application.

[0023] Label Explanation

[0024] 1, 2, 3a, 3b: wiring substrate; 10: first substrate; 20: second substrate; 11: insulating layer (first insulating layer); 21: insulating layer (second insulating layer); 12: conductor layer (first conductor layer); 22: conductor layer (second conductor layer); 12fp, 12sp, 22fp, 22sp: conductor pad; 100: core substrate (first core substrate); 101: core insulating layer (first core insulating layer); 102: core conductor layer (first core conductor layer); 200: core substrate (second core substrate); 201: core insulating layer (second core insulating layer); 202: core conductor layer (second core conductor layer); 13: via conductor (first via conductor); 23: via conductor (second via conductor); 103: through conductor; 203: through-hole conductor; BP: conductor bump; EA, EAA, EAB: component mounting region. DETAILED DESCRIPTION

[0025] A wiring substrate of one embodiment is described with reference to drawings. Figure 1 is a cross-sectional view of a wiring substrate 1 that shows one example of the wiring substrate of one embodiment. Figure 2 is Figure 1 is a plan view of the wiring substrate 1. Figure 1 is a cross-sectional view of the wiring substrate 1. Figure 2 is a cross-sectional view along line I-I in FIG. 1A. Note that the wiring substrate 1 is only one example of the wiring substrate of one embodiment. The stacked structure of the wiring substrate of one embodiment, the number of each of the conductor layers and the insulating layers, and the arrangement relationship of the plurality of substrates that constitute the wiring substrate are not limited to those of the wiring substrate 1. Figure 1 is a cross-sectional view of the wiring substrate 1.

[0026] The wiring substrate of one embodiment includes a first substrate and a plurality of second substrates each of which is formed of a plurality of conductor layers and a plurality of insulating layers that are alternately stacked. The wiring substrate 1 of the illustrated example includes one first substrate 10 and two second substrates 20. The first substrate 10 has one surface 10F and another surface 10S opposite to the one surface 10F as two main surfaces perpendicular to the thickness direction thereof. The plurality of second substrates 20 each has a first surface 20F and a second surface 20S opposite to the first surface 20F as two main surfaces perpendicular to the thickness direction thereof. The plurality of second substrates 20 are each arranged so that the second surface 20S faces the one surface 10F of the first substrate 10.

[0027] In addition, in the description of the wiring substrate, the first surface 20F side of the second substrate 20 is referred to as "upper" or "upper side", and the other surface 10S side of the first substrate 10 is referred to as "lower" or "lower side". In addition, among the respective structural elements of the wiring substrate, the surface of the second substrate 20 facing the first surface 20F side is also referred to as "upper surface", and the surface of the first substrate 10 facing the other surface 10S side is also referred to as "lower surface".

[0028] The first substrate 10 and the second substrate 20 each include insulating layers and conductor layers alternately laminated. Specifically, in the illustrated example, the first substrate 10 includes a core substrate 100 having an insulating layer 101 and a conductor layer 102 formed in contact with both surfaces of the insulating layer 101 perpendicular to the thickness direction, and four layers of insulating layers 11 and four layers of conductor layers 12 laminated on both surfaces (upper and lower sides) of the core substrate 100. The second substrate 20 includes a core substrate 200 having an insulating layer 201 and a conductor layer 202 formed in contact with both surfaces of the insulating layer 201 perpendicular to the thickness direction, and six layers of insulating layers 21 and six layers of conductor layers 22 laminated on both surfaces (upper and lower sides) of the core substrate 200. In addition, the core substrate 100 constituting the first substrate 10 is also referred to as the first core substrate 100. The insulating layer 11 constituting the first substrate 10 is also referred to as the first insulating layer 11, and the conductor layer 12 constituting the first substrate 10 is also referred to as the first conductor layer 12. The insulating layer 101 of the first core substrate 100 constituting the first substrate 10 is also referred to as the first core insulating layer 101, and the conductor layer 102 of the first core substrate 100 constituting the first substrate 10 is also referred to as the first core conductor layer 102. The core substrate 200 constituting the second substrate 20 is also referred to as the second core substrate 200. The insulating layer 21 constituting the second substrate 20 is also referred to as the second insulating layer 21, and the conductor layer 22 constituting the second substrate 20 is also referred to as the second conductor layer 22. The insulating layer 201 of the second core substrate 200 constituting the second substrate 20 is also referred to as the second core insulating layer 201, and the conductor layer 202 of the second core substrate 200 constituting the second substrate 20 is also referred to as the second core conductor layer 202.

[0029] In the first substrate 10, the first core conductor layer 102 formed in contact with both surfaces of the first core insulating layer 101 that constitutes the first core substrate 100 is connected through the through conductor 103 that penetrates the first core insulating layer 101 in the thickness direction. The via conductors 13 are respectively formed in the first insulating layer 11 that constitutes the first substrate 10, and connect conductor layers (the first conductor layers 12 to each other, or the first conductor layers 12 and the first core conductor layer 102) that face each other across the first insulating layer 11, in the thickness direction. The second core conductor layer 202 formed in contact with both surfaces of the second core insulating layer 201 that constitutes the second core substrate 200 is connected through the via conductor 203 that penetrates the second core insulating layer 201 in the thickness direction. The via conductors 23 are respectively formed in the second insulating layer 21 that constitutes the second substrate 20, and connect conductor layers (the second conductor layers 22 to each other, or the second conductor layers 22 and the second core conductor layer 202) that face each other across the second insulating layer 21, in the thickness direction. Further, the via conductors 13 formed in the first insulating layer 11 are also referred to as first via conductors 13, and the via conductors 23 formed in the second insulating layer 21 are also referred to as second via conductors 23.

[0030] The through conductor 103 is formed by filling a through hole 101a formed in the core insulating layer 101 with an electrically conductive body, and has a so-called filled via hole form. The through conductor 103 is formed integrally with the core conductor layer 102. The via conductor 203 includes a conductor film 213 that covers the inner wall of a through hole 201a formed in the core insulating layer 201, and a filling material 223 that fills a region (a void) defined by the conductor film 213, such as an insulating resin. That is, the via conductor 203 includes the conductor film 213 that assumes an electrically conductive property, and the filling material 223 that fills the inside of the conductor film 213. The conductor film 213 that constitutes the via conductor 203 is formed integrally with the core conductor layer 202. The first via conductor 13 is formed by filling a through hole 11a formed in the first insulating layer 11 with an electrically conductive body. The first via conductor 13 is formed integrally with the first conductor layer 12 that is in contact with the upper side of the first insulating layer 11 through which the first via conductor 13 penetrates. The second via conductor 23 is formed by filling a through hole 21a formed in the second insulating layer 21 with an electrically conductive body. The second via conductor 23 is formed integrally with the second conductor layer 22 that is in contact with the surface of the second insulating layer 21 opposite the core substrate 200 through which the second via conductor 23 penetrates.

[0031] The first core insulating layer 101, the first insulating layer 11, the second core insulating layer 201, and the second insulating layer 21 are formed using an insulating resin. As the insulating resin, an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin, or the like can be exemplified. The first core insulating layer 101, the first insulating layer 11, the second core insulating layer 201, and the second insulating layer 21 can also contain any one of a fluororesin, a liquid crystal polymer (LCP), a fluorinated ethylene resin (PTFE), a polyester resin (PE), a modified polyimide resin (MPI).

[0032] As the conductor that constitutes the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the through conductor 103, the via conductor 203, the first core conductor layer 102, and the second core conductor layer 202, copper, nickel, or the like is exemplified, and copper is preferably used. In the case of using copper, the copper can be used as a copper foil, a copper film, or the like. Figure 1 In the example shown, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 213, the through conductor 103, the first core conductor layer 102, and the second core conductor layer 202 are each shown in a single layer, but can be configured in multiple layers. The first conductor layer 12, the core conductor layer 202, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 213, the through conductor 103, the first core conductor layer 102, and the second core conductor layer 202 can have, for example, a multi-layer configuration including any one of a metal foil layer (preferably, a copper foil), a metal film layer (preferably, a copper film formed by chemical plating or sputtering), and a plated film layer (preferably, an electroplated copper film). For example, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 213, and the through conductor 103 can have a two-layer configuration including a metal film layer and a plated film layer. For example, the first core conductor layer 102, the first conductor layer 12 can have a three-layer configuration including a metal foil layer, a metal film layer, and a plated film layer. The second core conductor layer 202 can have a five-layer configuration including a metal foil layer, a metal film layer, a plated film layer, a metal film layer, and a plated film layer.

[0033] Each of the conductor layers (the first conductor layer 12, the second conductor layer 22, the first core conductor layer 102, and the second core conductor layer 202) that constitute the wiring substrate 1 is patterned to have a prescribed conductor pattern. The second conductor layer 22 that constitutes the first face 20F of the second substrate 20 is formed in a pattern having a conductor pad 22fp. The second conductor layer 22 that constitutes the second face 20S of the second substrate 20 is formed in a pattern having a conductor pad 22sp. The first conductor layer 12 that constitutes one face 10F of the first substrate 10 is formed in a pattern having a conductor pad 12fp. The first conductor layer 12 that constitutes the other face 10S of the first substrate 10 is formed in a pattern having a conductor pad 12sp.

[0034] In the drawing, a solder resist layer 20Rf is layered on the uppermost second conductor layer 22 of the second substrate 20, for example, using a photosensitive polyimide resin, an epoxy resin. An opening 20Rfa is formed in the solder resist layer 20Rf, and a conductor pad 22fp is exposed from the opening 20Rfa. That is, the first surface 20F includes the surface of the solder resist layer 20Rf and the surface of the conductor pad 22fp exposed from the opening 20Rfa. A solder resist layer 20Rs is layered on the lower side of the lowermost second conductor layer 22 of the second substrate 20. An opening 20Rsa is formed in the solder resist layer 20Rs, and a conductor pad 22sp is exposed from the opening 20Rsa. That is, the second surface 20S includes the surface of the solder resist layer 20Rs and the surface of the conductor pad 22sp exposed from the opening 20Rsa.

[0035] A solder resist layer 10Rf is layered on the uppermost first conductor layer 12 of the first substrate 10. An opening 10Rfa is formed in the solder resist layer 10Rf, and a conductor pad 12fp is exposed from the opening 10Rfa. That is, one surface 10F includes the surface of the solder resist layer 10Rf and the surface of the conductor pad 12fp exposed from the opening 10Rfa. A solder resist layer 10Rs is layered on the lower side of the lowermost first conductor layer 12 of the first substrate 10. An opening 10Rsa is formed in the solder resist layer 10Rs, and a conductor pad 12sp is exposed from the opening 10Rsa. That is, the other surface 10S includes the surface of the solder resist layer 10Rs and the surface of the conductor pad 12sp exposed from the opening 10Rsa.

[0036] The first surface 20F of the second substrate 20 constituting the outermost surface of the wiring substrate 1 is configured as a component mounting surface for connecting external electronic components. In the example shown in the drawing, the plurality of (two) second substrates 20 each have one component mounting region EA. That is, the wiring substrate 1 is capable of mounting a plurality of components in use thereof. The conductor pad 22fp is formed within the component mounting region EA. The conductor pad 22fp is connected to a connection pad Dp of an external electronic component D in use of the wiring substrate 1. When mounting an external electronic component on the wiring substrate 1, a conductive joining material (not shown), such as solder, is disposed on the upper surface of the exposed conductor pad 22fp, and the conductor pad 22fp is electrically and mechanically connected to the connection pad Dp of the external electronic component D via the conductive joining material.

[0037] As the electronic component D that can be mounted on the wiring substrate 1, for example, an electronic component such as a semiconductor integrated circuit device, an active component such as a transistor, or the like is exemplified. Specifically, the electronic component D that can be mounted on the wiring substrate 1 can be, for example, an integrated circuit such as a logic chip in which a logic circuit is assembled, or a processing device such as an MPU (Micro Processor Unit), a storage element such as an HBM (High Bandwidth Memory), or the like.

[0038] The conductor pads 22sp constituting the second surfaces 20S of the plurality of second substrates 20 are mechanically and electrically connected with the conductor pads 12fp constituting one surface 10F of the first substrate 10 via the conductor bumps BP. A under-fill material UF such as an epoxy resin or a polyimide resin is filled between the second surfaces 20S of the second substrates 20 and the one surface 10F of the first substrate 10. By filling the under-fill material UF between the second substrates 20 and the first substrate 10, the connection reliability of the second substrates 20 and the first substrate 10 against physical stress (thermal stress or physical external force) can be improved.

[0039] In a case where the wiring substrate 1 is mounted to an external element such as an external wiring substrate (a mother board of an arbitrary electric device) or the like, the other surface 10S of the first substrate 10 on the opposite side of the first surface 20F of the second substrate 20 serving as a component mounting surface in the wiring substrate 1 can be a connection surface to be connected to the external element. Therefore, in use of the wiring substrate 1, the conductor pads 12sp can be connected to an arbitrary substrate, an electric component, a mechanical component, or the like.

[0040] In the wiring substrate of the embodiment, the plurality of second substrates 20 having the component mounting regions EA are connected to the first substrate 10. If a wiring substrate having a structure in which a single second substrate is connected to the first substrate is assumed, in a case where the wiring substrate has a plurality of component mounting regions, it is necessary to have all of the plurality of component mounting regions in the single second substrate, and thus, it is sometimes necessary to increase the size in the planar direction of the second substrate. It is considered that, as the size in the planar direction of the second substrate increases, the degree of warping that can occur in the second substrate due to differences in the thermal expansion rates of the respective structural elements of the second substrate or the like becomes relatively large. In a case where the degree of warping of the second substrate is large, the connection reliability of the second substrate to the first substrate and the connection reliability of the second substrate to an external electronic component decrease. Therefore, in the structure in which a single second substrate is connected to the first substrate, it is considered that the connection reliability of the second substrate to the first substrate and the connection reliability of the second substrate to an external electronic component are low. Here, the "size in the planar direction" refers to the size of an object when the object is observed in a view (from above) in which a line of sight is parallel to the thickness direction of the wiring substrate.

[0041] In the wiring substrate of the embodiment, the plurality of second substrates 20 each having the component mounting region EA are connected to the first substrate 10. With the structure in which the wiring substrate includes the plurality of second substrates 20, each of the plurality of second substrates 20 can be implemented in a size corresponding to the size of each of the plurality of component mounting regions EA. Therefore, compared to the case in which a single second substrate is connected to the first substrate, the size in the planar direction of each of the plurality of second substrates 20 is suppressed, and along with this, it is considered that the degree of warping that can occur in each of the second substrates 20 is small. In the connection of the second substrates 20 to the first substrate 10 and the connection of the second substrates 20 to the external electronic components D, a connection with high reliability can be achieved.

[0042] In addition, the wiring substrate including the plurality of second substrates can be produced with good yield. In a structure in which a single second substrate is connected to the first substrate, in the case in which a part of the second substrate has failed in the production of the wiring substrate, the entire single second substrate needs to be replaced. In contrast, in the structure in which the plurality of second substrates 20 are connected to the first substrate 10, in the case in which the second substrate has failed, the wiring substrate can be manufactured by replacing only the second substrate 20 of the plurality of second substrates 20 that includes the part that has failed. Therefore, it is considered that the wiring substrate of the embodiment is suitable for production with good yield. In addition, it is considered that the loss cost at the time of each failure is also reduced. In addition, the plurality of second substrates included in the wiring substrate of the embodiment each have a thickness (the shortest distance between the first face 20F and the second face 20S) that is substantially equal to one another. In addition, the size in the planar direction of each of the plurality of second substrates, the number of layers of the insulating layer and the conductor layer included, and the materials that constitute each of the insulating layer and the conductor layer can be the same.

[0043] The first conductor layer 12 of the first substrate 10 and the second conductor layer 22 of the second substrate 20 can each include wiring of different sizes. The first conductor layer 12 of the first substrate 10 can include wiring FW1, and the second conductor layer 22 of the second substrate 20 can include high-density wiring, i.e., wiring FW2, of a small pattern width and a small inter-pattern distance. Specifically, the minimum value of the pattern width of the wiring FW1 that can be included in the first conductor layer 12 of the first substrate 10 can be different from the minimum value of the pattern width of the wiring FW2 that can be included in the second conductor layer 22 of the second substrate 20. The wiring FW2 included in the second substrate 20 can have a pattern width that is smaller than the minimum value of the pattern width of the wiring FW1 that can be included in the first conductor layer 12 within the first substrate 10. The minimum value of the inter-pattern distance of the wiring FW1 that can be included in the first conductor layer 12 of the first substrate 10 can be different from the minimum value of the inter-pattern distance of the wiring FW2 that can be included in the second conductor layer 22 of the second substrate 20. The wiring FW2 included in the second substrate 20 can have an inter-pattern distance that is smaller than the minimum value of the inter-pattern distance of the wiring included in the first conductor layer 12 within the first substrate 10. Specifically, for example, the minimum value of the pattern width of the wiring FW2 is 12 μm or less, and the minimum value of the inter-pattern distance of the wiring FW2 is 15 μm or less. By having the second substrate 20 include the fine wiring FW2, a wiring having more appropriate characteristics can sometimes be provided in a circuit that is connected to an external electronic component D. Forming such a relatively fine wiring FW2 can sometimes reduce the yield of the second substrate 20. However, in the wiring substrate of the embodiment that includes a plurality of second substrates, as described above, the size of the second substrate can be suppressed, and thus the reduction in the yield during the manufacture of the second substrate 20 can be suppressed.

[0044] In the case where the second conductor layer 22 is formed to include the wiring FW2 formed in a fine pattern width and a fine inter-pattern distance as described above, it is sometimes preferable that the second via conductor 23 also be formed in a fine pitch. In this case, it is necessary to form the small-diameter through holes 21a in the second insulating layer 21. Therefore, the second insulating layer 21 can include inorganic fillers such as microparticles of silicon dioxide (SiO2), aluminum oxide, mullite, or the like, but in order to easily form the small-diameter through holes 21a, it is sometimes preferable that the second insulating layer 21 not include inorganic fillers. In addition, in the case where the second conductor layer 22 has the wiring FW2, the second insulating layer 21 preferably does not include a core material (reinforcing material) composed of glass fibers, aramid fibers, or the like.

[0045] The thickness of the second conductor layer 22 that can include the wiring FW2 is formed to be, for example, 10 μm or more and 25 μm or less. The thickness of the second insulating layer 21 in the second substrate 20 is, for example, 15 μm or more and 40 μm or less. The thickness of the first conductor layer 12 that can include the wiring FW1 is formed to be, for example, 15 μm or more and 40 μm or less. The thickness of the first insulating layer 11 in the first substrate 10 is, for example, 40 μm or more and 100 μm or less.

[0046] The second substrate 20 has a relatively large thickness by including the core substrate 200. The core substrate 200 has a core insulating layer 201 that includes a core material (reinforcing material) composed of, for example, glass fiber, aramid fiber, or the like, and thus has a relatively high rigidity. Therefore, the degree of warping that can occur in the second substrate 20 can be further suppressed. In the second substrate 20, when the second insulating layer 21 and the second conductor layer 22 are formed in the same number of layers on the upper side and the lower side of the core substrate 200, it is considered that the degree of warping that can occur in the second substrate 20 can be further suppressed.

[0047] The thickness (the shortest distance between the first face 20F and the second face 20S) of the second substrate 20 including the core substrate 200 is preferably large, and is preferably larger than the thickness (the shortest distance between the one face 10F and the other face 10S) of the first substrate 10. When an external electronic component D is mounted to the component mounting face, stress applied to the second substrate 20 is absorbed by the second substrate 20 before reaching the connection portion of the second substrate 20 and the first substrate 10, and it is considered that generation of defects at the connection portion of the second substrate 20 and the first substrate 10 can be suppressed.

[0048] Next, another example of the wiring substrate according to the embodiment will be described with reference to Figures 3-5 In Figures 3-5 , the upper surface of the wiring substrate is shown as in Figure 2 . In the example shown in Figures 3-5 , the arrangement relationship between the first substrate 10 and the second substrate 20 is different from that in the example shown in Figure 2 .

[0049] Figure 3The wiring substrate 2 shown has a plurality of (two) second substrates 20 and a plurality of (two) first substrates 10. Thus, the wiring substrate of this embodiment sometimes includes a plurality of first substrates. Compared to a wiring substrate containing a single first substrate, by including a plurality of first substrates, the dimensions of each first substrate in its planar direction can be suppressed. In a wiring substrate 2 having a plurality of first substrates 10, as described for the plurality of second substrates 20 of wiring substrate 1, the warpage that may occur in the first substrate 10 can be suppressed to a smaller extent compared to a structure having a single first substrate 10. Therefore, in wiring substrate 2, the reliability of the connection between the first substrate 10 and the second substrates 20 is further improved. Furthermore, as described for the plurality of second substrates 20 of wiring substrate 1, compared to a wiring substrate 1 having a single first substrate 10, the wiring substrate 2 having a plurality of first substrates 10 can be manufactured with a good yield.

[0050] exist Figure 3 In the wiring substrate 2 shown, one second substrate 20 is connected to multiple (two) first substrates 10. In other words, the second substrate 20 is arranged such that it is mounted on multiple first substrates 10. In the illustrated example, two second substrates 20 are connected to two first substrates 10 respectively. It is believed that with such a structure, the stress that may be applied to the wiring substrate 2 when mounting external electronic components is effectively dispersed, suppressing the generation of local defects (e.g., poor connection between the first substrate 10 and the second substrate 20). In addition, the multiple first substrates 10 included in the wiring substrate 2 each have approximately equal thickness (the shortest distance between one surface 10F and another surface 10S). Furthermore, the dimensions in the planar direction of each of the multiple first substrates 10, the number of insulating and conductive layers they contain, and the materials constituting each insulating and conductive layer can be the same.

[0051] The wiring substrate of the embodiment may also have the same Figure 2 The example shown is a wiring substrate 1 and Figure 3 The example shown includes a wiring substrate 2 with varying numbers of second substrates 20 and a first substrate 10. Additionally, in Figure 2 The example shown is a wiring substrate 1 and Figure 3 In the example wiring substrate 2 shown, an example is illustrated where multiple (two) second substrates 20 have substantially the same size in the planar direction and component mounting areas EA of substantially the same size. However, the planar dimensions of each of the multiple second substrates 20 and the size of the component mounting areas EA of each of the multiple second substrates 20 may also be different.

[0052] Figure 4The wiring substrate 3a illustrated has four first substrates 10 and three second substrates 20A, 20B. Two of the three second substrates 20B of the wiring substrate 3a are equal in size, and the second substrates 20B are different in size from the second substrate 20A. In addition, the component mounting region EAA of the second substrate 20A is different in size from the component mounting region EAB of the second substrate 20B. In this way, by the structure in which the second substrates 20A, 20B different in size have the component mounting regions EAA, EAB different in size, it is possible to mount a plurality of external electronic components different in size to the wiring substrate.

[0053] In addition, the wiring substrate 3a has four first substrates 10, and thus, as described with reference to Figure 3 As described with regard to the wiring substrate 2, it is considered that the degree of further suppressing warping that can occur in the first substrates 10 is increased, and the reliability of the connection of the first substrates 10 to the second substrates 20 is further improved. In the wiring substrate 3a as well, a plurality of first substrates 10 are connected to each of the second substrates 20A, 20B, and the second substrates 20A, 20B are disposed so as to be positioned above the plurality of first substrates 10. In particular, in the example illustrated, the second substrate 20A is connected to all of the four first substrates 10 that constitute the wiring substrate 3a, and by this connection structure, it is considered that it is possible to more effectively suppress the occurrence of local defects in the wiring substrate, as described with regard to the wiring substrate 2.

[0054] In the case where the wiring substrate has a plurality of first substrates, from the viewpoint of suppressing the occurrence of local defects in the wiring substrate described above, it is preferable that the plurality of first substrates be physically connected to each other. In the case where the wiring substrate has a plurality of first substrates, sometimes the plurality of first substrates are sealed with resin. In Figure 5 In the case where the wiring substrate has a plurality of first substrates, from the viewpoint of suppressing the occurrence of local defects in the wiring substrate described above, it is preferable that the plurality of first substrates be physically connected to each other. In the case where the wiring substrate has a plurality of first substrates, sometimes the plurality of first substrates are sealed with resin. In Figure 4 In the example in which the plurality of first substrates 10 of the wiring substrate 3a illustrated are integrated by being sealed with resin, a wiring substrate 3b is illustrated. The gaps between the plurality of first substrates 10 are filled with sealing resin MR, and further, the sealing resin MR covers the side surfaces and the upper surfaces of the plurality of first substrates 10. Therefore, in the illustration, the plurality of first substrates 10 are indicated by broken lines in a state of being buried in the sealing resin MR. The sealing resin MR, for example, sometimes contains a photosensitive epoxy resin, and sometimes contains a thermoplastic resin such as a fluororesin, a liquid crystal polymer (LCP), a fluorinated ethylene resin (PTFE), a polyester resin (PE), a modified polyimide resin (MPI), and the like. The sealing resin MR integrates the four first substrates 10 by physically bonding the four first substrates 10 to each other. By integrating the plurality of first substrates 10 with the sealing resin MR, the upper surfaces of the plurality of first substrates 10 have better planarity, and thus, it is considered that the reliability of the connection of the first substrates 10 to the second substrates 20A, 20B is improved.

[0055] Next, with reference to Figures 6A-6D , Figures 7A-7C and Figures 8A-8C , a manufacturing method of the wiring substrate according to the embodiment will be described, taking the case of manufacturing the wiring substrate 1 shown in Figure 1 . Further, in the manufacturing method described below, each structural element formed therein can be formed using the materials exemplified in the description of the wiring substrate 1 of Figure 1 as the materials of the corresponding structural elements, unless otherwise specifically described. In addition, in Figures 6A-6D , Figures 7A-7C and Figures 8A-8C referenced below, in Figures 6A-6D , Figures 7A-7C , each conductor layer is depicted as a structural element of a metal foil layer, a metal film layer, and a plating film layer, but in Figures 8A-8C , each conductor layer is depicted as a single layer, as in Figure 1 .

[0056] The manufacturing method of the wiring substrate 1 includes the steps of preparing the first substrate 10, preparing a plurality of second substrates 20, and connecting the first substrate 10 and the plurality of second substrates 20. First, with reference to Figures 6A-6D , the case of preparing the first substrate 10 will be described. In addition, in the description with reference to Figures 6A-6D , the side of the first core substrate 100 closer to the first core insulating layer 101 is referred to as "lower", "inner", or "lower side", "inner side", and the side farther from the first core insulating layer 101 is referred to as "upper", "outer", or "upper side", "outer side". Therefore, the face of each element constituting the first substrate 10 toward the first core insulating layer 101 is referred to as "lower surface", and the face toward the side opposite to the first core insulating layer 101 is also referred to as "upper surface".

[0057] First, as shown in Figure 6A , the first core substrate 100 is formed. For example, a laminated board (for example, a double-sided copper-clad laminated board) having a first core insulating layer 101 composed of an insulating resin such as an epoxy resin and a metal foil mf provided on both sides of the first core insulating layer 101 is prepared. After forming a through-hole 101a for the through conductor 103 by laser processing, the first core conductor layer 102 and the through conductor 103 are formed by subtractive method. The through conductor 103 is formed as a so-called filled via hole in which the through-hole 101a is filled with a conductive body.

[0058] Next, as shown in Figure 6BAs shown, a first insulating layer 11 is formed, covering the surface of the first core conductor layer 102 and exposing the pattern of the first core conductor layer 102. Then, a first via conductor 13 penetrating the first insulating layer 11 and a first conductor layer 12 on the first insulating layer 11 are integrally formed using a subtractive forming method. As the first insulating layer 11, for example, a film-like insulating resin comprising epoxy resin, phenolic resin, etc., can be used.

[0059] Specifically, a first insulating layer 11 having a metal foil mf is laminated on one side of the surface (upper surface). A through-hole 11a is formed at the location of the first via conductor 13 in the first insulating layer 11, for example, by irradiation with a carbon dioxide laser. Next, a metal film layer 121 is formed on the inner wall of the through-hole 11a and on the surface of the metal foil mf by chemical plating or sputtering. A plating film layer 122 is formed on the metal film layer 121 by electroplating the metal film layer 121 as a power supply layer. The interior of the through-hole 11a is completely filled by the electroplated film 122, forming the first via conductor 13. Next, for example, a dry film resist containing photosensitive epoxy resin is bonded to the upper surface of the electroplated film 122, forming a resist with openings corresponding to the conductor pattern of the first conductor layer 12 formed on the first insulating layer 11. The plating film layer 122, the metal film layer 121, and the metal foil mf exposed within the openings of the resist are removed by etching. As a result, as... Figure 6B As shown, a first conductor layer 12 is formed having a three-layer structure consisting of a metal foil mf, a metal film layer 121, and a plating film layer 122.

[0060] Next, as Figure 6C As shown, the same process as the stacking of the first insulating layer 11 and the formation of the first via conductor 13 and conductor layer 12 described above is repeated to stack the desired number of first insulating layers 11 and first conductor layers 12. The outermost first conductor layer 12 is formed as a pattern including conductor pads 12fp and 12sp. In addition, any one of the first conductor layers 12 can be formed in a manner that includes wiring FW1.

[0061] Next, as Figure 6D As shown, after stacking the first insulating layer 11 and the first conductor layer 12 with the desired number of layers, a photosensitive epoxy resin and polyimide resin layer is formed on the surface of the first insulating layer 11 exposed from the pattern of the outermost first conductor layer 12, thereby forming solder resist layers 10Rf and 10Rs. Using photolithography, an opening 10Rfa is formed in the solder resist layer 10Rf to expose the conductor pad 12fp, and an opening 10Rsa is formed in the solder resist layer 10Rs to expose the conductor pad 12sp. The formation of the first substrate 10, having one surface 10F and another surface 10S opposite to the one surface 10F, is completed.

[0062] Further, in the case where a plurality of first substrates 10 are prepared, a plurality of first substrates 10 having substantially equal thicknesses to each other are prepared. In the case where a plurality of first substrates 10 as shown in FIG. 1 are prepared, the plurality of first substrates 10 are integrated by a sealing resin MR (refer to FIG. 2). Specifically, the plurality of first substrates 10 in which the formation of the solder resist layers 10Rf, 10Rs described with reference to FIG. 1 is omitted are placed on an arbitrary support body in a manner to contact the conductor pads 12sp. Next, a resin material such as a photosensitive epoxy resin constituting the sealing resin MR is injected in a state of having fluidity inside a frame body that surrounds a space including a region in which the plurality of first substrates 10 are arranged. The injected resin material fills gaps between the plurality of first substrates 10 each other and completely covers exposed surfaces of the plurality of first substrates 10. After the resin material is cured, the frame body is detached to integrate the plurality of first substrates 10. The sealing resin MR is formed with an opening that exposes the conductor pads 12fp. Next, the support body is detached, and the solder resist layer 10Rs having the opening that exposes the conductor pads 12sp is formed on a surface exposed by detaching the support body. Figure 5 Figure 5 Figure 6D

[0063] Next, the case where the second substrate 20 is prepared will be described with reference to FIGS. 3 to 5. First, as shown in FIG. 3, a core substrate 200 is prepared. In addition, in the description of the preparation of the second substrate 20, the side of the core substrate 200 close to the core insulating layer 201 is referred to as "lower" or "lower side", and the side away from the core insulating layer 201 is referred to as "upper" or "upper side". Therefore, the surface of each element constituting the second substrate 20 facing the core insulating layer 201 is referred to as "lower surface", and the surface facing the side opposite to the core insulating layer 201 is also referred to as "upper surface". Figures 7A-7C Figure 7A

[0064] In the preparation of the core substrate 200, for example, a double-sided copper-clad laminate including the core insulating layer 201 composed of a glass epoxy resin and copper foils mfc laminated on both sides of the core insulating layer 201 is prepared. The through hole 201a is formed on the double-sided copper-clad laminate, for example, by drilling. Next, the metal film layer 212 is formed on the inner wall of the through hole 201a and the upper surface of the copper foil by chemical plating, and the plating film layer 222 is formed on the metal film layer 212 by electroplating using the metal film layer 212 as a power supply layer. As a result, the conductor film 213 having a two-layer structure of the metal film layer 212 and the plating film layer 222 and covering the inner wall of the through hole 201a is formed.

[0065] ​​​​​Next, the inner side of the conductor film 213 is filled with a filler material 223, such as epoxy resin. After the filler material 223 cures, a metal film layer 232 and a plating film layer 242 are further formed on the upper surface of the filler material 223 and the plating film layer 222. As a result, a core conductor layer 202 with a five-layer structure consisting of a metal foil layer (MFC), a metal film layer 212, a plating film layer 222, a metal film layer 232, and a plating film layer 242 is formed on both sides of the core insulating layer 201. Then, the core conductor layer 202 is patterned using a subtractive method to obtain a core substrate 200 with a predetermined conductor pattern.

[0066] Next, as Figure 7B As shown, a second insulating layer 21 is formed on both sides of the core substrate 200, and a second conductor layer 22 is formed on the second insulating layer 21. For example, the second insulating layer 21 is formed by hot-pressing a film-like insulating resin onto the core substrate 200. The second conductor layer 22 and the via conductor 23 are formed simultaneously using an arbitrary conductor pattern forming method such as a semi-additive method, and the via conductor 23 fills a through hole 21a in the second insulating layer 21, for example, which can be formed using a laser.

[0067] Next, as Figure 7C As shown, the formation of the second insulating layer 21 and the second conductor layer 22 is repeated a desired number of times on the upper sides of both sides of the core substrate 200. On the outermost side of the second conductor layer 22 and the second insulating layer 21 on one side of the core substrate 200, a solder resist layer 20Rf is formed having an opening 20Rfa that exposes the conductor pad 22fp. On the outermost side of the second conductor layer 22 and the second insulating layer 21 on the other side of the core substrate 200, a solder resist layer 20Rs is formed having an opening 20Rsa that exposes the conductor pad 22sp. The formation of the second substrate 20, including a first side 20F having a component mounting region EA and a second side 20S opposite to the first side, is completed. Furthermore, the second conductor layer 22 is formed with a conductor pattern including wiring FW2 as relatively fine wiring. In the preparation of the second substrate 20, multiple (two) second substrates 20 having approximately equal thicknesses are prepared.

[0068] Next, refer to Figures 8A-8C The case where the first substrate 10 and the second substrate 20 are connected will be described.

[0069] First, such as Figure 8A As shown, on the conductor pad 12fp exposed in the opening 10Rfa of the solder resist layer 10Rf that constitutes one side 10F of the first substrate 10, a conductor protrusion BP is formed as a bonding material, for example, made of solder.

[0070] Next, as Figure 8BAs shown, the prepared plurality (2) of second substrates 20 having substantially equal thicknesses are connected to the first substrate 10 via the conductor bumps BP. Specifically, the 2 second substrates 20 are each arranged so that the second surface 20S faces one surface 10F of the first substrate 10, and the conductor pads 22sp exposed in the openings 20Rsa of the solder resist layer 20Rs constituting the second surface 20S are connected to the conductor bumps BP. In the description of the wiring substrate, as described above, in the case where a defect occurs in any one of the plurality of second substrates 20, the wiring substrate can be manufactured by replacing only the second substrate 20 including the portion in which the defect has occurred, and thus, by connecting the plurality of second substrates 20 to the first substrate 10, the wiring substrate can be manufactured with good yield. In addition, the size in the planar direction of each of the plurality of second substrates 20 is relatively small, and thus, the degree of warping that can occur in each of the plurality of second substrates 20 is relatively small, and the first substrate 10 and the second substrates 20 can be connected more reliably.

[0071] Next, as shown in FIG. 6, the gap between one surface 10F of the first substrate 10 and the second surface 20S of the second substrate 20 connected to each other via the conductor bumps BP is filled with an underfill material UF, and then hardened. The manufacturing of the wiring substrate 1 is completed. Figure 8C

[0072] The wiring substrate of the embodiment is not limited to having the configuration exemplified in each drawing and the configuration, shape, and material exemplified in the present specification. The wiring substrate of the embodiment can include a first substrate and a second substrate having an arbitrary layer stack, and the first substrate and the second substrate can include an arbitrary number of conductor layers and insulating layers. In addition, the wiring substrate of the embodiment can include an arbitrary number of first substrates and an arbitrary number of two or more second substrates.

[0073] The manufacturing method of the wiring substrate of the embodiment is not limited to the method described with reference to Figures 6A-6D , Figures 7A-7C , and Figures 8A-8C The conditions, order, and the like can be arbitrarily changed. In addition, a specific process can be omitted, or another process can be added. In the manufacturing method of the wiring substrate of the embodiment, the second surface of the plurality of second substrates including the core substrate can be connected to one surface of the first substrate via the conductor bumps, and for example, a plated layer including a nickel layer and a tin layer or the like can be formed on the surface of the conductor pad.​

Claims

1. A wiring substrate comprising: A first substrate having one side and another side opposite to said one side, the first substrate comprising a first conductor layer and a first insulating layer alternately stacked on both sides of a first core substrate; and The second substrate includes a first side having a component mounting area and a second side opposite to the first side. The second substrate includes a second conductor layer and a second insulating layer alternately stacked on both sides of the second core substrate. in, One side of the first substrate is connected to the second side of a plurality of second substrates of substantially equal thickness via a conductor protrusion.

2. The wiring substrate according to claim 1, wherein, The wiring substrate comprises a plurality of first substrates of approximately equal thickness. A second substrate is connected to a plurality of first substrates.

3. The wiring substrate according to claim 2, wherein, Multiple first substrates are integrated by sealing resin.

4. The wiring substrate according to claim 1, wherein, Any two of the plurality of second substrates have different dimensions in the planar direction.

5. The wiring substrate according to claim 1, wherein, The thickness of the second substrate is greater than the thickness of the first substrate.

6. The wiring substrate according to claim 1, wherein, The gap between the first surface and the second surface is filled with bottom filler material.

7. The wiring substrate according to claim 1, wherein, The minimum pattern width of the wiring contained in the first conductor layer is different from the minimum pattern width of the wiring contained in the second conductor layer.

8. The wiring substrate according to claim 7, wherein, The minimum pattern width of the wiring contained in the second conductor layer is less than the minimum pattern width of the wiring contained in the first conductor layer.

9. A method for manufacturing a wiring substrate, the method comprising the following steps: Prepare a first substrate having one side and another side opposite to the one side, the first substrate comprising a first conductor layer and a first insulating layer alternately stacked on both sides of a first core substrate; Prepare a second substrate, the second substrate including a first side having a component mounting area and a second side opposite to the first side, the second substrate including a second conductor layer and a second insulating layer alternately stacked on both sides of the second core substrate; as well as The second substrate is connected to the first substrate via a conductor protrusion. in, In the step of preparing the second substrate, a plurality of second substrates with approximately equal thickness are prepared. The second surface of a plurality of second substrates is connected to the first surface of the first substrate.

10. The method for manufacturing a wiring substrate according to claim 9, wherein, The method for manufacturing the wiring substrate further includes the following step: filling the space between the second surface and the first surface with a bottom filler material.

11. The method for manufacturing a wiring substrate according to claim 9, wherein, In the step of preparing the first substrate, a plurality of first substrates having approximately equal thickness are prepared, and the plurality of first substrates are integrated by means of a sealing resin.

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