Semiconductor structure, manufacturing method thereof and memory

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a semiconductor layer which comprises a first end part, a second end part and a middle part located between the first end part and the second end part, wherein the first end part and the second end part are integrally formed; in the first section, the middle part is annular; the second end part comprises a first extension part and a second extension part; the first extension part extends along a first direction and a second direction; the second extension part extends along the third direction and is connected with the middle part and the first extension part; in the first section, the first extending part is in a solid closed shape, the second extending part is annular, and the size of the first extending part is larger than the outer side overall size of the second extending part. According to the invention, the floating body effect can be inhibited.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] As the integration of semiconductor devices increases and their size continues to shrink, the power consumption, density, and mobility of transistors in semiconductor devices, such as Dynamic Random Access Memory (DRAM), are limited after the transistor feature size is reduced to the nanoscale, posing a greater challenge to improving transistor performance. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for manufacturing the same, and a memory. This application enables the suppression of the buoyancy effect.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure comprising: a semiconductor layer including an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross-section intersecting the extension direction of the semiconductor layer, the intermediate portion has an annular shape; wherein the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the intermediate portion and the first extension; in the first cross-section, the first extension has a solid closed shape, the second extension has an annular shape, and the size of the first extension is larger than the outer contour size of the second extension.

[0005] In some embodiments, the semiconductor layer is made of monocrystalline silicon.

[0006] In some embodiments, the thickness of the middle portion ranges from 5 nm to 15 nm.

[0007] In some embodiments, the concentration of P-type or N-type dopant elements in the material of the intermediate portion is inversely correlated with the thickness of the intermediate portion.

[0008] In some embodiments, within the first cross-section, the shape of the outer contour of the middle portion includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments; the shape of the inner contour of the middle portion includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments.

[0009] In some embodiments, within the first cross-section, the shape of the outer contour of the middle portion and the shape of the inner contour of the middle portion are substantially the same, and include a circle, an ellipse or a square.

[0010] In some embodiments, within the first cross-section, the dimensions of the outer contours of the first end and the middle portion are smaller than the dimensions of the outer contours of the second extension.

[0011] In some embodiments, the semiconductor structure further includes a gate structure; the gate structure surrounds the outer wall of the middle portion; within a first cross section, the dimension of the outer contour of the gate structure is greater than the dimension of the outer contour of the second end portion.

[0012] In some embodiments, the semiconductor structure includes a plurality of semiconductor layers; the plurality of semiconductor layers are arranged in an array along a first direction and a second direction; the semiconductor structure also includes a plurality of word lines; the word lines extend along the first direction and are coupled to the middle portion of a row of semiconductor layers; the word lines include a plurality of first portions and a plurality of second portions; the first portions surround the outer sidewall of a corresponding middle portion; in the first direction, the second portions connect two adjacent first portions; wherein, in the second direction, the size of the first portion is larger than the size of the second portion; in the third direction, the size of the first portion is larger than the size of the second portion.

[0013] In some embodiments, the multiple semiconductor layers are arranged in a hexagonal or rectangular pattern.

[0014] In some embodiments, the semiconductor structure further includes multiple bit lines; the bit lines extend along a second direction and are connected to a column of first extensions.

[0015] In some embodiments, the semiconductor structure further includes a plurality of memory cells; the memory cells are connected to a first end of a corresponding semiconductor layer; the memory cells are capacitor memory structures, phase change memory structures, resistive switching memory structures, or ferroelectric memory structures.

[0016] In some embodiments, the semiconductor structure further includes a plurality of memory cell contacts; the memory cell contacts include a third portion and a fourth portion; within a first cross section, the third portion surrounds the outer sidewall and inner sidewall of the first end portion; in a third direction, the fourth portion is located above the third portion and the first end portion.

[0017] Secondly, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; removing a portion of the substrate to form a semiconductor layer; the semiconductor layer including an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross-section intersecting the extension direction of the semiconductor layer, the intermediate portion having an annular shape; wherein the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the intermediate portion and the first extension; in the first cross-section, the first extension has a solid closed shape, the second extension has an annular shape, and the size of the first extension is larger than the outer contour size of the second extension.

[0018] In some embodiments, forming a semiconductor layer includes: removing a portion of the substrate on a first side of the substrate to form a first base layer and a plurality of second base layers integrally formed with the first base layer; the plurality of second base layers are arranged in an array along a first direction and a second direction; the second base layers extend along a third direction; on the first side, removing a portion of the second base layers to form a first end and a middle portion of the semiconductor layer; in a first cross section, the first end has an annular shape; on a second side of the substrate, removing a portion of the first base layer to form second ends of the semiconductor layer spaced apart from each other; a first extension of the second end includes a retained portion of the first base layer; a second extension of the second end includes a retained portion of the second base layer; the first side and the second side are two opposite sides of the substrate along a third direction.

[0019] In some embodiments, forming a first substrate layer and a plurality of second substrate layers integrally formed with the first substrate layer includes: on a first side, firstly removing a portion of the substrate to form a plurality of first holes extending into the substrate; and forming a columnar structure filling the first holes in the first holes; forming a first hard mask on the columnar structure and the portion of the substrate; and based on the first hard mask, secondly removing a portion of the substrate to form the first substrate layer and the plurality of second substrate layers; the second substrate layers surround the sidewalls of the columnar structure.

[0020] In some embodiments, the manufacturing method further includes: forming a plurality of word lines; the word lines extending along a first direction and coupled to a middle portion of a row of semiconductor layers; the word lines including a plurality of first portions and a plurality of second portions; the first portions surrounding the outer sidewall of a corresponding middle portion; in a first direction, the second portions connecting two adjacent first portions; wherein, in a second direction, the size of the first portion is larger than the size of the second portion; and in a third direction, the size of the first portion is larger than the size of the second portion.

[0021] In some embodiments, forming multiple word lines includes: forming an isolation structure and word line grooves extending into the isolation structure; the isolation structure is located on a first substrate layer and at least between the third ends of two adjacent second substrate layers; the word line groove includes a plurality of first spaces and a plurality of second spaces; the first spaces surround the outer walls of the fourth ends of corresponding second substrate layers and the fifth ends of second substrate layers; in a first direction, the second spaces connect two adjacent first spaces; wherein, in a third direction, the second substrate layer includes a fifth end away from the first substrate layer, a third end close to the first substrate layer, and a fourth end located between the third end and the fifth end; word lines are formed based on the word line grooves; a first portion of the word line is located in the first space; and a second portion of the word line is located in the second space.

[0022] In some embodiments, the manufacturing method further includes: forming a third space; exposing an outer sidewall and an inner sidewall of a portion of the fifth end in the third space; forming a third portion of a storage cell contact in the third space; within a first cross section, the third portion surrounds the outer sidewall and the inner sidewall of a portion of the first end; forming a fourth portion of the storage cell contact above the third portion and the first end; and forming a capacitor storage structure on the storage cell contact.

[0023] In some embodiments, the manufacturing method further includes: forming a bit line on a second side; the bit line extending along a second direction.

[0024] In some embodiments, providing a substrate includes: providing a substrate; the material of the substrate includes monocrystalline silicon.

[0025] Thirdly, embodiments of this application provide a memory, the memory comprising: any of the semiconductor structures provided in the first aspect, or a semiconductor structure obtained according to any of the manufacturing methods provided in the second aspect; word lines of the semiconductor structure are configured to receive word line voltages and control the conduction or cutoff of the middle portion of the semiconductor layer of the semiconductor structure by means of word line voltages, for connecting / disconnecting the first end and the second end of the semiconductor layer of the semiconductor structure; bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the middle portion of the semiconductor layer is turned on.

[0026] In various embodiments of this application, the middle part of the semiconductor layer has a hollow annular thin film structure. During operation, the charge carriers can be completely depleted, eliminating the accumulation of charge and thus suppressing the floating body effect. The semiconductor layer is integrally formed, and the size of the first extension is larger than the outer contour size of the second extension. Compared with the second extension, the area of ​​the first extension is larger, which can be used to increase the contact area with other components (e.g., bit lines) and reduce the contact resistance. Attached Figure Description

[0027] Figure 1 A three-dimensional perspective schematic diagram of the first semiconductor structure provided in the embodiments of this application; Figure 2 This is a three-dimensional perspective schematic diagram of a second semiconductor structure provided in an embodiment of this application; Figure 3 A three-dimensional perspective schematic diagram of the third semiconductor structure provided in the embodiments of this application; Figure 4 Multiple cross-sectional schematic diagrams of the fourth semiconductor structure provided in the embodiments of this application; Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method according to an embodiment of this application; Figures 6A to 6P A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in this application embodiment; Figure 7 This application provides various array arrangements of multiple first holes in its embodiments. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0032] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0035] In semiconductor devices such as DRAM transistors, the channel region is often quite thick (e.g., a solid channel region). The floating body effect causes the accumulation of charge carriers (e.g., holes) in the channel region, negatively impacting both the threshold voltage and off-state current. This increases the off-state current and reduces device performance. For example, transistors with a thick body region and no electrical connections in this region form a floating structure. This thick body region exhibits a floating body effect, leading to increased off-state current. The accumulated charge carriers generated during transistor operation cannot be effectively discharged, causing potential fluctuations and resulting in threshold voltage drift.

[0036] Figure 1 A three-dimensional perspective schematic diagram of the first semiconductor structure provided in the embodiments of this application. Figure 2 A three-dimensional perspective schematic diagram of a second semiconductor structure provided in an embodiment of this application. Figure 3This is a three-dimensional perspective schematic diagram of a third semiconductor structure provided in an embodiment of this application. It should be noted that, to clearly show the first end of the semiconductor layer and the first insulating layer, [the following is omitted as it is not part of the schematic diagram]. Figures 1 to 3 Only a portion of the gate dielectric layer, a portion of the first end, and a portion of the second end are shown in any of the accompanying drawings (only the second extension of the second end is shown, and the first extension of the second end is not shown).

[0037] Figure 4 These are schematic diagrams of multiple cross-sections of a fourth semiconductor structure provided in the embodiments of this application. Figure 4 Figure (a) shows a schematic diagram of the semiconductor structure along section AA (see Figure (b), also known as section XZ), and Figure (b) shows a schematic diagram of the semiconductor structure along section BB (see Figure (a), also known as section XY). It should be noted that, to clearly show the relative positional relationship between the bit lines and word lines, [the diagram is missing here]. Figure 4 The perspective view in diagram (b) shows the position of the bit line.

[0038] refer to Figure 4 According to a first aspect of the present application, a semiconductor structure is provided, the semiconductor structure comprising: a semiconductor layer 114p1 including an integrally formed first end portion 114p1a, a second end portion 114p1b, and an intermediate portion 114p1c located between the first end portion 114p1a and the second end portion 114p1b; in a first cross section intersecting the extension direction of the semiconductor layer 114p1, the intermediate portion 114p1c is annular in shape; wherein, the second end portion 114p1b includes a first extension portion b_1 and a second extension portion b_2; the first extension portion b_1 extends along a first direction and a second direction; the second extension portion b_2 extends along a third direction to connect the intermediate portion 114p1c and the first extension portion b_1; in the first cross section, the first extension portion b_1 is solid and closed in shape, the second extension portion b_2 is annular in shape, and the dimension D12 of the first extension portion b_1 is larger than the outer contour dimension D11 of the second extension portion b_2. In this embodiment, the middle part of the semiconductor layer has a hollow annular thin film structure. During operation, the charge carriers can be completely depleted, eliminating the accumulation of charge and thus suppressing the floating body effect. The semiconductor layer is integrally formed, and the size of the first extension is larger than the outer contour size of the second extension. Compared with the second extension, the area of ​​the first extension is larger, which can be used to increase the contact area with other components (such as bit lines) and reduce the contact resistance.

[0039] For ease of description of the embodiments of this application, the first direction and the second direction can be understood as two intersecting (e.g., orthogonal) directions parallel to the plane of the substrate (or substrate structure). For example, the first direction can be understood as the extension direction of the word line, and the second direction can be understood as the extension direction of the bit line. The third direction can be understood as a direction intersecting (e.g., orthogonal) to the plane of the substrate (or substrate structure). For example, the third direction can be understood as the extension direction of the semiconductor layer (or the stacking direction of the layers of the substrate structure). Exemplarily, the first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the third direction can be represented as the Z direction in the figures. Any two of the X, Y, and Z directions are orthogonal to each other.

[0040] In this text, the top and bottom surfaces of a component, part, area, layer, or portion can be understood as two opposing surfaces of the component, part, area, layer, or portion in a third direction. For example, the top surface of the first portion 124a can be understood as a surface of the first portion 124a that is closer to the first end 114p1a in a third direction, and the bottom surface of the first portion 124a can be understood as another surface of the first portion 124a that is farther away from the first end 114p1a in a third direction.

[0041] In this paper, the term "first section" can be understood as the BB section (also known as the XY section). The term "second section" can be understood as the AA section (also known as the XZ section).

[0042] refer to Figure 4 In some embodiments, the semiconductor layer 114p1 is made of a metal oxide semiconductor. Exemplarily, the semiconductor layer 114p1 is made of at least one of indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), and indium zinc oxide (IZO). In some embodiments, the semiconductor layer 114p1 is made of at least one of gallium arsenic (GaAs) and indium gallium arsenic (InGaAs).

[0043] refer to Figure 4In some embodiments, the semiconductor layer 114p1 is made of monocrystalline silicon. In this embodiment, etching (e.g., etching silicon and leaving the silicon to form the semiconductor layer) can be used. Compared to other materials (e.g., metal oxide semiconductors), monocrystalline silicon is purer and has a more uniform crystal structure. Compared to etching metal oxide semiconductors, etching monocrystalline silicon makes it easier to form a thinner, hollow, annular semiconductor layer. The hollow, annular semiconductor layer can eliminate charge accumulation and suppress the buoyancy effect by completely depleting the charge carriers.

[0044] refer to Figure 4 In some embodiments, the thickness of the intermediate portion 114p1c ranges from 5 nm to 15 nm. Exemplarily, the thickness of the intermediate portion 114p1c is 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm. Preferably, the thickness of the intermediate portion 114p1c ranges from 6 nm to 12 nm.

[0045] refer to Figure 4 In some embodiments, the material of the intermediate portion 114p1c includes monocrystalline silicon, and the concentration of P-type or N-type dopant elements in the material of the intermediate portion 114p1c is inversely correlated with the thickness of the intermediate portion 114p1c. For example, if the material of the intermediate portion 114p1c is doped with a P-type dopant element (e.g., boron), a higher concentration of the P-type dopant element results in a higher threshold voltage for forming an N-type transistor, thus requiring a thinner intermediate portion 114p1c. Similarly, if the material of the intermediate portion 114p1c is doped with an N-type dopant element (e.g., phosphorus), a higher concentration of the N-type dopant element results in a lower threshold voltage for forming a P-type transistor, again requiring a thinner intermediate portion 114p1c.

[0046] refer to Figure 4 In some embodiments, within the first cross-section, the outer contour of the middle portion 114p1c includes a circle, ellipse, rectangle, parallelogram, trapezoid, or a closed shape composed of arc segments and line segments; the inner contour of the middle portion 114p1c includes a circle, ellipse, rectangle, parallelogram, trapezoid, or a closed shape composed of arc segments and line segments. Within the first cross-section, the shape of the outer or inner contour of the middle portion 114p1c can be adaptively selected according to the specific requirements of the process. Although Figures 1 to 4The example described uses the circular shape of the outer and inner contours of the middle portion 114p1c as an example, but this example is not intended to limit the embodiments of this application. It should be noted that, in this document, the annular shape of the semiconductor layer within the first cross-section can be understood as at least the annular shape of the middle portion of the semiconductor layer. For example, refer to... Figure 4 The first end, the middle part, and the second extension of the second end of the semiconductor layer are all annular in shape, and the first extension of the second end is planar in shape (e.g., circular or elliptical).

[0047] refer to Figure 4 In some embodiments, within the first cross-section, the shape of the outer contour of the middle portion 114p1c is substantially the same as the shape of the inner contour of the middle portion 114p1c, including circular, elliptical, or square shapes. In this document, the term "substantially the same" can be understood as being the same within the allowable range of process tolerances.

[0048] refer to Figure 4 In some embodiments, within the first cross-section, the dimension D16 of the outer contour of the first end portion 114p1a and the middle portion 114p1c is smaller than the dimension D11 of the outer contour of the second extension portion b_2.

[0049] refer to Figure 4 In some embodiments, the semiconductor structure further includes a gate structure; the gate structure includes a gate dielectric layer (which can be understood as a fourth dielectric layer 122) and a gate (which can be understood as the first portion 124a of a word line 124); the gate dielectric layer surrounds the outer wall of the first end portion 114p1a and the middle portion 114p1c; the gate surrounds the outer wall of the gate dielectric layer corresponding to the middle portion 114p1c. In this embodiment, a gate-all-around architecture is formed by the gate surrounding the middle portion. The gate-all-around architecture enhances the gate control capability, and the potential of the middle portion is controlled by the gate to form a pinning effect, reducing or avoiding potential fluctuations.

[0050] In some embodiments, the gate dielectric layer comprises an oxide of the semiconductor layer material. Exemplarily, the gate dielectric layer includes, but is not limited to, silicon oxide. In alternative embodiments, the gate dielectric layer may be a high-k dielectric layer with a dielectric constant higher than 3.8, such as aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.; the gate dielectric layer may also be a low-k dielectric layer with a dielectric constant lower than 3.8.

[0051] In some embodiments, the gate material may be a metallic material or a semiconductor conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. For example, the gate material may include tungsten.

[0052] refer to Figure 4In some embodiments, within the first cross-section, the dimension D17 of the outer contour of the gate structure is greater than the dimension D11 of the outer contour of the second extension.

[0053] refer to Figure 4 In some embodiments, the semiconductor structure includes a plurality of semiconductor layers 114p1; the plurality of semiconductor layers 114p1 are arranged in an array along a first direction and a second direction; the semiconductor layers 114p1 extend along a third direction; the semiconductor structure also includes a plurality of word lines 124; the word lines 124 extend along the first direction and are coupled to the middle portion 114p1c of a row of semiconductor layers 114p1; the word lines 124 include a plurality of first portions 124a and a plurality of second portions 124b; the first portions 124a surround the outer sidewall of the corresponding middle portion 114p1c; in the first direction, the second portions 124b connect two adjacent first portions 124a; wherein, in the second direction, the dimension D7 of the first portion 124a is greater than the dimension D8 of the second portion 124b; wherein, in the third direction (which can also be understood as within the second cross section), the dimension D9 of the first portion 124a is greater than the dimension D10 of the second portion 124b.

[0054] In some embodiments, the word line 124 may be made of a metallic material or a semiconductor conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. For example, the word line 124 may be made of tungsten.

[0055] The relative positional relationship between Part 124a and Part 224b can also be found by referring to Figures 1 to 3 As shown. Reference Figure 1 In some embodiments, in the third-party direction, the top surface of the first portion 124a is substantially flush with the top surface of the second portion 124b, and the bottom surface of the first portion 124a is lower than the bottom surface of the second portion 124b. (See reference) Figure 2 In some embodiments, in a third-party orientation, the top surface of the first portion 124a is higher than the top surface of the second portion 124b, and the bottom surface of the first portion 124a is lower than the bottom surface of the second portion 124b. (See reference...) Figure 3 In some embodiments, in the third-party direction, the top surface of the first portion 124a is higher than the top surface of the second portion 124b, and the bottom surface of the first portion 124a is substantially flush with the bottom surface of the second portion 124b. In this document, the term "substantially flush" can be understood as flush within the allowable range of process tolerances.

[0056] refer to Figure 4 In some embodiments, the plurality of semiconductor layers 114p1 are arranged in a hexagonal or rectangular pattern. Specific details regarding the arrangement of the plurality of semiconductor layers 114p1 can also be found in [reference needed]. Figure 7The arrangement of the multiple first holes shown is explained. The arrangement of the multiple semiconductor layers 114p1 can be adaptively selected according to the specific requirements of the process technology. Although Figure 4 The example described uses a hexagonal arrangement of multiple semiconductor layers 114p1 as an example, but this example is not intended to limit the embodiments of this application.

[0057] refer to Figure 4 In some embodiments, the semiconductor structure further includes multiple bit lines 134; the bit lines 134 extend along a second direction and are connected to a column of first extensions b_1. In the embodiments of this application, the area of ​​the first extension is larger than that of the second extension, which can be used to increase the contact area with the bit lines.

[0058] refer to Figure 4 In some embodiments, the semiconductor structure further includes a plurality of bit line contacts 132, and the bit line 134 is connected to the first extension b_1 of the corresponding second end 114p1b through the bit line contacts 132.

[0059] refer to Figure 4 In some embodiments, the materials of bit line contact 132 and bit line 134 can be metallic or semiconductor conductive materials, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of bit line contact 132 includes titanium nitride. Exemplarily, the material of bit line 134 includes titanium nitride.

[0060] refer to Figure 4 In some embodiments, in the first direction, the dimension D14 of the bit line contact 132 is greater than or equal to the dimension D12 of the first extension b_1, and the dimension D15 of the bit line 134 is smaller than the dimension D13 of the inner contour of the second extension b_2. Thus, having a bit line contact dimension greater than or equal to the first extension dimension in the first direction increases the contact area between the bit line contact and the first extension, reducing contact resistance. Furthermore, having a smaller bit line dimension in the first direction results in a larger spacing between adjacent bit lines, reducing coupling between adjacent bit lines and decreasing parasitic capacitance.

[0061] refer to Figure 4 In some embodiments, the semiconductor structure further includes multiple memory cells; the memory cells are connected to the first end 114p1a of the corresponding semiconductor layer; the memory cells are capacitor memory structures 130, phase-change memory structures, resistive switching memory structures, or ferroelectric memory structures. Although Figure 4 The example described uses a capacitor storage structure 130 as the storage cell, but this example is not intended to limit the embodiments of this application.

[0062] In some embodiments, the capacitor storage structure 130 includes a first electrode layer 130a, a dielectric layer 130c, and a second electrode layer 130b. In some embodiments, the materials of the first electrode layer 130a and the second electrode layer 130b include, but are not limited to, metallic materials or semiconductor conductive materials, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicides, nitrides, or any combination thereof. Exemplarily, the materials of the first electrode layer 130a and the second electrode layer 130b include, but are not limited to, titanium nitride. In some embodiments, the materials of the dielectric layer 130c include, but are not limited to, alumina, zirconium oxide, hafnium oxide, etc. Exemplarily, the material of the dielectric layer 130c is hafnium oxide.

[0063] refer to Figure 4 In some embodiments, the semiconductor structure further includes a plurality of memory cell contacts 128; each memory cell contact 128 includes a third portion 128a and a fourth portion 128b; in a first cross-section, the third portion 128a surrounds the outer and inner sidewalls of a portion of the first end portion 114p1a; in a third direction, the fourth portion 128b is located above the third portion 128a and the first end portion 114p1a. Thus, the third portion of the memory cell contact contacts both the outer and inner sidewalls of the portion of the first end portion, which helps to increase the contact area between the memory cell contact and the first end portion and reduce the contact resistance.

[0064] In some embodiments, the material of the third portion 128a may be a metallic material or a semiconductor conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. For example, the material of the third portion 128a includes tungsten. In some embodiments, the material of the fourth portion 128b may be a metallic material or a semiconductor conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. For example, the material of the fourth portion 128b includes polycrystalline silicon.

[0065] Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method provided in this application.

[0066] refer to Figure 5 According to a second aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided, the method comprising the following steps: Step S501: Provide a substrate; Step S502: Remove part of the substrate to form a semiconductor layer; the semiconductor layer includes an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross section intersecting the extension direction of the semiconductor layer, the intermediate portion has an annular shape; wherein, the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the intermediate portion and the first extension; in the first cross section, the first extension has a solid closed shape, the second extension has an annular shape, and the size of the first extension is larger than the outer contour size of the second extension.

[0067] It should be understood that Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be adjusted in order according to actual needs.

[0068] Figures 6A to 6P This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application. Figures 6A to 6P Figure (a) in any of the accompanying figures is a schematic diagram of the semiconductor structure along section AA (see Figure (b), also known as section XZ), and Figure (b) is a schematic diagram of the semiconductor structure along section BB (see Figure (a), also known as section XY). For example, Figure 6A Figure (a) shows the semiconductor structure along section AA (reference). Figure 6A The schematic diagram shown in Figure (b), also known as the XZ section, is as follows. Figure 6A Figure (b) shows the semiconductor structure along the BB section (reference). Figure 6A The diagram shown in Figure (a), also known as the XY section, is a schematic diagram.

[0069] To facilitate the description of the embodiments of this application, the etching (or removal) processes used herein may include wet etching, dry etching, and combinations thereof. For example, plasma etching may be used. The deposition (or filling) processes used herein may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and combinations thereof. For example, plasma-enhanced chemical vapor deposition (PECVD) may be used. The growth processes used herein include, but are not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0070] The following is combined with Figure 5 , Figures 6A to 6P The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail.

[0071] refer to Figure 6A Step S501 is executed to provide a substrate.

[0072] refer to Figure 6A In some embodiments, the substrate 102 may be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc. It may also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), or a stacked structure, such as silicon / silicon-germanium, etc., or other epitaxial structures, such as silicon-germanium-on-insulator (SGOI), etc.

[0073] In some embodiments, the substrate 102 is made of monocrystalline silicon. In this embodiment, etching (e.g., etching silicon to leave silicon as a semiconductor layer) can be used. Compared to other materials (e.g., metal oxide semiconductors), monocrystalline silicon is purer and has a more uniform crystal structure. Compared to etching metal oxide semiconductors, etching monocrystalline silicon makes it easier to form a thinner, hollow, annular semiconductor layer. The hollow, annular semiconductor layer can eliminate charge accumulation and suppress the floating body effect by completely depleting charge carriers.

[0074] refer to Figures 6A to 6I ,as well as, Figures 6M to 6O In some embodiments, a semiconductor layer is formed, including: refer to Figures 6A to 6C On the first side of the substrate, a portion of the substrate is removed to form a first base layer and a plurality of second base layers integrally formed with the first base layer; the plurality of second base layers are arranged in an array along a first direction and a second direction; the second base layers extend along a third direction. refer to Figures 6D to 6I On the first side, a portion of the second substrate layer is removed to form the first end and middle portion of the semiconductor layer; within the first cross-section, the shape of the first end is annular; refer to Figures 6M to 6O On the second side of the substrate, a portion of the first base layer is removed to form a second end of a spaced-apart semiconductor layer; the first extension of the second end includes a retained portion of the first base layer; the second extension of the second end includes a retained portion of the second base layer; the first side and the second side are two opposite sides of the substrate along a third direction.

[0075] refer to Figures 6A to 6C In some embodiments, a first substrate layer and a plurality of second substrate layers integrally formed with the first substrate layer are formed, including: a reference layer. Figure 6A On the first side S1 of the substrate, a portion of the substrate 102 is removed for the first time, forming a plurality of first holes H1 extending into the substrate; Reference Figure 6B And in the first hole H1 (reference) Figure 6A In the process, a columnar structure 108 is formed to fill the first hole H1; Reference Figure 6C In the columnar structure 108 and part of the substrate 102 (reference) Figure 6B On the substrate 102, a first hard mask 110p is formed; based on the first hard mask 110p, a portion of the substrate 102 is removed for the second time to form a first base layer 112 and a plurality of second base layers 114; the second base layers 114 surround the sidewalls of the columnar structure 108.

[0076] refer to Figure 6AThe first photolithography-etching (LE) process can be used to remove a portion of the substrate 102 on the first side S1 to form a plurality of first holes H1. The plurality of first holes H1 are arranged in an array along a first direction and a second direction, and the first holes H1 extend into the substrate 102. Exemplarily, one or more patterning processes can be used to form the plurality of first holes H1. The patterning process includes, but is not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof. It should be noted that, in order to clearly show the first holes H1, Figure 6A Figure (b) does not show the substrate 102 at the bottom of the first hole H1.

[0077] Figure 7 This application provides various array arrangements of multiple first holes in its embodiments. It should be noted that... Figure 7 Figure (a) in the text can be understood as Figure 6A Figure (b) in the middle, Figure 7 Figures (b) and (c) in the text can be understood as being relative to... Figure 7 The diagram in Figure (a) shows other arrangements with different arrangements. Figure 7 The arrangement density of the multiple first holes shown in Figures (a), (b), and (c) decreases sequentially. (Reference) Figure 7 In some embodiments, the plurality of first holes H1 are arranged in a hexagonal pattern. Figure 7 (as shown in Figure (a)) or rectangular arrangement ( Figure 7 (See Figures (b) and (c) in the text). The arrangement of the multiple first holes H1 can be adaptively selected according to the specific requirements of the process. In the following description, the arrangement of the multiple first holes H1 in a hexagonal shape is used as an example, but this example is not intended to limit the embodiments of this application. In some embodiments, within the first cross-section, the shape of the first hole H1 includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments. The shape of the first hole H1 can be adaptively selected according to the specific requirements of the process. In the following description, the arrangement of the first hole H1 in a circle is used as an example, but this example is not intended to limit the embodiments of this application.

[0078] refer to Figure 6B A deposition process can be used to form a filling of the first pore H1 (see reference). Figure 6AThe columnar structure 108 includes a first insulating layer 104 and a second insulating layer 106 situated on top of the first insulating layer 104. In some embodiments, the materials of the first insulating layer 104 and the second insulating layer 106 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. In some embodiments, the materials of the first insulating layer 104 and the second insulating layer 106 are different. Exemplarily, the material of the first insulating layer 104 is silicon oxide, and the material of the second insulating layer 106 is silicon nitride.

[0079] Continue to refer to Figure 6B A deposition process can be used to form a first hard mask material layer 110 covering the top surface of the columnar structure 108 and the top surface of the substrate 102. In some embodiments, the first hard mask material layer 110 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. In some embodiments, the materials of the first hard mask material layer 110 and the second insulating layer 106 are different. Exemplarily, the first hard mask material layer 110 is silicon oxide.

[0080] refer to Figure 6C A second photolithography-etching process can be used to remove part of the first hard mask material layer 110 (see reference). Figure 6B ), forming a first hard mask 110p; and, based on the first hard mask 110p, on the first side S1 (refer to Figure 6A Second removal of part of substrate 102 (reference) Figure 6B A first hard mask 110p forms a first gap GAP1, a first base layer 112, and a plurality of second base layers 114. The second base layers 114 are integrally formed with the first base layer 112 and surround the sidewalls of the columnar structure 108. A first hard mask 110p covers the top surface of the columnar structure 108 and the top surface of the second base layers 114. The first gap GAP1 exposes the sidewalls of the second base layers 114. In a third direction, the second base layer 114 includes a fifth end 114c away from the first base layer 112, a third end 114a close to the first base layer 112, and a fourth end 114b located between the third end 114a and the fifth end 114c. In some embodiments, within a first cross-section, the shape of the first hard mask 110p includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments. The shape of the first hard mask 110p can be adaptively selected according to the specific requirements of the process. In the following description, the first hard mask 110p is circular as an example, but this example is not intended to limit the embodiments of this application.

[0081] In some embodiments, within the first cross-section, the shape of the outer contour of the second base layer 114 is substantially the same as, or may be different from, the shape of the inner contour of the second base layer 114. It should be noted that the shape of the inner contour of the second base layer 114 can be understood as being based on the shape of the first hole H1, and the shape of the outer contour of the second base layer 114 can be understood as being based on the shape of the first hard mask 110p. In some embodiments, within the first cross-section, the shape of the outer contour of the second base layer 114 is substantially the same as the shape of the inner contour of the second base layer 114, which can ensure that the second base layer 114 has a consistent thickness in the circumferential direction. In some embodiments, within the first cross-section, the shape of the outer contour of the second base layer 114 includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments. The shape of the outer contour of the second base layer 114 can be adaptively selected according to the specific requirements of the process. In the following description, a circular outer contour of the second base layer 114 is used as an example, but this example is not intended to limit the embodiments of this application.

[0082] In this document, the term "first section" can be understood as the BB section (also known as the XY section). It should be noted that within the first section, the dimension D2 of the outer contour of the second base layer 114 is greater than the dimension D1 of the columnar structure 108. Dimensions D1 and D2 can be understood as dimensions within the first section along a specific direction, such as the first direction, or the second direction, or other directions. (Appendix) Figure 6C The dimensions D1 and D2 are used as examples to illustrate the dimensions along a first direction within a first cross-section, but this example is not intended to limit the embodiments of this application. In some embodiments, the thickness of the second substrate layer 114 within the first cross-section ranges from 5 nm to 25 nm. Exemplarily, the thickness of the second substrate layer 114 is 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, or 24 nm. Preferably, the thickness of the second substrate layer 114 ranges from 10 nm to 20 nm.

[0083] refer to Figures 6D to 6J In some embodiments, the method of manufacturing the semiconductor structure further includes: forming a plurality of word lines; referencing Figure 6JWord lines 124 extend along a first direction and are coupled to the middle portion of a row of semiconductor layers. Word lines 124 include a plurality of first portions 124a and a plurality of second portions 124b. The first portions 124a surround the outer wall of a corresponding middle portion. In the first direction, the second portions 124b connect two adjacent first portions 124a. In the second direction, the dimension D7 of the first portion 124a is larger than the dimension D8 of the second portion 124b. In some embodiments, in a third direction, the dimension D9 of the first portion 124a is larger than the dimension D10 of the second portion 124b.

[0084] refer to Figures 6D to 6J In some embodiments, multiple word lines are formed, including: references Figures 6D to 6I An isolation structure and word line grooves extending into the isolation structure are formed; the isolation structure is located on a first base layer and at least between the third ends of two adjacent second base layers; the word line groove includes a plurality of first spaces and a plurality of second spaces; the first spaces surround the outer walls of the corresponding fourth ends and fifth ends of the second base layers; in a first direction, the second spaces connect two adjacent first spaces; wherein, in a third direction, the second base layer includes a fifth end away from the first base layer, a third end close to the first base layer, and a fourth end located between the third end and the fifth end; Reference Figure 6H A word line 124 is formed based on the word line trench (also called the second trench T2); the first portion 124a of the word line 124 is located in the first space; the second portion 124b of the word line 124 is located in the second space. In the following description, the isolation structure includes a first dielectric layer and a reserved third dielectric layer; the second trench constitutes the word line trench.

[0085] refer to Figure 6D A deposition process can be used to form GAP1, which fills the first gap (see reference). Figure 6C The first dielectric material layer 116 is a first dielectric material layer. In some embodiments, the first dielectric material layer 116 and the first hard mask 110p are made of different materials. In some embodiments, the first dielectric material layer 116 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. Exemplarily, the first dielectric material layer 116 is silicon nitride.

[0086] refer to Figure 6E An etching process, such as an etch-back process, can be used to remove part of the first dielectric material layer 116 (see reference). Figure 6DA first dielectric layer 116p and a second gap GAP2 are formed; the first dielectric layer 116p includes a retained first dielectric material layer 116; the first dielectric layer 116p is located on the first substrate layer 112 and between the third ends 114a of two adjacent second substrate layers 114; the second gap GAP2 exposes the sidewalls of the fourth ends 114b and the fifth ends 114c of the second substrate layers 114.

[0087] refer to Figure 6F Oxidation processes, such as in-situ steam generation (ISSG), can be used to expose the second gap GAP2 (see reference). Figure 6E The second substrate layer 114 in the second dielectric layer 114 is oxidized in situ to form a second dielectric layer 118 and a third gap GAP3. The second dielectric layer 118 at least covers the surface of the second substrate layer 114 exposed in the second gap GAP2. The third gap GAP3 at least exposes the sidewalls of the second dielectric layer 118. The material of the second dielectric layer 118 may be an oxide of the material of the second substrate layer 114. For example, the material of the second substrate layer 114 is silicon, and the material of the second dielectric layer 118 is silicon oxide.

[0088] In some embodiments, within the first cross-section, the inner contour dimension D3 of the second dielectric layer 118 is smaller than the outer contour dimension D2 of the second base layer 114 (which can also be understood as the outer contour dimension D2 of the third end 114a). In some embodiments, within the first cross-section, the outer contour dimension D4 of the second dielectric layer 118 is larger than the outer contour dimension D2 of the second base layer 114. In some embodiments, within the first cross-section, the thickness of the second dielectric layer 118 ranges from 8 nm to 12 nm. Exemplarily, the thickness of the second dielectric layer 118 is 9 nm, 10 nm, or 11 nm. Preferably, the thickness of the second dielectric layer 118 ranges from 9 nm to 11 nm.

[0089] refer to Figure 6G A deposition process can be used to form GAP3, which fills the third gap (see reference). Figure 6F The third dielectric material layer 120 is a third dielectric material layer. In some embodiments, the material of the third dielectric material layer 120 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. In some embodiments, the materials of the third dielectric material layer 120 and the second dielectric layer 118 are different. Exemplarily, the third dielectric material layer 120 is silicon nitride.

[0090] refer to Figure 6H A photolithography-etching process can be used to remove part of the third dielectric material layer 120 (reference). Figure 6GA third dielectric layer 120p and a plurality of first trenches T1 are formed, the plurality of first trenches T1 being arranged in an array along a first direction and a second direction; wherein, in the first direction, the first trenches T1 expose a portion of the second dielectric layer 118; and in the second direction, the dimension D5 of the first trenches T1 is smaller than the dimension D6 of the outer contour of the fourth end 114b. In some embodiments, in the third direction, the first trenches T1 extend into the third dielectric layer 120p. In an optional embodiment, the first trenches penetrate the third dielectric layer. In some embodiments, during the removal of the third dielectric material layer 120, the first hard mask 110p is partially removed. In an optional embodiment, during the removal of the third dielectric material layer, the first hard mask is completely removed.

[0091] refer to Figure 6I An etching process, such as wet etching, can be used, based on the first trench T1 (see reference). Figure 6H Remove the second dielectric layer 118 (reference) Figure 6H A second trench T2 is formed, comprising a plurality of first spaces T2a and a plurality of second spaces T2b. The first spaces T2a surround the outer walls of corresponding fourth end 114b and fifth end 114c. In a first direction, the second spaces T2b connect adjacent first spaces T2a. In some embodiments, in a third direction, the first spaces T2a pass through the third dielectric layer 120p, and the bottom surfaces of the second spaces T2b extend into the third dielectric layer 120p. In some embodiments, during the removal of the second dielectric layer 118, the retained first hard mask 110p (see reference 110p) is... Figure 6H The second insulating layer may be partially removed during the removal of the second dielectric layer.

[0092] refer to Figure 6J An oxidation process, such as the ISSG process, can be used to expose the second trench T2 (see reference). Figure 6IThe second substrate layer 114 in the first dielectric layer is oxidized in situ to form a fourth dielectric material layer. Exemplarily, the fourth dielectric material layer is silicon oxide. In an optional embodiment, an ALD process can be used to form the fourth dielectric material layer covering the sidewalls of the fourth end and the fifth end. In an optional embodiment, the fourth dielectric material layer can be a high-k dielectric layer with a dielectric constant higher than 3.8, such as aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.; the fourth dielectric material layer can also be a low-k dielectric layer with a dielectric constant lower than 3.8. In some embodiments, after forming the fourth dielectric material layer, the thickness of the first end 114p1a and the middle portion 114p1c ranges from 5 nm to 15 nm. Exemplarily, the thickness of the first end 114p1a and the middle portion 114p1c is 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm. Preferably, the thickness of the first end portion 114p1a and the middle portion 114p1c ranges from 6 nm to 12 nm.

[0093] Continue to refer to Figure 6J A deposition process can be used to form the second trench T2 (refer to) where the fourth dielectric material layer is formed. Figure 6I In ), a first conductive layer is formed ( Figure 6J (Not shown); and, using an etching process, a portion of the first conductive layer is etched back to remove it, forming word lines 124. In an optional embodiment, during the etch-back process of removing a portion of the first conductive layer, due to the loading effect, the removal rate of the first conductive layer located in the second space T2b is greater than that of the first conductive layer located in the first space T2a, resulting in word lines obtained after the etching process; in a third direction, the top surface of the first portion of the word line is higher than the top surface of the second portion of the word line (see reference). Figure 2 or Figure 3 (For understanding). In some embodiments, the word line 124 may be made of a metallic material or a semiconductor conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicide, nitride, or any combination thereof. For example, the material of the word line 124 includes tungsten.

[0094] Continue to refer to Figure 6J A deposition process can be used to form the second trench T2 with the letter 124 (see reference). Figure 6I In ), a fifth dielectric material layer is formed covering the word line 124. Figure 6J (not shown); and, using a planarization process, such as Chemical Mechanical Polishing (CMP), to remove the second insulating layer 106 (see reference). Figure 6I ), part of the fifth end 114c (reference) Figure 6IThe semiconductor layer comprises a first end 114p1a, a middle portion 114p1c, a fourth dielectric layer 122, and a fifth dielectric layer 126, consisting of a fourth dielectric material layer and a fifth dielectric material layer. It should be noted that the first end 114p1a of the semiconductor layer can be understood as a retained fifth end 114c (see reference). Figure 6I The middle part 114p1c of the semiconductor layer can be understood as the fourth end 114b (see reference). Figure 6I The fourth dielectric layer 122 can be understood as a retained fourth dielectric material layer, and the fifth dielectric layer 126 can be understood as a retained fifth dielectric material layer. In some embodiments, the material of the fifth dielectric layer 126 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. Exemplarily, the material of the fifth dielectric layer 126 is silicon nitride.

[0095] refer to Figures 6K to 6P In some embodiments, the method for manufacturing the semiconductor structure further includes: on the first side S1 (referencing...) Figure 6A ), forming multiple memory cells; the memory cells are connected to the first end of the corresponding semiconductor layer; the memory cells are capacitor memory structure 130, phase change memory structure, resistive switching memory structure or ferroelectric memory structure; on the second side S2 (refer to Figure 6A Multiple bit lines 134 are formed; the bit lines 134 extend along the second direction and are connected to the second end of a column of semiconductor layers.

[0096] refer to Figures 6K to 6M In some embodiments, the method for manufacturing the semiconductor structure further includes: referencing Figure 6K This forms a third space T3; the third space T3 exposes part of the outer and inner walls of the first end; reference Figure 6L In the third space, a third portion 128a is formed to contact the storage cell; within the first cross-section, the third portion 128a surrounds the outer and inner walls of the partial first end portion 114p1a; Reference Figure 6M A fourth portion 128b is formed on top of the third portion 128a and the first end 114p1a, forming the memory cell contact 128; Reference Figure 6M A capacitor storage structure 130 is formed on the storage cell contact 128.

[0097] refer to Figure 6K An etching process, such as a wet etching process, can be used to remove part of the fourth dielectric layer 122 and part of the first insulating layer 104 to form a third space T3; the third space T3 exposes part of the outer and inner sidewalls of the first end 114p1a.

[0098] refer to Figure 6L A deposition process can be used in the third space T3 (reference). Figure 6KIn the process of forming the third part 128a, the contact between the memory cells is formed. The material selection for the third part 128a can be referred to the relevant description in the first aspect, and will not be repeated here.

[0099] refer to Figure 6M A deposition process can be used to form a fourth portion 128b of the memory cell contact 128 on top of the third portion 128a and the first end portion 114p1a. The material selection for the fourth portion 128b can be referred to the relevant description in the first aspect, and will not be repeated here.

[0100] In this way, the third part of the storage cell contact is in contact with both the outer and inner sidewalls of the first end, which helps to increase the contact area between the storage cell contact and the first end and reduce the contact resistance.

[0101] Continue to refer to Figure 6M In some embodiments, forming the capacitor storage structure 130 includes sequentially forming a first electrode layer 130a, a dielectric layer 130c, and a second electrode layer 130b. The material selection for the first electrode layer 130a, the dielectric layer 130c, and the second electrode layer 130b can be referred to the relevant description in the first aspect, and will not be repeated here.

[0102] refer to Figure 6N A bonding process can be used, on the first side S1 (reference). Figure 6A ), semiconductor structure 100 (reference) Figure 6M ) is bonded to the carrier wafer 200, exposing the second side S2 of the semiconductor structure 100 (reference) Figure 6A The structure forms bit lines 134 on the second side S2 of the semiconductor structure 100. In some embodiments, the carrier wafer 200 may be retained, removed, or partially removed. The retention, removal, or partial removal of the carrier wafer 200 can be adaptively selected according to the specific requirements of the process. For example, a debonding process can be used to remove the carrier wafer 200.

[0103] Continue to refer to Figure 6N A removal process, such as CMP, can be used to thin the first substrate layer 112.

[0104] refer to Figure 6O The photolithography-etching process can be used to remove part of the thinned first substrate layer 112 to form the second end 114p1b of the semiconductor layer 114p1.

[0105] In some embodiments, the semiconductor layer 114p1 includes an integrally formed first end portion 114p1a, a second end portion 114p1b, and an intermediate portion 114p1c located between the first end portion 114p1a and the second end portion 114p1b; in a first cross section, the intermediate portion 114p1c has an annular shape; wherein, the second end portion 114p1b includes a first extension portion b_1 and a second extension portion b_2; the first extension portion b_1 extends along a first direction and a second direction; the second extension portion b_2 extends along a third direction to connect the intermediate portion 114p1c and the first extension portion b_1; in the first cross section, the first extension portion b_1 has a solid closed shape, the second extension portion b_2 has an annular shape, and the dimension D12 of the first extension portion b_1 is larger than the outer contour dimension D11 of the second extension portion b_2.

[0106] refer to Figure 6P In some embodiments, the method of manufacturing the semiconductor structure further includes: forming a bit line on a second side; the bit line extending along a second direction.

[0107] refer to Figure 6P Multiple bit lines 134 can be formed using a photolithography-etching process. It should be noted that, to clearly show the relative positional relationship between bit lines 134 and word lines 124, [the following text is missing from the original] Figure 6P The perspective view in diagram (b) shows the position of the bit line.

[0108] Continue to refer to Figure 6P In some embodiments, before forming multiple bit lines 134, the method of manufacturing the semiconductor structure further includes: on the second side S2 (refer to...) Figure 6A Multiple bit line contacts 132 are formed, and each bit line contact 132 is connected to the first extension b_1 of the corresponding second end 114p1b. The material selection for the bit line 134 and bit line contacts 132 can be referred to the relevant description in the first aspect, and will not be repeated here. In some embodiments, in the first direction, the dimension D14 of the bit line contact 132 is greater than or equal to the dimension D12 of the first extension b_1, and the dimension D15 of the bit line 134 is smaller than the dimension D13 of the inner contour of the second extension b_2. Thus, in the first direction, the bit line dimensions are smaller, and the spacing between adjacent bit lines is larger, which can reduce the coupling between adjacent bit lines and reduce parasitic capacitance.

[0109] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in this application is similar to the semiconductor structure in the embodiments of the first aspect above. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0110] Thirdly, embodiments of this application provide a memory, the memory comprising: any of the semiconductor structures provided in the first aspect, or a semiconductor structure obtained according to any of the manufacturing methods provided in the second aspect; word lines of the semiconductor structure are configured to receive word line voltages and control the conduction or cutoff of the middle portion of the semiconductor layer of the semiconductor structure by means of word line voltages, for connecting / disconnecting the first end and the second end of the semiconductor layer of the semiconductor structure; bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the middle portion of the semiconductor layer is turned on.

[0111] For example, the semiconductor structure includes: a semiconductor layer including an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross-section intersecting the extension direction of the semiconductor layer, the intermediate portion has an annular shape; wherein the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the intermediate portion and the first extension; in the first cross-section, the first extension has a solid closed shape, the second extension has an annular shape, and the size of the first extension is larger than the outer contour size of the second extension.

[0112] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0113] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor layer includes an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; In a first cross section intersecting the extension direction of the semiconductor layer, the shape of the middle portion is annular; wherein, the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the middle portion and the first extension; in the first cross section, the shape of the first extension is a solid closed shape, the shape of the second extension is annular, and the size of the first extension is larger than the outer contour size of the second extension.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer is made of monocrystalline silicon.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the intermediate portion ranges from 5 nm to 15 nm.

4. The semiconductor structure according to claim 1, characterized in that, The concentration of P-type or N-type dopant elements in the material of the intermediate portion is inversely correlated with the thickness of the intermediate portion.

5. The semiconductor structure according to claim 1, characterized in that, Within the first cross-section, the outer contour of the middle portion includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments; the inner contour of the middle portion includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments.

6. The semiconductor structure according to claim 5, characterized in that, Within the first cross section, the shape of the outer contour of the middle part is substantially the same as the shape of the inner contour of the middle part, and includes a circle, an ellipse or a square.

7. The semiconductor structure according to claim 1, characterized in that, Within the first cross-section, the dimensions of the outer contours of the first end and the middle portion are smaller than the dimensions of the outer contour of the second extension.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a gate structure; the gate structure surrounds the outer wall of the middle portion; within the first cross-section, the dimension of the outer contour of the gate structure is greater than the dimension of the outer contour of the second end.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a plurality of semiconductor layers; the plurality of semiconductor layers are arranged in an array along a first direction and a second direction; the semiconductor structure also includes a plurality of word lines; the word lines extend along the first direction and are coupled to the middle portion of a row of semiconductor layers; the word lines include a plurality of first portions and a plurality of second portions; the first portions surround the outer sidewall of the corresponding middle portion; in the first direction, the second portions connect two adjacent first portions; In the second direction, the size of the first part is larger than the size of the second part; in the third direction, the size of the first part is larger than the size of the second part.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor layers are arranged in a hexagonal or rectangular pattern.

11. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure further includes multiple bit lines; the bit lines extend along the second direction and are connected to a column of the first extensions.

12. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure further includes multiple memory cells; each memory cell is connected to the first end of the corresponding semiconductor layer; the memory cell is a capacitor memory structure, a phase change memory structure, a resistive switching memory structure, or a ferroelectric memory structure.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure further includes a plurality of memory cell contacts; the memory cell contacts include a third portion and a fourth portion; within the first cross section, the third portion surrounds the outer sidewall and inner sidewall of a portion of the first end; in the third direction, the fourth portion is located above the third portion and the first end.

14. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A portion of the substrate is removed to form a semiconductor layer; the semiconductor layer includes an integrally formed first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross-section intersecting the extension direction of the semiconductor layer, the intermediate portion is annular in shape; wherein, the second end includes a first extension and a second extension; the first extension extends along a first direction and a second direction; the second extension extends along a third direction to connect the intermediate portion and the first extension; in the first cross-section, the first extension is solid and closed, the second extension is annular in shape, and the size of the first extension is larger than the outer contour size of the second extension.

15. The manufacturing method according to claim 14, characterized in that, The formation of the semiconductor layer includes: On a first side of the substrate, a portion of the substrate is removed to form a first base layer and a plurality of second base layers integrally formed with the first base layer; the plurality of second base layers are arranged in an array along the first direction and the second direction; the second base layers extend along the third direction. On the first side, a portion of the second substrate layer is removed to form the first end and the middle portion of the semiconductor layer; within the first cross-section, the shape of the first end is annular; On the second side of the substrate, a portion of the first base layer is removed to form the second ends of the semiconductor layers spaced apart from each other; the first extension of the second end includes a retained portion of the first base layer; the second extension of the second end includes a retained portion of the second base layer; the first side and the second side are two opposite sides of the substrate along the third direction.

16. The manufacturing method according to claim 15, characterized in that, The formation of the first base layer and the plurality of second base layers integrally formed with the first base layer includes: On the first side, a portion of the substrate is removed for the first time to form a plurality of first holes extending into the substrate; and In the first hole, a columnar structure is formed to fill the first hole; A first hard mask is formed on the columnar structure and part of the substrate; Based on the first hard mask, a second portion of the substrate is removed to form the first base layer and a plurality of second base layers; the second base layers surround the sidewalls of the columnar structure.

17. The manufacturing method according to claim 16, characterized in that, The manufacturing method further includes: Multiple word lines are formed; the word lines extend along the first direction and are coupled to the middle portion of a row of semiconductor layers; the word lines include multiple first portions and multiple second portions; the first portions surround the outer sidewall of the corresponding middle portion; in the first direction, the second portions connect two adjacent first portions; In the second direction, the size of the first part is larger than the size of the second part; in the third direction, the size of the first part is larger than the size of the second part.

18. The manufacturing method according to claim 17, characterized in that, The formation of multiple character lines includes: An isolation structure and word line grooves extending into the isolation structure are formed; the isolation structure is located on the first base layer and at least between the third ends of two adjacent second base layers; the word line grooves include a plurality of first spaces and a plurality of second spaces; the first spaces surround the outer walls of the corresponding fourth ends and fifth ends of the second base layers; in the first direction, the second spaces connect two adjacent first spaces; wherein, in the third direction, the second base layer includes a fifth end away from the first base layer, a third end close to the first base layer, and a fourth end located between the third end and the fifth end; The word line is formed based on the word line groove; the first portion of the word line is located in the first space; the second portion of the word line is located in the second space.

19. The manufacturing method according to claim 18, characterized in that, The manufacturing method further includes: A third space is formed; the third space exposes a portion of the outer and inner walls of the first end. In the third space, a third portion is formed for the contact of the storage cell; within the first cross-section, the third portion surrounds the outer and inner sidewalls of the portion of the first end. A fourth portion is formed above the third portion and the first end, to form the contact of the storage cell; A capacitor storage structure is formed on the contacts of the storage cell.

20. The manufacturing method according to claim 15, characterized in that, The manufacturing method further includes: On the second side, a bit line is formed; the bit line extends along the second direction.

21. The manufacturing method according to claim 14, characterized in that, The provision of the substrate includes: The substrate is provided; the material of the substrate includes monocrystalline silicon.

22. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 13, or the semiconductor structure obtained by the manufacturing method according to any one of claims 14 to 21; The word line of the semiconductor structure is configured to receive a word line voltage and control the conduction or cutoff of the middle part of the semiconductor layer of the semiconductor structure through the word line voltage, for connecting / disconnecting the first end and the second end of the semiconductor layer of the semiconductor structure. The bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the middle portion of the semiconductor layer is turned on.

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