Semiconductor structure, manufacturing method thereof and memory

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure includes a semiconductor layer including a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with the extending direction of the semiconductor layer, the middle part is annular, and the size of the outer side outline of the middle part is smaller than that of the outer side outline of the first end part and / or smaller than that of the outer side outline of the second end part. According to the invention, the purpose of inhibiting the floating body effect can be achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] As the integration of semiconductor devices increases and their size continues to shrink, the power consumption, density, and mobility of transistors in semiconductor devices, such as Dynamic Random Access Memory (DRAM), are limited after the transistor feature size is reduced to the nanoscale, posing a greater challenge to improving transistor performance. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for manufacturing the same, and a memory. This application achieves the goal of suppressing the buoyancy effect.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure comprising: a semiconductor layer including a first end, a second end, and an intermediate portion located between the first end and the second end; in a first cross-section intersecting the extension direction of the semiconductor layer, the intermediate portion is annular in shape, and the size of the outer contour of the intermediate portion is smaller than the size of the outer contour of the first end, and / or smaller than the size of the outer contour of the second end.

[0005] In some embodiments, the semiconductor layer is made of metal oxide semiconductor.

[0006] In some embodiments, the thickness of the middle portion within the first cross-section ranges from 5 nm to 25 nm.

[0007] In some embodiments, within the first cross-section, the shape of the outer contour of the middle portion includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments.

[0008] In some embodiments, within the first cross section, the outer contour dimension of the middle portion is smaller than the outer contour dimension of the first end portion and the outer contour dimension of the second end portion, and the difference between the outer contour dimension of the first end portion or the outer contour dimension of the second end portion and the outer contour dimension of the middle portion ranges from 16 nm to 24 nm.

[0009] In some embodiments, the semiconductor structure further includes a gate structure; the gate structure includes a gate dielectric layer and a gate; the gate dielectric layer surrounds the outer wall of the semiconductor layer; the gate surrounds the outer wall of the gate dielectric layer corresponding to the middle portion; within a first cross section, the size of the outer contour of the gate structure is greater than the size of the outer contour of the first end and the size of the outer contour of the second end.

[0010] In some embodiments, the material of the gate dielectric layer comprises a dielectric material with a dielectric constant higher than 3.8.

[0011] In some embodiments, the semiconductor structure comprises a plurality of semiconductor layers; the plurality of semiconductor layers are arranged in an array along a first direction and a second direction; the semiconductor layers extend along a third direction; the semiconductor structure further comprises a plurality of word lines; the word lines extend along the first direction and are coupled to middle portions of a row of the semiconductor layers; the word lines comprise a plurality of first portions and a plurality of second portions; the first portions surround outer sidewalls of the corresponding middle portions; in the first direction, the second portions connect two adjacent first portions; and in the second direction, a size of the first portion is greater than a size of the second portion.

[0012] In some embodiments, the plurality of semiconductor layers are arranged in a hexagonal pattern or a rectangular pattern.

[0013] In some embodiments, the semiconductor structure further comprises a plurality of bit lines; the bit lines extend along the second direction and are connected to second end portions of a column of the semiconductor layers; in a second cross section parallel to the extending direction of the semiconductor layers, the second end portions have a U shape; and the bit lines are connected to the bottom of the U shape.

[0014] In some embodiments, the semiconductor structure further comprises a plurality of memory cells; the memory cells are connected to the first end portions of the corresponding semiconductor layers; and the memory cells are capacitive memory structures, phase change memory structures, resistive memory structures, or ferroelectric memory structures.

[0015] In a second aspect, the embodiments of the present application provide a manufacturing method of a semiconductor structure, the manufacturing method comprising: providing a substrate structure; removing part of the substrate structure to form semiconductor layers; the semiconductor layers comprise first end portions, second end portions, and middle portions between the first end portions and the second end portions; in a first cross section intersecting the extending direction of the semiconductor layers, the middle portions have a ring shape, and an outer contour of the middle portions has a size smaller than an outer contour of the first end portions and / or an outer contour of the second end portions.

[0016] In some embodiments, the providing the substrate structure comprises: providing a substrate; forming, on the substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in sequence; and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

[0017] In some embodiments, the forming the semiconductor layers comprises: removing part of the substrate structure on a first side of the substrate structure to form a plurality of first holes passing through the first dielectric layer, the second dielectric layer, and the third dielectric layer; and forming the semiconductor layers in the first holes; the semiconductor layers cover the sidewalls and the bottom surface of the first holes; and the plurality of semiconductor layers are arranged in an array along a first direction and a second direction; and the semiconductor layers extend along a third direction.

[0018] In some embodiments, forming the plurality of first holes comprises: removing portions of the base structure at the first side of the base structure to form a plurality of second holes through the first dielectric layer, the second dielectric layer, and the third dielectric layer; forming a fourth dielectric layer in the second holes to obtain the first holes; the fourth dielectric layer is on a surface of the second dielectric layer exposed in the second holes; and in the first cross section, the fourth dielectric layer has a shape of a ring, and an inner profile of the fourth dielectric layer has a size smaller than a size of an inner profile of the first dielectric layer exposed in the first holes and a size of an inner profile of the third dielectric layer.

[0019] In some embodiments, the manufacturing method further comprises: sequentially forming a fifth dielectric layer and a semiconductor layer covering sidewalls and a bottom surface of the first holes; removing portions of the fifth dielectric layer at a bottom of the semiconductor layer at the second side of the base structure to form a gate dielectric layer; the gate dielectric layer encircles an outer sidewall of the semiconductor layer; the first side and the second side are two opposite sides of the base structure along the third direction.

[0020] In some embodiments, the manufacturing method further comprises: forming a plurality of word lines; the word lines extend along the first direction and are coupled to the middle portions of the row of semiconductor layers; the word lines comprise a plurality of first portions and a plurality of second portions; the first portions encircle the outer sidewalls of the corresponding middle portions; in the first direction, the second portions connect two adjacent first portions; and in the second direction, the first portions have a size larger than a size of the second portions.

[0021] In some embodiments, forming the plurality of word lines comprises: removing portions of the third dielectric layer and portions of the second dielectric layer to form a plurality of first trenches; in the first direction, the first trenches expose portions of the fourth dielectric layer; in the second direction, the first trenches have a size smaller than a size of the outer profile of the middle portions; removing the fourth dielectric layer based on the first trenches to form second trenches; the second trenches comprise a plurality of first spaces and a plurality of second spaces; the first spaces encircle the fifth dielectric layer of the first end portions and the middle portions; in the first direction, the second spaces connect two adjacent first spaces; forming a first conductive layer in the second trenches; removing portions of the first conductive layer to form the word lines; the first portions are in the first spaces; and the second portions are in the second spaces.

[0022] In some embodiments, before forming the first conductive layer, the manufacturing method further comprises: forming a sixth dielectric layer in the second trenches, the sixth dielectric layer is on a surface of the second dielectric layer exposed in the second trenches; and forming the first conductive layer based on the second trenches with the sixth dielectric layer.

[0023] In some embodiments, the manufacturing method further comprises: forming a plurality of memory cells on the first side of the base structure; the memory cells are connected with the first end portions of the corresponding semiconductor layers; the memory cells are capacitive memory structures, phase change memory structures, resistive memory structures, or ferroelectric memory structures; forming a plurality of bit lines on the second side of the base structure; the bit lines extend along the second direction and are connected with the second end portions of the column of semiconductor layers.

[0024] In some embodiments, the forming the plurality of bit lines comprises: removing the substrate and part of the fifth dielectric layer to expose the bottom of the semiconductor layer; and forming the bit lines connected with the bottom of the semiconductor layer.

[0025] In a third aspect, the embodiments of the present application provide a memory, comprising: any of the semiconductor structures provided in the first aspect, or a semiconductor structure obtained by the manufacturing method provided in the second aspect; the word line of the semiconductor structure is configured to receive a word line voltage and control the conduction or cutoff of the middle portion of the semiconductor layer of the semiconductor structure by the word line voltage, for connecting / disconnecting the first end portion and the second end portion of the semiconductor layer of the semiconductor structure; the bit line of the semiconductor structure is configured to perform a read or write operation on the memory cell of the semiconductor structure when the middle portion of the semiconductor layer is in conduction.

[0026] In the embodiments of the present application, the middle portion of the semiconductor layer is in a hollow annular film structure, and during operation, the carriers can be fully depleted, which can eliminate the accumulation of charges and thus achieve the purpose of suppressing the floating body effect; the size of the outer profile of the middle portion of the semiconductor layer is smaller than the size of the outer profile of the first end portion of the semiconductor layer, and / or smaller than the size of the outer profile of the second end portion of the semiconductor layer, which can increase the number of memory cells per unit density. That is, the semiconductor structure provided in the embodiments of the present application can increase the number of memory cells per unit density while achieving the purpose of suppressing the floating body effect. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 A three-dimensional perspective schematic diagram and a cross-sectional schematic diagram of a first semiconductor structure provided in the embodiments of the present application; FIG. 2 A three-dimensional perspective schematic diagram and a cross-sectional schematic diagram of a second semiconductor structure provided in the embodiments of the present application; FIG. 3 A plurality of cross-sectional schematic diagrams of a third semiconductor structure provided in the embodiments of the present application; FIG. 4 A plurality of cross-sectional schematic diagrams of a fourth semiconductor structure provided in the embodiments of the present application; FIG. 5 An implementation flowchart of a manufacturing method of a semiconductor structure provided in the embodiments of the present application; FIGS. 6A-6L A cross-sectional schematic view of a manufacturing process of a semiconductor structure is provided for embodiments of the present application. FIG. 7 Different array arrangement manners of the plurality of second holes are provided for embodiments of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the embodiments of the present application and the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one intervening element or layer can exist. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0032] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] For a thorough understanding of the present application, reference will be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] The floating body effect causes the accumulation of carriers (e.g., holes) in the channel region of a transistor in a semiconductor device such as a DRAM, which has a relatively thick channel region (e.g., a solid channel region), to adversely affect the threshold voltage and the off-state current of the device, increasing the off-state current and reducing the performance of the device. For example, a transistor having a relatively thick body region that forms a floating body structure because the body region is not electrically connected, the floating body effect of the thick body region causes the off-state current of the device to increase, and the accumulation of carriers generated during the operation of the transistor cannot be effectively discharged, resulting in fluctuations in the potential and a shift in the threshold voltage.

[0036] FIG. 1 A three-dimensional perspective view and a cross-sectional view of a first semiconductor structure according to an embodiment of the present application. FIG. 2 A three-dimensional perspective view and a cross-sectional view of a second semiconductor structure according to an embodiment of the present application. FIG. 1 and FIG. 2Fig. 1(a) of any of the accompanying drawings is a three-dimensional perspective view of a semiconductor structure, and Fig. 1(b) of any of the accompanying drawings is a cross-sectional view of the semiconductor structure along the X-Z section shown in Fig. 1(a). It should be noted that, in order to clearly show the first end portion of the semiconductor layer and the first insulating layer, only a portion of the gate dielectric layer, a portion of the first end portion, and a portion of the second end portion are shown in Fig. 1(a). FIG. 1 and FIG. 2 In Fig. 1(a) of any of the accompanying drawings, only a portion of the gate dielectric layer, a portion of the first end portion, and a portion of the second end portion are shown.

[0037] FIG. 3 Fig. 2 of the accompanying drawings is a plurality of cross-sectional views of a third semiconductor structure provided by an embodiment of the present application. FIG. 4 Fig. 3 of the accompanying drawings is a plurality of cross-sectional views of a fourth semiconductor structure provided by an embodiment of the present application. FIG. 3 and FIG. 4 Fig. 1(a) of any of the accompanying drawings is a schematic view of a semiconductor structure along the A-A section (also referred to as the X-Z section, as shown in Fig. 1(b)), and Fig. 1(b) of any of the accompanying drawings is a schematic view of the semiconductor structure along the B-B section (also referred to as the X-Y section, as shown in Fig. 1(a)). It should be noted that, in order to clearly show the relative position relationship between the bit line and the word line, only a portion of the gate dielectric layer, a portion of the first end portion, and a portion of the second end portion are shown in Fig. 1(a). FIG. 3 and FIG. 4 In Fig. 1(b) of any of the accompanying drawings, the position of the bit line is shown in perspective.

[0038] Referring to FIGS. 1-4 According to a first aspect of an embodiment of the present application, a semiconductor structure is provided, and the semiconductor structure comprises: a semiconductor layer 114p1, comprising a first end portion 114p1a, a second end portion 114p1b, and an intermediate portion 114p1c located between the first end portion 114p1a and the second end portion 114p1b; in a first section intersecting the extension direction of the semiconductor layer 114p1, the intermediate portion 114p1c has a ring shape, and the size of the outer contour of the intermediate portion 114p1c is smaller than the size of the outer contour of the first end portion 114p1a, and / or, smaller than the size of the outer contour of the second end portion 114p1b. In the present embodiment, the intermediate portion of the semiconductor layer has a hollow ring film structure, and during operation, the carriers can be fully depleted, and the accumulation of electric charges can be eliminated, thereby achieving the purpose of suppressing the floating body effect; the size of the outer contour of the intermediate portion of the semiconductor layer is smaller than the size of the outer contour of the first end portion of the semiconductor layer, and / or, smaller than the size of the outer contour of the second end portion of the semiconductor layer, which can increase the storage units per unit density. That is, the semiconductor structure provided by the present embodiment can increase the storage units per unit density while achieving the purpose of suppressing the floating body effect.

[0039] For the convenience of describing the embodiments of the present application, the first direction and the second direction can be understood as two intersecting (e.g., orthogonal) directions parallel to the plane of the substrate (or the base structure), for example, the first direction can be understood as the extension direction of the word line, and the second direction can be understood as the extension direction of the bit line; the third direction can be understood as a direction intersecting (e.g., orthogonal) to the plane of the substrate (or the base structure), for example, the third direction can be understood as the extension direction of the semiconductor layer (or the stacking direction of the layers of the base structure). Exemplarily, the first direction can be represented as the X direction in the drawings; the second direction can be represented as the Y direction in the drawings; and the third direction can be represented as the Z direction in the drawings; any two of the X direction, the Y direction and the Z direction are orthogonal to each other.

[0040] Herein, the top surface and the bottom surface of an element, a component, a region, a layer or a portion can be understood as two opposite surfaces of an element, a component, a region, a layer or a portion in the third direction. For example, the top surface of the first portion 124a can be understood as a surface of the first portion 124a close to the first end portion 114p1a in the third direction, and the bottom surface of the first portion 124a can be understood as another surface of the first portion 124a away from the first end portion 114p1a in the third direction.

[0041] Herein, the term "first cross section" can be understood as the B-B cross section (also referred to as the X-Y cross section). Herein, the term "second cross section" can be understood as the A-A cross section (also referred to as the X-Z cross section).

[0042] Reference FIG. 1 and FIG. 2 In some embodiments, the material of the semiconductor layer 114p1 includes a metal oxide semiconductor. Exemplarily, the material of the semiconductor layer 114p1 includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tungsten Oxide (IWO), Indium Tin Oxide (ITO), indium-zinc oxide (IZO). In some embodiments, the material of the semiconductor layer 114p1 includes at least one of Gallium Arsenic (GaAs), Indium Gallium Arsenic (InGaAs). Compared with a semiconductor layer composed of a silicon material, a semiconductor layer composed of a metal oxide semiconductor can reduce floating body effect.

[0043] In the embodiments of the present application, a thin thickness of the metal oxide semiconductor can be formed by a plating film (or deposition material) in a better way, and compared with an etching (for example, silicon or silicon germanium reserved after etching silicon or silicon germanium to form a semiconductor layer), the process is simpler; based on the thin thickness of the metal oxide semiconductor, the carrier can be fully depleted, the charge accumulation can be eliminated, and the floating body effect can be inhibited.

[0044] Reference FIG. 1 and FIG. 2 In some embodiments, in the first cross section, the thickness of the intermediate portion 114p1c ranges from 5 nm to 25 nm. For example, the thickness of the intermediate portion 114p1c is 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm or 24 nm. Preferably, the thickness of the intermediate portion 114p1c ranges from 10 nm to 20 nm.

[0045] In optional embodiments, the material of the intermediate portion 114p1c includes single crystal silicon, and the concentration value of the P-type or N-type doping element in the material of the intermediate portion 114p1c is inversely related to the thickness value of the intermediate portion 114p1c. For example, the higher the concentration value of the P-type doping element (for example, doping boron element) in the material of the intermediate portion 114p1c, the higher the threshold voltage of the N-type transistor can be formed, and then the thickness value of the intermediate portion 114p1c needs to be controlled to be thinner. For example, the higher the concentration value of the N-type doping element (for example, doping phosphorus element) in the material of the intermediate portion 114p1c, the lower the threshold voltage of the P-type transistor can be formed, and then the thickness value of the intermediate portion 114p1c needs to be controlled to be thinner.

[0046] Reference FIG. 1 and FIG. 2 In some embodiments, in the first cross section, the shape of the outer profile of the intermediate portion 114p1c includes a circular shape, an elliptical shape, a rectangular shape, a parallelogram shape, a trapezoidal shape, or a closed shape composed of an arc segment and a line segment. In the first cross section, the shape of the outer profile of the intermediate portion 114p1c can be adaptively selected according to the specific needs of the process. Although FIGS. 1-4 The shape of the outer profile of the intermediate portion 114p1c is circular as an example, but this example is not used to limit the embodiments of the present application. It should be noted that in the first cross section, the shape of the semiconductor layer is a ring shape, which can be understood as at least the shape of the intermediate portion of the semiconductor layer is a ring shape. For example, referring to FIG. 1 and FIG. 2In some embodiments, the first end portion, the middle portion and the second end portion of the semiconductor layer are all ring-shaped. In alternative embodiments, the first end portion, the middle portion and the second end portion of the semiconductor layer are all circular-shaped.

[0047] Referring to FIG. 1 and FIG. 2 In some embodiments, in the first cross-section, the outer lateral profile of the middle portion 114plc is smaller than the outer lateral profile of the first end portion 114pla and the outer lateral profile of the second end portion 114plb, and the difference between the outer lateral profile of the first end portion 114pla or the outer lateral profile of the second end portion 114plb and the outer lateral profile of the middle portion 114plc is in the range of 2 times Dx (as shown in FIG. 1C) ranging from 16 nm to 24 nm. FIG. 1 and FIG. 2 Exemplarily, the value of 2 times Dx is 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm or 23 nm. Preferably, the value of 2 times Dx is in the range of 19 nm to 21 nm.

[0048] Referring to FIG. 1 and FIG. 2 In some embodiments, the semiconductor structure further comprises a gate structure; the gate structure comprises a gate dielectric layer 112p2 and a gate electrode (which can be understood as a first portion 124a of the word line 124); the gate dielectric layer 112p2 surrounds the outer lateral wall of the semiconductor layer 114pl; the gate electrode surrounds the outer lateral wall of the gate dielectric layer 112p2 corresponding to the middle portion 114plc. In the embodiments of the present application, a Gate-All-Around architecture is formed by the gate electrode surrounding the middle portion, and the Gate-All-Around architecture enhances the gate control capability, and the potential of the middle portion is controlled by the gate electrode to form a pinning effect, thereby reducing or avoiding potential floating.

[0049] Referring to FIG. 1 and FIG. 2 In some embodiments, in the first cross-section, the outer lateral profile of the gate structure has a size D16 which is larger than the outer lateral profile of the first end portion 114pla and the outer lateral profile of the second end portion 114plb.

[0050] Referring to FIG. 3 and FIG. 4In some embodiments, the material of the gate dielectric layer 112p2 includes a dielectric material with a dielectric constant higher than 3.8. In some embodiments, the gate dielectric layer 112p2 can be a high-k dielectric layer with a dielectric constant higher than 3.8. The material of the gate dielectric layer 112p2 includes, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. Illustratively, the material of the gate dielectric layer 112p2 is hafnium oxide. In alternative embodiments, the gate dielectric layer 112p2 can be a silicon oxide or a low-k dielectric layer with a dielectric constant lower than 3.8. Illustratively, the material of the gate dielectric layer 112p2 is silicon oxide.

[0051] Referring to FIG. 3 and FIG. 4 In some embodiments, the semiconductor structure includes a plurality of semiconductor layers 114p1; the plurality of semiconductor layers 114p1 are arranged in an array along a first direction and a second direction; the semiconductor layers 114p1 extend along a third direction; the semiconductor structure further includes a plurality of word lines 124; the word lines 124 extend along the first direction and are coupled to a middle portion 114p1c of a row of the semiconductor layers 114p1; the word lines 124 include a plurality of first portions 124a and a plurality of second portions 124b; the first portions 124a encircle an outer sidewall of a corresponding middle portion 114p1c; in the first direction, the second portions 124b connect two adjacent first portions 124a; and in the second direction, a dimension D11 of the first portions 124a is greater than a dimension D12 of the second portions 124b.

[0052] In some embodiments, the material of the word lines 124 can be a metallic material or a semiconducting conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof, etc. Illustratively, the material of the bit line contact 132 includes titanium nitride. Illustratively, the material of the word lines 124 includes tungsten.

[0053] Referring to FIG. 7 and FIGS. 3-4 In some embodiments, the plurality of semiconductor layers 114p1 are arranged in a hexagonal array or a rectangular array. The specific arrangement of the plurality of semiconductor layers 114p1 can also be understood with reference to the specific arrangement of the plurality of second holes shown in FIG. 3 The specific arrangement of the plurality of semiconductor layers 114p1 can be adaptively selected according to the specific requirements of the process procedure. Although FIG. 4 the specific arrangement of the plurality of semiconductor layers 114p1 is illustrated as a hexagonal array in the embodiments of the present application, the embodiments of the present application are not limited thereto.

[0054] Referring to FIG. 3 and FIG. 4In some embodiments, the semiconductor structure further comprises a plurality of bit lines 134; the bit lines 134 extend along the second direction and are connected with the second end portions 114p1b of the semiconductor layers 114p1 in the column; wherein, in the second cross section parallel to the extending direction of the semiconductor layers 114p1, the second end portions 114p1b are in the shape of U; and the bit lines 134 are connected with the bottom of the U. In the embodiments of the present application, in the second cross section, the second end portions are in the shape of U, and the bottom of the U has a larger area, which can be used to increase the contact area between the second end portions of the semiconductor layers and the bit lines.

[0055] Reference is made to FIG. 3 and FIG. 4 In some embodiments, the semiconductor structure further comprises a plurality of bit line contacts 132, and the bit lines 134 are connected with the second end portions 114p1b of the corresponding semiconductor layers 114p1 through the bit line contacts 132.

[0056] In some embodiments, the material of the bit line contacts 132 and the material of the bit lines 134 can be metal materials or semiconductor conductive materials, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof, etc. Illustratively, the material of the bit line contacts 132 comprises titanium nitride. Illustratively, the material of the bit lines 134 comprises titanium nitride.

[0057] In some embodiments, in the first direction, the size D33 of the bit line contacts 132 is greater than the size D32 of the outer profile of the semiconductor layers 114p1, and the size D34 of the bit lines 134 is less than the size D31 of the inner profile of the semiconductor layers 114p1. In this way, in the first direction, the size of the bit line contacts is greater than or equal to the size of the first extending portions, which can increase the contact area between the bit line contacts and the first extending portions and reduce the contact resistance; and in the first direction, the size of the bit lines is smaller, and the spacing between two adjacent bit lines is larger, which can reduce the coupling between the two adjacent bit lines and reduce the parasitic capacitance.

[0058] Reference is made to FIGS. 3-4 and FIG. 3 In some embodiments, the semiconductor structure further comprises a plurality of memory cells; the memory cells are connected with the first end portions 114p1a of the corresponding semiconductor layers 114p1; and the memory cells are in the form of a capacitor storage structure 130, a phase change storage structure, a resistance change storage structure or a ferroelectric storage structure. Although FIG. 4 In the embodiments of the present application, the memory cells are in the form of the capacitor storage structure 130, but this example is not used to limit the embodiments of the present application.

[0059] In some embodiments, the capacitive storage structure 130 includes a first electrode layer 130a, a dielectric layer 130c, and a second electrode layer 130b. In some embodiments, the material of the first electrode layer 130a and the second electrode layer 130b includes, but is not limited to, a metallic material or a semiconductive conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof, etc. Illustratively, the material of the first electrode layer 130a and the material of the second electrode layer 130b includes, but is not limited to, titanium nitride. In some embodiments, the material of the dielectric layer 130c includes, but is not limited to, aluminum oxide, zirconium oxide, hafnium oxide, etc. Illustratively, the material of the dielectric layer 130c is hafnium oxide.

[0060] Referring to FIG. 3 and FIG. 4 In some embodiments, the semiconductor structure further includes a plurality of storage cell contacts 128, the storage cells are connected to the first end portion 114p1a of the corresponding semiconductor layer 114p1 through the storage cell contacts 128.

[0061] In some embodiments, the material of the storage cell contacts 128 can be a metallic material or a semiconductive conductive material, such as tungsten, titanium, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof, etc. Illustratively, the material of the storage cell contacts 128 includes polysilicon.

[0062] Referring to FIG. 3 In some embodiments, the semiconductor structure further includes a carrier wafer 200, the carrier wafer 200 is bonded to the storage cells on the first side, and the bit lines 134 are located on the second side. Referring to FIG. 4 In some embodiments, the carrier wafer 200 can also be removed or partially removed FIG. 5 and FIG. 5 (not shown). Whether the carrier wafer is retained, removed, or partially removed can be adaptively selected according to the specific requirements of the process.

[0063] FIG. 5 An implementation flowchart of a manufacturing method of a semiconductor structure is provided for the embodiments of the present application.

[0064] Referring to FIG. 5 According to a second aspect of the embodiments of the present application, a manufacturing method of a semiconductor structure is provided, the manufacturing method includes the following steps: Step S501, providing a substrate structure; In step S502, part of the base structure is removed to form a semiconductor layer; the semiconductor layer comprises a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with the extension direction of the semiconductor layer, the intermediate portion has a ring shape, and the size of the outer contour of the intermediate portion is smaller than the size of the outer contour of the first end portion, and / or smaller than the size of the outer contour of the second end portion.

[0065] It should be understood that, FIGS. 6A-6L The steps shown in the above embodiments are not exclusive, and other steps can be performed before, after or between any of the steps shown; FIGS. 6A-6L The order of the steps shown in the above embodiments can be adjusted according to actual needs.

[0066] FIG. 6A A cross-sectional schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present application. FIG. 6A Fig. (a) in any of the drawings of the above embodiments is a schematic diagram of the semiconductor structure along the A-A cross section (also referred to as the X-Z cross section, as shown in Fig. (b)), and Fig. (b) is a schematic diagram of the semiconductor structure along the B-B cross section (also referred to as the X-Y cross section, as shown in Fig. (a)). For example, FIG. 6A Fig. (a) in the above embodiments is a schematic diagram of the semiconductor structure along the A-A cross section (also referred to as the X-Z cross section, as shown in Fig. FIG. 6A (b) in the above embodiments is a schematic diagram of the semiconductor structure along the B-B cross section (also referred to as the X-Y cross section, as shown in Fig. FIG. 5 (b) in the above embodiments is a schematic diagram of the semiconductor structure along the B-B cross section (also referred to as the X-Y cross section, as shown in Fig. FIGS. 6A-6L (a) in the above embodiments is a schematic diagram of the semiconductor structure along the A-A cross section (also referred to as the X-Z cross section, as shown in Fig.

[0067] For the convenience of describing the embodiments of the present application, the etching (or removing) process used herein can include a wet etching process, a dry etching process, a combination thereof, and the like. For example, a plasma etching process is used. The deposition (or filling) process used herein can include a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD), a combination thereof, and the like. For example, a plasma enhanced chemical vapor deposition (PECVD) process is used. The growth process used herein includes but is not limited to a vapour phase epitaxy (VPE), a liquid phase epitaxy (LPE), a molecular beam epitaxy (MBE), an ion beam epitaxy, a solid phase epitaxy, a combination thereof, and the like.

[0068] The manufacturing method of the semiconductor structure provided by the embodiments of the present application will be described in detail below. FIG. 6A 、 FIG. 6A The manufacturing method of the semiconductor structure provided by the embodiments of the present application will be described in detail below.

[0069] Referring to FIG. 6A , a substrate structure is provided in step S501.

[0070] Referring to FIGS. 6B-6E In some embodiments, providing the substrate structure comprises: providing a substrate 102; forming a first dielectric layer 104, a second dielectric layer 106 and a third dielectric layer 108 which are sequentially stacked on the substrate 102; the material of the second dielectric layer 106 is different from the material of the first dielectric layer 104 and the third dielectric layer 108.

[0071] Referring to FIGS. 6B-6E The first dielectric layer 104, the second dielectric layer 106 and the third dielectric layer 108 which are sequentially stacked on the substrate 102 can be formed by a deposition process.

[0072] In some embodiments, the substrate 102 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate or a Germanium On Insulator (GOI) substrate, etc., and can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a laminated structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as Silicon Germanium On Insulator (SGOI), etc. In some embodiments, the substrate 102 can also be retained, or can be removed or partially removed. Whether the substrate 102 is retained, removed or partially removed can be adaptively selected according to the specific requirements of the process.

[0073] In some embodiments, the material of the first dielectric layer 104 and the material of the third dielectric layer 108 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, and other high dielectric constant (high-k) dielectrics; the material of the second dielectric layer 106 includes, but is not limited to, nitride, silicon carbide, silicon, and silicon germanium. Exemplarily, the first dielectric layer 104 and the third dielectric layer 108 can be formed of silicon nitride, and the second dielectric layer 106 can be formed of silicon (e.g., polysilicon). In alternative embodiments, the material of the first dielectric layer 104 can be the same as or different from the material of the third dielectric layer 108. In some embodiments, the first dielectric layer 104 and the third dielectric layer 108 can have the same thickness as each other or different thicknesses from each other. In some embodiments, the thickness of the second dielectric layer 106 is greater than the thickness of the first dielectric layer 104 and greater than the thickness of the third dielectric layer 108.

[0074] Referring to FIG. 6B , step S502 is performed to form the semiconductor layer.

[0075] Referring to FIG. 6C In some embodiments, forming the semiconductor layer includes: referring to FIG. 6A and FIG. 6D , removing part of the base structure at the first side S1 (referring to FIG. 6E ) of the base structure to form a plurality of first holes H1 passing through the first dielectric layer 104, the second dielectric layer 106, and the third dielectric layer 108; referring to FIG. 6C and FIG. 6E , forming the semiconductor layer 114p1 in the first hole H1 (referring to FIG. 6B ); referring to FIG. 6C , the semiconductor layer 114p1 covers the sidewall and the bottom surface of the first hole; wherein the plurality of semiconductor layers 114p1 are arranged in the first direction and the second direction; the semiconductor layer 114p1 extends in the third direction.

[0076] Referring to FIG. 6B and FIG. 6C In some embodiments, forming the plurality of first holes H1 includes: referring to FIG. 6B , removing part of the base structure at the first side S1 (referring to FIG. 6B ) of the base structure to form a plurality of second holes H2 passing through the first dielectric layer 104, the second dielectric layer 106, and the third dielectric layer 108; referring to FIG. 7 , forming the fourth dielectric layer 110 in the second hole H2 (referring to FIG. 7 ) to obtain the first hole H1; the fourth dielectric layer 110 is located on the surface of the second dielectric layer 106 exposed in the second hole H2; wherein referring to FIG. 6BWithin the first cross section, the fourth dielectric layer 110 is annular in shape, and the dimension D1 of the inner contour of the fourth dielectric layer 110 is smaller than the dimension D3 of the inner contour of the first dielectric layer 104 exposed in the first hole H1 and the dimension D4 of the inner contour of the third dielectric layer 108.

[0077] refer to FIG. 7 The process can employ lithography-etching (LE) to remove portions of the first dielectric layer 104, the second dielectric layer 106, and the third dielectric layer 108, forming a plurality of second holes H2; the plurality of second holes H2 are arranged in an array along the first and second directions. Exemplarily, one or more patterning processes can be used to form the plurality of second holes H2. These patterning processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof. It should be noted that, for clear visualization of the second holes H2, FIG. 7 Figure (b) does not show the substrate 102 at the bottom of the second hole H2.

[0078] FIG. 7 This application provides various array arrangements of multiple second holes in its embodiments. It should be noted that... FIG. 7 Figure (a) in the text can be understood as FIG. 7 Figure (b) in the middle, FIG. 7 Figures (b) and (c) in the text can be understood as being relative to... FIG. 6C The diagram in Figure (a) shows other arrangements with different arrangements. FIG. 6B The arrangement density of the multiple second pores shown in Figures (a), (b), and (c) decreases sequentially. (Reference) FIG. 6C In some embodiments, the plurality of second holes H2 are arranged in a hexagonal pattern. FIG. 6C (as shown in Figure (a)) or rectangular arrangement ( FIG. 6D (See Figures (b) and (c) in the text). The arrangement of the multiple second holes H2 can be adaptively selected according to the specific requirements of the process. In the following description, the arrangement of the multiple second holes H2 in a hexagonal shape is used as an example, but this example is not intended to limit the embodiments of this application. In some embodiments, within the first cross-section, the shape of the second hole H2 includes a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape composed of arc segments and line segments. The shape of the second hole H2 can be adaptively selected according to the specific requirements of the process. In the following description, the arrangement of the second hole H2 in a circle is used as an example, but this example is not intended to limit the embodiments of this application.

[0079] refer to FIG. 6EOxidation processes, such as in-situ steam generation (ISSG), can be used to expose the H2 exposed in the second pore (see reference). FIG. 6K The second dielectric layer 106 in the second dielectric layer 106 is oxidized in situ to form a fourth dielectric layer 110 and a first hole H1; the fourth dielectric layer 110 covers the surface of the second dielectric layer 106 exposed in the second hole H2; the first hole H1 can be understood as being based on the second hole H2 on which the fourth dielectric layer 110 is formed. The material of the fourth dielectric layer 110 can be an oxide of the material of the second dielectric layer 106. Exemplarily, the material of the second dielectric layer 106 is polycrystalline silicon, and the material of the fourth dielectric layer 110 is silicon oxide. In some embodiments, the thickness of the fourth dielectric layer 110 ranges from 8 nm to 12 nm. Exemplarily, the thickness of the fourth dielectric layer 110 is 9 nm, 10 nm, or 11 nm. In optional embodiments, the thickness of the fourth dielectric layer 110 can be less than 8 nm, for example, 7 nm or 6 nm. It should be noted that, in order to clearly show the first hole H1, FIG. 6D Figure (b) does not show the substrate 102 at the bottom of the first hole H1.

[0080] In some embodiments, within the first cross-section, the dimension D1 of the inner contour of the fourth dielectric layer 110 is smaller than the dimension D3 of the inner contour of the first dielectric layer 104 exposed in the first hole H1 and the dimension D4 of the inner contour of the third dielectric layer 108. In some embodiments, within the first cross-section, the dimension D2 of the outer contour of the fourth dielectric layer 110 is larger than the dimension D3 of the inner contour of the first dielectric layer 104 exposed in the first hole H1 and the dimension D4 of the inner contour of the third dielectric layer 108. It should be noted that dimensions D1, D2, D3, and D4 can be understood as dimensions along a specific direction within the first cross-section, such as dimensions along a first direction, or dimensions along a second direction or other directions. FIG. 6E The dimensions D1, D2, D3, and D4 are used as examples to illustrate the dimensions along the first direction within the first cross section, but these examples are not intended to limit the embodiments of this application.

[0081] refer to FIG. 6C , FIG. 6K and FIG. 6A In some embodiments, the method for manufacturing the semiconductor structure further includes: referencing FIG. 6E and FIG. 6A The first hole H1 is formed sequentially (see reference). FIG. 6D The fifth dielectric layer 112p1 and semiconductor layer 114p1 on the sidewalls and bottom surface; Reference FIG. 6C On the second side S2 of the base structure (reference) FIG. 6E), a portion of the fifth dielectric layer 112p1 located at the bottom of the semiconductor layer 114p1 is removed (refer to FIG. 6D ), a gate dielectric layer 112p2 is formed; the gate dielectric layer 112p2 encircles the outer sidewall of the semiconductor layer 114p1; the first side S1 (refer to FIG. 6D ) and the second side S2 are two opposite sides of the base structure along the third direction. Compared with the way of etching (for example, the silicon or silicon germanium remaining after etching silicon or silicon germanium constitutes the semiconductor material layer), in the embodiment of the present application, the way of plating (or depositing material) is adopted, and the deposited material constitutes the semiconductor material layer, which can form a semiconductor material layer with a relatively thin thickness.

[0082] Referring to FIG. 6D , a deposition process is adopted to sequentially form a fifth dielectric material layer 112 covering the top surface of the third dielectric layer 108, the sidewall and the bottom surface of the first hole H1 (refer to FIG. 6C ), a semiconductor material layer 114, and a first insulating material layer 116. Exemplarily, the ALD process can be adopted to form the fifth dielectric material layer 112. Exemplarily, the ALD process can be adopted to form the semiconductor material layer 114. Exemplarily, the PECVD process can be adopted to form the first insulating material layer 116.

[0083] In some embodiments, the thickness of the semiconductor material layer 114 in the first cross section ranges from 5 nm to 25 nm. Exemplarily, the thickness of the semiconductor material layer 114 is 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, or 24 nm. Preferably, the thickness of the semiconductor material layer 114 ranges from 10 nm to 20 nm.

[0084] In some embodiments, the fifth dielectric material layer 112 can be a high-k dielectric layer with a dielectric constant higher than 3.8. The fifth dielectric material layer 112 includes but is not limited to aluminum oxide, zirconium oxide, hafnium oxide, etc. Exemplarily, the fifth dielectric material layer 112 is hafnium oxide. In optional embodiments, the fifth dielectric material layer 112 can be a silicon oxide or a low-k dielectric layer with a dielectric constant lower than 3.8. Exemplarily, the fifth dielectric material layer 112 is silicon oxide.

[0085] In some embodiments, the semiconductor material layer 114 includes a metal oxide semiconductor. Exemplarily, the semiconductor material layer 114 includes at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, indium zinc oxide. In some embodiments, the semiconductor material layer 114 includes at least one of gallium arsenide, indium gallium arsenide.

[0086] In the embodiments of the present application, the semiconductor material layer 114 adopts metal oxide semiconductor (for example, IGZO), and the metal oxide semiconductor with a thin thickness can be formed by plating (or deposition material) in a better way. Compared with the way of forming the semiconductor material layer by etching silicon or silicon germanium material and then reserving the silicon or silicon germanium material, the process is simpler.

[0087] In some embodiments, the first insulating material layer 116 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or other insulating medium material. Exemplarily, the first insulating material layer 116 is silicon oxide.

[0088] Reference FIG. 6F The fifth medium material layer 112 (refer to FIGS. 6G-6J ), the semiconductor material layer 114 (refer to FIG. 6J ) and the first insulating material layer 116 (refer to FIGS. 6G-6J ) covering the top surface of the third medium layer 108 can be removed by a planarization process, for example, a chemical mechanical polishing (CMP) process, to obtain the fifth medium layer 112p1, the semiconductor layer 114p1 and the first insulating layer 116p formed in sequence covering the side wall and the bottom surface of the first hole H1 (refer to FIG. 6G ).

[0089] In some embodiments, the semiconductor layer 114p1 includes a first end portion 114p1a, a second end portion 114p1b and an intermediate portion 114p1c between the first end portion 114p1a and the second end portion 114p1b; in a first cross section intersecting the extension direction of the semiconductor layer 114p1, the intermediate portion 114p1c has a ring shape, and the size D23 of the outer contour of the intermediate portion 114p1c is smaller than the size D21 of the outer contour of the first end portion 114p1a and smaller than the size D22 of the outer contour of the second end portion 114p1b.

[0090] In some embodiments, in a second cross section, the second end portion 114p1b has a U shape, and the bottom area of the second end portion 114p1b is large, which can be used to increase the contact area with the bit line.

[0091] Reference FIG. 6H The first covering material layer 118 and the second covering material layer 120 covering the top surface of the third medium layer 108, the top surface of the fifth medium layer 112p1, the top surface of the semiconductor layer 114p1 and the top surface of the first insulating layer 116p can be formed in sequence by a deposition process; the materials of the first covering material layer 118 and the second covering material layer 120 are different.

[0092] In some embodiments, the first and second cap material layers 118 and 120 comprise, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric material. Illustratively, the first cap material layer 118 is silicon nitride and the second cap material layer 120 is silicon oxide. In some embodiments, the first cap material layer 118 is the same material as the third dielectric layer 108.

[0093] Referring to FIG. 6G In some embodiments, the method of manufacturing a semiconductor structure further comprises: forming a plurality of word lines 124; referring to FIG. 6G The word lines 124 extend along a first direction and are coupled to the middle portions 114p1c of a row of semiconductor layers 114p1; the word lines 124 comprise a plurality of first portions 124a and a plurality of second portions 124b; the first portions 124a encircle the outer sidewalls of the corresponding middle portions 114p1c; in the first direction, the second portions 124b connect two adjacent first portions 124a; wherein in a second direction, a dimension D11 of the first portions 124a is greater than a dimension D12 of the second portions 124b.

[0094] Referring to FIG. 6I In some embodiments, forming the plurality of word lines 124 comprises: referring to FIG. 6J removing portions of the third dielectric layer and portions of the second dielectric layer to form a plurality of first trenches T1; in the first direction, the first trenches T1 expose portions of the fourth dielectric layer 110; in the second direction, a dimension D5 of the first trenches T1 is less than a dimension D6 of an outer profile of the middle portions 114p1c; referring to FIG. 6H removing the fourth dielectric layer 110 (referring to FIG. 6J ) based on the first trenches T1 (referring to FIG. 6G ) to form second trenches T2; the second trenches T2 comprise a plurality of first spaces T2a and a plurality of second spaces T2b; the first spaces T2a encircle the fifth dielectric layer 112p1 of the first end portions 114p1a and the middle portions 114p1c; in the first direction, the second spaces T2b connect two adjacent first spaces T2a; referring to FIG. 6H and FIG. 6I forming a first conductive layer in the second trenches T2 (referring to FIG. 6G ); removing portions of the first conductive layer to form the word lines 124; referring to FIG. 6F The first portions 124a are located in the first spaces; the second portions 124b are located in the second spaces. It is noted that, for clarity of showing the first trenches T1, FIG. 6F in (b) of FIG. 4, the first dielectric layer 104 at the bottom of the first trenches T1 is not shown. For clarity of showing the second trenches T2, FIG. 6H in (b) of FIG. 5, the first dielectric layer 104 at the bottom of the second trenches T2 is not shown. For clarity of showing the third trenches T3,FIG. 6G Figure (b) does not show the first dielectric layer 104 at the bottom of the third trench T3.

[0095] refer to FIG. 6G A photolithography-etching process can be used to remove part of the first cover material layer 118 (see reference). FIG. 6G ) and part of the second covering material layer 120 (reference) FIG. 6G The process involves forming a first capping layer 118p and a portion of a second capping layer 120p, which sequentially cover the top surface of the fifth dielectric layer 112p1, the top surface of the semiconductor layer 114p1, and the top surface of the first insulating layer 116p; and removing a portion of the third dielectric layer 108 and a portion of the second dielectric layer 106 to form a plurality of first trenches T1, which are arranged in an array along a first direction and a second direction; wherein, in the first direction, the first trenches T1 expose a portion of the fourth dielectric layer 110; in the second direction, the size D5 of the first trenches T1 is smaller than the size D6 of the outer contour of the middle portion 114p1c; and in the third direction, the first trenches T1 pass through the third dielectric layer 108 and the second dielectric layer 106.

[0096] refer to FIG. 6I An etching process, such as wet etching, can be used, based on the first trench T1 (see reference). FIG. 6J Remove the fourth dielectric layer 110 (reference) FIG. 6I A second trench T2 is formed; the second trench T2 includes a plurality of first spaces T2a and a plurality of second spaces T2b; the first spaces T2a surround the fifth dielectric layer 112p1 of the outer wall of the first end 114p1a and the middle part 114p1c; in a first direction, the second spaces T2b connect two adjacent first spaces T2a; in a second direction, the size D7 of the first space T2a is greater than the size D8 of the second space T2b; in a third direction, the first trench T1 passes through the third dielectric layer 108 and the second dielectric layer 106.

[0097] In some embodiments, during the removal of the fourth dielectric layer 110, the second cover layer 120p (reference) FIG. 6J The fourth dielectric layer 110 can be completely or partially removed. In an alternative embodiment, during the removal of the fourth dielectric layer 110, the second cover layer 120p (refer to...) can be completely or partially removed. FIG. 6I ) can be completely removed, and the first overlay 118p is partially removed.

[0098] refer to FIG. 6H and FIG. 6H In some embodiments, before forming the first conductive layer, the method of manufacturing the semiconductor structure further includes: referencing FIG. 6IIn the second trench T2, a sixth dielectric layer 122 is formed on the surface of the second dielectric layer 106 exposed in the second trench T2; refer to FIG. 6H Based on the second trench T2 with the sixth dielectric layer 122 formed thereon, a first conductive layer is formed. For the convenience of description of the present application, the third trench T3 is obtained after the second trench T2 with the sixth dielectric layer 122 formed thereon; refer to FIG. 6J The third trench T3 includes a plurality of third spaces T3a corresponding to the plurality of first spaces T2a (refer to FIG. 6I ) and a plurality of fourth spaces T3b corresponding to the plurality of second spaces T2b (refer to FIG. 6J ). In some embodiments, the size D9 of the third space T3a is smaller than the size D7 of the first space T2a, and the size D10 of the fourth space T3b is smaller than the size D8 of the second space T2b. In other embodiments, the size D9 of the third space T3a is substantially the same as the size D7 of the first space T2a, and the size D10 of the fourth space T3b is substantially the same as the size D8 of the second space T2b. Herein, the term "substantially the same" can be understood as the same within the range of process error.

[0099] Refer to FIG. 2 The sixth dielectric layer 122 covering the second dielectric layer 106 exposed in the second trench T2 (refer to FIG. 2 ) can be formed by an oxidation process, such as an ISSG process. The material of the sixth dielectric layer 122 can be an oxide of the material of the second dielectric layer 106. Exemplarily, the material of the second dielectric layer 106 is polysilicon, and the material of the sixth dielectric layer 122 is silicon oxide.

[0100] Refer to FIG. 6J The first conductive layer (not shown) in the third trench T3 (refer to FIG. 6I ) can be formed by a deposition process, and the first conductive layer is partially removed by an etching process to form the word line 124. FIG. 6J

[0101] In some embodiments, the word line 124 extends along the first direction and is coupled to the middle part 114p1c of a row of the semiconductor layer 114p1; the word line 124 includes a plurality of first portions 124a and a plurality of second portions 124b; the first portion 124a surrounds the outer sidewall of the corresponding middle part 114p1c; in the first direction, the second portion 124b connects two adjacent first portions 124a; and in the second direction, the size D11 of the first portion 124a is greater than the size D12 of the second portion 124b.

[0102] ​In an optional embodiment, during the etch-back process to remove a portion of the first conductive layer, due to the loading effect, the removal rate of the first conductive layer located in the fourth space T3b is greater than that of the first conductive layer located in the third space T3a, resulting in a word line obtained after the etching process is completed; in the third direction, the size D14 of the first portion of this word line (refer to...) FIG. 6K (For understanding) The size of the second part of the word line is greater than D13 (reference) FIG. 6L (To understand).

[0103] Continue to refer to FIG. 6K A deposition process can be used to form the third trench T3 with the letter 124 (see reference). FIG. 6A In ), a second insulating material layer is formed covering the word line 124. FIG. 6L (not shown); and, using a planarization process, the first cover layer 118p and a portion of the second insulating material layer are removed, exposing at least the top surface of the semiconductor layer 114p1, to obtain the second insulating layer 126.

[0104] In some embodiments, the second insulating layer 126 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. Exemplarily, the second insulating layer 126 is silicon oxide. In some embodiments, the material of the second insulating layer 126 is the same as the material of the third dielectric layer.

[0105] refer to FIG. 6A and FIG. 6K In some embodiments, the method for manufacturing the semiconductor structure further includes: referencing FIG. 6K On the first side S1 of the base structure (reference) FIG. 6A Multiple memory cells are formed; each memory cell is connected to the first end 114p1a of the corresponding semiconductor layer 114p1; the memory cell is a capacitor memory structure 130, a phase-change memory structure, a resistive switching memory structure, or a ferroelectric memory structure; Reference FIG. 6L On the second side S2 of the base structure (reference) FIG. 6L Multiple bit lines 134 are formed; the bit lines 134 extend along the second direction and are connected to the second end 114p1b of a column of semiconductor layers 114p1.

[0106] refer to FIG. 6L In some embodiments, forming the capacitor storage structure 130 includes sequentially forming a first electrode layer 130a, a dielectric layer 130c, and a second electrode layer 130b. The material selection for the first electrode layer 130a, the dielectric layer 130c, and the second electrode layer 130b can be referred to the relevant description in the first aspect, and will not be repeated here.

[0107] refer to FIG. 6KIn some embodiments, before forming the memory cells, the method of fabricating the semiconductor structure further comprises: forming a plurality of memory cell contacts 128 on the first side S1 (refer to FIG. 6A of the base structure (refer to

[0108] Referring to FIG. 6A In some embodiments, forming the plurality of bit lines 134 comprises: removing the substrate 102 and part of the fifth dielectric layer 112p1 to expose the bottom of the semiconductor layer 114p1; and forming the bit lines 134 connected to the bottom of the semiconductor layer 114p1. It is noted that, for the sake of clarity of the relative position relationship between the bit lines 134 and the word lines 124, the position of the bit lines is shown in perspective in (b) of FIG. 13. FIG. 6L

[0109] Referring to FIG. 6A The semiconductor structure 100 can be bonded with a carrier wafer 200 (refer to ​ ) on the first side S1 (refer to ​ ) of the semiconductor structure 100 to expose the structure of the second side S2 (refer to ​ ) of the semiconductor structure 100, and the bit lines 134 can be formed on the second side S2 of the semiconductor structure 100. In some embodiments, the carrier wafer 200 can be retained, or can be removed or partially removed. The retention, removal or partial removal of the carrier wafer 200 can be adaptively selected according to the specific requirements of the process procedure. For example, the carrier wafer 200 can be removed by a debonding process.

[0110] Referring to ​ In some embodiments, before forming the plurality of bit lines 134, the method of fabricating the semiconductor structure further comprises: forming a plurality of bit line contacts 132 on the second side S2 (refer to ​ of the base structure (refer to In some embodiments, in the first direction, the size D33 of the bit line contacts 132 is greater than the size D32 of the outer profile of the semiconductor layer 114p1, and the size D34 of the bit lines 134 is less than the size D31 of the inner profile of the semiconductor layer 114p1. The material selection of the bit lines 134 and the bit line contacts 132 can refer to the related description of the first aspect, which will not be repeated here.

[0111] The semiconductor structure manufactured by the method for manufacturing a semiconductor structure provided in the embodiments of the present application is similar to the semiconductor structure in the embodiments of the first aspect. For technical features not disclosed in the embodiments of the present application, refer to the above embodiments for understanding, which will not be described here.

[0112] In a third aspect, the embodiments of the present application provide a memory, comprising: any of the semiconductor structures provided in the first aspect, or the semiconductor structure obtained by the manufacturing method provided in the second aspect; the word line of the semiconductor structure is configured to receive a word line voltage and control the conduction or cutoff of the middle part of the semiconductor layer of the semiconductor structure by the word line voltage, for connecting / disconnecting the first end part and the second end part of the semiconductor layer of the semiconductor structure; the bit line of the semiconductor structure is configured to perform a read or write operation on the memory cell of the semiconductor structure when the middle part of the semiconductor layer is in conduction.

[0113] Exemplarily, the semiconductor structure comprises: a semiconductor layer; in the extension direction of the semiconductor layer, the semiconductor layer comprises a first end part, a second end part and a middle part between the first end part and the second end part; in a first cross section intersecting the extension direction of the semiconductor layer, the shape of the middle part is annular, and the size of the outer contour of the middle part is smaller than the size of the outer contour of the first end part, and / or, smaller than the size of the outer contour of the second end part.

[0114] It should be understood that the “one embodiment” or “an embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of the above processes in various embodiments of the present application does not mean the order of execution, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The sequence number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0115] The above description is only the preferred embodiments of the present application, and does not limit the protection scope of the present application, and any equivalent structural transformation made according to the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields within the concept of the present application are included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized by, Comprising: a semiconductor layer comprising a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with an extending direction of the semiconductor layer, the intermediate portion has a ring shape, and an outer contour of the intermediate portion has a size smaller than that of an outer contour of the first end portion, and / or, smaller than that of an outer contour of the second end portion.

2. The semiconductor structure of claim 1, wherein, a material of the semiconductor layer comprises a metal-oxide semiconductor.

3. The semiconductor structure of claim 1, wherein, in the first cross section, the intermediate portion has a thickness ranging from 5 nm to 25 nm.

4. The semiconductor structure of claim 1, wherein, in the first cross section, the intermediate portion has an outer contour shape comprising a circle, an ellipse, a rectangle, a parallelogram, a trapezoid, or a closed shape formed by an arc segment and a line segment.

5. The semiconductor structure of claim 1, wherein, in the first cross section, the intermediate portion has an outer contour size smaller than that of an outer contour of the first end portion and that of an outer contour of the second end portion, and a difference between the outer contour size of the first end portion or the outer contour size of the second end portion and the outer contour size of the intermediate portion ranges from 16 nm to 24 nm.

6. The semiconductor structure of claim 5, wherein, the semiconductor structure further comprises a gate structure; the gate structure comprises a gate dielectric layer and a gate electrode; the gate dielectric layer surrounds an outer sidewall of the semiconductor layer; the gate electrode surrounds an outer sidewall of the gate dielectric layer corresponding to the intermediate portion; in the first cross section, an outer contour of the gate structure has a size larger than that of an outer contour of the first end portion and that of an outer contour of the second end portion.

7. The semiconductor structure of claim 6, wherein, a material of the gate dielectric layer comprises a dielectric material with a dielectric constant higher than 3.

8.

8. The semiconductor structure of claim 1, wherein, the semiconductor structure comprises a plurality of the semiconductor layers; the plurality of the semiconductor layers are arranged in an array along a first direction and a second direction; the semiconductor layers extend along a third direction; the semiconductor structure further comprises a plurality of word lines; the word lines extend along the first direction and are coupled to the intermediate portions of a row of the semiconductor layers; the word lines comprise a plurality of first portions and a plurality of second portions; the first portions surround outer sidewalls of corresponding intermediate portions; in the first direction, the second portions connect two adjacent first portions; wherein, in the second direction, the first portions have a size larger than that of the second portions.

9. The semiconductor structure of claim 8, wherein, the plurality of the semiconductor layers are arranged in a hexagonal array or a rectangular array.

10. The semiconductor structure of claim 8, wherein, the semiconductor structure further comprises a plurality of bit lines; the bit lines extend along the second direction and are connected to the second end portions of a column of the semiconductor layers; wherein, in a second cross section parallel to the extending direction of the semiconductor layers, the second end portions have a U shape; the bit lines are connected to bottoms of the U shapes.

11. The semiconductor structure of claim 8, wherein, the semiconductor structure further comprises a plurality of memory cells; the memory cells are connected to the first end portions of corresponding semiconductor layers; the memory cells are capacitive memory structures, phase-change memory structures, resistive memory structures, or ferroelectric memory structures.

12. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing a substrate structure; removing part of the base structure to form a semiconductor layer; the semiconductor layer comprises a first end portion, a second end portion and an intermediate portion between the first end portion and the second end portion; in a first cross section intersecting with an extending direction of the semiconductor layer, the intermediate portion has a ring shape, and an outer profile of the intermediate portion has a size smaller than an outer profile of the first end portion, and / or, smaller than an outer profile of the second end portion.

13. The manufacturing method according to claim 12, wherein The base structure is provided, comprising: a substrate is provided; a first dielectric layer, a second dielectric layer and a third dielectric layer are formed on the substrate in sequence; the second dielectric layer has a material different from materials of the first dielectric layer and the third dielectric layer.

14. The manufacturing method according to claim 13, wherein The semiconductor layer is formed, comprising: on a first side of the base structure, part of the base structure is removed to form a plurality of first holes passing through the first dielectric layer, the second dielectric layer and the third dielectric layer; the semiconductor layer is formed in the first holes; the semiconductor layer covers side walls and a bottom surface of the first holes; wherein a plurality of the semiconductor layers are arranged in a first direction and a second direction; the semiconductor layer extends in a third direction.

15. The manufacturing method according to claim 14, wherein The plurality of first holes are formed, comprising: on a first side of the base structure, part of the base structure is removed to form a plurality of second holes passing through the first dielectric layer, the second dielectric layer and the third dielectric layer; a fourth dielectric layer is formed in the second holes to obtain the first holes; the fourth dielectric layer is located on a surface of the second dielectric layer exposed in the second holes; wherein in the first cross section, the fourth dielectric layer has a ring shape, and an inner profile of the fourth dielectric layer has a size smaller than an inner profile of the first dielectric layer exposed in the first holes and an inner profile of the third dielectric layer.

16. The manufacturing method according to claim 15, wherein The manufacturing method further comprises: a fifth dielectric layer covering the side walls and the bottom surface of the first holes and the semiconductor layer are formed in sequence; on a second side of the base structure, part of the fifth dielectric layer located at a bottom of the semiconductor layer is removed to form a gate dielectric layer; the gate dielectric layer surrounds an outer side wall of the semiconductor layer; the first side and the second side are two opposite sides of the base structure in the third direction.

17. The manufacturing method according to claim 16, wherein The manufacturing method further comprises: a plurality of word lines are formed; the word lines extend in the first direction and are coupled to the intermediate portions of a row of the semiconductor layers; the word lines comprise a plurality of first portions and a plurality of second portions; the first portions surround the outer side walls of the corresponding intermediate portions; in the first direction, the second portions connect two adjacent first portions; wherein in the second direction, the first portions have a size larger than a size of the second portions.

18. The manufacturing method according to claim 17, wherein The plurality of word lines are formed, comprising: part of the third dielectric layer and part of the second dielectric layer are removed to form a plurality of first grooves; in the first direction, the first grooves expose part of the fourth dielectric layer; in the second direction, the first grooves have a size smaller than a size of the outer profile of the intermediate portions; forming a second trench based on the first trench, the second trench comprising a plurality of first spaces and a plurality of second spaces, the first space surrounding the fifth dielectric layer of the outer sidewall of the first end portion and the middle portion, the second space connecting two adjacent first spaces in the first direction; forming a first conductive layer in the second trench; removing part of the first conductive layer to form the word line, the first part being in the first space, the second part being in the second space.

19. The manufacturing method according to claim 18, wherein Before forming the first conductive layer, the manufacturing method further comprises: forming a sixth dielectric layer in the second trench, the sixth dielectric layer being on the surface of the second dielectric layer exposed in the second trench; forming the first conductive layer based on the second trench with the sixth dielectric layer.

20. The manufacturing method of claim 16, wherein, The manufacturing method further comprises: forming a plurality of memory cells on the first side of the base structure, the memory cell being connected to the first end portion of the corresponding semiconductor layer, the memory cell being a capacitor memory structure, a phase change memory structure, a resistive memory structure, or a ferroelectric memory structure; forming a plurality of bit lines on the second side of the base structure, the bit line extending along the second direction and being connected to the second end portion of a column of the semiconductor layer.

21. The manufacturing method according to claim 20, wherein The forming a plurality of bit lines comprises: exposing the bottom of the semiconductor layer by removing the substrate and part of the fifth dielectric layer; and forming the bit line connected to the bottom of the semiconductor layer.

22. A memory, comprising: comprises: the semiconductor structure of any one of claims 1 to 11, or the semiconductor structure obtained by the manufacturing method of any one of claims 12 to 21; the word line of the semiconductor structure is configured to receive a word line voltage and control the middle portion of the semiconductor layer of the semiconductor structure to be on or off by the word line voltage, for connecting / disconnecting the first end portion and the second end portion of the semiconductor layer of the semiconductor structure; the bit line of the semiconductor structure is configured to perform a read or write operation on the memory cell of the semiconductor structure when the middle portion of the semiconductor layer is on.

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