Semiconductor structure, semiconductor device and preparation method
By introducing a low-doped cap layer into the semiconductor structure and etching trenches to fill the ohmic contact metal, the problem of electrochemical corrosion at the edge of the ohmic contact metal is solved, improving the stability and reliability of the device and reducing the ohmic contact resistance.
Patent Information
- Application Number
- CN202511692067.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-13
AI Technical Summary
Electrochemical corrosion is prone to occur at the interface between traditional ohmic contact metals and heavily doped semiconductors, affecting the stability and reliability of the device.
A low-doped second cap layer is formed on a highly doped first cap layer, and trenches are etched on it. Ohmic contact metal fills the trenches and forms an ohmic contact with the first cap layer. The low-doped cap layer is used as a protective layer to isolate and reduce the interfacial electric field.
It significantly reduces or avoids electrochemical corrosion effects, improves the stability and reliability of devices, and reduces ohmic contact resistance.
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Figure CN121531744A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure, a semiconductor device and a preparation method. BACKGROUND
[0002] With the increasing of the working frequency of pHEMT (pseudomorphic high electron mobility transistor) process, the long-term stability and reliability of the device become a serious challenge. The preparation of ohmic contact is one of the key links affecting the performance of the device, and its quality directly determines the contact resistance and the current transmission capacity of the device.
[0003] In the traditional ohmic contact process of pHEMT, the ohmic contact metal is usually directly prepared on the heavily doped cap layer. However, this structure has an inherent defect: in the subsequent acid-base cleaning process, due to the potential difference between the ohmic contact metal and the heavily doped semiconductor caused by the difference in work function, a closed electrochemical circuit is easily formed together with the electrolyte. The current in this circuit will be concentrated at the interface between the edge of the ohmic contact metal and the heavily doped semiconductor, causing electrochemical corrosion in this area, forming pits, and thus affecting the stability and reliability of the device. SUMMARY
[0004] The purpose of the present application is to provide a semiconductor structure, a semiconductor device and a preparation method to solve the problem that in the traditional ohmic contact process, the interface between the edge of the metal and the heavily doped semiconductor is prone to electrochemical corrosion to form pits, thereby affecting the stability and reliability of the device performance.
[0005] To solve the above problems, the present application provides a semiconductor structure, comprising:
[0006] a semiconductor substrate, an epitaxial layer and a cap layer stacked in sequence, the cap layer comprising a first cap layer with high doping and a second cap layer with low doping, the second cap layer being located on the first cap layer, and the second cap layer having a groove; and
[0007] an ohmic contact metal, the ohmic contact metal at least filling the groove and forming an ohmic contact with the first cap layer after annealing.
[0008] Optionally, in the semiconductor structure, the ohmic contact metal not only fills the groove but also extends to the surface of part of the second cap layer.
[0009] Optionally, in the semiconductor structure, the thickness of the second cap layer is 10 Å~100 Å.
[0010] Optionally, in the semiconductor structure, the bottom of the groove is located in the second cap layer, or the groove penetrates through the second cap layer to expose the first cap layer.
[0011] Optionally, in the semiconductor structure, the ohmic contact metal has an extension width of 100 nm to 800 nm on the surface of the second cap layer.
[0012] The application further provides a semiconductor device comprising the semiconductor structure according to any one of the preceding embodiments, wherein the ohmic contact metal forms a source and a drain of the semiconductor device.
[0013] The application further provides a method for manufacturing a semiconductor structure, comprising:
[0014] providing a semiconductor substrate, and sequentially forming an epitaxial layer, a high-doped first cap layer and a low-doped second cap layer on the semiconductor substrate;
[0015] etching the second cap layer and stopping on the first cap layer to form a trench;
[0016] depositing an ohmic contact metal, wherein the ohmic contact metal at least fills the trench; and
[0017] performing a tempering treatment so that the ohmic contact metal forms an ohmic contact with the first cap layer.
[0018] Optionally, in the method for manufacturing a semiconductor structure, the process step of etching the second cap layer comprises:
[0019] forming a photoresist layer on the second cap layer, and performing exposure and first development on the photoresist layer so that the photoresist layer has an opening pattern; and
[0020] etching the second cap layer to form the trench by taking the photoresist layer as a mask.
[0021] Optionally, in the method for manufacturing a semiconductor structure, before depositing the ohmic contact metal, the method further comprises:
[0022] performing second development on the photoresist layer to expand the size of the opening pattern, so as to expose part of the surface of the second cap layer;
[0023] in the step of depositing the ohmic contact metal, the ohmic contact metal fills the trench while covering the exposed surface of the second cap layer.
[0024] Optionally, in the method for manufacturing a semiconductor structure, after depositing the ohmic contact metal, the method further comprises: removing the photoresist layer.
[0025] In summary, in the semiconductor structure, semiconductor device and preparation method provided by the present application, by optimizing the cap layer structure, a low-doped second cap layer is formed on the high-doped first cap layer as a protective layer. The second cap layer as a protective layer, on the one hand, isolates the first cap layer from the process solution, and on the other hand, reduces the interface electric field of the metal edge by using its high resistance characteristics, thereby significantly weakening or avoiding the electrochemical corrosion effect. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 The flow chart of the manufacturing method of the semiconductor structure provided by the first embodiment of the present application;
[0027] Figures 2-6 The device structure schematic diagram corresponding to part of the steps in the Figure 1
[0028] Figure 7 The flow chart of the manufacturing method of the semiconductor structure provided by the second embodiment of the present application;
[0029] Figures 8-11 The device structure schematic diagram corresponding to part of the steps in the Figure 7 In the drawings:
[0030]
[0031] 11-epitaxial layer; 12-first cap layer; 13-second cap layer; 131-trench; 14-photoresist layer; 15-ohmic contact metal; 151-main body part; 152-edge part. DETAILED DESCRIPTION
[0032] The semiconductor structure, semiconductor device and preparation method provided by the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are all very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different proportions are sometimes used in different drawings to show different focuses. It should be recognized that relative terms such as "above", "below", "top", "bottom" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of the elements in addition to the orientation depicted in the drawings. For example, if the device is inverted with respect to the view in the drawing, the element described as "above" another element will now be below the element. It should also be understood that the terms "first", "second", "third" and the like in the description are merely used to distinguish various components, elements, steps and the like in the description, and are not intended to represent a logical relationship or sequential relationship between the various components, elements, steps and the like.
[0033] Embodiment One
[0034] As shown in Figure 6 , the embodiment provides a semiconductor structure, which comprises:
[0035] a semiconductor substrate (not shown in the figure), an epitaxial layer 11, and a cap layer, which is sequentially stacked, and comprises a high-doped first cap layer 12 and a low-doped second cap layer 13, the second cap layer 13 is located on the first cap layer 12, and the second cap layer 13 has a trench; and
[0036] an ohmic contact metal 15, which at least fills the trench, and forms an ohmic contact with the first cap layer 12 after annealing treatment.
[0037] The semiconductor structure provided by the embodiment, the low-doped second cap layer 13 serves as a protective layer of the first cap layer 12, which on one hand isolates the first cap layer 12 from the process solution, and on the other hand reduces the interface electric field of the metal edge by using its high-resistance characteristics, thereby significantly weakening or avoiding the electrochemical corrosion effect.
[0038] Correspondingly, the embodiment also provides a preparation method for preparing the semiconductor structure, as shown in Figure 1 , the preparation method comprises:
[0039] S11, providing a semiconductor substrate, and sequentially forming an epitaxial layer 11, a high-doped first cap layer 12, and a low-doped second cap layer 13 on the semiconductor substrate;
[0040] S12, etching the second cap layer 13 to form a trench;
[0041] S13, depositing an ohmic contact metal 15, which at least fills the trench;
[0042] S14, performing annealing treatment, so that the ohmic contact metal 15 forms an ohmic contact with the first cap layer 12.
[0043] The above steps S11-S14 are further described below, and the structure characteristics of the semiconductor structure provided by the embodiment will also be clearer through the further description of steps S11-S14. Figures 2-6
[0044] First, as shown in Figure 2 , step S11 is performed to provide a semiconductor substrate (not shown in the figure), and sequentially form an epitaxial layer 11, a high-doped first cap layer 12, and a low-doped second cap layer 13 on the semiconductor substrate.
[0045] As an example, the semiconductor substrate can be a GaAs substrate, which is used to provide mechanical support.
[0046] The epitaxial layer 11 can include a buffer layer, a channel layer, a barrier layer, a diffusion barrier layer, etc. stacked in sequence. As an example, the buffer layer can be an undoped or semi-insulating GaAs buffer layer, the channel layer can be an InGaAs channel layer, the barrier layer can be an AlGaAs barrier layer, which forms a heterojunction with the InGaAs channel layer thereunder, and the diffusion barrier layer can be an InGaP barrier layer or an AlAs barrier layer.
[0047] As an example, the cap layer can be a GaAs cap layer, in which the first cap layer 12 is an n+ GaAs cap layer and the second cap layer 13 is an n-GaAs cap layer.
[0048] It should be noted that the above examples of the substrate, the epitaxial layer 11 and the cap layer do not constitute a limitation on the present application. In other embodiments, when the substrate material changes, the materials of the epitaxial layer 11 and the cap layer can also change accordingly.
[0049] Secondly, as shown in FIG. 1C, step S12 is performed to etch the second cap layer 13 and stop at the first cap layer 12 to form a trench 131. Figure 4
[0050] The trench 131 formed by the etching step can optionally be located within the second cap layer 13, or the trench 131 can penetrate through the second cap layer 13 to expose the first cap layer 12.
[0051] In the present embodiment, preferably, the bottom of the trench 131 is located within the second cap layer 13, i.e., the second cap layer 13 remains fully covering the first cap layer 12.
[0052] The trench 131 is preferably formed by a dry etching process such as a reactive ion etching (RIE) process. When a dry etching process is used, the anisotropy is good, and a nearly vertical sidewall can be formed, which is beneficial to control the morphology and size of the trench 131.
[0053] Please refer to FIGS. 1C and 1D, and FIGS. 2A and 2B, which show a method for forming the trench 131. Figure 2 Figure 3 Specifically, a photoresist layer 14 can be formed on the second cap layer 13, and the photoresist layer 14 can be exposed and developed to form a patterned photoresist layer 14. Then, the patterned photoresist layer 14 can be used as a mask to perform a RIE process using an etching gas based on chlorine (Cl2), and the etching time can be accurately controlled to stop within the second cap layer 13 or stop at the first cap layer 12.
[0054] Next, as shown in FIG. 1D, step S13 is performed to etch the first cap layer 12 and stop at the buffer layer to form a first trench 132. Figure 5 As shown, step S13 is performed to deposit ohmic contact metal 15, which at least fills the trench 131. In this embodiment, the ohmic contact metal 15 only fills the trench 131.
[0055] The ohmic contact metal 15 may be a stacked metal deposited using an electron beam evaporation process, with a total thickness of not less than 250 nm. As an example, the ohmic contact metal 15 includes an adhesion layer, an ohmic forming layer, a diffusion barrier layer, and a main conductive layer stacked sequentially. Optionally, the adhesion layer includes a Ni layer, the ohmic forming layer includes a Ge layer and a first Au layer, the diffusion barrier layer includes a Ti layer, and the main conductive layer includes a second Au layer, the thickness of which should be greater than the thickness of the first Au layer.
[0056] Finally, as Figure 6 As shown, step S14 is performed, followed by tempering. After tempering, the ohmic contact metal 15 located in the trench 131 and on the surface of the second cap layer 13 penetrates into the first cap layer 12, forming an ohmic contact with it. Before performing step S14, the photoresist layer 14 can be removed. When the photoresist layer 14 is removed, the metal on its surface is also removed simultaneously.
[0057] Optionally, the tempering temperature is 300°C to 480°C. A specific process example is as follows:
[0058] The prepared structure was rapidly heated from room temperature to 400°C at a certain heating rate;
[0059] At 400°C, the temperature is maintained for a certain period of time, during which time the metal penetrates into the first cap layer 12 and undergoes a eutectic reaction with the first cap layer 12, and then the temperature is cooled.
[0060] Furthermore, this embodiment also provides a semiconductor device, including: the semiconductor structure as provided in this embodiment, wherein the ohmic contact metal 15 constitutes the source and drain of the semiconductor device.
[0061]
Example 2
[0062] Unlike Embodiment 1, in the semiconductor structure provided in this embodiment, the ohmic contact metal 15 fills the trench 131 and extends to the surface of a portion of the second cap layer 13.
[0063] That is, such as Figure 11 As shown in the figure, the semiconductor structure provided in this embodiment includes an ohmic contact metal 15 comprising a body portion 151 and an edge portion 152 extending onto the second cap layer 13.
[0064] In the embodiment one, the ohmic contact metal 15 only includes the main body part 151. Although the second cap layer 13 protects the first cap layer 12 to some extent and the chemical corrosion of the interface between the second cap layer 13 and the metal is slower than that in the conventional structure, electrochemical corrosion will still occur along the sidewall of the second cap layer 13 in a long-term process cleaning or in a harsh environment, and can eventually endanger the underlying first cap layer 12, resulting in a larger contact resistance.
[0065] The semiconductor structure provided by the embodiment creates a high-resistance "buffer zone" by locating the metal edge on the low-doped second cap layer 13, which further isolates the electrolyte from the first cap layer 12 and improves the difficulty of electrochemical corrosion occurring at the interface between the metal and the first cap layer 12, thereby being able to more effectively ensure a lower ohmic contact resistance.
[0066] Correspondingly, please refer to Figure 7 in combination with Figures 2-4 and Figures 8-11 The embodiment provides a manufacturing method for manufacturing the semiconductor structure, and the manufacturing method comprises the following steps:
[0067] S21, providing a semiconductor substrate, and sequentially forming an epitaxial layer 11, a high-doped first cap layer 12, and a low-doped second cap layer 13 on the semiconductor substrate;
[0068] S22, forming a photoresist layer 14 on the second cap layer 13, and performing exposure and first development on the photoresist layer 14, so that the photoresist layer 14 has an opening pattern;
[0069] S23, taking the photoresist layer 14 as a mask to etch the second cap layer 13 to form a groove 131;
[0070] S24, performing second development on the photoresist layer 14 to expand the size of the opening pattern, so as to expose part of the surface of the second cap layer 13;
[0071] S25, depositing an ohmic contact metal 15, the ohmic contact metal 15 fills the groove 131 while covering the exposed surface of the second cap layer 13;
[0072] S26, removing the photoresist layer 14.
[0073] S27, performing a tempering treatment to form an ohmic contact between the ohmic contact metal 15 and the first cap layer 12.
[0074] That is, different from the manufacturing method provided in Embodiment One, the manufacturing method provided in the present embodiment includes two developing operations, the opening pattern formed by the first developing operation defines the trench width of the second cap layer 13, and the second developing operation exposes part of the surface of the second cap layer 13, so that the ohmic contact metal 15 can extend to the edge portion 152 on the second cap layer 13 while filling the trench 131 to form the main body portion 151. The difference between the opening size CD2 formed after the second developing operation and the opening size CD1 formed after the first developing operation defines the extension width L of the ohmic contact metal 15 on the surface of the second cap layer 13.
[0075] Preferably, the extension width L of the ohmic contact metal 15 on the surface of the second cap layer 13 (i.e. the width of the edge portion 152) is 100 nm to 800 nm, in this size range, the electrochemical corrosion loop can be effectively cut off, and the problem of increased parasitic capacitance or increased process difficulty caused by excessive extension can be avoided.
[0076] After the annealing treatment, the main body portion 151 and the edge portion 152 of the ohmic contact metal 15 form ohmic contact with the first cap layer 12.
[0077] Preferably, the thickness of the second cap layer 13 is 10 Å to 100 Å, in this thickness range, the isolation and protection effects can be ensured, and at the same time, it can be ensured that the metal on the second cap layer 13 can penetrate the second cap layer 13 of this thickness to form ohmic contact with the first cap layer 12 under standard annealing process conditions.
[0078] Similarly, the present embodiment also provides a semiconductor device, which includes the semiconductor structure provided in the present embodiment, and the ohmic contact metal 15 forms the source and drain of the semiconductor device.
[0079] In summary, in the semiconductor structure, semiconductor device and manufacturing method provided in the embodiments of the present application, by optimizing the cap layer structure, a low-doped second cap layer is formed on a high-doped first cap layer as a protective layer, the second cap layer as a protective layer, on the one hand, isolates the first cap layer from the process solution, and on the other hand, utilizes its high-resistance characteristic to reduce the interface electric field of the metal edge, thereby significantly weakening or avoiding the electrochemical corrosion effect.
[0080] It should be noted that the embodiments in the present specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts of each embodiment can be referred to each other, and in addition, the different parts of each embodiment can also be used in combination, and the present application is not limited in this regard.
[0081] The above description is only the description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any change and modification made by the person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: A semiconductor substrate, an epitaxial layer, and a cap layer are stacked sequentially. The cap layer includes a highly doped first cap layer and a low-doped second cap layer. The second cap layer is located on the first cap layer and has trenches. as well as, An ohmic contact metal that at least fills the trench and is annealed to form an ohmic contact with the first cap layer.
2. The semiconductor structure as described in claim 1, characterized in that, The ohmic contact metal fills the trench and extends to the surface of a portion of the second cap layer.
3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the second cap layer is 10 Å to 100 Å.
4. The semiconductor structure as described in claim 1, characterized in that, The bottom of the groove is located within the second cap layer, or the groove penetrates the second cap layer, exposing the first cap layer.
5. The semiconductor structure as described in claim 1, characterized in that, The ohmic contact metal extends 100 nm to 800 nm on the surface of the second cap layer.
6. A semiconductor device, characterized in that, The semiconductor structure includes any one of claims 1 to 5, wherein the ohmic contact metal constitutes the source and drain of the semiconductor device.
7. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, and an epitaxial layer, a highly doped first cap layer, and a lightly doped second cap layer are sequentially formed on the semiconductor substrate; The second cap layer is etched to form trenches; Deposit ohmic contact metal, the ohmic contact metal at least filling the trench; as well as, A tempering process is performed to enable the ohmic contact metal to form an ohmic contact with the first cap layer.
8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, The etching process for the second cap layer includes: A photoresist layer is formed on the second cap layer, and the photoresist layer is exposed and first developed to give the photoresist layer an opening pattern; and, The second cap layer is etched using the photoresist layer as a mask to form the trench.
9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, Prior to depositing the ohmic contact metal, the preparation method further includes: The photoresist layer is developed a second time to enlarge the size of the opening pattern, thereby exposing part of the surface of the second cap layer; In the step of depositing the ohmic contact metal, the ohmic contact metal fills the trench while simultaneously covering the exposed surface of the second cap layer.
10. The method for preparing the semiconductor structure as described in claim 8, characterized in that, After depositing the ohmic contact metal, the fabrication method further includes removing the photoresist layer.