Silicon carbide MOSFET, preparation method thereof and power device

Abstract

The embodiment of the invention relates to a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a preparation method thereof and a power device. The silicon carbide MOSFET comprises an N-type substrate layer; the N-type epitaxial layer is formed on the front surface of the N-type substrate layer; the drain electrode layer is formed on the back surface of the N-type substrate layer; the first P-type well region and the second P-type well region are formed on the N-type epitaxial layer and are respectively positioned at two ends of the N-type epitaxial layer; the P-type ring is formed on the N-type epitaxial layer and located between the first P-type well region and the second P-type well region; the N-type source regions are respectively formed in the first P-type well layer and the second P-type well layer; the gate dielectric layer is formed on the first P-type well layer, the second P-type well layer and the P-type ring; the first grid electrode, the second grid electrode and the polycrystalline silicon field plate are respectively formed in the grid electrode dielectric layer and are not in contact with each other; wherein the polycrystalline silicon field plate corresponds to the P-type ring, and the first grid electrode and the second grid electrode are arranged on the two opposite sides of the polycrystalline silicon field plate respectively. According to the embodiment of the invention, the reliability of the silicon carbide MOSFET can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a silicon carbide MOSFET, a power device and a preparation method of the silicon carbide MOSFET. BACKGROUND

[0002] Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistor (MOSFET) has outstanding characteristics such as wide band gap, high critical breakdown field strength, high saturated electron drift speed and high thermal conductivity, so that it can play a role in high temperature, high pressure and high frequency fields compared with silicon material. Among them, the silicon carbide MOSFET has the characteristics of high voltage resistance and low on-resistance, and is more widely used than silicon-based devices of the same voltage level. Since the silicon carbide MOSFET has a higher critical breakdown field than the silicon-based device, the gate oxide layer in the silicon carbide has a high field strength. When the silicon carbide MOSFET is converted from a planar device to a trench device, the high field strength of the gate oxide layer will cause the reliability of the silicon carbide MOSFET to decrease. SUMMARY

[0003] Therefore, in order to overcome at least part of the defects and deficiencies of the prior art, the embodiments of the present application propose a silicon carbide MOSFET which can improve the reliability of the silicon carbide MOSFET.

[0004] In one aspect, the silicon carbide MOSFET according to the embodiments of the present application comprises: an N-type substrate layer; an N-type epitaxial layer formed on the front surface of the N-type substrate layer; a drain layer formed on the back surface of the N-type substrate layer; a first P-type well layer and a second P-type well layer, both of which are formed on the N-type epitaxial layer and are located on both ends of the N-type epitaxial layer, respectively; a P-type ring formed on the N-type epitaxial layer and located between the first P-type well layer and the second P-type well layer; an N-type source region formed in the first P-type well layer and the second P-type well layer, respectively; a gate dielectric layer formed on the first P-type well layer, the second P-type well layer and the P-type ring; a first gate, a second gate and a polysilicon field plate, which are respectively formed in the gate dielectric layer and do not contact each other; wherein the polysilicon field plate corresponds to the P-type ring, the first gate and the second gate are respectively arranged on opposite sides of the polysilicon field plate, the first gate corresponds to the first P-type well layer, and the second gate corresponds to the second P-type well layer.

[0005] In one embodiment of the present invention, the polysilicon field plate includes a main body portion, a first extension portion and a second extension portion, the main body portion corresponding to the P-type ring, the first extension portion and the second extension portion being disposed on both sides of the main body portion away from the N-type epitaxial layer; the first extension portion extends toward the first gate, and the second extension portion extends toward the second gate.

[0006] In one embodiment of the present invention, a trench region is provided at the end of the main body away from the P-ring, and the gate dielectric layer fills the trench region.

[0007] In one embodiment of the present invention, the depth of the trench region is 0.4 micrometers.

[0008] In one embodiment of the present invention, the thickness of the gate oxide layer is 0.46~0.5 micrometers.

[0009] In one embodiment of the present invention, the doping concentration of the P-type ring is higher than that of the first P-type well region and / or the second P-type well region.

[0010] In one embodiment of the present invention, the first P-type well layer includes a first heavily doped P-type well region and a first doped P-type well region. The first doped P-type well region is disposed close to the P-type ring, and the first heavily doped P-type well region is disposed on the side of the first P-type doped well region away from the P-type ring. The N-type source region is located on the first P-type doped well region. The P-type doping concentration of the first heavily doped P-type well region is higher than that of the first P-type doped well region. The second P-type well layer includes a second heavily doped P-type well region and a second doped P-type well region. The second doped well region is disposed close to the P-type ring, and the second heavily doped P-type well region is disposed on the side of the second P-type doped well region away from the P-type ring. The N-type source region is located on the second P-type doped well region. The P-type doping concentration of the second heavily doped P-type well region is higher than that of the second P-type doped well region.

[0011] In one embodiment of the present invention, the silicon carbide MOSFET further includes a source layer formed on the first P-type well layer, the second P-type well layer and the P-type ring, and the source layer is located on both sides of the gate dielectric layer.

[0012] On the other hand, an embodiment of the present invention provides a power device including: a silicon carbide MOSFET as described above.

[0013] In another aspect, the present invention provides a method for fabricating a silicon carbide MOSFET, comprising: forming an N-type epitaxial layer on the front side of an N-type substrate, and implanting a first P-type dopant ion and an N-type dopant ion in a portion of the N-type epitaxial layer away from the N-type substrate to form a first P-type well region, a second P-type well region and an N-type source region; A second P-type dopant ion is implanted into the N-type epitaxial layer to form a P-type ring between the first P-type well region and the second P-type well region. A first gate oxide layer is formed on the N-type source region and the P-type ring in the first P-type well region, the second P-type well region, and the P-type ring by a high-temperature thermal oxidation process. Polysilicon is deposited and etched on the gate oxide layer to form a first gate and a second gate, wherein the first gate corresponds to the first P-type well layer and the second gate corresponds to the second P-type well layer. A second gate oxide layer is deposited on the first gate and the second gate, and the second gate oxide layer is etched to form a first channel, which corresponds to the P-type ring. Polysilicon is deposited and etched on the first channel to form a polysilicon field plate. A third oxide layer is deposited on the polysilicon field plate so that the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer form a gate dielectric layer. The gate dielectric layer is etched and a source metal material is deposited to form a source layer. A drain layer is formed on the back side of the N-type substrate. As can be seen from the above, the technical features of the present invention can have the following beneficial effects: This application, by setting a polysilicon field plate in the gate dielectric layer and separating the gate into a first gate and a second gate, with the polysilicon field plate positioned above and corresponding to the P-type ring, can limit the highest electric field of the gate dielectric layer within the silicon carbide MOSFET and away from the gate dielectric layer when the silicon carbide MOSFET is reverse-biased, thereby improving the reliability of the silicon carbide MOSFET. Simultaneously, the gate being split into a first gate and a second gate, with the first and second gates respectively located on opposite sides of the polysilicon field plate, can reduce the capacitance of the gate dielectric layer in the silicon carbide MOSFET and improve the switching losses of the silicon carbide MOSFET. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a silicon carbide MOSFET provided in the first embodiment of the present invention.

[0016] Figure 2 for Figure 1The diagram shows a partial structural schematic.

[0017] Figure 3 This is a flowchart of a method for fabricating a silicon carbide MOSFET according to a second embodiment of the present invention.

[0018] Figures 4a-4j for Figure 3 The flowchart shown illustrates the specific preparation method.

[0019] [Explanation of Labels in the Attached Image] 10: Silicon carbide MOSFET; 100: N-type substrate layer; 110: N-type epitaxial layer; 120: Drain layer; 130: First P-type well layer; 131: First heavily doped P-type well region; 132: First P-type doped region; 140: Second P-type well layer; 141: Second heavily doped P-type well region; 142: Second P-type doped region; 150: P-type ring; 160: N-type source region; 170: Gate dielectric layer; 171: Polysilicon field plate; 172: First gate; 173: Second gate; 174: First gate oxide layer; 175: Second gate oxide layer; 176: Third gate oxide layer; 177: First channel; 180: Source layer; 1711: Body portion; 1712: First extension portion; 1713: Second extension portion; 1714: Trench region. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) possess outstanding characteristics such as a wide bandgap, high critical breakdown electric field, high saturation electron drift velocity, and high thermal conductivity, making them more suitable for high-temperature, high-voltage, and high-frequency applications compared to silicon. Among these, SiC MOSFETs, due to their combination of high voltage withstand capability and low on-resistance, have a wider range of applications compared to silicon-based devices of the same voltage rating.

[0022] Nevertheless, silicon carbide MOSFET devices still have a problem in current applications: when silicon carbide MOSFETs are converted from planar devices to trench devices, the high electric field strength of the gate oxide layer will lead to a decrease in the reliability of silicon carbide MOSFETs.

[0023] [First Embodiment] To further improve the reliability of silicon carbide MOSFETs and thus enhance device performance, this application proposes a silicon carbide MOSFET 10, such as... Figure 1 As shown, this embodiment of the invention provides a silicon carbide MOSFET 10. The silicon carbide MOSFET 10 includes, for example, an N-type substrate layer 100, an N-type epitaxial layer 110, a drain layer 120, a first P-type well layer 130, a second P-type well layer 140, a P-type ring 150, an N-type source region 160, a gate dielectric layer 170, a first gate 172, a second gate 173, and a polysilicon field plate 171.

[0024] Specifically, the N-type epitaxial layer 110 is formed on the front side of the N-type substrate layer 100, and the drain layer 120 is formed on the back side of the N-type substrate layer 100. The N-type substrate 100 is, for example, an N+ substrate, which forms the basis for fabricating silicon carbide MOSFETs. Subsequent components, such as epitaxial layers, need to be grown on the N-type substrate 100. The substrate can be, for example, a wafer made of semiconductor single-crystal material, which is an important step in semiconductor fabrication, laying the foundation for subsequent circuit etching. The drain layer 120 can be, for example, a drain metal electrode, which is horizontally placed, with the N+ region located on the upper surface of the drain metal circuit. The N-type epitaxial layer 110 can be, for example, an N- drift region, located on the upper surface of the N-type substrate layer 110.

[0025] The first P-type well layer 130 and the second P-type well layer 140 are both formed on the N-type epitaxial layer 110 and are located at both ends of the N-type epitaxial layer 110, respectively. The first P-type well layer 130 and the second P-type well layer 140 are arranged in a U-shape and are symmetrically located at the top inside the N-type epitaxial layer 110.

[0026] The P-type ring 150 is located between the first P-type well layer 130 and the second P-type well layer 140 in the N-type epitaxial layer 110. The N-type source region 160 is located within the first P-type well layer 130 and the second P-type well layer 140, respectively, and is attached to the upper surface of the N-type epitaxial layer 110. The gate dielectric layer 170 is located on the upper surface of the region of the N-type epitaxial layer 110 excluding the first P-type well layer 130, the second P-type well layer 140, the N-type source region 160, and the P-type ring 150, that is, on the upper surfaces of the first P-type well layer 130, the second P-type well layer 140, the N-type source region 160, and the P-type ring 150. The first gate 172, the second gate 173, and the polysilicon field plate 171 are respectively formed within the gate dielectric layer 170 and do not contact each other; wherein, the polysilicon field plate 171 corresponds to the P-type ring 150, the first gate 172 and the second gate 173 are respectively disposed on opposite sides of the polysilicon field plate 171, the first gate 172 corresponds to the first P-type well layer 130, and the second gate 173 corresponds to the second P-type well layer 140.

[0027] The N-type source region 160 can be, for example, an N+ source region, and there are, for example, two N-type source regions 160, which are respectively disposed at the top of the interior of the first P-type well layer 130 and the second P-type well layer 140. The P-type ring is, for example, a P-ring, wherein the doping concentration of P- ions in the P-ring is higher than the doping concentration of P- ions in the first P-type well layer 130 and / or the second P-type well layer 140. The bottom of the gate dielectric layer 170 is in contact with the top of the N-type source region 160, the P-type ring 150, the first P-type well layer 130, and the second P-type well layer 140. The polysilicon field plate 171 is located at the center of the interior of the gate dielectric layer 170. The first gate 172 and the second gate 173 are respectively located on both sides of the polysilicon field plate 171 and close to the bottom of the gate dielectric layer 170. The first gate 172 and the second gate 173 are not in contact with the polysilicon field plate 171, the N-type source region 160, the first P-type well layer 130 and the second P-type well layer.

[0028] In this embodiment, a polysilicon field plate 171 is disposed in the gate dielectric layer 170, and the gate is separated into a first gate 172 and a second gate 172. The polysilicon field plate 171 is disposed above and corresponds to the P-type ring 150. By combining the polysilicon field plate 171 with the P-type ring 150, the polysilicon field plate 171 disperses the vertical electric field in the gate dielectric layer 170 to the lateral direction through capacitive coupling, thereby reducing the peak electric field of the gate dielectric layer 170. The P-type ring 150 can extend the depletion region laterally, transferring the peak electric field at the curvature to the first P-type well layer and the second P-type well layer. When the silicon carbide MOSFET 10 is reverse biased, the highest electric field of the gate dielectric layer 170 can be limited within the silicon carbide MOSFET 10 and away from the gate dielectric layer 170, thereby improving the reliability of the silicon carbide MOSFET 10. Simultaneously, the gate is split into a first gate 172 and a second gate 173 in the gate dielectric layer 170, with the first gate 172 and the second gate 173 located on opposite sides of the polysilicon field plate 171. This reduces the capacitance of the 10 gate dielectric layer in the silicon carbide MOSFET and improves the switching losses of the silicon carbide MOSFET. In other words, this application forms a split gate structure based on existing planar gate devices, and forms a P-type field ring in the middle part of the split gate structure by ion implantation. A floating field plate is formed above the field ring. When the device is reverse biased, the depletion layer of the field ring connects with the depletion layer of the p-well region, protecting the gate dielectric layer. Furthermore, the field plate suppresses high electric fields on the surface, keeping them away from the surface and ensuring the reliability of the gate dielectric layer.

[0029] Furthermore, such as Figure 2 As shown, the polysilicon field plate 171 includes a main body 1711, a first extension 1712, and a second extension 1713. The main body 1711 corresponds to the P-type ring 150. The first extension 1712 and the second extension 1713 are disposed on both sides of the main body 1711 away from the N-type epitaxial layer 110. The first extension 1712 extends toward the first gate 172, and the second extension 1713 extends toward the second gate 173. By setting the structure of the polysilicon field plate 171 to resemble a T-shaped structure, it can cooperate with the P-type ring when the silicon carbide MOSFET is operating normally, thereby widening the depletion region at the bottom of the first gate 172 and the second gate 173, thereby reducing the electric field at this point and improving the high-frequency performance and short-circuit capability of the device.

[0030] Furthermore, a trench region 1714 is provided at one end of the main body portion 1711 away from the P-ring 150, and the gate dielectric layer 170 can fill the trench region 1714.

[0031] Furthermore, the depth of the trench region 1714 is 0.4 micrometers.

[0032] Furthermore, the thickness of the gate dielectric layer 170 is 0.46-0.5 micrometers. Specifically, the thickness of the gate dielectric layer 170 can be, for example, 0.46 micrometers, 0.48 micrometers, or 0.5 micrometers, wherein the distance between the first gate 172 and the second gate 173 and the underlying epitaxial layer 110 can be, for example, 0.045 micrometers, and the distance between the first gate 172 and the second gate 173 and the top of the gate dielectric layer can be, for example, 0.45 micrometers. By setting the thickness of the gate dielectric layer, the electric field strength of the silicon carbide MOSFET can be reduced, thereby further improving the reliability of the silicon carbide MOSFET.

[0033] Furthermore, the doping concentration of the P-ring 150 is higher than that of the first P-well layer 130 and / or the second P-well layer 140. The concentration of P-ions implanted during the formation of the P-ring 150 is also higher than that implanted during the formation of the first P-well layer 130 and / or the second P-well layer 140.

[0034] Furthermore, such as Figure 1 As shown, the first P-type well layer 130 includes a first heavily doped P-type well region 131 and a first doped P-type well region 132. The first P-type doped well region 132 is located close to the P-type ring 150, and the first heavily doped P-type well region 131 is located on the side of the first P-type doped well region 132 away from the P-type ring 150. The N-type source region 160 is located on the first P-type doped well region 132. The P-type doping concentration of the first heavily doped P-type well region 131 is higher than that of the first P-type doped well region 132. The first P-type doped well region 132 can be, for example, a lightly doped P-type region formed by implanting low to medium doses of boron or indium ions, which can construct the channel region of a silicon carbide MOSFET. The first heavily doped P-type well region 131 can be implanted with a high concentration of P+ at a specific location on the first P-type doped well region 132, such as near the outer edge, to suppress the lateral expansion of the depletion region. Of course, the ion implantation of the first P-type doped well region 132 and the first P-type doped well region 131 can be formed with reference to the relevant parameters of silicon carbide MOSFET in the prior art, and the specifics will not be elaborated here.

[0035] The second P-type well layer 140 includes a second heavily doped P-type well region 141 and a second doped P-type well region 142. The second P-type doped well region 142 is disposed close to the P-type ring 150, and the second heavily doped P-type well region 141 is disposed on the side of the second P-type doped well region 142 away from the P-type ring 150. The N-type source region 160 is located on the second P-type doped well region 142. The P-type doping concentration of the second heavily doped P-type well region 141 is higher than that of the second P-type doped well region 142.

[0036] The formation process and differences between the second P-type heavily doped well region 141 and the second P-type doped well region 142 can be referred to the first P-type doped well region 131 and the first P-type doped well region 132 described above, and will not be repeated here.

[0037] Furthermore, the silicon carbide MOSFET also includes a source layer 180, which is formed on the first P-type well layer 130, the second P-type well layer 140 and the P-type ring 150, and the source layer 180 is located on both sides of the gate dielectric layer 170.

[0038] [Second Embodiment] like Figure 3 , Figure 4a Figure 4 shows a fabrication process for a silicon carbide MOSFET in this embodiment. The silicon carbide MOSFET can be described with reference to the silicon carbide MOSFET 10 described in the first embodiment above. The specific structure of the silicon carbide MOSFET can be referred to the silicon carbide MOSFET described in the first embodiment above, and will not be repeated here.

[0039] Specifically, such as Figure 3 As shown in the figure, this embodiment provides a silicon carbide MOSFET fabrication process as follows: S11. An N-type epitaxial layer is formed on the front side of the N-type substrate, and first P-type dopant ions and N-type dopant ions are implanted in a portion of the N-type epitaxial layer away from the N-type substrate to form a first P-type well region, a second P-type well region and an N-type source region. S12. Implant a second P-type dopant ion into the N-type epitaxial layer to form a P-type ring between the first P-type well region and the second P-type well region; S13. A first gate oxide layer is formed on the N-type source region and the P-type ring of the first P-type well layer, the second P-type well layer, and the P-type ring by a high-temperature thermal oxidation process. S14. Polysilicon is deposited and etched on the gate oxide layer to form a first gate and a second gate; wherein the first gate corresponds to the first P-type well layer and the second gate corresponds to the second P-type well layer. S15. A second gate oxide layer is deposited on the first gate and the second gate, and the second gate oxide layer is etched to form a first channel, the first channel corresponding to the P-type ring; S16. Deposit and etch polysilicon in the first trench to form a polysilicon field plate; S17. A third oxide layer is deposited on the polysilicon field plate so that the first oxide layer, the second gate oxide layer and the third oxide layer together form a gate dielectric layer. S18. Etch the gate dielectric layer and deposit the source metal material to form the source layer; S19. A drain layer is formed on the back side of the N-type substrate.

[0040] See Figure 4a - The specific process for fabricating the silicon carbide MOSFET in this application is as follows: First, such as Figure 4a As shown, an N-type epitaxial layer 110 is epitaxially grown on a silicon carbide-based N-type substrate 100, and then P- ions are implanted on the surface of the N-type epitaxial layer 110 to form a first P-type well layer 130 and a second P-type well layer 140 (that is, to form a channel region).

[0041] Secondly, such as Figure 4b As shown, P-ions are implanted between the first P-type well layer 130 and the second P-type well layer 140 to form a P-type ring 150, wherein the ion doping concentration implanted in the P-type ring 150 is higher than the ion doping concentration implanted in the first P-type well layer 130 and / or the second P-type well layer 140.

[0042] like Figure 4c As shown, N+ ions are implanted on top of the first P-type well layer 130 and the second P-type well layer 140 to form an N-type source region on top of the first P-type well layer 130 and the second P-type well layer 140.

[0043] like Figure 4d As shown, P+ ions are implanted on both outer sides of the first P-type well layer 130 and the second P-type well layer 140 to form regions that suppress depletion and lateral expansion. Figure 4a The implanted p-ions can form a first doped well region 132 of the first p-type well region 130, and the region formed by the implantation of p+ ions in the first p-type well region 130 is the first heavily doped well region 131. Meanwhile, Figure 4a The implanted P- ions can form the second doped well region 142 of the second P-type well region 140, and the region formed by the implantation of P+ ions in the second P-type well region 140 is the second heavily doped well region 141.

[0044] like Figure 4eAs shown, a first gate oxide layer 174 is first formed on the upper surface of the N-type epitaxial layer 110 using a high-temperature process. This gate oxide layer serves as an insulating layer, insulating the N-type source region 160, the first P-type well region 130, the second P-type well region 140, and the P-type ring 150. Then, polysilicon is deposited on the first gate oxide layer 174, and the polysilicon is etched to form a first gate 172 and a second gate 173. The first gate 172 is located above a portion of the N-type source region 160 and a portion of the first P-type well region 130, and the second gate 173 is located above a portion of the N-type source region 160 and a portion of the second P-type well region 140.

[0045] like Figure 4f As shown, in Figure 4e On top of that, a thick oxide layer is deposited to form a second gate oxide layer 175 on the first gate oxide layer 174. Then, the second gate oxide layer 175 is etched at the P-ring 150 to form a first channel 177.

[0046] like Figure 4g As shown, polysilicon is deposited again to completely fill the first channel 177. Then, the polysilicon is etched to form a U-shaped polysilicon field plate 171. The specific structure of the polysilicon field plate 171 can be referred to the structure described in the first embodiment, and will not be repeated here.

[0047] like Figure 4h As shown, an oxide layer is deposited again to form a third gate oxide layer 176 on the second gate oxide layer 175. At the same time, the first gate oxide layer 174, the second gate oxide layer 175 and the third gate oxide layer 176 can jointly form a gate dielectric layer 170.

[0048] like Figures 4i-4j As shown, the outer side of the gate dielectric layer 170 is etched, and metal is deposited at the etched area to form the source layer 180, and a drain layer 120 is formed below the N-type substrate layer 100 to complete the fabrication process of the silicon carbide MOSFET.

[0049] In this embodiment, a polysilicon field plate 171 is disposed in the gate dielectric layer 170, and the gate is separated into a first gate 172 and a second gate 172. The polysilicon field plate 171 is disposed above and corresponds to the P-type ring 150. By combining the polysilicon field plate 171 with the P-type ring 150, the polysilicon field plate 171 disperses the vertical electric field in the gate dielectric layer 170 to the lateral direction through capacitive coupling, thereby reducing the peak electric field of the gate dielectric layer 170. The P-type ring 150 can extend the depletion region laterally, transferring the peak electric field at the curvature to the first P-type well layer and the second P-type well layer. When the silicon carbide MOSFET 10 is reverse biased, the highest electric field of the gate dielectric layer 170 can be limited within the silicon carbide MOSFET 10 and away from the gate dielectric layer 170, thereby improving the reliability of the silicon carbide MOSFET 10. Meanwhile, the gate is split into a first gate 172 and a second gate 173 in the gate dielectric layer 170, and the first gate 172 and the second gate 173 are located on both sides of the polysilicon field plate 171, which can reduce the capacitance of the gate dielectric layer in the silicon carbide MOSFET and improve the switching loss of the silicon carbide MOSFET.

[0050] [Third Embodiment] In this embodiment, the power device includes the silicon carbide MOSFET as described in the first embodiment above, and the power device is, for example, a low-voltage to medium-voltage power MOSFET.

[0051] The specific effects of the power device are as described in the first embodiment above, and will not be repeated here.

[0052] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide MOSFET (10), characterized in that, include: N-type substrate layer (100); An N-type epitaxial layer (110) is formed on the front side of the N-type substrate layer (100); A drain layer (120) is formed on the back side of the N-type substrate layer (100); The first P-type well layer (130) and the second P-type well layer (140) are both formed on the N-type epitaxial layer (110) and are located at both ends of the N-type epitaxial layer (110); A P-type ring (150) is formed on the N-type epitaxial layer (110) and located between the first P-type well layer (130) and the second P-type well layer (140); N-type source regions (160) are formed in the first P-type well layer (130) and the second P-type well layer (140), respectively; A gate dielectric layer (170) is formed on the first P-type well layer (130), the second P-type well layer (140), and the P-type ring (150); The first gate (172), the second gate (173), and the polysilicon field plate (171) are respectively formed in the gate dielectric layer (170) and do not contact each other; wherein, the polysilicon field plate (171) corresponds to the P-type ring (150), the first gate (172) and the second gate (173) are respectively disposed on opposite sides of the polysilicon field plate (171), the first gate (172) corresponds to the first P-type well layer (130), and the second gate (173) corresponds to the second P-type well layer (140).

2. The silicon carbide MOSFET (10) according to claim 1, characterized in that, The polycrystalline silicon field plate (171) includes a main body (1711), a first extension (1712) and a second extension (1713). The main body (1711) corresponds to the P-type ring (150). The first extension (1712) and the second extension (1713) are disposed on both sides of the main body (1711) away from the N-type epitaxial layer (110). The first extension (1712) extends toward the first gate (172), and the second extension (1713) extends toward the second gate (173).

3. The silicon carbide MOSFET (10) according to claim 2, characterized in that, The main body (1711) has a trench region (1714) at one end away from the P-ring (150), and the gate dielectric layer (170) can fill the trench region (1714).

4. The silicon carbide MOSFET (10) according to claim 2, characterized in that, The depth of the trench region (1714) is 0.4 micrometers.

5. The silicon carbide MOSFET (10) according to claim 1, characterized in that, The thickness of the gate dielectric layer (170) is 0.46~0.5 micrometers.

6. The silicon carbide MOSFET (10) according to claim 1, characterized in that, The doping concentration of the P-type ring (150) is higher than that of the first P-type well layer (130) and / or the second P-type well layer (140).

7. The silicon carbide MOSFET (10) according to claim 1, characterized in that, The first P-type well layer (130) includes a first heavily doped P-type well region (131) and a first doped P-type well region (132). The first P-type doped well region (132) is located close to the P-type ring (150), and the first heavily doped P-type well region (131) is located on the side of the first P-type doped well region (132) away from the P-type ring (150). The N-type source region (160) is located on the first P-type doped well region (132). The P-type doping concentration of the first heavily doped P-type well region (131) is higher than that of the first P-type doped well region (132). The second P-type well layer (140) includes a second heavily doped P-type well region (141) and a second doped P-type well region (142). The second P-type doped well region (142) is located close to the P-type ring (150), and the second heavily doped P-type well region (141) is located on the side of the second P-type doped well region (142) away from the P-type ring (150). The N-type source region (160) is located on the second P-type doped well region (142). The P-type doping concentration of the second heavily doped P-type well region (141) is higher than that of the second P-type doped well region (142).

8. The silicon carbide MOSFET (10) according to any one of claims 1-7, characterized in that, The silicon carbide MOSFET further includes a source layer (180), which is formed on the first P-type well layer (130), the second P-type well layer (140) and the P-type ring (150), and the source layer (180) is located on both sides of the gate dielectric layer (170).

9. A power device, characterized in that, include: The silicon carbide MOSFET as described in any one of claims 1-8 above.

10. A method for fabricating a silicon carbide MOSFET, characterized in that, include: An N-type epitaxial layer is formed on the front side of the N-type substrate, and first P-type dopant ions and N-type dopant ions are implanted in a portion of the N-type epitaxial layer away from the N-type substrate to form a first P-type well region, a second P-type well region and an N-type source region. A second P-type dopant ion is implanted into the N-type epitaxial layer to form a P-type ring between the first P-type well region and the second P-type well region; A first gate oxide layer is formed on the N-type source region and the P-type ring of the first P-type well layer and the second P-type well layer by a high-temperature thermal oxidation process. Polysilicon is deposited and etched on the gate oxide layer to form a first gate and a second gate; wherein the first gate corresponds to the first P-type well layer and the second gate corresponds to the second P-type well layer; A second gate oxide layer is deposited on the first gate and the second gate, and the second gate oxide layer is etched to form a first channel, the first channel corresponding to the P-type ring; Polysilicon is deposited and etched in the first trench to form a polysilicon field plate; A third oxide layer is deposited on the polysilicon field plate such that the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer together form a gate dielectric layer; The gate dielectric layer is etched and the source metal material is deposited to form the source layer; A drain layer is formed on the back side of the N-type substrate.

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