A photovoltaic silicon monocrystal wafer set, a crystal column set, a photovoltaic cell and a photovoltaic assembly

Abstract

The application discloses a photovoltaic silicon monocrystal wafer group, a crystal column group, a photovoltaic cell and a photovoltaic module. The wafer group comprises rectangular silicon wafers cut from the middle of a base circle silicon wafer and axisymmetric non-rectangular polygonal silicon wafers symmetrically cut from the periphery of the rectangular silicon wafers. The cutting size of the rectangular silicon wafers is determined according to the distribution of vacancy-type point defect density C V and interstitial-type point defect density C I of the base circle silicon wafer and the distribution of minority carrier lifetime in different radial regions of the base circle silicon wafer, so that the rectangular silicon wafers are located in the region of C V ‑ C I ≥0, and the ratio d of the distance between the four corners of the rectangular silicon wafer and the minimum point of the minority carrier lifetime in the edge region of the base circle silicon wafer to the diameter of the base circle silicon wafer is 2%≤d≤8%. The method is based on the quality distribution rule of the silicon wafer to divide the silicon wafers into two types, and different cell processes are adopted to fully tap the potential of each type, so that the area utilization rate of the base circle silicon wafer is more than 90% while high-quality photovoltaic modules are obtained.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic power generation technology, specifically to a photovoltaic silicon single crystal wafer array, a crystal pillar array, a photovoltaic cell, and a photovoltaic module. Background Technology

[0002] The background technology of this invention is based on the production of square, hexagonal and octagonal silicon wafers cut from cylindrical silicon single crystal pillars and the photovoltaic cells and photovoltaic modules made therefrom.

[0003] The shortcomings of existing technology;

[0004] 1) The differences in quality parameters in different areas of the silicon wafer were not taken into account.

[0005] The quality parameters of the material differ significantly between the edge and center of a Czochralski silicon wafer. Current technology fabricates photovoltaic cells on the same wafer without distinguishing between these differences. This results in the lower-quality regions limiting the photoelectric conversion efficiency of the higher-quality regions. Furthermore, the edge region experiences greater mechanical stress and a higher density of self-gap point defects (C0). I Both low minority carrier lifetime and low efficiency reduce the overall conversion efficiency and operational reliability of photovoltaic cells.

[0006] 2) The standardization of silicon wafer slicing is low.

[0007] Existing silicon wafer utilization technology is low. In particular, the most commonly used rectangular-divided silicon single-wafer has the lowest material utilization. In order to improve the area utilization of the base wafer, many silicon wafer division methods based on regular hexagons, regular octagons, and edge reuse have been proposed. However, the shape and size of the silicon wafers divided by existing silicon wafer division methods rarely consider compatibility with the size of standard photovoltaic modules, making it difficult to achieve product standardization and serialization, and hindering the reduction of production, transportation, installation and operation costs.

[0008] 3) Sliced ​​silicon wafers often have sharp corners, which can cause stress concentration.

[0009] Existing silicon wafer slicing techniques often result in sharp corners, which can easily lead to chipping and missing corners, affecting product quality and causing numerous inconveniences in use.

[0010] 4) Bypass diodes are complex to set up and costly.

[0011] Existing technologies, due to the small area of ​​spliced ​​cells and the large number of series-connected cells, increase the output voltage of photovoltaic modules in series, requiring more bypass diodes for bypass protection, which increases the complexity of the wiring. To address this, existing technologies use a method of first connecting in series and then in parallel, but this also complicates the connection of photovoltaic modules, increasing costs, failure rates, and fire risks.

[0012] The present invention is proposed to address at least one deficiency in the prior art.

[0013] Nouns and terms

[0014] For ease of expression, this application document defines the following terms and concepts:

[0015] Base circle:

[0016] The base circle is the outline circle of the cross-section of a cylindrical silicon single crystal pillar or the outline circle of a circular silicon wafer cut from a cylindrical silicon single crystal pillar. If the cross-section of the silicon single crystal deviates significantly from the circle and does not meet the subsequent slitting requirements, then the base circle is the circumscribed circle that has undergone preliminary processing and can encompass all the slitted parts.

[0017] Photovoltaic silicon single crystal wafers:

[0018] The silicon single crystal used to manufacture photovoltaic cells is also referred to as "silicon wafer" in this application.

[0019] Silicon wafer:

[0020] A photovoltaic silicon single crystal wafer with its outer contour circle as the base circle.

[0021] Rectangular silicon wafers:

[0022] This application document refers to a rectangular or square silicon wafer cut from the middle of a base-circle silicon wafer.

[0023] Pentagonal silicon wafer:

[0024] This application document refers to an axisymmetric quasi-pentagonal silicon wafer cut from the outer periphery of the rectangular silicon wafer.

[0025] Hexagonal silicon wafer:

[0026] This application refers to an axisymmetric quasi-hexagonal silicon wafer cut from the outer periphery of the rectangular silicon wafer, wherein one side of the hexagon can be a straight line or a curve with a chord height less than 1% of the base circle diameter.

[0027] Film series:

[0028] 1) All rectangular and non-rectangular polygonal silicon wafers that can be used to fabricate photovoltaic cells, cut from the same base silicon wafer;

[0029] 2) All non-rectangular polygonal silicon wafers or non-rectangular polygonal solar cells used to form a single cell parallel group.

[0030] Base silicon pillar:

[0031] A cylindrical silicon cylinder based on the shape of a base silicon wafer.

[0032] Rectangular silicon pillars:

[0033] A rectangular silicon cylinder with the shape of a rectangular silicon wafer as its base.

[0034] Pentagonal silicon pillar:

[0035] A pentagonal silicon cylinder based on the shape of a pentagonal silicon wafer.

[0036] Hexagonal silicon pillars:

[0037] A hexagonal silicon cylinder based on the shape of a hexagonal silicon wafer.

[0038] Column group:

[0039] All rectangular silicon pillars and non-rectangular polygonal silicon pillars are divided from the same basic circular silicon pillar.

[0040] Curve, chord height of the curve:

[0041] In this application, the chord of a curve is defined as the line connecting the two endpoints that intersect with an adjacent side; the chord height of a curve is defined as the maximum distance between the pole of the curve and the chord of the curve; a straight line is a curve with a chord height of zero, and the curves in this application include straight lines.

[0042] Quasi-rectangle (quasi-n-gon, etc.):

[0043] It refers to a rectangle (or n-sided polygon) that can be viewed in engineering terms, but is not a perfect rectangle (or n-sided polygon) in the geometric sense, and has some gaps, machining allowances, chamfers, and transition curves.

[0044] Median minority carrier lifetime test results for silicon wafers (silicon pillars):

[0045] The median (or median value) refers to the middle value in a set of data arranged in order of magnitude, or the average of two middle values. In this application, the median minority carrier lifetime of a silicon wafer (silicon pillar) refers to the median of all data measured at points excluding the data measured within 20 mm of the base circle of the silicon wafer (silicon pillar).

[0046] Test method: Measure at equal intervals along the diameter of the base circle silicon pillar, starting 20mm from the outer edge, with a spacing of no more than 20mm, and take the median value.

[0047] Tandem photovoltaic cells:

[0048] This refers to a combined photovoltaic cell that includes a top cell and a bottom cell, with the optical path connected in series.

[0049] Back contact photovoltaic cells:

[0050] A photovoltaic cell with positive and negative electrodes extending from the back of the battery (not the main light-receiving surface).

[0051] Two-part and three-part films:

[0052] A rectangular silicon wafer with the same length as the side length of the aforementioned rectangular silicon wafer and the same width as half the side length of the aforementioned rectangular silicon wafer is called a two-part wafer; a rectangular silicon wafer with the same length as the side length of the aforementioned rectangular silicon wafer and the same width as one-third the side length of the aforementioned rectangular silicon wafer is called a three-part wafer.

[0053] The lowest minority carrier lifetime in the edge region of the silicon wafer:

[0054] Example: Based on simulation and experimental results, for silicon single crystals produced by the Czochralski method, the "minority carrier lifetime minimum point in the edge region of the base wafer" is located on the circumference of the base wafer. Depending on the type of silicon single crystal, the "minority carrier lifetime minimum point in the edge region of the base wafer" may also be located in a region close to the circumference of the base wafer, for example, a region 0.1mm-100mm, 0.12mm-50mm, 0.13mm-30mm, 0.13mm-20mm, 0.13mm-10mm, etc., at a distance from the circumference of the base wafer. Summary of the Invention

[0055] To overcome at least one of the shortcomings of the prior art, the present invention provides the following technical solution:

[0056] In a first aspect, the present invention provides a photovoltaic silicon monolithic wafer assembly with a (100) crystal plane, the wafer assembly comprising a rectangular silicon wafer cut from the center of a base wafer and an axisymmetric non-rectangular polygonal silicon wafer symmetrically cut from the periphery of the rectangular silicon wafer, wherein the rectangular silicon wafer is cut according to the vacancy-type point defect density C of the base wafer. V and self-gap type point defect density C I The distribution of the rectangular silicon wafer places it in C V - C I Regions ≥0, C V - C I Regions with C ≥ 0 can be simulated using simulation software such as CGSim and FEMAG, where initial and boundary conditions are substituted into the silicon single crystal rod. V -C I The distribution map is determined; after engineering verification, the specific operation can be controlled so that the rectangular silicon wafer, including its four corners, is located in the region where the minority carrier lifetime of the base circular silicon wafer is higher than 80% of its "median"; and / or, based on the distribution of minority carrier lifetime in different radial regions of the base circular silicon wafer, the ratio d of the distance between the four corners of the rectangular silicon wafer to the inferred lowest point of the minority carrier lifetime in the edge region of the base circular silicon wafer and the diameter of the base circular silicon wafer is determined, 2%≤d≤8%.

[0057] Its beneficial effects are explained as follows:

[0058] See Figure 6 , Figure 7 , Figure 8 .

[0059] Figure 6 This is an example of a simulation calculation of the internal stress in a 300mm diameter silicon single crystal rod, by... Figure 6 It is evident that at a meaningful pulling speed, the von Mises stress increases significantly within a 10mm radius at the edge of the silicon single crystal. This stress originates from the heat dissipation on the surface of the silicon single crystal rod and the pulling action during its fabrication, which results in a concave crystallization interface. Higher pulling speeds lead to a steeper slope at the concave edge, resulting in greater internal stress within the crystal. Therefore, Figure 6 The stress growth curve shown is common to Czochralski silicon single crystals.

[0060] Figure 7 It is a simulated silicon single crystal rod in C V -C I The distribution map of C, where C V It is the concentration of vacancy-type defects within a silicon single crystal, C I The concentration of interstitial micro-defects within a silicon single crystal, where C I The negative impact on minority carrier lifetime of silicon single crystals is much greater than that on C. V When C V -C I When C is close to 0, V C I The impact on the minority carrier lifetime of silicon single crystals is minimal. Therefore, C V -C I The changes in [the value] show a good correlation with the minority carrier lifetime of silicon single crystals. Therefore, the rectangular silicon wafer is positioned at C [the desired value]. V - C I The region ≥0 is, in engineering alternatives, determined by having the rectangular silicon wafer, including its four corners, located in the region where the minority carrier lifetime of the base circular silicon wafer is higher than 80% of its "median".

[0061] Figure 8 The measured value is the radial distribution of minority carrier lifetime of a silicon single crystal pillar with a diameter of 315 mm. The measured value of this embodiment shows the radial distribution of minority carrier lifetime of the silicon single crystal in the constant diameter growth section of the silicon rod. As can be seen from the figure, the edge of the silicon single crystal pillar in this embodiment is about 10 mm thick, which is the low minority carrier lifetime region.

[0062] Regions with low minority carrier lifetime and stress distribution in silicon single crystals and C V -C I The changes are strongly correlated.

[0063] Therefore, it can be seen that silicon wafers obtained in the middle of the base wafer have lower stress and longer minority carrier lifetime, and rectangular silicon wafers obtained in the middle of the base wafer are of better quality.

[0064] Therefore, one of the beneficial effects of the present invention is that, based on the vacancy-type point defect density C of the base wafer... V and self-gap type point defect density CI The distribution of the rectangular silicon wafer places it in C V - C I The region ≥0, or the position of the rectangular silicon wafer corner determined based on the distribution of minority carrier lifetime in different radial regions of the base wafer, controlled by the ratio d of the distance between the corner of the rectangular silicon wafer and the lowest point of minority carrier lifetime in the edge region of the base wafer to the diameter of the base wafer, and / or by ensuring that the rectangular silicon wafer, including its four corners, is located in a region where the minority carrier lifetime of the base wafer is higher than 80% of its "median value". Preferably, both conditions are met simultaneously, thereby avoiding any point of the rectangular silicon wafer (e.g., the corner) from potentially influential areas such as the von Mises stress mutation range, and C. I Regions with high defect density and low minority carrier lifetime are avoided, thus improving the quality of rectangular silicon wafers. This allows for the optimization of photovoltaic cell manufacturing processes for both the rectangular wafers in the center and the non-rectangular polygonal wafers at the edges, fully maximizing the potential of each wafer and achieving a photovoltaic cell combination with optimal quality.

[0065] Furthermore, the non-rectangular polygonal silicon wafer is an axisymmetric pentagonal silicon wafer or an axisymmetric hexagonal silicon wafer. If it is a hexagonal silicon wafer, one of its sides is a curve, and the ratio of the chord height of the curve to the diameter of the base circle silicon wafer is less than 1%. The longest side of the pentagonal or hexagonal silicon wafer is aligned with the long side of the rectangular silicon wafer. The term "aligned" means that, after taking into account factors such as gaps, processing allowances, and transition chamfers, the longest side of the pentagonal or hexagonal silicon wafer is flush with the long side of the rectangular silicon wafer.

[0066] Furthermore, the pentagonal or hexagonal silicon wafer is the first silicon wafer. The pentagonal or hexagonal silicon wafer is cut along the axis of symmetry to obtain the second silicon wafer. The n (n≥1) first silicon wafers and the two second silicon wafers are spliced ​​together to form a rectangle.

[0067] Furthermore, the number of the first silicon wafers is odd. The odd number of first silicon wafers are spliced ​​with two second silicon wafers to form a rectangle compatible with the dimensions of the rectangular silicon wafer. Compatibility means that the width of the spliced ​​rectangle is a simple fraction of the width of the rectangular silicon wafer, such as 1 / 2, 1 / 3, etc., and the length of the spliced ​​rectangle is a simple multiple of the length of the rectangular silicon wafer, such as 1, 2, 3, ... 12. It should be noted that the dimensions here are only for obtaining the width and serialized length of photovoltaic modules compatible with the rectangular silicon wafer, and are not precise dimensions.

[0068] For example, one of the pentagonal or hexagonal silicon wafers can be cut along its axis of symmetry and then spliced ​​with another pentagonal or hexagonal silicon wafer to form a rectangle with an aspect ratio of 2:1 or 3:1. This allows for the production of products with electrical and installation parameters completely consistent with those of conventional "two-piece" or "three-piece" wafers.

[0069] Its beneficial effects are as follows: the size of the rectangular silicon wafer located in the middle of the base wafer is fully compatible with existing battery process equipment, photovoltaic module technical parameters, and photovoltaic power station system design, which is conducive to improving the standardization and compatibility of related batteries, modules, and power stations; when the non-rectangular polygonal silicon wafer adopts a pentagonal or hexagonal silicon wafer, the length of the pentagonal or hexagonal silicon wafer is the same as the length of one side of the central rectangular silicon wafer. After cutting one of the pentagonal or hexagonal silicon wafers along the axis of symmetry, the pentagonal or hexagonal silicon wafers can be spliced ​​into a rectangle compatible with the size of the rectangular silicon wafer. For example, they can be spliced ​​into the commonly used "three-part wafer" or "two-part wafer", so that the photovoltaic module can have the same external dimensions, output voltage, current, and power as existing products.

[0070] Furthermore, the ratio of the sum of the areas of the wafer group to the area of ​​the base wafer, k, is one of the following:

[0071] 1) 88% < k ≤ 92%;

[0072] 2) 92% < k ≤ 95%.

[0073] Furthermore, the thickness d of the silicon wafers of the same shape in the wafer group falls within one of the following ranges:

[0074] 1) 50μm≤d<85μm;

[0075] 2) 85μm≤d<98μm;

[0076] 3) 98μm≤d<115μm;

[0077] 4) 115μm≤d<135μm;

[0078] 5) 135μm≤d<160μm.

[0079] This allows for the use of different silicon wafer thicknesses for silicon wafers of different areas, minimizing energy consumption and improving battery quality through different processes.

[0080] In a second aspect, the present invention provides a silicon single crystal pillar assembly for cutting photovoltaic silicon single crystal wafers with a (100) crystal plane, comprising a rectangular silicon pillar with the aforementioned rectangular silicon wafer as the base and a non-rectangular polygonal silicon pillar with the aforementioned non-rectangular polygonal silicon wafer as the base, wherein the angle between the direction of the generatrix of the silicon pillar and the <100> crystal direction is 0° to 3°.

[0081] Preferably, the non-rectangular polygonal silicon wafer is an axisymmetric pentagon or an axisymmetric hexagon, one side of which is a curve, and the ratio of the chord height of the curve to the diameter of the base circle silicon wafer is less than 1%.

[0082] Furthermore, the slitting of the silicon single crystal pillar assembly includes the following steps:

[0083] 1) Determine the relative positions of the desired rectangular silicon pillar and the base circular silicon pillar, based on the vacancy-type point defect density C of the base circular silicon wafer. V and self-gap type point defect density C I Distribution, such that the rectangular silicon wafer is in C V - C I Regions ≥0; and / or, based on the ratio d of the distance between the edge of the rectangular silicon pillar and the lowest point of minority carrier lifetime in the outer edge region of the base circular silicon pillar to the diameter of the base circular silicon wafer, such that 2% ≤ d ≤ 8%;

[0084] 2) The base circle silicon cylinder is longitudinally cut along its outer edge to form two outer cylindrical surfaces. The base circle silicon cylinder is rotated and cut out eight outer cylindrical surfaces in four feed cycles.

[0085] 3) Continue to cut along the inner longitudinal direction of the base circle silicon pillar, rotate 90° twice to form the four cylindrical faces of the rectangular silicon pillar and the remaining cylindrical faces of the non-rectangular polygonal silicon pillar, to obtain one rectangular silicon pillar and four non-rectangular polygonal silicon pillars; when the non-rectangular polygonal silicon pillar is a hexagonal silicon pillar, one cylindrical face of the hexagonal silicon pillar is formed by a portion of the cylindrical face of the retained base circle silicon pillar, or processed into a plane.

[0086] Thirdly, the present invention provides a silicon monocrystalline photovoltaic cell, fabricated using silicon wafers from any of the aforementioned photovoltaic silicon monocrystalline wafer arrays. The silicon monocrystalline photovoltaic cell is a back-contact cell, or a silicon monocrystalline back-contact photovoltaic cell within a tandem photovoltaic cell. The back-contact cell provides convenient conditions for series and parallel connection of the cells.

[0087] Furthermore, the silicon monocrystalline photovoltaic cell is equipped with a bypass diode, which provides bypass protection and freewheeling for the silicon monocrystalline photovoltaic cell itself and photovoltaic cells connected in parallel with it. The integrated bypass diode provides reliable and efficient bypass protection and freewheeling for high-voltage output photovoltaic modules.

[0088] Preferably, the bypass diode is a Schottky barrier diode, which has a low forward voltage and low conduction loss, making it suitable for photovoltaic modules.

[0089] Fourthly, the present invention provides a silicon single-wafer splicing battery, comprising a first battery prepared from the aforementioned axisymmetric hexagonal or pentagonal silicon wafers, and a second and third battery obtained by axisymmetrically dividing the first battery, or a second and third battery prepared by axisymmetrically dividing the hexagonal or pentagonal silicon wafers into quadrilateral shapes, spliced ​​together. The second battery and the third battery are mirror images of each other.

[0090] Understandably, when the aforementioned hexagonal silicon wafers or solar cells are symmetrically divided, due to further division, one side of the hexagonal silicon wafer or solar cell generated by the outer circle of the crystal pillar is relatively shorter, and can be regarded as not constituting an independent side. The quasi-quadrilateral it is made into can be regarded as a quadrilateral.

[0091] The spliced ​​batteries facilitate the achievement of standardized dimensions or suitable output current and voltage.

[0092] Fifthly, the present invention provides a photovoltaic module composed of the aforementioned silicon monocrystalline photovoltaic cell or silicon monocrystalline wafer splicing cell.

[0093] Preferably, the battery cells in the photovoltaic module are arranged in u rows and one column or u rows and two columns in terms of electrical connection and row and column relationship. Each row consists of v first battery cells, 1 second battery cell, and 1 third battery cell connected in parallel, and each column consists of w battery cells connected in series; u, v, and w are natural numbers greater than or equal to 1.

[0094] Its beneficial effects are:

[0095] 1) Reduce the number of second and third solar cells used to lower process costs;

[0096] 2) Facilitates the layout and installation of external bypass freewheeling diodes.

[0097] The beneficial effects of this invention are:

[0098] 1) Considering the distribution pattern of the quality level of technical elements on silicon single wafers, rectangular silicon wafers in the middle of the base wafer and non-rectangular polygonal silicon wafers at the edges of the rectangular silicon wafers are separated. Different photovoltaic cell manufacturing processes are applied to the two types of silicon wafers to fully explore the potential of each silicon wafer and obtain photovoltaic modules with the best quality. At the same time, the area utilization rate of the base wafer can reach more than 90%.

[0099] 2) In a preferred embodiment, the non-rectangular polygonal silicon wafer adopts an axisymmetric pentagon or a better axisymmetric hexagon. The photovoltaic cell prepared by this embodiment has no acute angle stress concentration phenomenon, is fully compatible with the size and technical parameters of existing photovoltaic cells, and can be expanded into a standardized series of products with different lengths and output currents under the same width and output voltage conditions. Similarly, it can be fully compatible with the size and technical parameters of existing photovoltaic modules, and can be expanded into a standardized series of photovoltaic module products with different lengths and output voltages under the same width and output current conditions.

[0100] 3) The low-current, high-voltage photovoltaic module constructed from non-rectangular polygonal cells integrates hot spot protection and freewheeling bypass diodes on its cells, which makes the hot spot protection of the photovoltaic module more efficient, reliable, low-power, and simpler than the external bypass diodes in the existing technology.

[0101] 4) The silicon pillar assembly process is simple. In the preferred scheme, the silicon pillar has no sharp edges and the silicon wafer has no sharp corners. Using existing squaring or grinding equipment, one clamping and one reinforcement are performed, and six feed cuts are made in the generatrix direction to obtain one standard rectangular silicon ingot and four pentagonal or hexagonal silicon pillars.

[0102] 5) The connection method of single-row or double-row photovoltaic module cell cells facilitates the arrangement of multiple external bypass and freewheeling diodes for hot spot protection. Attached Figure Description

[0103] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0104] Figure 1 This is a schematic diagram corresponding to Embodiment 1 of the present invention, showing the rectangular silicon single crystal pillar and four axisymmetric hexagonal silicon single crystal pillars obtained by dividing the base circular silicon single crystal pillar, and the shape of the resulting silicon single crystal wafer;

[0105] Figure 2 This is a longitudinal cross-sectional schematic diagram of a silicon photovoltaic cell prepared from a silicon single wafer obtained in Example 1, corresponding to Example 2 of the present invention;

[0106] Figure 3 This corresponds to Embodiment 2 of the present invention, which is an electrical schematic diagram of the photovoltaic cell connection;

[0107] Figure 4 This is a schematic diagram of the shape of a silicon monocrystalline photovoltaic cell and the photovoltaic module connection group prepared from an axisymmetric hexagonal silicon monocrystalline wafer, corresponding to Embodiment 3 of the present invention;

[0108] Figure 5 This is a schematic diagram of the shape of a silicon monocrystalline photovoltaic cell and the photovoltaic module connection group prepared from an axisymmetric hexagonal silicon monocrystalline wafer, corresponding to Embodiment 4 of the present invention;

[0109] Figure 6 This is a simulation result of the internal stress of a φ300mm Czochralski silicon single crystal under certain process conditions;

[0110] Figure 7 The vacancy-type point defect density C of a φ300mm Czochralski silicon single crystal under certain process conditions V and self-gap type point defect density C I The difference simulation distribution diagram;

[0111] Figure 8This is a measured value of the radial distribution of minority carrier lifetime in a silicon single crystal pillar with a diameter of 315 mm.

[0112] Explanation of reference numerals in the attached figures: 1-Basic circular silicon pillar; 11-Rectangular silicon pillar; 12-Hexagonal silicon pillar; 121-Semi-hexagonal silicon pillar; 141-First dicing line; 142-Second dicing line; 2-Parallel cell; 20-Substrate region; 21-First doped region; 22-Second doped region; 3-Bypass diode; 33-Third doped region; 34-Fourth doped region; 35-Schottky / electrode metal; 3533-Schottky barrier junction; 281-First electrode; 282-Second electrode; 4-First photovoltaic module; 5-Second photovoltaic module; 201-First cell; 202-Second cell; 203-Third cell; 481-First terminal; 482-Second terminal. Detailed Implementation

[0113] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The apparatus of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0114] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0115] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0116] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0117] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0118] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0119] Example 1:

[0120] See Figure 1 A group of silicon single crystal pillars is formed by cutting a base circular silicon pillar 1 with a diameter of φ292mm. This includes one rectangular silicon pillar 11 with a cross-section of 182mm × 182mm, four hexagonal silicon pillars 12 with a long side of 182mm, or semi-hexagonal silicon pillars 121 obtained by further cutting the hexagonal silicon pillar 12. The angle between the direction of the generatrix of the silicon single crystal pillars and the <100> crystal orientation is 0°~3°. The crystal orientation of the symmetry axis of the hexagonal silicon pillar 12 is <100>. The distance δ = 17mm from the edge of the rectangular silicon pillar 11 to the circumference of the base circular silicon pillar 1 where the minority carrier lifetime is lowest is approximately 5.8%. The minority carrier lifetime τ at the edge of the rectangular silicon pillar 11 is... e The median minority carrier lifetime τ of a rectangular silicon pillar with an 11-section cross-section m Satisfying τ e >0.8τ m Rectangular silicon pillar 11 is located in C V - C I Regions ≥ 0.

[0121] One cylindrical surface of the axisymmetric hexagonal silicon cylinder 12 is a curved surface, which is a portion of the cylindrical surface of the base circle silicon cylinder 1, and the chord height of the curved surface cross-section is less than 0.5 mm. The cutting method of the base circle silicon cylinder 1 includes the following steps:

[0122] 1) With two parallel diamond wires, feed in the direction of the generatrix of the base circle silicon cylinder 1, and cut along the first cutting line 141. Each feed forms two cylindrical surfaces of the hexagonal silicon cylinder 12, and 8 cylindrical surfaces are cut out in 4 feeds.

[0123] 2) Similarly, using two parallel diamond wires, feed along the generatrix of the base circle silicon pillar 1, cutting along the second cutting line 142. The first feed forms two parallel cylindrical surfaces of the rectangular silicon pillar 11. Temporarily reinforce the top of the base circle silicon pillar 1 appropriately, rotate 90°, and feed again along the second cutting line 142. Repeat the four feeds of step 1), for a total of six feeds, to cut one rectangular silicon pillar 11 and four hexagonal silicon pillars 12, forming a group of five silicon single crystal pillars. It is worth noting that one cylindrical surface of the hexagonal silicon pillar 12 is formed from a portion of the arc surface of the retained base circle silicon pillar 1.

[0124] The resulting silicon pillar assembly, after transverse slicing, has a rectangular silicon pillar 11 slice thickness of 110 μm and a hexagonal silicon pillar 12 slice thickness of 80 μm. This yields a set of photovoltaic silicon single-crystal wafers with a (100) crystal plane according to the present invention. If necessary, the rectangular silicon pillar 11 can be further slicing into bi-slice silicon pillars, tri-slice silicon pillars, etc., and the hexagonal silicon pillar 12 can be further slicing into semi-hexagonal silicon pillars 121.

[0125] Beneficial effects of Example 1:

[0126] 1. The segmentation and slicing of silicon pillars results in a narrow distribution of quality characteristics among the silicon pillars in each region. The rectangular silicon pillars exhibit high and consistent minority carrier lifetime, which facilitates targeted product design and process optimization, thereby improving product quality and consistency.

[0127] 2. The utilization rate of silicon wafer materials reaches 93%;

[0128] 3. All silicon wafers have the same dimensions in one dimension of the plane, which allows for the design of photovoltaic module products with the same width, length, or series of lengths, facilitating product standardization and serialization;

[0129] 4. The cut silicon wafers have no sharp corners, which helps to eliminate edge chipping and corner defects;

[0130] 5. It can be easily achieved using existing squaring or grinding equipment at a low cost.

[0131] Example 2:

[0132] See Figure 2 , Figure 3 , Figure 4 The first cell 201, the second cell 202, and the third cell 203 of the back-contact silicon monocrystalline photovoltaic cell are prepared using silicon wafers made of hexagonal silicon pillars 12 or semi-hexagonal silicon pillars 121. The first cell 201 is used as an example for illustration.

[0133] A first doped region 21 (conductivity type n) is formed on the substrate region 20 (taking n conductivity type as an example). + ), second doped region 22 (conductivity type p) + ), fourth doped region 34 (conductivity type p) + A third doped region 33 (conductivity type n) is prepared on the fourth doped region 34. + The first doped region 21 forms the first contact window (the negative electrode of the first battery 201) of the substrate region 20; the second doped region 22 forms the charge separation pn junction and the second contact window (the positive electrode of the first battery 201) between the second doped region 22 and the substrate region 20.

[0134] A fourth doped region 34 is prepared on the substrate region 20, and a third doped region 33 is prepared on the fourth doped region 34. A pn ​​junction with a pnp or npn structure is formed between the substrate region 20 and the third doped region 33 for isolation. A Schottky / electrode metal 35 is prepared on the surface of the third doped region 33 to form a Schottky barrier junction 3533. One end of the Schottky / electrode metal 35 is the positive electrode of the Schottky barrier junction 3533, and the third doped region 33 is the negative electrode of the Schottky barrier junction 3533.

[0135] By connecting the positive electrode (Schottky / electrode metal 35) of the Schottky barrier junction 3533 to the negative electrode 281 of the first battery 201, and connecting the negative electrode (third doped region 33) to the positive electrode 282 of the first battery 201, fault follow current protection for hot spot protection of the first battery 201 is achieved.

[0136] The beneficial effect of this embodiment is that the bypass diode 3 provides hot spot protection and fault freewheeling for the single first battery 201 and the second battery 202 and the third battery 203 connected in parallel with it.

[0137] Beneficial effects of Example 2:

[0138] The bypass diode 3 is located on the back of the battery and is isolated from the substrate region 20 by a pn junction. While providing hot spot protection and fault freewheeling for the first battery 201, it does not affect the sunlight reception and photoelectric conversion of the first battery 201. The Schottky junction has a low forward voltage, provides reliable battery protection, and has low power loss during conduction.

[0139] Example 3:

[0140] See Figure 4 The first photovoltaic module 4 considers the first battery 201, the second battery 202, and the third battery 203 as a parallel battery unit 2, and connects them in series with the next parallel battery unit 2 composed of the first battery 201, the second battery 202, and the third battery 203, and so on, until the preset voltage is reached, and finally outputs electrical power through the first terminal 481 and the second terminal 482.

[0141] Since each parallel cell unit 2 has three bypass diodes 3 available for connection, the first photovoltaic module 4 does not need to be connected to external bypass diodes 3, and provides the most detailed hot spot protection and fault follow current. Because the integrated bypass diode 3 operates in the forward direction and is a low-voltage-drop Schottky barrier diode, it can withstand a large current density without generating heat.

[0142] Example 4:

[0143] See Figure 5The second photovoltaic module 5, and the parallel battery unit 2, includes 11 first batteries 201, 1 second battery 202, and 1 third battery 203. The entire parallel battery unit 2 occupies one row of the second photovoltaic module 5, for a total of u rows, forming a series connection of batteries in the second photovoltaic module 5. This series connection continues until a preset voltage is reached, and finally, electrical power is output from the first terminal 481 and the second terminal 482.

[0144] The beneficial effects of this embodiment are as follows:

[0145] 1) Due to the segmented cutting, the parameters of each cell are highly consistent, which helps to maximize the quality potential of silicon single crystal wafers;

[0146] 2) The single-row series connection of the parallel battery cells facilitates the addition of multiple hot spot protection bypass freewheeling diodes;

[0147] 3) Fully compatible with the technical parameters of existing photovoltaic modules.

[0148] In summary, the technical solution provided by this invention has significant technical and cost advantages, and is of great significance to the development of the industry.

[0149] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A group of photovoltaic silicon single crystal wafers having a (100) crystal plane, characterized in that, The wafer set includes a rectangular silicon wafer cut from the center of a base wafer and axially symmetric non-rectangular polygonal silicon wafers cut symmetrically from the periphery of the rectangular silicon wafer. The cutting dimensions of the rectangular silicon wafers are based on the vacancy-type point defect density C of the base wafer. V and self-gap type point defect density C I The distribution of the rectangular silicon wafers, located at C V - C I Regions ≥0; and / or, based on the distribution of minority carrier lifetime in different radial regions of the base wafer, the ratio d of the distance between the four corners of the rectangular silicon wafer to the lowest point of minority carrier lifetime in the edge region of the base wafer to the diameter of the base wafer, 2%≤d≤8%; The non-rectangular polygonal silicon wafer is an axisymmetric pentagonal silicon wafer or an axisymmetric hexagonal silicon wafer. In the hexagonal silicon wafer, one side is a curve, and the ratio of the chord height of the curve to the diameter of the base circle silicon wafer is less than 1%. The longest side of the pentagonal or hexagonal silicon wafer is consistent with the long side of the rectangular silicon wafer. The pentagonal silicon wafer or the hexagonal silicon wafer is the first silicon wafer. The pentagonal silicon wafer or the hexagonal silicon wafer is cut along the axis of symmetry to obtain the second silicon wafer. n first silicon wafers and 2 second silicon wafers are spliced ​​together to form a rectangle, where n≥1.

2. The photovoltaic silicon single crystal wafer set according to claim 1, wherein The number of the first silicon wafers is odd. The odd number of the first silicon wafers and two second silicon wafers are spliced ​​together to form a rectangle compatible with the size of the rectangular silicon wafer. The aspect ratio of the spliced ​​rectangle is (3.3×m):1~(1.8×m):1, where m is a natural number from 1 to 12.

3. The photovoltaic silicon single crystal wafer set according to claim 1, wherein The ratio of the sum of the areas of the wafer group to the area of ​​the base wafer, k, is one of the following: 1）88%＜k≤92%； 2）92%＜k≤95%。 4. The photovoltaic silicon single crystal wafer set according to claim 1, wherein The thickness d of the silicon wafers of the same shape in the wafer group falls within one of the following ranges: 1) 50μm≤d<85μm; 2) 85μm≤d<98μm; 3) 98μm≤d<115μm; 4) 115μm≤d<135μm; 5) 135μm≤d<160μm.

5. A group of silicon single crystal pillars for cutting a group of photovoltaic silicon single crystal wafers having a (100) crystal plane as claimed in any one of claims 1 to 4, characterized in that, It includes rectangular silicon pillars with the rectangular silicon wafer as the base and non-rectangular polygonal silicon pillars with the non-rectangular polygonal silicon wafer as the base, wherein the angle between the direction of the silicon pillar generatrix and the <100> crystal orientation is 0°~3°.

6. The silicon single crystal column set according to claim 5, wherein The base of the non-rectangular polygonal silicon pillar is an axisymmetric pentagon or an axisymmetric hexagon, one side of which is a curve, and the ratio of the chord height of the curve to the diameter of the base circle silicon wafer is less than 1%.

7. The silicon single crystal pillar assembly according to claim 5, characterized in that, The slitting of the silicon single crystal pillar assembly involves the following steps: 1) Determine the relative positions of the desired rectangular silicon pillar and the base circular silicon pillar, based on the vacancy-type point defect density C of the base circular silicon wafer. V and self-gap type point defect density C I The distribution of the rectangular silicon wafer places it in C V - C I Regions ≥0; and / or, such that the ratio d of the distance between the edge of the rectangular silicon pillar and the lowest point of minority carrier lifetime in the outer edge region of the base circular silicon pillar to the diameter of the base circular silicon wafer is within the following range: 2% ≤ d ≤ 8%; 2) The base circle silicon cylinder is longitudinally cut along its outer edge to form two outer cylindrical surfaces. The base circle silicon cylinder is rotated and cut out eight outer cylindrical surfaces in four feed cycles. 3) Continue to cut along the inner longitudinal direction of the base circle silicon pillar, rotate 90° twice to form the four cylindrical surfaces of the rectangular silicon pillar and the remaining cylindrical surfaces of the non-rectangular polygonal silicon pillar, to obtain one rectangular silicon pillar and four non-rectangular polygonal silicon pillars. When the non-rectangular polygonal silicon pillar is a hexagonal silicon pillar, one of the cylindrical faces of the hexagonal silicon pillar is formed by a portion of the cylindrical face of the retained base circle silicon pillar, or is processed into a plane.

8. A silicon single crystal photovoltaic cell, characterized by, The silicon wafer is prepared using the photovoltaic silicon monocrystalline wafer array according to any one of claims 1-4, wherein the silicon monocrystalline photovoltaic cell is a back contact cell or a silicon monocrystalline back contact photovoltaic cell in a tandem photovoltaic cell.

9. The silicon single crystal photovoltaic cell of claim 8, wherein, The silicon monocrystalline photovoltaic cell is equipped with a bypass diode, which provides bypass protection and freewheeling for the silicon monocrystalline photovoltaic cell itself and the photovoltaic cells connected in parallel with it.

10. The silicon single crystal photovoltaic cell of claim 9, wherein, The bypass diode is a Schottky barrier diode.

11. A silicon single crystal wafer tiled cell prepared from the silicon wafers of the photovoltaic silicon single crystal wafer set of claim 1, wherein, A first cell made of an axisymmetric hexagonal or pentagonal silicon wafer, and a second and third cell obtained by axisymmetrically dividing the first cell, or a quadrilateral second and third cell made by axisymmetrically dividing the hexagonal or pentagonal silicon wafer, are spliced ​​together.

12. A photovoltaic module, characterized in that, Prepared from any one of the silicon monocrystalline photovoltaic cells according to claims 8-10.

13. A photovoltaic module, characterized by, It is prepared by splicing silicon monocrystalline cells as described in claim 11.

14. The photovoltaic module of claim 13, wherein, The battery cells in the photovoltaic module are arranged in u rows and one column or u rows and two columns in terms of electrical connection and row and column relationship. Each row consists of v first battery cells, 1 second battery cell, and 1 third battery cell connected in parallel. Each column consists of w battery cells connected in series. u, v, and w are natural numbers greater than or equal to 1.

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