Infrared detector and preparation method thereof

Abstract

The embodiment of the invention provides an infrared detector and a preparation method thereof. The infrared detector sequentially comprises a bottom electrode layer, a P-type layer, an N-type layer and a top electrode layer, wherein the P-type layer comprises PbS (lead sulfide); the N-type layer comprises CdSexS (1-x), wherein x is a positive number. And low dark current and high quantum efficiency can be considered.

Description

Technical Field

[0001] This invention belongs to the field of optical imaging technology, and specifically relates to an infrared detector and its preparation method. Background Technology

[0002] Short-wave infrared imaging has unique value in haze penetration, water content identification, vegetation and mineral remote sensing, and low-light perception in consumer and industrial vision. Traditional InGaAs / InP and HgCdTe devices rely on vacuum epitaxy, resulting in high manufacturing costs and system complexity. PbS with a room-temperature bandgap of approximately 0.42 eV, prepared at low temperatures using solution methods, has the potential for large-area, low-cost fabrication and compatibility with readout circuits. Therefore, constructing a p-n heterojunction on the PbS absorber layer has become a key path to reduce dark current and improve speed. Existing technologies mostly use CdSe as the n-type layer, forming a stepped bandgap arrangement with PbS. While this is beneficial for electron selection, it still faces constraints from dark current and noise caused by interface recombination and hole reverse injection in low-bias and array applications. Faced with the dual requirements of low-temperature processing and pixel uniformity for monolithic integration, relying solely on CdSe is insufficient to achieve a stable balance between quantum efficiency, dark current, and readout compatibility. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an infrared detector and its fabrication method, which can respond quickly while significantly suppressing dark current.

[0004] In a first aspect, the present invention provides an infrared detector, comprising, in sequence: a bottom electrode layer, a P-type layer, an N-type layer, and a top electrode layer; wherein the P-type layer comprises PbS; and the N-type layer comprises CdSe. x S1- x ,in x It is a positive number.

[0005] Secondly, the present invention provides a method for preparing an infrared detector, comprising: A P-type layer is fabricated on the bottom electrode layer; An N-type layer is prepared on a surface of the P-type layer that is away from the bottom electrode layer; A top electrode layer is prepared on a surface of the N-type layer that is away from the bottom electrode layer; The P-type layer comprises PbS; the N-type layer comprises CdSe. x S1- x , where x is a positive number.

[0006] The infrared detector and its fabrication method provided by this invention sequentially include: a bottom electrode layer, a P-type layer, an N-type layer, and a top electrode layer; wherein the P-type layer comprises PbS; and the N-type layer comprises CdSe. xS1- x ,in x It is a positive number. It can balance low dark current and high quantum efficiency. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structure of an embodiment of the infrared detector of the present invention; Figure 2 This is a schematic flowchart of an embodiment of the method for preparing the infrared detector of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] To make the technical problems, technical solutions, and beneficial effects of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0011] See Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the infrared detector of the present invention, which sequentially includes: a bottom electrode layer, a P-type layer, an N-type layer, and a top electrode layer; wherein, the P-type layer includes PbS; and the N-type layer includes CdSe. x S1- x , where x is a positive number.

[0012] In one embodiment, the infrared detector further includes: a hole transport layer disposed between the bottom electrode layer and the P-type layer; and an electron transport layer disposed between the N-type layer and the top electrode layer.

[0013] This invention addresses the challenge of achieving both low dark current and high quantum efficiency in a single CdSe n-type layer by proposing a method using CdSe... x S1- x It is an infrared detector for n-type layers.

[0014] In one embodiment, x ∈[0.67,0.99]. By adjusting the atomic fractions of Se and S, the relative height of the n-layer conduction band bottom to PbS is precisely set, so that the interface transitions from a "step-like" interface to a "peak-like" interface with a slight positive step. When the "peak" height is maintained in the range of approximately 0.07–0.16 eV, electrons can still be efficiently selected by thermal emission / tunneling, while holes are effectively blocked, and interface recombination and reverse injection are significantly suppressed.

[0015] In one embodiment, CdSe x S1- x The thickness of PbS is 10-200 nm. The thickness of PbS is 200 nm - 2 μm. Preferably, the thickness of PbS is 600 nm.

[0016] The infrared detector provided by this invention comprises, from bottom to top, a bottom electrode layer, a hole transport layer, a P-type layer, an N-type layer, an electron transport layer, and a top electrode layer. The PbS thin film, serving as the P-type layer, preferably has a thickness of about 600 nm, and the CdSe film, serving as the N-type layer... x S1- x The thickness is preferably about 10-200nm, and the interface “peak” barrier height can be designed by adjusting the atomic fraction x of Se and S.

[0017] In one embodiment, the CdSe x S1- x Components x Located in a continuous range of 0.67–0.99, a stable and controllable compositional sequence (corresponding to CdSe0.99S0.01 to CdSe0.67S0.33) can be achieved by changing the amount of thiourea (TU) in the precursor from 0.33–66.4 mg / mL. Its crystal structure is a homogeneous solid solution. The XRD peak position shifts from 25.40° to 26.05° with increasing S content, and the band gap increases from 1.70 eV to 2.05 eV.

[0018] In one embodiment, when x When the value is 0.95 or 0.91, the conduction band levels of PbS are approximately 0.07 eV and 0.16 eV, respectively, which can achieve both low dark current and high quantum efficiency at room temperature.

[0019] In one embodiment, n layers of CdSe x S1- xControlling the thickness of the "window layer" to approximately 10-200 nm can reduce parasitic absorption and improve photon utilization (the average deposition rate of chemical liquid phase is approximately 1.2 nm / min, and ~50 nm can be achieved after 50 min of deposition).

[0020] In one embodiment, the p-type PbS absorber layer has a thickness of approximately 600 nm and together with the n-layer forms a depletion region, enabling a fast response.

[0021] See Figure 2 , Figure 2 This is a schematic flowchart of an embodiment of the method for fabricating the infrared detector of the present invention, specifically including: Step S21: Prepare a P-type layer on the bottom electrode layer.

[0022] Specifically, using FTO / ITO as the bottom electrode, after conventional ultrasonic cleaning, a chemical bath containing lead nitrate / sodium hydroxide / thiourea was used to obtain ~600 nm PbS, followed by chloride ion passivation to ensure interface stability and depletion region broadening.

[0023] PbS is deposited on the bottom electrode layer using chemical liquid phase deposition, followed by chloride ion passivation to form a P-type layer. Specifically, approximately 600 nm thick PbS is deposited on the bottom electrode layer (such as FTO / ITO) using chemical liquid phase deposition, followed by chloride ion passivation to form a P-type layer, and then cleaned and dried for later use.

[0024] Step S22: Prepare an N-type layer on the surface of the P-type layer away from the bottom electrode layer.

[0025] A Cd / Se solution is obtained by mixing an equal volume of CdCl2 aqueous solution with dimethylselenourea. Thiourea is then added to the Cd / Se solution to obtain a Cd / Se / S solution. Specifically, CdCl2 aqueous solution is used as the cadmium source, and any one of selenourea, dimethylselenourea (DMSeU), or sodium thioselenate is used as the selenium source, with thiourea (TU) as the sulfur source. For example, using dimethylselenourea (DMSeU) as the selenium source, CdCl2 and DMSeU are mixed in equal volumes to obtain a Cd / Se solution, and then TU of the target concentration is added. The pH of the solution is adjusted to approximately 10.0 using dilute nitric acid / ammonia water to obtain the Cd / Se / S solution.

[0026] Precise setting via TU concentration-component mapping x For example, when TU is 0.33, 0.66, 3.32, 6.64, 33.2, and 66.4 mg / mL, CdSe can be obtained respectively. 0.99 S 0.01 CdSe 0.95 S 0.05 CdSe 0.91S 0.09 CdSe 0.87 S 0.13 CdSe 0.77 S 0.23 CdSe 0.67 S 0.33 The corresponding band gap and XRD height change with the S content.

[0027] A substrate with a p-type layer is immersed in a Cd / Se / S solution to prepare an N-type layer on the surface of the p-type layer away from the bottom electrode layer. The substrate with the p-type layer is then immersed in the Cd / Se / S solution and reacted at approximately 50°C for approximately 50 minutes to obtain a CdSe / S1- layer with a thickness of approximately 10-200 nm. x The alloy film, after being removed, is rinsed with deionized water, dried with nitrogen, and placed in a glove box. This process can form a dense and uniform CdSe film. x S1- x The thin film forms a good interface with PbS.

[0028] In one embodiment, CdCl2·2.5H2O (2 mg / mL) and DMSeU (1.37 mg / mL) were mixed in equal volumes, and then a pre-set TU (0.33–66.4 mg / mL) was added to control the concentration. x Adjust the pH to approximately 10 using dilute nitric acid / ammonia solution, then place the substrate in a 50°C constant temperature bath for 50 min to obtain CdSe. x S1- x The film is about 10-200 nm thick, with 20-50 nm particles and a dense and uniform morphology; after rinsing and nitrogen drying, it is placed in a glove box for assembly.

[0029] Step S23: Prepare a top electrode layer on a surface of the N-type layer away from the bottom electrode layer.

[0030] An electron transport layer is deposited on the N-type layer, and a top electrode is vapor-deposited or sputtered, followed by packaging and electrical / optical testing.

[0031] The bottom electrode layer can be made of materials such as ITO, FTO, or Au, while the top electrode can be made of materials such as Al, Ag, or ITO.

[0032] This invention, through precise setting of the Se and S ratio, forms a moderate "peak" potential barrier at the PbS interface, significantly reducing dark current and noise while maintaining a high-speed pulse response at 1 kHz; when x When adjusted within the range of 0.91–0.95, a significantly lower dark current density than that of unalloyed CdSe-PbS can be obtained experimentally at -0.1 V, with a specific detectivity of ~10. 11Jones, with a response time of approximately 0.64 μs and a dynamic range exceeding 90 dB, and due to the chemical co-deposition process at approximately 50 °C and pH ≈ 10 throughout the entire process, along with subsequent mild processing, the inter-pixel film thickness and bandgap remain consistent within controllable tolerances, facilitating large-area array fabrication on TFT / CMOS readout circuits.

[0033] In one specific embodiment, a clean ITO substrate or a pre-fabricated p-PbS electrode substrate was selected. An equal volume of 2 mg / mL CdCl₂·2.5H₂O solution and 1.37 mg / mL DMSeU solution was mixed, followed by the addition of 0.66 mg / mL TU. The pH was adjusted to approximately 10 using dilute nitric acid / ammonia. A CdSe₀.₉₅S₀.₀₅ film (approximately 10-200 nm) was co-deposited at approximately 50 °C for approximately 50 min. The film was then rinsed with deionized water and dried with nitrogen. The device exhibited a peak detectivity of approximately 1.06 × 10¹¹ Jones and a pulse response of approximately 0.64 μs at 1 kHz, with a dynamic range greater than 90 dB. The dark current at -0.1 V was significantly lower than that of the unalloyed CdSe-PbS reference device.

[0034] Furthermore, the TU concentration was increased to 3.32 mg / mL, resulting in the deposition of a CdSe0.91S0.09 thin film. Its conduction band bottom was raised to approximately 0.16 eV relative to PbS, with a higher "peak," making it suitable for applications requiring lower bias voltages and lower dark current constraints. After the same packaging and testing, the device maintained comparable EQE while further reducing low-frequency noise and dark current.

[0035] Furthermore, a thin seed layer close to PbS was first deposited at TU 3.32 mg / mL for 2–5 min, and then the deposition was continued at TU 0.66 mg / mL to the target thickness. This resulted in a slight S enhancement layer at the interface, further improving noise suppression and stability without significantly increasing the series resistance. After long-term bias and illumination cycling tests, the device's J–V and frequency response maintained good repeatability.

[0036] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. An infrared detector, characterized in that, In order, they include: Bottom electrode layer, P-type layer, N-type layer, and top electrode layer; wherein the P-type layer includes PbS; The N-type layer includes CdSe. x S1- x ,in x It is a positive number.

2. The infrared detector according to claim 1, characterized in that, x ∈[0.67,0.99]。 3. The infrared detector according to claim 1, characterized in that, The infrared detector further includes: a hole transport layer disposed between the bottom electrode layer and the P-type layer; and an electron transport layer disposed between the N-type layer and the top electrode layer.

4. The infrared detector according to claim 1, characterized in that, CdSe x S1- x The thickness is 10-200nm.

5. The infrared detector according to claim 1, characterized in that, The thickness of PbS is 200 nm - 2 μm.

6. A method for fabricating an infrared detector, characterized in that, include: A P-type layer is fabricated on the bottom electrode layer; An N-type layer is prepared on a surface of the P-type layer that is away from the bottom electrode layer; A top electrode layer is prepared on a surface of the N-type layer that is away from the bottom electrode layer; The P-type layer includes PbS; The N-type layer includes CdSe. x S1- x ,in x It is a positive number.

7. The preparation method according to claim 6, characterized in that, Fabricating a P-type layer on the bottom electrode layer includes: PbS was deposited on the bottom electrode layer using chemical liquid phase deposition, and then subjected to chloride ion passivation to form a P-type layer.

8. The preparation method according to claim 6, characterized in that, An N-type layer is fabricated on a surface of the P-type layer away from the bottom electrode layer, comprising: A Cd / Se solution is obtained by mixing an aqueous CdCl2 solution with an equal volume of a selenium source solution; the selenium source solution includes any one of selenourea, dimethylselenourea, or sodium thioselenate. Thiourea was added to a Cd / Se solution to obtain a Cd / Se / S solution; The substrate with the P-type layer is immersed in a Cd / Se / S solution to prepare an N-type layer on the surface of the P-type layer away from the bottom electrode layer.

9. The preparation method according to claim 6, characterized in that, x ∈[0.67,0.99]。 10. The preparation method according to claim 6, characterized in that, CdSe x S1- x The thickness is 10-200nm.

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