Method for improving roughness of InAs / GaSb superlattice etched side wall

Abstract

The invention discloses a method for improving the roughness of an InAs / GaSb superlattice etching side wall. A to-be-etched InAs / GaSb superlattice sample and at least one solid indium-containing auxiliary source dummy wafer are jointly placed in an etching reaction cavity for etching. According to the method, an existing mainstream chlorine-based dry etching platform does not need to be changed, only the solid indium-containing auxiliary source dummy wafer needs to be added in the cavity, additional complex steps are not introduced, and the solid indium-containing auxiliary source dummy wafer can be easily integrated into an existing production line; by introducing the external indium source to actively modify the side wall, the problem of etching non-uniformity caused by material difference is fundamentally compensated, the effect is better than that of simply optimizing etching parameters, the quality of the side wall is remarkably improved, the dark current of the infrared detector is remarkably reduced, and the reliability and the yield of the device are improved. The method is suitable for various mesa etching processes of infrared detectors based on InAs / GaSb superlattices, and has wide applicability.

Description

Technical Field

[0001] This application relates to the fields of semiconductor micro / nano fabrication and infrared detector chip preparation, and more specifically, to a method for improving the sidewall roughness of InAs / GaSb superlattice etching. Background Technology

[0002] InAs / GaSb superlattices, as a high-performance infrared detection material, have shown great application potential in the field of third-generation infrared focal plane detectors due to their advantages such as tunable bandgap and low dark current. However, in actual device fabrication, especially when forming mesa isolation structures through dry etching, the quality of the etched sidewalls has always been a technological challenge.

[0003] In traditional chlorine-based dry etching processes, the differences in the physicochemical properties of InAs and GaSb lead to significant differences in their etching rates to chlorine-based plasmas. Typically, GaSb has a faster etching rate than InAs. Furthermore, the volatility of byproducts generated during etching (such as InCl3, GaCl3, and SbCl3) also differs, with InCl3 exhibiting relatively lower volatility. This inconsistency between etching rate and byproduct volatility results in the formation of periodic, undulating structures on the etched sidewalls, corresponding to the superlattice period, macroscopically manifesting as severe vertical striations or a rough morphology resembling "onion skin."

[0004] A rough surface implies a larger surface area and more surface dangling bonds, leading to a sharp increase in the number of surface states, which become effective recombination centers for charge carriers. The rough sidewall regions, heavily pinned by these surface states, form PN junctions with pinned surfaces. Their band structure may be distorted, causing what should be an insulating bandgap region to become a narrow channel near the surface, allowing electron tunneling or direct conduction. The combined effect of these two factors ultimately results in a sharp increase in the device's dark current, severely degrading detector performance, such as increased noise and reduced detectivity.

[0005] In existing technologies, methods such as optimizing etching parameters (e.g., power, gas pressure, gas ratio) or performing sidewall passivation are commonly used to improve the etching morphology. However, these methods have limited effectiveness, narrow process windows, or require additional complex steps, and they cannot fundamentally solve the problems caused by differences in the etching characteristics of the materials themselves.

[0006] Therefore, there is an urgent need for a new method that can improve the sidewall quality of InAs / GaSb superlattice etching in situ and actively during the etching process. Summary of the Invention

[0007] To achieve the above objectives, this invention provides a method for improving the sidewall roughness of InAs / GaSb superlattices. The core idea is to introduce a "sacrificial" material—a solid indium-containing auxiliary source pseudo-film—during the dry etching process, utilizing its etching products to in-situ modify and protect the sidewalls of the InAs / GaSb superlattice.

[0008] This invention provides a method for improving the sidewall roughness of InAs / GaSb superlattice etching. The method involves placing the InAs / GaSb superlattice sample to be etched and at least one solid indium-containing auxiliary source dummy in an etching reaction chamber for etching. During the etching process, the solid indium-containing auxiliary source dummy is etched, and the resulting material disperses in the plasma and selectively adsorbs onto the freshly etched, active sidewall surface of the InAs / GaSb superlattice sample, forming a thin, uniform, and dynamically balanced "protective layer" to smooth the etched sidewalls.

[0009] Specifically, the solid indium-containing auxiliary source dummy is selected from one or more of InP, InAs, and InSb; The surface area ratio of the solid indium-containing auxiliary source dummy to the sample to be etched is 1:10 to 1:1. Within this ratio range, the concentration of the etched product (InClx) of the solid indium-containing auxiliary source dummy in the etching environment can be well balanced. If the ratio is too low, the provided In source will be insufficient, and a continuous and uniform protection cannot be formed on the sidewall, resulting in an insignificant improvement effect. If the ratio is too high, excessive In source will be deposited on the sidewall in the etching environment, causing roughness of the etched sidewall. Preferably, the surface area ratio of the solid indium-containing auxiliary source dummy to the sample to be etched is 1:5. The solid indium-containing auxiliary source dummy is placed next to the sample or on a support tray.

[0010] The method specifically includes the following steps: (1) Prepare the InAs / GaSb superlattice sample to be etched, on which an etching mask has been prepared; (2) Place the InAs / GaSb superlattice sample together with at least one solid indium-containing auxiliary source dummy into the dry etching reaction chamber; (3) Close the reaction chamber, evacuate the vacuum, and introduce chlorine-containing etching gas; (4) Stimulate plasma to begin the etching process.

[0011] Specifically, the chlorine-containing etching gas includes one or more of Cl2, BCl3, and SiCl4; The dry etching method is either inductively coupled plasma etching or reactive ion etching. The temperature of the etching platform is controlled between 20°C and 150°C.

[0012] The present invention also provides an application of the aforementioned method for improving the sidewall roughness of InAs / GaSb superlattice etching in the fabrication of infrared detector mesa structures.

[0013] The beneficial effects of this invention include: In-situ processing with a simple process: It does not require changes to the existing mainstream chlorine-based dry etching platform. Only a solid indium-containing auxiliary source dummy needs to be added in the chamber. It does not introduce additional complex steps, is low in cost, and is easy to integrate into the existing production line.

[0014] Improving morphology at its root: By introducing an external indium source (InClx generated by a solid indium-containing auxiliary source dummy wafer) to actively modify the sidewalls, the problem of etching non-uniformity caused by the differences in the material itself is fundamentally compensated, and the effect is better than simply optimizing the etching parameters.

[0015] Significantly improved sidewall quality: It can obtain near-ideal smooth, vertical etched sidewalls, effectively eliminating vertical lines and onion-skin-like morphology, and reducing sidewall roughness by an order of magnitude.

[0016] Significantly improved device performance: The smooth sidewalls greatly reduce surface states and defects, thereby significantly reducing the dark current of the infrared detector and improving device reliability and yield.

[0017] High versatility: This method is applicable to mesa etching processes for various InAs / GaSb superlattice-based infrared detectors (such as MWIR, LWIR, VLWIR), and has wide applicability. Attached Figure Description

[0018] Figure 1 Scanning electron microscope image of the sidewall of the InAs / GaSb superlattice etched using conventional methods in Comparative Example 1; Figure 2 This is a scanning electron microscope image of the sidewalls of the InAs / GaSb superlattice etched using the method of the present invention in Example 1; Figure 3 This is a schematic diagram showing the relative positions of the solid indium-containing auxiliary source dummy and the InAs / GaSb sample within the reaction chamber of the present invention. Figure 4 A comparison chart of the dark current-voltage characteristic curves of the infrared detectors prepared by the conventional method in Comparative Example 1 and by the method of the present invention in Example 1. In the figure, 1 is the rough surface etched by conventional method; 2 is the surface etched by the method of the present invention; 3 is the support tray; 4 is the solid indium-containing auxiliary source dummy; 5 is the InAs / GaSb superlattice sample to be etched; 6 is the IV curve of the device etched by conventional method; 7 is the IV curve of the etching method of the present invention. Detailed Implementation

[0019] The present invention will be further described and illustrated below with reference to embodiments. However, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the present invention and the embodiments, all other inventions and embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0021] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0022] First, let's introduce and explain several terms involved in this invention: Surface states: Inside a crystal, atomic bonding is complete. However, at the surface, the crystal structure abruptly terminates, creating a large number of unbonded "dangling bonds." These dangling bonds introduce energy levels in the band gap that allow electrons to occupy, and are called surface states.

[0023] Fermi level pinning effect: When a semiconductor surface has a high density of defects (such as dangling bonds created by rough etching), these defects introduce a large number of localized energy levels into the band gap. These "pins" forcibly fix the Fermi level, which characterizes the electron filling level, at a specific energy position, making it difficult to effectively modulate by an external electric field or doping. This effect leads to severe distortion of the intended band structure of the semiconductor device at the surface, often forming fatal conductive leakage channels on the sidewalls, thus significantly increasing the device's dark current and degrading its performance.

[0024] A pinned PN junction: The pinned band structure forms a narrow, low-energy conductive channel in the originally insulated sidewall region of the PN junction. Current no longer needs to overcome a high potential barrier within the bulk and can easily flow along this surface channel, forming surface leakage current. For infrared detectors, this is one of the main sources of dark current, which significantly reduces the detector's signal-to-noise ratio and performance.

[0025] This invention provides a method for improving the sidewall roughness of InAs / GaSb superlattice etching, comprising the following steps: Step 1: Prepare the InAs / GaSb superlattice sample 5 to be etched, on which an etching mask has been prepared.

[0026] Step 2: Place the sample 5 and at least one solid indium-containing auxiliary source dummy wafer 4 together on the support tray 3 inside the dry etching reaction chamber; Step 3: Chlorine-containing etching gas (such as Cl2, BCl3, etc.) is introduced into the reaction chamber and plasma is generated to simultaneously etch the InAs / GaSb superlattice sample 5 and the solid indium-containing auxiliary source dummy 4.

[0027] During the etching process, the solid indium-containing auxiliary source dummy is etched to generate indium-containing chlorides (InClx, where x=1, 2, 3). The indium-containing chlorides are dispersed in the plasma and then transported to the etched sidewall region of the InAs / GaSb superlattice sample being etched. These indium-containing chlorides selectively adsorb onto the freshly etched, active sidewall surface, forming a thin, uniform, and dynamically balanced "protective layer" to achieve smoothing of the etched sidewalls.

[0028] The working mechanism of this protective layer is: (1) Etching homogenization: The protective layer covers the surface of the GaSb layer that etches faster, which can locally slow down its etching rate; at the same time, for the InAs layer that etches slower, the protective layer also reduces the possibility of it being etched laterally, thereby balancing the etching rate difference between different material layers.

[0029] (2) Suppress physical bombardment: This protective layer can effectively block or weaken the physical sputtering effect of high-energy ions on the sidewall, thereby suppressing the generation of vertical striations and onion-like morphology.

[0030] (3) Promote sidewall smoothness: During the entire etching process, the protective layer is in a dynamic process of being continuously removed by ion bombardment and replenished by new InClx, which eventually leads to a globally smooth sidewall morphology.

[0031] Example 1: A method for improving the sidewall roughness of InAs / GaSb superlattice etching Includes the following steps: Step 1: An InAs / GaSb superlattice material epitaxial wafer with a complete structure is obtained by growing it on a GaSb substrate using a molecular beam epitaxy device. Then, the surface of the InAs / GaSb superlattice material epitaxial wafer is cleaned with an organic solvent (acetone, isopropanol, anhydrous ethanol, etc.), and the surface defects and contamination are observed under a microscope. Step 2: Grow an epitaxial wafer containing a hard mask by PECVD (ICPCVD or ALD, etc., are also acceptable), wherein the hard mask is SiOx; Step 3: Photolithography is performed on the surface of the epitaxial wafer containing the hard mask through steps such as spin coating, hardening, exposure, and development. Step 4: Etch the hard mask on the surface of the epitaxial wafer containing the hard mask using ICP (RIE equipment can also be used), and then remove the photoresist on the surface using an organic solvent; Step 5, as follows Figure 3 As shown, an InP dummy wafer with a surface area ratio of approximately 1:5 to the sample to be etched was placed on the sample stage of the inductively coupled plasma etching (ICP) machine along with the superlattice sample. The reaction chamber was evacuated to a background vacuum below 1.0 × 10⁻⁵ Torr. Etching gas was introduced into the chamber, with the following composition: Cl₂ flow rate of 10 sccm and BCl₃ flow rate of 5 sccm. The chamber pressure was adjusted to 5 mTorr. The RF power supply was turned on, and the ICP source power was set to 300 W and the bias power to 50 W to generate high-density plasma. The sample stage temperature was controlled at 140 °C. Etching continued for 8 minutes to ensure complete etching through the superlattice structure. After etching, the power supply and gas were turned off, and the sample was removed.

[0032] Step 6: Grow a 300nm passivation layer using PECVD (ICPCVD or ALD is also acceptable). At this point, the surface of the epitaxial wafer and the inside of the trenches are completely covered by the passivation layer. Step 7: Through steps such as spin coating, hardening, exposure, and development, windowing photolithography is performed on the surface of the epitaxial wafer to expose a designated area. Then, metal electrodes are deposited in the exposed area, and metals Ti 100nm, Pt 200nm, and Au 100nm are deposited sequentially to obtain a complete and measurable type II superlattice device.

[0033] Comparative Example 1: InAs / GaSb superlattice etching using traditional methods The process parameters and samples were exactly the same as in Example 1, but InP dummy wafers were not placed in step 5.

[0034] Result characterization: Scanning electron microscopy revealed that the etched sidewalls of the sample obtained in step 5 of Comparative Example 1 exhibited the following characteristics: Figure 1 The clearly defined, dense vertical striations shown indicate a roughness Ra > 10 nm. However, as... Figure 2 As shown, the etched sidewalls of the sample obtained in step 5 of Example 1 are very smooth, with almost no periodic undulations observed, and the roughness Ra < 2 nm.

[0035] After fabricating the devices of Example 1 and Comparative Example 1 into mesa-type infrared detectors, their dark current was tested at 77K. Figure 4 As shown, under a bias voltage of -0.1V, the dark current density of the device in Comparative Example 1 is 5×10-4 A / cm², while the dark current density of the device in Example 1 is reduced to 4.5×10-5 A / cm², with the improvement effect exceeding one order of magnitude.

Claims

1. A method for improving the sidewall roughness of InAs / GaSb superlattice etching, characterized in that, The InAs / GaSb superlattice sample to be etched and at least one solid indium-containing auxiliary source dummy are placed together in the etching reaction chamber for etching.

2. The method according to claim 1, characterized in that, The solid indium-containing auxiliary source dummy is selected from one or more of InP, InAs, and InSb.

3. The method according to claim 1, characterized in that, The surface area ratio of the solid indium-containing auxiliary source dummy to the sample to be etched is 1:10 to 1:

1.

4. The method according to claim 3, characterized in that, The surface area ratio of the solid indium-containing auxiliary source dummy to the surface area of ​​the sample to be etched is 1:

5.

5. The method according to claim 1, characterized in that, The solid indium-containing auxiliary source dummy is placed next to the sample or on a support tray.

6. The method according to claim 1, characterized in that, The method specifically includes the following steps: (1) Prepare the InAs / GaSb superlattice sample to be etched, on which an etching mask has been prepared; (2) Place the InAs / GaSb superlattice sample together with at least one solid indium-containing auxiliary source dummy into the dry etching reaction chamber; (3) Close the reaction chamber, evacuate the vacuum, and introduce chlorine-containing etching gas; (4) Stimulate plasma to begin the etching process.

7. The method according to claim 6, characterized in that, The chlorine-containing etching gas includes one or more of Cl2, BCl3, and SiCl4.

8. The method according to claim 6, characterized in that, The dry etching is inductively coupled plasma etching or reactive ion etching; and / or, the mesa temperature during the etching process is controlled between 20°C and 150°C.

9. The application of the method according to any one of claims 1-8 in the fabrication of an infrared detector mesa structure.

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