Display device, display system and method thereof

Abstract

The invention relates to a display device, a display system and a method thereof. A display device includes: a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile including: a lighting die including at least one lighting element; a semiconductor device includes a lighting die, a first region of the lighting die, and a tiled backplane die, the tiled backplane die including pixel logic circuitry and input / output logic circuitry, where the lighting die is coupled to a front surface of the tiled backplane die such that a first region of the backplane die is aligned with at least one lighting element in the lighting die; each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of a respective tiled backplane die, the plurality of openings in the back surface being aligned with a second region of the backplane die.

Description

[0001] This application is a divisional application of the application patent application entitled “Systems and Methods for Configuring Display Devices and Display Systems” having an international application number of PCT / US2022 / 074542, filed on August 4, 2022, a Chinese application number of 202280053280.5 after entering the Chinese national phase, and a filing date of August 4, 2022.

[0002] CLAIM OF PRIORITY

[0003] This patent application claims the benefit of priority of U.S. Application Serial No. 63 / 229,642, filed August 5, 2021, the entire contents of which are incorporated herein by application. TECHNICAL FIELD

[0004] The present disclosure relates to displays, such as light emitting diode (LED) displays, including LED displays and OLED displays, as well as micro-displays or micro versions thereof (e.g., micro-LED and micro-OLED displays). More particularly, the present disclosure relates to configurable LED displays. BACKGROUND

[0005] Generally, direct view applications with mid-size displays for portable, wearable, mobile, or handheld devices (i.e., not micro-displays, nor monitors, televisions, etc.) are typically made with transmissive LCD or OLED technology with a TFT backplane. OLED displays have short lifetimes and limited brightness, while LCD displays require backlighting, which consumes power for each pixel regardless of whether the pixel is on or off. TFTs, while inexpensive, are too resistive (waste power) and too large to make complex circuitry under each pixel, thus limiting to a driving scheme that drives each row of the display in sequence, with each pixel having a very short duty cycle, thus requiring high current density to get sufficient brightness. In contrast, while micro-LED displays have long lifetimes, micro-LED arrays, when coupled to a silicon backplane to form a micro-LED display, typically result in displays with random defects.

[0006] In constructing micro-LED displays with a silicon backplane to enable physically larger applications (i.e., not micro-displays, but direct view displays, such as for VR headsets, wearable devices such as watches, and smartphones, or even monitors and televisions), building various shapes and sizes typically requires redesigning the display and manufacturing process for each new application. As the size of the display increases, the yield decreases, which makes some applications cost prohibitive or at least not competitive. SUMMARY

[0007] According to embodiments of the present disclosure, the display can be used in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. According to embodiments of the present disclosure, tiled or tileable displays and methods provide displays of different sizes, such that the tiled or tileable displays are configured to accommodate display sizes required by various wearable devices and mobile devices that include the displays.

[0008] According to embodiments of the present disclosure, there is provided a display device comprising: a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile comprising: an illumination die comprising at least one illumination element; and a tileable backplane die comprising: pixel logic circuitry arranged on, embedded in, integrated into, formed on, deposited on, or coupled to a first region of the backplane die; and input / output logic circuitry arranged on, embedded in, integrated into, formed on, deposited on, or coupled to a second region of the backplane die; wherein the illumination die is coupled to a front surface of the tileable backplane die such that the first region is aligned with at least one illumination element in the illumination die; and wherein each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of the respective tileable backplane die, the plurality of openings in the back surface being aligned with the second region of the backplane die.

[0009] According to embodiments of the present application, there is also provided a display system comprising: a pixel array of pixels, each pixel having at least one illumination element in an illumination die, each illumination element of a pixel electrically coupled to pixel circuitry in a tileable backplane die of a tile, the tileable backplane die comprising: pixel drive and logic circuitry on a first area of the backplane die, the pixel drive and logic circuitry comprising: a receive pixel memory device; an active pixel memory device electrically coupled to the receive pixel memory device; a logic function circuitry coupled to the active pixel memory device; a latch coupled to the logic function circuitry; and a current drive device coupled to the latch, wherein the current drive device drives operation of each pixel of the pixel array; and tile controller circuitry on a second area of the backplane die, the tile controller circuitry comprising circuitry configured to: receive a serial data stream; extract image data or video data from the serial data stream according to when an address of the tile is in the data stream; decode the image data or video data after it has been extracted from the data stream; control writing of the image data or video data to the receive pixel memory device; and write the image data or video data that has been extracted and subsequently decoded to a data bus, the data bus corresponding to or associated with a column of one or more pixels comprising or containing the pixel array, the column identified as a destination for writing the image data or video data; wherein the illumination die is coupled to a front surface of the tileable backplane die such that the first area is aligned with at least one illumination element in the illumination die, and wherein the tileable backplane die comprises a plurality of openings in a back surface of the tileable backplane die, the plurality of openings configured to receive the serial data stream from a tile array controller.

[0010] According to embodiments of the present application, there is also provided a method comprising: transmitting serial data from a master controller to one or more tiles of a plurality of tiles via a printed circuit board, the data having a header comprising a tile address associated with a first tile of the plurality of tiles; receiving the serial data at a tile controller of the first tile, the tile controller comprising a backplane comprising: a first area comprising a plurality of first strip areas; a second area comprising a plurality of second strip areas alternating with the plurality of first strip areas; pixel logic circuitry at least one of disposed on, embedded in, integrated into, formed on, deposited onto, or coupled to the first area, the pixel logic circuitry coupled to one or more illumination elements in an illumination die coupled to a front surface of the backplane; and input / output logic circuitry at least one of disposed on, embedded in, integrated into, formed on, deposited onto, or coupled to the second area, the input / output logic circuitry coupled to the printed circuit board through a plurality of openings in a back surface of the backplane aligned with the second area; and at the tile controller of the first tile: identifying the tile address in the header of the serial data; identifying tile data as a subset of the serial data received from the master controller; and storing the tile data at a memory component in the first tile or at a memory component associated with the first tile. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 A tile array for a circular watch display is shown in accordance with embodiments of the present disclosure.

[0012] Figure 2 A tile with a seam is shown in accordance with embodiments of the present disclosure.

[0013] Figure 3 Conversion of an operational die (e.g., backplane die) to a form capable of nearly seamless abutment is shown in accordance with embodiments of the present disclosure.

[0014] Figure 4 A cross-section of a tile on a PCB is shown in accordance with embodiments of the present disclosure.

[0015] Figure 5 A backside of a tile is shown in accordance with embodiments of the present disclosure.

[0016] Figure 6Connection of tiles for forming an array is shown in accordance with embodiments of the present disclosure.

[0017] Figure 7 Tile backplane circuitry is shown in accordance with embodiments of the present disclosure.

[0018] Figure 8 Single pixel circuitry is shown in accordance with embodiments of the present disclosure.

[0019] Figure 9 Serial stream format in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] Detailed implementations are disclosed herein as needed. It must be understood that the disclosed implementations are merely examples of various alternatives. As used herein, the word “exemplary” is used extensively in

[0021] The present disclosure uses displays composed of “tiles” that are independently and individually manufactured and independently tested (solving yield limitations because they are smaller and tested during the manufacturing process and can be repaired before the manufacturing process is complete, improving yield). Further, different wearable or mobile device manufacturers attempt to differentiate themselves through industrial design, which results in displays of varying sizes and shapes that would require new designs for each customer, but using tiled or tileable displays and methods in accordance with embodiments of the present disclosure allows new displays to be designed or configured by arranging tiles on a PCB (which can be designed and manufactured quickly compared to creating new silicon dies and micro LED arrays).

[0022] Figure 1 A pseudo-circular array of display tiles is shown. In embodiments of the present disclosure, a tile array or display tile array approximates a circle and can be used as a display device for a circular device (e.g., an LED display device or LED panel). In embodiments of the present disclosure, any number of tiles can be arranged in any shape. In embodiments of the present disclosure, an illumination device (e.g., a tile) includes an illumination die (e.g., an LED die) and an operations die (e.g., a backplane die).

[0023] In embodiments of the present disclosure, a lighting die (e.g., LED die) includes lighting elements coupled to or integrated into a lighting substrate (e.g., GaN substrate). In embodiments of the present disclosure, the lighting elements, e.g., an array of lighting elements (e.g., LEDs of any type or size), are formed on the lighting substrate. The lighting elements (e.g., LEDs) or lighting array (e.g., array of lighting elements) and the lighting substrate (e.g., LED substrate) are integrated and / or coupled together and form a lighting die (e.g., LED die).

[0024] In embodiments of the present disclosure, a pixel is formed when a lighting element of a lighting die is coupled (e.g., electrically coupled) to control or for operation (e.g., including driving the corresponding one or more lighting elements) circuitry (at least including pixel circuitry). In embodiments of the present disclosure, the pixel circuitry includes at least driving circuitry. In embodiments of the present disclosure, the driving circuitry includes at least pixel logic circuitry that determines the on / off state of the pixel as a function of time and input / output circuitry that provides current to the LED. In embodiments of the present disclosure, each lighting element (e.g., LED) has a set of pixel circuitry.

[0025] In embodiments of the present disclosure, each lighting die (e.g., LED die) is coupled to (e.g., electrically coupled to) an operations die (e.g., backplane die). The operations die (e.g., backplane die) includes a backplane substrate and pixel circuitry and / or pixel-related circuitry.

[0026] In embodiments of the present disclosure, the operations die (e.g., backplane die) is then made of silicon and is referred to as a silicon operations die (e.g., backplane die). In embodiments of the present disclosure, the operations die (e.g., backplane die) includes circuitry (e.g., pixel circuitry) disposed on, coupled to, integrated into, formed in, deposited on, or embedded in the backplane substrate.

[0027] In embodiments of the present disclosure, the circuitry (e.g., pixel circuitry) or driving circuitry is at least divided into pixel logic circuitry and input / output circuitry. In embodiments of the present disclosure, the pixel logic circuitry is operated in or located in one or more portions of the backplane substrate that are different from one or more portions of the backplane substrate in which the input / output circuitry is operated.

[0028] In embodiments of the disclosure, the pixel logic circuitry is operated in or is located in one or more strips or strip portions of the backplane substrate that are different from the one or more strips or strip portions of the backplane substrate in which the input / output circuitry is operated or is located.

[0029] In embodiments of the disclosure, each of the lighting elements is associated with its own pixel circuitry (i.e., drive circuit or drive circuitry) that drives the lighting element (e.g., determines the grayscale output of the lighting element). In embodiments of the disclosure, each of the lighting elements is associated with its own pixel circuit (i.e., drive circuit or drive circuitry) that drives the lighting element (e.g., determines the grayscale output of the lighting element). In embodiments of the disclosure, each of the lighting elements is associated with pixel logic circuitry or circuitry and input / output circuitry or circuitry. In embodiments of the disclosure, the combination of each lighting element (e.g., LED) and its corresponding circuitry (e.g., pixel circuitry) including but not limited to drive circuitry forms a tile’s pixel. In embodiments of the disclosure, there is an electrical contact element between the LED and the pixel circuitry as they are on different wafers before bonding. In embodiments of the disclosure, the electrical contact element can be on the wafer where the LED is located or on the wafer where the pixel circuitry is located.

[0030] In embodiments of the disclosure, the combination of each lighting element (e.g., LED) and its corresponding circuitry, for example, the combination of each lighting element (e.g., LED) and its corresponding circuitry (e.g., its corresponding pixel logic circuitry and its corresponding input / output circuitry) forms a tile’s pixel.

[0031] In embodiments of the disclosure, the lighting element is a primary lighting element. In embodiments of the disclosure, the primary lighting element includes more than one lighting element (e.g., LED). In embodiments of the disclosure, the primary lighting element includes at least three (3) lighting elements, for example, a set of three (3) lighting elements (e.g., LEDs).

[0032] In embodiments of the present disclosure, a pixel is formed when a lighting element (e.g., LED) is coupled to (e.g., electrically coupled to) circuitry (e.g., pixel circuitry) that drives each lighting element (e.g., LED). In embodiments of the present disclosure, a primary pixel is formed when a primary lighting element (e.g., a set or collection of LEDs, such as three (3) LEDs) is coupled to (e.g., electrically coupled to) circuitry (e.g., pixel circuitry) that drives each lighting element (e.g., LED) of the primary lighting element. In embodiments of the present disclosure, a lighting element (e.g., LED) is a set of 3 primary colors, and when the LEDs are grouped into a set, there is a gap between them, enabling a seamless abutment in perception. In embodiments of the present disclosure, a tile includes more than one primary pixel, e.g., an array of primary pixels. In embodiments of the present disclosure, pixel circuitry includes at least drive circuitry. In embodiments of the present disclosure, drive circuitry includes at least pixel logic circuitry and input / output circuitry.

[0033] In embodiments of the present disclosure, tiles can be arranged, e.g., on a PCB, in any pattern, for example. In embodiments of the present disclosure, tiles can be arranged, e.g., on a PCB, in any pattern, to form a display, for example. For purposes of illustrating the use of tiles, a pseudo-circular array of tiles is shown in FIG. 1, in accordance with embodiments of the present disclosure. Figure 1 A pseudo-circular array of tiles is shown in FIG. 1, in accordance with embodiments of the present disclosure. For example, as shown in FIG. 1, a pseudo-circular array of display tiles is arranged on a printed circuit board (PCB) (not shown), and is used for a dial display. In the example shown, 88 tiles - each tile 3.6 mm Figure 1 A pseudo-circular array of display tiles is arranged on a printed circuit board (PCB) (not shown), and is used for a dial display, as shown in FIG. 2, in accordance with embodiments of the present disclosure. In the example shown, 88 tiles - each tile 3.6 mm 3.6 mm, contain 60 60 pixels - are arranged to form a dial of, e.g., 36 mm diameter. However, one of ordinary skill in the art will appreciate that the number of tiles, the number of pixels and / or primary pixels per tile, the shape of the tiles, and / or the shape of the array of tiles can vary. In embodiments of the present disclosure, the pattern or arrangement of tiles on a PCB can vary.

[0034] In embodiments of the present disclosure, as shown in FIG. 3, adjacent tiles are arranged on a PCB with space, gaps, or seams between the tiles, in accordance with embodiments of the present disclosure. Figure 2 In embodiments of the present disclosure, as shown in FIG. 3, adjacent tiles are arranged on a PCB with space, gaps, or seams between the tiles, in accordance with embodiments of the present disclosure. Figure 2As shown in FIG. 1, in embodiments of the present disclosure, there is a space, gap, or seam between the sides or edges of two adjacent tiles, where each tile has one or more primary pixels or a set of three (3) lighting elements (e.g., LEDs and their associated pixel circuitry). Those of ordinary skill in the art will appreciate that any reference to LEDs includes any type of LED (e.g., LED, OLED, micro-LED, or micro-OLED). As shown in FIG. 1, in embodiments of the present disclosure, there is a gap, space, or seam between adjacent tiles. Those of ordinary skill in the art will appreciate that the number and color of LEDs in the primary lighting elements or primary pixels (e.g., the set of LEDs and / or the circuitry electrically coupled to each of the LEDs) can vary. Figure 2 As shown in FIG. 1, in embodiments of the present disclosure, there is a gap, space, or seam between adjacent tiles. Those of ordinary skill in the art will appreciate that the number and color of LEDs in the primary lighting elements or primary pixels (e.g., the set of LEDs and / or the circuitry electrically coupled to each of the LEDs) can vary.

[0035] In embodiments of the present disclosure, the pitch (i.e., the center-to-center distance between lighting elements (e.g., primary pixels, primary lighting elements, or the set of lighting elements (e.g., LEDs))) must be such that the space between lighting elements (e.g., primary pixels, primary lighting elements, pixels, or the set of lighting elements (e.g., LEDs)) is sufficient to account for the gap, seam, space without interrupting the pixel pitch (i.e., the distance between the center of one lighting element (e.g., primary pixel or primary lighting element) and the center of another lighting element (e.g., primary pixel or primary lighting element)) and at the same time keeping the pixel pitch the same or substantially / approximately the same for all adjacent lighting elements (e.g., primary lighting elements or primary pixels) or at least some adjacent lighting elements (e.g., primary lighting elements or primary pixels). In embodiments of the present disclosure, when the tile is a single-color tile, the primary pixels and pixels are the same.

[0036] Figure 3 The difference between a conventional backplane die and a tiled or tileable operating die (e.g., backplane die) according to embodiments of the present disclosure, for example, operating die (e.g., backplane die (such as a silicon backplane die)) is shown in the form of apparently seamlessly abutting tiles, as the pitch between primary lighting elements or primary pixels is the same. The conventional die floor plan has or includes 1 / 0 and logic circuitry areas (where the input area includes 1 / 0 buffers, and the buffers are used to convert between the logic levels used externally and internally, and the logic area includes registers, state machines, and pixel drive circuitry, and is used to receive image data from externally, distribute it to the pixels in the active area).

[0037] In traditional die designs, the input region and logic region are located or positioned around the active area of the display (i.e., the area containing the pixels that will generate, for example, an image). In embodiments of operating the die, according to embodiments of the present disclosure, the operating die (e.g., a tileable backplane, a backplane die such as a silicon backplane die) includes strips of alternating pixel logic circuitry and 1 / 0 circuitry. In embodiments of the present disclosure, the 1 / 0 circuitry includes 1 / 0 buffers, and the buffers are used to convert between logic levels used externally and internal logic levels. In embodiments of the present disclosure, the logic region includes registers, state machines, and pixel drive circuitry, and is used to receive image data from externally, distribute it to the pixels in the active area, and wire the arrangement in rows and columns so that connections to the LED pixels are maintained in the array. In embodiments of the present disclosure, the illumination elements, for example, LEDs, can be positioned over the pixel logic circuitry or strips, the 1 / 0 circuitry or strips, or over both the pixel logic circuitry or strips and the 1 / 0 circuitry or strips. In embodiments of the present disclosure, the circuitry strips are embedded in the backplane substrate of the operating die.

[0038] Traditional backplanes typically contain peripheral bond pads on the silicon die or bump / pillar connections on the silicon die to connect the 1 / 0 buffers to a circuit board or package. Tileable or tiling backplanes are different from traditional backplanes in that the tileable or tiling backplanes according to embodiments of the present disclosure have through silicon vias (TSVs) that are used to connect or electrically couple one side or front side of the operating die (e.g., a backplane die such as a silicon backplane die) with an illumination die (including, for example, illumination elements (e.g., LEDs) or a primary illumination element or a set of LEDs that form a primary pixel when coupled or electrically coupled to the pixel circuitry) to a second side or back side of the operating die (e.g., a backplane die such as a silicon backplane die) and / or circuitry of the PCB.

[0039] Figure 4 A cross-section of a tile on a PCB is shown. In embodiments of the present disclosure, the tile includes an operating die (e.g., a backplane die such as a silicon backplane die or wafer) coupled (e.g., bonded and / or electrically coupled) to an illumination die (e.g., an LED wafer or die) using bonding and connection methods known in the art.

[0040] In embodiments of the illumination die, in accordance with embodiments of the present disclosure, the LEDs are formed in, integrated into, or fabricated in a substrate, such as a GaN substrate. However, one of ordinary skill in the art will appreciate that the substrate material can vary, for example, the substrate can be any semiconductor material capable of forming a light emitting structure. In embodiments of the present disclosure, a metal contact is coupled to or integrated into the illumination die (e.g., LED die) for electrically coupling the illumination die to the operational die (e.g., backplane die, silicon die, or silicon operational die).

[0041] In accordance with embodiments of the present disclosure, the illumination device (e.g., tile) includes a via (e.g., substrate via or a through-silicon via (TSV)) for making connections between a first or back side and a second or front side of the operational die (e.g., silicon die) and a power supply and interface for providing power to the tile circuitry (e.g., 1 / 0 logic circuitry and / or strip, pixel circuitry logic and / or strip, and / or conductive circuitry portion (e.g., copper deposit or other conductive element) deposited in, coupled to, or integrated into the PCB). In embodiments of the present disclosure, the via (e.g., substrate via or a through-silicon via (TSV)) receives data voltage input at the 1 / 0 buffer and is used to connect power and ground devices, components, and / or sources to the illumination die (e.g., LED die) and / or operational die (e.g., backplane die).

[0042] In embodiments of the present disclosure, the opening of the substrate via, such as a through-silicon via (TSV), at or on the back of the operational die (e.g., silicon die) is wetted with solder or other conductive material for attaching the solder to the underlying PCB or circuitry of the underlying PCB.

[0043] In embodiments of the present disclosure, the tile circuitry (e.g., 1 / 0 logic circuit or circuitry strip and pixel or drive circuitry logic strip) is deposited, formed, embedded, or integrated into the operational die (e.g., backplane substrate, silicon operational die, or backplane die or silicon die). In embodiments of the present disclosure, the illumination die (e.g., LED die) is at least electrically connected, coupled, and / or bonded to the operational die, and the silicon die is connected, coupled, electrically coupled, or connected and / or bonded to the PC. In embodiments of the present disclosure, there is connectivity between tiles or tile arrays via the PCB (i.e., the substrate that houses the tiles or the substrate on which the tiles are deposited, coupled, bonded, or positioned).

[0044] In embodiments of the present disclosure, circuitry or one or more conductive elements are deposited into, fabricated in, or integrated into the PCB (e.g., on one or more sides of the PCB) and are used, for example: (1) to electrically connect the illumination die (e.g., LED die) and / or the operational die (e.g., backplane die) to a power source or electrical power, a data source, a voltage source, and / or a current source, and / or (2) to receive data, voltage, or other input. In embodiments of the present disclosure, the circuitry or conductive elements or deposits on the PCB are made of copper material and can be referred to as copper traces or copper traces. However, one of ordinary skill in the art will appreciate that the conductive elements can be made of conductive materials other than copper. The PCB also serves as a structure to provide support, rigidity, or rigid surface to the tile array. In embodiments of the present disclosure, the PCB can include one, two, or more layers of circuitry (e.g., any tile-related circuitry).

[0045] Figure 5 The backside of the tile is shown. In embodiments of the present disclosure, as shown in Figure 5 On the back or bottom of the tile is an array of TSV openings for receiving, for example, input data or voltage, output data or voltage, or signals, as shown in

[0046] Figure 5 A via in, for example, the operational die (e.g., silicon die) is shown in Figure 5 An example I-layer routing pattern of the PCB of embodiments of the present disclosure is also shown, for example, wires or conductive elements deposited on or embedded in the PCB. In embodiments of the present disclosure, the TSVs labeled DI are used to connect serial data input from a controller (which is in Figure 6 A serial data input connection from a tile array controller, array controller, and / or master controller is shown in Figure 6The controller shown in FIG. 1 is external to the tile and / or tile array. In embodiments of the present disclosure, the controller (e.g., a tile array controller or a host controller) is located at or coupled to a substrate such as a PCB to which the tile is also coupled or located. In embodiments of the present disclosure, the controller controls the operation of the tile, each tile in the tile array, and / or the tile array as a unit. In embodiments of the present disclosure, the controller (e.g., a tile array controller or a host controller) distributes data to the tiles and controls when they display new data. In embodiments of the present disclosure, Figure 6 The arrows between the controller of FIG. 1 and Figure 6 The arrows between the tiles of FIG. 1 represent serial data and clock tap transmission (“T”) lines (i.e., conductive elements (e.g., wired elements such as copper wire elements)) to the PCB. Figure 5 The TSVs labeled CK are used to connect clock voltage output from the controller to the tile to sample the serial data and provide a clock to the logic circuitry of the tile. As will be described with respect to FIG. 2, the tile receives serial data (DI) and clock output (CK) from the controller.

[0047] The TSVs labeled CK are used to connect clock voltage output from the controller to the tile to sample the serial data and provide a clock to the logic circuitry of the tile. As will be described with respect to FIG. 2, the tile receives serial data (DI) and clock output (CK) from the controller. Figure 6

[0048] In embodiments of the present disclosure, at least one via is used to connect or deliver power to the tile and / or the lighting die (e.g., LED die) via, for example, a power rail (e.g., a conductive element, a ground element / component, a cable, and / or other component coupled or electrically connected to the operational die (e.g., backplane die or silicon operational die)) coupled or deposited in, embedded in, and / or integrated to the PCB. As a result, in accordance with embodiments of the present disclosure, power is provided to the lighting device (e.g., tile and / or lighting die (e.g., LED die)).

[0049] In embodiments of the present disclosure, the lighting die (e.g., LED die) is coupled to the operational die (e.g., silicon operational die or backplane die). In embodiments of the present disclosure, the silicon vias (e.g., four TSVs) are used to connect the PCB to the power rail (i.e., VDD) of the lighting die (e.g., LED die) and / or tile and provide sufficient current carrying capacity and low resistance. It will be appreciated by one of ordinary skill in the art that the number of vias used to connect components of the operational die (e.g., backplane die) to a power source, other components of the display system, the PCB, and / or other components of the PCB (or electrically coupled to the PCB) can vary.

[0050] ​In embodiments of the disclosure, the controller (e.g., tile array controller, array controller, master controller, and / or master controller chip) broadcasts or sends data to all tiles, or for broadcasting or sending data to all tiles or at least some of the tiles, and each tile (or at least some of the tiles) knows which portion of the data is reserved for itself based on its (i.e., the tile’s) address or, for example, based on the way the tile’s address pins are connected. In embodiments of the disclosure, the controller (e.g., array controller) sends data to a first tile, and the data is then subsequently streamed or transferred to the next tile in the tile array. In embodiments of the disclosure, as shown in Figure 6 In embodiments of the disclosure, each tile identifies and extracts data intended for it according to information in a header associated with the data sent from the controller (e.g., array controller, master controller, or master controller chip), in embodiments of the disclosure, each tile can receive data (e.g., data represented as voltage waveforms or pulses) according to the tile’s address identified in the address bits of the data received at the array from the controller (e.g., array controller, master controller, or master controller chip). For example, in embodiments of the disclosure, each of the TSVs labeled A0 through A5 identifies a location within the LED or master pixel array, and is electrically connected to a pixel, master pixel, and / or LED, master lighting element, or LED in the master pixel array.

[0051] In embodiments of the disclosure, as shown in Figure 6 In embodiments of the disclosure, tiles are assembled into a tile array and are electrically interconnected (by, for example, through a cable) via a serial bus, for example, consisting of a data signal and an optional clock signal. In embodiments of the disclosure, as shown in Figure 6 In embodiments of the disclosure, the controller (e.g., array controller, master controller, or master controller chip) converts incoming image or video data in a format, for example, a standard format (e.g., MIPI DSI), to a custom serial format that the tiles can process.

[0052] Figure 6 The first or left side of FIG. 1 shows the tile array, and the second or right side of the tile (the side pointed to by the arrow) shows that the array is made up of multiple tiles connected in series, and is controlled by a controller (e.g., array controller, master controller, or master controller chip) coupled to at least one of the series of tiles or multiple tiles.

[0053] In embodiments of the disclosure, the custom format is determined according to embodiments that enable the data to be distributed to all tiles and enable each tile to easily capture its own portion of the data. In embodiments of the disclosure, each tile has a predetermined position in the array, as shown in Figure 5The described, and when identifying or knowing its address, save and / or display data identified for it, and know how data on a serial data input is arranged as it travels along a bus associated with its address or its geographic location or portion of the array (i.e., the entire array or at least a portion of the array). In embodiments of the present disclosure, the tile ignores any data on the serial bus that is not associated with its address.

[0054] In embodiments of the present disclosure, the terminated, tapped transmission line at the end of the termination includes transmission line segments, and in accordance with embodiments of the transmission line matching method (i.e., a method for providing a transmission path free of impairments such as reflections and for matching the impedance of the transmission line to other components (e.g., electrical components) and / or tiles that the transmission line is electrically connected to, to give a controlled transmission line impedance in combination with the input capacitance connected to the data input or data input pin on each tile), each transmission line segment (i.e., the transmission line segment between two tiles in series) is tuned by adjusting the width.

[0055] In embodiments of the present disclosure, when new data arrives at the tile from, for example, an image or video data source, data of a previous image or video frame is being displayed, and the transmission of the new data or data of the next frame is allowed over the period of the entire video frame (i.e., the frame being displayed), which reduces the required data rate. For example, as shown in Figure 1 As shown in FIG. 1, an array (e.g., of primary pixels or primary illumination elements) in embodiments of the present disclosure provides, for example, 220,000 pixels, with 660,000 sub-illumination elements (e.g., sub-pixels (e.g., red LEDs, green LEDs, blue LEDs)), each requiring 8 bits of data to define their brightness. In embodiments of the present disclosure, the serial data rate required to support the embodiments shown in FIG. 1 is 60 Hz refresh rate at 158.4 Mb / s. Figure 1 As shown in FIG. 1, an array (e.g., of primary pixels or primary illumination elements) in embodiments of the present disclosure provides, for example, 220,000 pixels, with 660,000 sub-illumination elements (e.g., sub-pixels (e.g., red LEDs, green LEDs, blue LEDs)), each requiring 8 bits of data to define their brightness. In embodiments of the present disclosure, the serial data rate required to support the embodiments shown in FIG. 1 is 60 Hz refresh rate at 158.4 Mb / s.

[0056] Figure 7 Embodiments of backplane circuitry, for example, operating die (e.g., silicon die or tile backplane) circuitry, are shown in accordance with embodiments of the present disclosure. In embodiments of the present disclosure, (1) the operating die (e.g., backplane or backplane die) circuitry of the tile includes or is coupled to a receiver for DIN (i.e., data input / signal) and CLK input / signal (e.g., serial data and clock voltage inputs), logic circuitry, algorithms, and / or software algorithms or modules to decode serial data received at the receiving logic circuit, circuitry, or block, and (2) the operating die (e.g., backplane or backplane die) circuitry of the tile determines when such serial data is to be loaded into the array of pixel circuits, and when to update the pixels to display the loaded data. In embodiments of the present disclosure, the pixel circuits (as shown inFigure 7 The pixel circuitry is included in the operating die (e.g., backplane, backplane die, or silicon die) circuitry and the pixel circuit contains a receive and active storage device (e.g., memory device) as shown in FIG. 1. It will be understood by those of ordinary skill in the art that the pixel circuitry can be driven using any modulation method. According to embodiments of the present disclosure, the pixel structure will be further described in Figure 8

[0057] The tile controller logic circuitry and / or device extracts data from the serial data stream (e.g., represented by voltage waveform) sent to the tile over the serial bus and places it on the data bus for the column of the pixel array (which it is to be written to) and then loads it into the active pixels using the ROW-WRITE strobe.

[0058] The tile controller also produces a LOAD output control voltage to all the active pixels or active illumination elements (or at least a subset thereof) in the tile, which controls the transfer of data from the receive memory to the active memory and outputs a time varying value on the TVV bus, which will be further described in Figure 8

[0059] The tile control logic / circuitry / software / device also includes a time varying value (TVV) generator that creates a varying digital pattern for use by the pixels. In embodiments of the present disclosure, the bias control circuitry, software, and / or device contains a brightness control register that provides a digital value to a DAC and a current DAC that converts the register value to a current. The current is then converted to a voltage suitable for biasing a current source in the pixel circuitry electrically coupled to the individual pixels or to the pixels.

[0060] In embodiments of the present disclosure, a Config register can be written from data extracted from the incoming serial data received by the deserializer and can be used to control the bias current set by the bias control circuitry and / or device. In embodiments of the present disclosure, the Config register can or can not store information about the X and Y pixel count of the tiled display (i.e., the pixel count in each row and the pixel count in each column) and the active state of the tile (such as sleep or wake up).

[0061] As Figure 8 ​​As shown in the middle, in embodiments of the present disclosure, each sub-pixel (one of a group of, for example, 3 for each primary pixel or primary illumination element) contains an illumination element (e.g., LED, micro-LED, OLED, or micro-LED device or component) electrically coupled to a memory element, for example, two sets of memory elements, a logic function circuitry with a control of its electrical coupling to a latch (e.g., final latch) output, a final latch, and a current driver for supplying modulated current to the LED. It will be appreciated by those of ordinary skill in the art that the number of memory elements, latches, and current drivers can vary.

[0062] In embodiments of the present disclosure, the receiving storage device (e.g., memory device or receiving pixel memory device) is loaded with image data or video data (e.g., image or video grayscale data) from the tile controller, which places or transfers the data it extracts from a serial data stream to be written to the tile onto or to a data bus containing columns of pixels or primary pixels to be written, and then the tile controller outputs a ROW WRITE signal for a row of pixels to be written. It will be appreciated by those of ordinary skill in the art that other row-column scanning methods can be used to control the ROW WRITE operation.

[0063] Then, in embodiments of the present disclosure, the tile controller outputs a LOAD output voltage or signal that initiates the transfer of data from the receiving storage device (e.g., memory device or receiving storage memory device) to the active storage device (e.g., memory or active pixel memory device). Then, in embodiments of the present disclosure, a display period begins. During this period, the tile controller provides varying values or voltages on a time-varying value (TVV) bus, which the pixel logic hardware and / or software or pixel logic hardware device or method and / or software function, algorithm, or module combines with values (in the case of software) or values represented by voltages in the active storage device, for example, memory, to produce a time-varying voltage, for example, a single-bit voltage, voltage pulse, or signal for modulating current. In embodiments of the present disclosure, at each change of the TVV bus caused by the tile controller, a COMPUTE signal or output generated by a counter in the tile controller is determined or output to the logic function circuitry and / or latch to cause the computation of a single-bit output or signal and latch it into a final latch, the output of which directly controls the on / off state of the current source. The modulation of the pixel logic hardware and / or software can be any of a variety of resulting digital patterns, for example, PWM or binary-weighted pulse width, for varying the brightness of each pixel according to the data loaded into the storage device (e.g., memory).

[0064] In embodiments of this disclosure, the serial data stream from the tile array controller or main controller to the tiles is formatted into frames corresponding to the display's refresh rate in both duration and frequency. In embodiments of this disclosure, such as... Figure 9 As shown, each frame contains a Start of Frame (SOF) marker, which contains a unique pattern that the decoding logic circuitry of the tile controller can use to robustly detect the start of a frame (i.e., in the data received by the tile), followed by header information describing the content of the video data, such as the expected number of words in the data stream and the number of bits in each word, information about the number of pixels per row in the configured display, and also includes global (i.e., for the entire pixel array or a predetermined portion thereof) register updates such as brightness control or sleep / wake state.

[0065] In embodiments of this disclosure, the serial data stream transmitted from the tile controller or display controller to the tile can be encoded, for example, using 8b10b or 8b9b encoding, to provide robust transmission and reception, error detection, unique symbols for frame start, and other control purposes (e.g., tile power state control). Each tile stores its individual data, indexed into the received pixel data using its address, and identifies the start and end of data sent to that tile.

[0066] According to some embodiments of this disclosure, a display device includes an illumination die, wherein the illumination die includes at least one illumination element, said at least one illumination element being coupled to an illumination element substrate, formed on an illumination element substrate, or integrated into an illumination element substrate; and a backplane device coupled to the illumination die, wherein the backplane device includes a backplane substrate and a pixel circuit system, and the pixel circuit system being embedded in the backplane substrate, integrated into the backplane substrate, formed on the backplane substrate, or coupled to the backplane substrate, and wherein said pixel circuit system includes a pixel logic circuit system and an input / output logic circuit system.

[0067] In some embodiments, the pixel circuit system includes a driving circuit system. In some embodiments, at least one lighting element includes three lighting elements. The lighting element is an LED in some embodiments, and a micro LED in others. In some embodiments, the pixel circuit system is electrically coupled to at least one lighting element, and the pixel circuit system drives at least one lighting element. In some embodiments, the pixel circuit system is coupled to at least one lighting element via a conductive element, and the pixel circuit system drives at least one lighting element.

[0068] In some implementations, the backplane device is fabricated from a material that includes silicon or other semiconductor in which transistors can be formed. In some implementations, the illumination elements have conductive portions, and the pixel circuitry includes conductive portions for electrically coupling the illumination elements to their respective pixel circuitry. In some implementations, the backplane device has TSVs, where the top side of the backplane device is connected to the back side of the backplane device by conductive material or devices on the ends of the TSVs. In some implementations, the PCB is electrically coupled to the backplane device via conductive elements that couple the PCB and the backplane device with TSVs. In some implementations, at least three illumination elements form a first master pixel. In some implementations, the display device includes a second master pixel, where the second master pixel is electrically coupled to the first master pixel via conductive members or a cable. In some implementations, the first master pixel and the second master pixel form a tile.

[0069] In some implementations, a display device includes a plurality of tiles, where a tile includes an illumination die. The illumination die includes at least one illumination element that is at least one of coupled to, formed in, and integrated to an illumination element substrate, and a backplane device coupled to the illumination die, where the backplane device includes a backplane substrate and pixel circuitry, and where the pixel circuitry is at least one of embedded in, integrated to, formed on, deposited on, and coupled to the backplane substrate. The pixel circuitry includes pixel logic circuitry and input / output logic circuitry, and a PCB. The plurality of tiles are electrically coupled via at least one circuitry that is at least one of embedded in, integrated to, formed on, deposited on, and coupled to the backplane substrate, and at least one circuitry that is at least one of embedded in, integrated to, formed on, deposited on, and coupled to the PCB.

[0070] In some implementations, the pixel logic circuitry is at least one of disposed on, embedded in, integrated to, formed on, deposited on, or coupled to a first strip region of the backplane substrate. In some implementations, the input / output logic circuitry is at least one of disposed on, embedded in, integrated to, formed on, deposited on, or coupled to a second strip region of the backplane.

[0071] In some embodiments, the display system includes a tile controller, where the tile controller controls the operation of the tile array or each tile of the plurality of tiles, and is included or integrated into the operation die of each of the tiles, and where each tile of the plurality of tiles has a tile address. A host controller is coupled to at least one of the tiles of the plurality of tiles or tile array, where the host controller sends data to the tile to which the host controller is coupled, and where the tile controller identifies tile data in the data received from the host controller, and where the tile data is a subset of the data sent from the host controller, and where the tile controller associated with the tile address stores the tile data at a memory component in the tile or a memory component associated with the tile.

[0072] In some embodiments, the data sent from the host controller includes the tile address in a header of the data sent from the host controller. In some embodiments, the host controller receives data from a first device in a first format, and where the host controller converts the data to a suitable second format or a second format that can be read or processed by the tile or tile controller associated with the tile.

[0073] In some embodiments, the first device is a device that generates and / or outputs images or image data. In some embodiments, the tiles of the plurality of tiles or tile array are electrically connected in series. In some embodiments, image or video data is sent to a tile while an image or video data of a current frame is displayed on the tile for display in a next frame. In some embodiments, each tile includes a lighting element, and each lighting element is coupled to a first storage device and a second storage device.

[0074] In some embodiments, the display system further includes a logic function circuitry electrically coupled to the latch, where the logic function circuitry performs a computation or Boolean logic function such as an equivalence or comparison function, and generates an output received by the latch to which the logic function circuitry is coupled, and where the latch stores the output of the logic function circuitry, and where the latch is further electrically coupled to a current driver circuit or component, and where the current driver circuit or component is electrically coupled to the lighting element, and where the current driver circuit or component supplies a modulated current to the lighting element, and where the current driver circuit or component can supply the modulated current to the lighting element according to the output generated by the logic function circuitry.

[0075] In some embodiments, a display system includes a pixel array of pixel elements, where each lighting element of a pixel of the pixel array or each lighting element of a primary pixel is electrically coupled to pixel circuitry, the pixel circuitry including: a first storage device or a receiving pixel memory device; a second storage device or an active pixel memory device electrically coupled to the receiving pixel memory device. A logic function circuitry is coupled to the active pixel memory device. A latch is coupled to the logic function circuitry; and a current drive device is coupled to the latch, and where the current drive device drives operation of each pixel or primary pixel of the pixel array. A tile controller includes a deserializer that receives incoming data from the receiving storage device. A decoder is electrically coupled to the deserializer, and the deserializer extracts image or video data from a data stream received at the deserializer of the tile controller according to or when an address of a tile is in the data stream, and where the deserializer controls writing of the extracted data to the first storage device or receiving pixel memory device.

[0076] In some embodiments, the decoder decodes the extracted data after the data is extracted from the data stream, and where the tile controller instructs the control logic block to write the decoded data that has been extracted and subsequently to be placed to a data bus corresponding to or associated with a column including or containing lighting elements, pixels, primary pixels, LEDs, or a set of LEDs that have been identified as a destination for writing the extracted and subsequently decoded data. In some embodiments, the tile controller outputs a ROW / WRITE output or signal to a row of lighting elements, pixels, primary pixels, LEDs, or a set of LEDs that have been identified to receive the extracted and subsequently decoded data.

[0077] In some embodiments, the display system further includes control logic circuitry of the tile controller that outputs a LOAD output voltage or signal that initiates transfer of data from the receiving storage device to the second storage device or active storage device. In some embodiments, the display system further includes a TVV (time varying value) generator, where after the data has been transferred to the second storage device or active storage device, a display period begins, where during the display period, the TVV generator provides a varying value or voltage on a time varying value (TVV) bus, where the pixel logic circuit or pixel logic device combines the varying value or voltage with a value or voltage in the second storage device or active storage device and produces a time varying voltage for modulating a current driver circuit or device electrically coupled to a primary pixel or primary lighting element.

[0078] In some implementations, a COM PUTE signal or output generated by a counter in the TVV generator of the tile controller reaches the logic function circuitry and / or latch of the pixel array upon each change of the TVV bus caused by the TVV generator, and wherein the logic function circuitry computes or performs a Boolean logic function and generates a single-bit output or signal and outputs it to the latch, and wherein the output of the latch directly controls the on / off state of the current source and thereby controls the on / off state of the pixel, the master pixel, the LED, or the set of LEDs.

[0079] The present disclosure provides the following solutions:

[0080] 1. A display device comprising:

[0081] an illumination die, wherein the illumination die comprises at least one illumination element, the at least one illumination element being at least one of coupled to, formed in, and integrated to an illumination element substrate; and

[0082] a backplane device coupled to the illumination die, wherein the backplane device comprises a backplane substrate and pixel circuitry, and wherein the pixel circuitry is at least one of embedded in, integrated to, formed on, or coupled to the backplane substrate, and wherein the pixel circuitry comprises pixel logic circuitry and input / output logic circuitry.

[0083] 2. The display device of solution 1, wherein the pixel circuitry comprises drive circuitry.

[0084] 3. The display device of solution 1, wherein the at least one illumination element comprises three illumination elements.

[0085] 4. The display device of solution 1, wherein the illumination element is an LED.

[0086] 5. The display device of solution 4, wherein the LED is a micro-LED.

[0087] 6. The display device of solution 1, wherein the pixel circuitry is electrically coupled to the at least one illumination element, and wherein the pixel circuitry drives the at least one illumination element.

[0088] 7. The display device of solution 1, wherein the pixel circuitry is coupled to the at least one illumination element by a conductive element, and wherein the pixel circuitry drives the at least one illumination element.

[0089] 8. The display device of Scheme 1, wherein the backplane device is fabricated from a material comprising silicon or other semiconductor in which transistors can be formed.

[0090] 9. The display device of Scheme 1, wherein the illumination element has a conductive portion, and wherein the pixel circuitry includes a conductive portion for electrically coupling the illumination element to its respective pixel circuit.

[0091] 10. The display device of Scheme 1, wherein the backplane device has a TSV, and wherein a top side of the backplane device is connected to a back side of the backplane device by a conductive material or device on an end of the TSV.

[0092] 11. The display device of Scheme 10, further comprising a PCB electrically coupled to the backplane device via a conductive element that couples the PCB and the backplane device with the TSV.

[0093] 12. The display device of Scheme 3, wherein the at least three illumination elements form a first master pixel.

[0094] 13. The display device of Scheme 12, further comprising a second master pixel, and wherein the second master pixel is electrically coupled to the first master pixel via a conductive component or cable.

[0095] 14. The display device of Scheme 13, wherein the first master pixel and the second master pixel form a tile.

[0096] 15. A display device, comprising:

[0097] a plurality of tiles, wherein a tile comprises:

[0098] an illumination die, wherein the illumination die comprises at least one illumination element that is at least one of coupled to, formed in, and integrated to an illumination element substrate; and

[0099] a backplane device coupled to the illumination die, wherein the backplane device comprises a backplane substrate and pixel circuitry, and wherein the pixel circuitry is at least one of embedded in, integrated to, formed on, deposited on, and coupled to the backplane substrate, and wherein the pixel circuitry comprises pixel logic circuitry and input-output logic circuitry; and

[0100] a PCB, wherein the plurality of tiles are electrically coupled via:

[0101] at least one circuitry that at least one of is embedded in, integrated to, formed on, deposited on, and coupled to the backplane substrate, and

[0102] at least one circuitry that at least one of is embedded in, integrated to, formed on, deposited on, and coupled to the PCB.

[0103] 16. The display device of Scheme 15, wherein the pixel logic circuitry at least one of is disposed on, embedded in, integrated to, formed on, deposited on, or coupled to the first strip region of the backplane substrate.

[0104] 17. The display device of Scheme 15, wherein the input / output logic circuitry at least one of is disposed on, embedded in, integrated to, formed on, deposited on, or coupled to the second strip region of the backplane.

[0105] 18. A display system comprising:

[0106] a tile controller, wherein the tile controller controls operation of a tile array or each tile of the plurality of tiles and is included or integrated into an operating die of each of the tiles, and wherein each tile of the plurality of tiles has a tile address; and

[0107] a master controller coupled to at least one of the tiles of the plurality of tiles or tile array, wherein the master controller sends data to the tile to which the master controller is coupled, and wherein the tile controller identifies tile data in the data received from the master controller, and wherein tile data is a subset of the data sent from the master controller, and wherein the tile controller associated with the tile address stores the tile data at a memory component in the tile or a memory component associated with the tile.

[0108] 19. The display system of Scheme 18, wherein the data sent from the master controller includes a tile address in a header of the data sent from the master controller.

[0109] 20. The display system of Scheme 19, wherein the master controller receives data from a first device in a first format, and wherein the master controller converts the data to a suitable second format or a second format that can be read or processed by the tile or the tile controller associated with the tile.

[0110] 21. The display system of Scheme 20, wherein the first device is a device that generates and / or outputs an image or image data.

[0111] 22. The display system of Scheme 18, wherein the tiles of the plurality of tiles or tile array are electrically connected in series.

[0112] 23. The display system of Scheme 22, wherein image or video data is sent to a tile while image or video data for a current frame is being displayed on the tile for display in a next frame.

[0113] 24. The display system of Scheme 18, wherein each tile includes a lighting element, and wherein each lighting element is coupled to a first storage device and a second storage device.

[0114] 25. The display system of Scheme 23, further comprising:

[0115] a logic function circuitry and a latch electrically coupled to the logic function circuitry, wherein the logic function circuitry performs a computational or Boolean logic function such as an equivalence or comparison function and generates an output that is received by a latch to which the logic function circuitry is coupled, and wherein the latch stores the output of the logic function circuitry, and wherein the latch is further electrically coupled to a current driver circuit or component, and wherein the current driver circuit or component is electrically coupled to a lighting element, and wherein the current driver circuit or component supplies a modulated current to the lighting element, and wherein the current driver circuit or component can supply a modulated current to the lighting element in accordance with the output generated by the logic function circuitry.

[0116] 26. A display system, comprising:

[0117] a pixel array of pixel elements, wherein each lighting element of a pixel of the pixel array or each lighting element of a primary pixel is electrically coupled to pixel circuitry, the pixel circuitry comprising:

[0118] a first storage device or a receive pixel memory device;

[0119] a second storage device or active pixel storage device electrically coupled to the receiving pixel storage device;

[0120] logic functional circuitry coupled to the active pixel storage device;

[0121] a latch coupled to the logic functional circuitry; and a current drive device coupled to the latch, and wherein the current drive device drives the operation of each pixel or master pixel of the pixel array; and

[0122] a tile controller, the tile controller comprising:

[0123] a deserializer that receives incoming data from the receiving storage device;

[0124] a decoder, wherein the decoder is electrically coupled to the deserializer, and wherein the deserializer extracts image or video data from a data stream received at the deserializer of the tile controller according to or when the address of a tile is in the data stream, and wherein the deserializer controls the writing of the extracted data to the first storage device or receiving pixel storage device.

[0125] 27. The display system of aspect 26, wherein the decoder decodes the extracted data after extracting the data from the data stream, and wherein the tile controller instructs a control logic block to write the decoded data that has been extracted and subsequently to be placed to a data bus corresponding to or associated with a column comprising or containing illumination elements, pixels, master pixels, LEDs, or a set of LEDs that has been identified as a destination for writing the extracted and subsequently decoded data.

[0126] 28. The display system of aspect 27, wherein the tile controller outputs a ROW / WRITE output or signal to a row of illumination elements, pixels, master pixels, LEDs, or a set of LEDs that has been identified to receive the extracted and subsequently decoded data.

[0127] 29. The display system of aspect 28, further comprising:

[0128] control logic circuitry of the tile controller that outputs a LOAD output voltage or signal that initiates the transfer of data from the receiving storage device to the second storage device or active storage device.

[0129] 30. The display system of aspect 29, further comprising:

[0130] a TVV (time-varying value) generator, wherein after the data has been transferred to the second storage or active storage, a display period starts, wherein during the display period the TVV generator provides a varying value or voltage on a time-varying value (TVV) bus, which is combined by a pixel logic circuit or pixel logic device with the value or voltage in the second storage or active storage and generates a time-varying voltage for modulating a current driver circuit or device electrically coupled to a main pixel or main illumination element.

[0131] 31. The display system according to scheme 30, wherein at each change of the TVV bus caused by the TVV generator, a COMPUTE signal or output generated by a counter in the TVV generator of the tile controller reaches the logic function circuitry and / or latches of the pixel array, and wherein the logic function circuitry computes or performs a Boolean logic function and generates a single-bit output or signal and outputs the single-bit output or signal to the latches, and wherein the output of the latches directly controls the on / off state of a current source and thereby the on / off state of a pixel, main pixel, LED or LED set.

[0132] The above-described embodiments are merely exemplary implementations of implementations offered for purposes of illustrative clarity. Variations, modifications and combinations of the above-described embodiments can be made without departing from the scope of the claims. All such variations, modifications and combinations are included herein within the scope of the present disclosure and the appended claims.

Claims

1. A display apparatus comprising: a plurality of tiles arranged in an array on a printed circuit board (PCB), the PCB configured to electrically couple the plurality of tiles, each tile comprising: an illumination die comprising at least one illumination element; and a tileable backplane die comprising: pixel logic circuitry disposed on, embedded in, integrated into, formed on, deposited on, or coupled to a first region of the backplane die; and input / output logic circuitry disposed on, embedded in, integrated into, formed on, deposited on, or coupled to a second region of the backplane die; wherein the illumination die is coupled to a front surface of the tileable backplane die such that the first region is aligned with at least one illumination element in the illumination die; and wherein each respective tile is coupled to the printed circuit board through a plurality of openings in a back surface of the respective tileable backplane die, the plurality of openings in the back surface aligned with the second region of the backplane die.

2. The display apparatus of claim 1, wherein: the first region comprises a first strip region; and the second region comprises a second strip region.

3. The display apparatus of claim 1, wherein: the first region comprises a plurality of first strip regions; and the second region comprises a plurality of second strip regions alternating with the plurality of first strip regions.

4. The display device according to claim 1, wherein the PCB electrically couples the plurality of tiles in series.

5. The display device according to claim 1, wherein image or video data is sent to the input / output logic circuitry of a tile for display in a next frame while image or video data for the current frame is displayed on the illumination die of the tile for display in the next frame.

6. The display apparatus of claim 1, wherein: each tile of the plurality of tiles has a corresponding tile address; the PCB comprises a master controller coupled to at least one tile of the plurality of tiles; the master controller sends data to the tile to which the master controller is coupled, the data having a header comprising a tile address identifier; a backplane apparatus of a tile identifies tile data in the data received from the master controller, the tile data being a subset of the data sent from the master controller; and the backplane apparatus of the tile associated with the tile address identifier stores the tile data at a memory component in the tile or a memory component associated with the tile.

7. The display apparatus of claim 6, wherein: the master controller receives data in a first format from a first apparatus; and the master controller converts the data in the first format to data in a second format. The master controller converts the data into a second format that can be read or processed by a tile's backplane device.

8. The display device of claim 7, wherein: The first device is a device that outputs image data.

9. The display device of claim 7, wherein: Each illumination element of the illumination die is coupled to a first storage device and a second storage device.

10. A display system, comprising: a pixel array of pixels, each pixel having at least one illumination element in an illumination die, each illumination element of a pixel being electrically coupled to pixel circuitry in a tileable backplane die of a tile, the tileable backplane die comprising: pixel drive and logic circuitry on a first area of the backplane die, the pixel drive and logic circuitry comprising: a receive pixel memory device; an active pixel memory device electrically coupled to the receive pixel memory device; logic function circuitry coupled to the active pixel memory device; a latch coupled to the logic function circuitry; and a current drive device coupled to the latch, wherein the current drive device drives operation of each pixel of the pixel array; and tile controller circuitry on a second area of the backplane die, the tile controller circuitry comprising circuitry configured to: receive a serial data stream; extract image data or video data from the serial data stream according to when the tile's address is in the data stream; decode the image data or video data after it has been extracted from the data stream; control writing of the image data or video data to the receive pixel memory device; and write the image data or video data that has been extracted and subsequently decoded to a data bus corresponding to or associated with a column of one or more pixels of the pixel array, the column being identified as a destination for writing the image data or video data; wherein the illumination die is coupled to a front surface of the tileable backplane die such that the first area is aligned with at least one illumination element in the illumination die, wherein the tileable backplane die comprises a plurality of openings in a back surface of the tileable backplane die, the plurality of openings configured to receive the serial data stream from a tile array controller.

11. The display system of claim 10, wherein: the first area comprises a first strip area; and the second area comprises a second strip area.

12. The display system of claim 10, wherein: the control logic circuitry writes a respective plurality of portions of the image data or video data that has been extracted and subsequently decoded to each data bus of a plurality of data buses corresponding to or associated with a plurality of columns of one or more pixels of the pixel array, each column being identified as a destination for writing a respective one of the plurality of portions of the image data or video data; the first area comprises a plurality of first strip areas; and the second area comprises a plurality of second strip areas. The second region includes a plurality of second strip regions alternating with the plurality of first strip regions.

13. The display system of claim 10, wherein, The tile controller circuitry is configured to output a ROW / WRITE signal to a row of pixels that have been identified as receiving data that has been fetched and subsequently decoded.

14. The display system of claim 13, wherein, The tile controller circuitry is configured to output a LOAD output signal that initiates transfer of data from the receiving pixel memory device to the active pixel memory device.

15. The display system of claim 14, further comprising: a time-varying value (TVV) generator, wherein, after the data has been transferred to the active pixel memory device, a display period begins, wherein, during the display period, the TVV generator provides a varying value or voltage on a TVV bus, the pixel circuitry combines the varying value or voltage with a value or voltage in the active pixel memory device, and generates a time-varying voltage for modulating a current driver device electrically coupled to a main pixel of the pixel array.

16. The display system of claim 10, wherein, The at least one illumination element of a pixel includes three illumination elements that generate light of three colors.

17. The display system of claim 10, wherein, The at least one illumination element of a pixel includes at least one LED.

18. The display system of claim 17, wherein, The at least one LED is at least one micro-LED.

19. A method comprising: transmitting serial data from a host controller to one or more tiles of a plurality of tiles via a printed circuit board, the data having a header including a tile address associated with a first tile of the plurality of tiles; receiving the serial data at a tile controller of the first tile, the tile controller including a backplane, the backplane including: a first region including a plurality of first strip regions; a second region including a plurality of second strip regions alternating with the plurality of first strip regions; pixel logic circuitry at least one of disposed on, embedded in, integrated into, formed on, deposited on, or coupled to the first region, the pixel logic circuitry coupled to one or more illumination elements in an illumination die coupled to a front surface of the backplane; and input / output logic circuitry at least one of disposed on, embedded in, integrated into, formed on, deposited on, or coupled to the second region, the input / output logic circuitry coupled to the printed circuit board through a plurality of openings in a back surface of the backplane aligned with the second region; and at the tile controller of the first tile: identifying the tile address in the header of the serial data; identifying tile data as a subset of the serial data received from the host controller; and storing the tile data at a memory component in the first tile or a memory component associated with the first tile.

20. The method of claim 19, further comprising: receiving image data at the host controller in a first format; and converting the image data at the host controller from the first format to a serial format to obtain the serial data.

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