Display panel and display module

Abstract

The invention provides a display panel and a display module including the same. The display panel of the present invention includes a display region including pixels and a non-display region adjacent to the display region, the non-display region including a pad region in which signal pads connected to the pixels through signal lines are disposed, and the signal pads are connected to the pixels through signal lines. The signal pad includes a first pad insulating layer, a first conductive pattern, a second conductive pattern, a second pad insulating layer, a third conductive pattern, a third pad insulating layer, a fourth conductive pattern, and at least one insulating pattern.

Description

TECHNICAL FIELD

[0001] The present application relates to a display panel and a display module, and more particularly to a display panel including a pad area and a display module including the same. BACKGROUND

[0002] A multimedia electronic device such as a television, a mobile phone, a tablet, a navigation, a game console, etc. can include a display module that displays an image and senses an external input.

[0003] The display module can be electrically connected by being bonded with a driving chip that provides an electrical signal required for image display. SUMMARY

[0004] An object of the present application is to provide a display panel, a display module, and an electronic device that improve bonding reliability.

[0005] A display panel according to an embodiment of the present application includes a display area including a pixel and a non-display area including a pad area adjacent to the display area, a signal pad configured in the pad area and connected to the pixel through a signal line. The signal pad includes a first pad insulating layer configured on a terminal portion of the signal line and defining a first contact hole exposing a portion of the terminal portion of the signal line, a first conductive pattern configured on the first pad insulating layer and connected to the terminal portion of the signal line through the first contact hole, a second conductive pattern configured on the first conductive pattern, a second pad insulating layer configured on the second conductive pattern and defining a second contact hole exposing a portion of the second conductive pattern, a third conductive pattern configured on the second pad insulating layer and connected to the second conductive pattern through the second contact hole, a third pad insulating layer configured on the third conductive pattern and defining a third contact hole exposing a portion of the third conductive pattern, a fourth conductive pattern configured on the third pad insulating layer and connected to the third conductive pattern through the third contact hole, and at least one insulating pattern configured between the third conductive pattern and the fourth conductive pattern.

[0006] The display area can include a base layer, a circuit element layer configured on the base layer, and a light emitting element layer including a light emitting element and configured on the circuit element layer. The circuit element layer includes a transistor, a first connection electrode connected to the transistor, and a second connection electrode connected to the first connection electrode and the light emitting element, respectively. The first conductive pattern and the first connection electrode are configured in the same layer, and the second conductive pattern and the second connection electrode are configured in the same layer.

[0007] The transistor can include a semiconductor pattern including a channel, a source, and a drain, and a gate electrode disposed in a different layer from the semiconductor pattern, and the first connection electrode can be connected to the source or the drain.

[0008] The light emitting element can include a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, and the second connection electrode can be connected to the first electrode.

[0009] The first conductive pattern can be formed in the same process step as the first connection electrode, and the second conductive pattern can be formed in the same process step as the second connection electrode.

[0010] The insulating pattern can include a polymer.

[0011] In a plan view, the insulating pattern can be disposed inside the third contact hole.

[0012] In a plan view, the insulating pattern can be spaced apart from the first contact hole.

[0013] The fourth conductive pattern can include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, the first and third layers each including titanium (Ti), and the second layer including aluminum (Al).

[0014] The non-display area can include a first area adjacent to the display area, a second area spaced apart from the first area, and a bending area disposed between the first area and the second area, and the second area can include the pad area.

[0015] A display module according to an embodiment of the disclosure includes a display panel including a display area including a pixel and a non-display area including a pad area adjacent to the display area and in which a signal pad connected to the pixel through a signal line is disposed, and an input sensing unit including a first sensing conductive layer disposed on the display panel, a first sensing insulating layer disposed on the first sensing conductive layer, and a second sensing conductive layer disposed on the first sensing insulating layer. The signal pad includes a first conductive pattern connected to a terminal portion of the signal line, a second conductive pattern disposed on the first conductive pattern, a third conductive pattern disposed on the second conductive pattern, a fourth conductive pattern disposed on the third conductive pattern, and at least one insulating pattern disposed between the third conductive pattern and the fourth conductive pattern. The third conductive pattern and the first sensing conductive layer include the same substance, and the fourth conductive pattern and the second sensing conductive layer include the same substance.

[0016] The thickness of the third conductive pattern can be the same as the thickness of the first sensing conductive layer, and the thickness of the fourth conductive pattern can be the same as the thickness of the second sensing conductive layer.

[0017] The third conductive pattern can be formed in the same process step as the first sensing conductive layer, and the fourth conductive pattern can be formed in the same process step as the second sensing conductive layer.

[0018] The fourth conductive pattern may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, wherein the first layer and the third layer respectively comprise titanium (Ti), and the second layer comprises aluminum (Al).

[0019] The signal pad may include: a first pad insulating layer disposed on the end portion of the signal line and defining a first contact hole that exposes a portion of the end portion of the signal line; a second pad insulating layer disposed on the second conductive pattern and defining a second contact hole that exposes a portion of the second conductive pattern; and a third pad insulating layer disposed on the third conductive pattern and defining a third contact hole that exposes a portion of the third conductive pattern. The first conductive pattern is disposed on the first pad insulating layer and connected to the end portion of the signal line through the first contact hole; the third conductive pattern is disposed on the second pad insulating layer and connected to the second conductive pattern through the second contact hole; and a fourth conductive pattern is disposed on the third pad insulating layer and connected to the third conductive pattern through the third contact hole.

[0020] The display area may include a substrate layer, a circuit element layer, and a light-emitting element layer. The circuit element layer is disposed on the substrate layer, and the light-emitting element layer includes a light-emitting element and is disposed on the circuit element layer. The circuit element layer includes: a transistor; a first connection electrode connected to the transistor; and a second connection electrode connected to the first connection electrode and the light-emitting element, respectively. The first conductive pattern and the first connection electrode are disposed on the same layer, and the second conductive pattern and the second connection electrode are disposed on the same layer.

[0021] The first conductive pattern can be formed in the same process step as the first connecting electrode, and the second conductive pattern can be formed in the same process step as the second connecting electrode.

[0022] The insulating pattern may contain polymers.

[0023] At least one of the first sensing conductive layer and the second sensing conductive layer may include a mesh opening.

[0024] An electronic device according to an embodiment of the present invention includes a display module, electronic components, and an adhesive layer for bonding the display panel and the electronic components. The display module includes a display panel and an input sensing unit disposed on the display panel. The display panel includes a display area and a non-display area. The display area includes pixels, and the non-display area includes a pad area adjacent to the display area. The electronic components include bump electrodes disposed on the pad areas. Signal pads connected to the pixels via signal lines are disposed on the pad areas. The input sensing unit includes: a first sensing conductive layer disposed on the display panel; a first sensing insulating layer disposed on the first sensing conductive layer; and a second sensing conductive layer disposed on the first sensing insulating layer. The signal pads include: a first conductive pattern connected to the end of the signal line; a second conductive pattern disposed on the first conductive pattern; a third conductive pattern disposed on the second conductive pattern; a fourth conductive pattern disposed on the third conductive pattern; and at least one insulating pattern overlapping the bump electrodes in a plane and disposed between the third and fourth conductive patterns. The third conductive pattern and the first sensing conductive layer contain the same material, and the fourth conductive pattern and the second sensing conductive layer contain the same material.

[0025] Invention Effects

[0026] As described above, the display panel and display module of the present invention can have excellent bonding reliability with electronic components.

[0027] Furthermore, the electronic device of the present invention can have excellent reliability. Attached Figure Description

[0028] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0029] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0030] Figure 3 This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0031] Figure 4 This is a top view of a display panel according to an embodiment of the present invention.

[0032] Figure 5 This is a top view of an input sensing unit according to an embodiment of the present invention.

[0033] Figure 6 This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0034] Figure 7 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0035] Figure 8A This is a top view of the pad area according to an embodiment of the present invention.

[0036] Figure 8B and Figure 8C These are cross-sectional views of the pad area according to an embodiment of the present invention.

[0037] Figure 8D This is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0038] Figures 9A to 10C These are top views of the pad area according to an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures

[0040] EA: Electronic Device; DM: Display Module; DP: Display Panel; ISP: Input Sensing Unit; DA: Display Area; NDA: Non-Display Area; PA1, PA2: Pad Areas; PD:

[0041] Pads; PP: Insulating pattern; CP1, CP2, CP3, CP4: First, second, third, and fourth conductive patterns; IL1-P, IL2-P, IL3-P: First, second, and third pad insulating layers; OP1-C,

[0042] OP2-C, OP3-C: First, second, and third contact holes Detailed Implementation

[0043] This invention can be implemented in various ways and can have various forms. Examples are illustrated in the accompanying drawings and detailed descriptions are provided in specific embodiments. However, this is not intended to limit the invention to a particular disclosed form, but should be understood to include all modifications, equivalents, and even substitutions falling within the spirit and technical scope of this invention.

[0044] In this specification, unless the context clearly indicates a different meaning, singular expressions include plural expressions.

[0045] In this specification, it should be understood that terms such as “comprising” or “having” are intended to specify the presence of the features, figures, steps, actions, constituent elements, components or combinations thereof described in the specification, and are not intended to pre-exclude the presence or additional possibility of one or more other features, figures, steps, actions, constituent elements, components or combinations thereof.

[0046] In this specification, when a component (or region, layer, part, etc.) is mentioned as being "above", "connected" or "combined" with another component, it means that the component can be directly configured / connected / combined with the other component, or that a third component can be configured between them.

[0047] In this specification, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the constituent elements shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0048] In this specification, "configured on" can mean not only the upper part of a component, but also the lower part of a component.

[0049] In this specification, "direct configuration" can mean that there are no additional layers, films, regions, plates, etc. between the layers, films, regions, plates, etc. and other parts. For example, "direct configuration" can mean that two layers or two components are configured without the use of additional components such as adhesive members.

[0050] In this specification, "and / or" includes all of the associated constituent elements that can be defined as one or more combinations.

[0051] In this specification, terms such as "first," "second," etc., can be used to describe various constituent elements, but the constituent elements are not limited to these terms. These terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the invention, a first constituent element may be referred to as a second constituent element, and similarly, a second constituent element may be referred to as a first constituent element.

[0052] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms identical to those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, wherein they shall not be construed as having an overly ideal or formal meaning unless expressly defined.

[0053] The same reference numerals denote the same constituent elements. Furthermore, in the drawings, for the purpose of effectively illustrating the technical content, the thickness, proportions, and dimensions of the constituent elements are exaggerated.

[0054] Hereinafter, a display panel, display module, and electronic device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0055] Figure 1 This is a perspective view of an electronic device EA according to an embodiment of the present invention. Figure 2 This is an exploded perspective view of an electronic device EA according to an embodiment of the present invention.

[0056] Reference Figure 1 and Figure 2 An electronic device EA can be a device that is activated by an electrical signal and displays an image IM and senses external input TC. For example, an electronic device EA can include devices such as a display, mobile phone, tablet computer, navigation system, or game console. However, the above-described embodiments of electronic devices EA are merely illustrative and are not limited to any particular embodiment without departing from the concept of the invention. In this embodiment, a mobile phone is illustrated as an example of an electronic device EA.

[0057] The electronic device EA can be rectangular in shape, having a short side extending along a first direction DR1 on a plane and a long side extending along a second direction DR2 intersecting the first direction DR1. However, it is not limited to this, and the electronic device EA can have various shapes such as circles and polygons on a plane.

[0058] In this embodiment, the third direction DR3 can be defined as a direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The front (or top) and back (or bottom) surfaces of the components constituting the electronic device EA can be opposite each other on the third direction DR3, and the normal directions of the front and back surfaces can be substantially parallel to the third direction DR3. The distance between the front and back surfaces defined along the third direction DR3 can correspond to the thickness of the component.

[0059] In this specification, "on a plane" can be defined as the state viewed from a third direction towards DR3. In this specification, "on a cross section" can be defined as the state viewed from a first direction DR1 or a second direction DR2. Furthermore, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be changed to other directions.

[0060] Electronic devices (EAs) can be rigid or flexible. "Flexible" refers to the property of being able to be bent, which can include everything from fully foldable structures to structures that can be bent at the nanometer level. For example, flexible electronic devices (EAs) can include curved, rollable, or foldable electronic devices.

[0061] The electronic device EA can display images IM through display surfaces FS that are parallel to the first direction DR1 and the second direction DR2. The images IM can include not only moving images but also still images. Figure 1 The icon is shown as an example of an image IM.

[0062] The display surface FS of the electronic device EA may consist only of a plane, or it may also include curved surfaces that curve from one or more sides of the plane. The display surface FS may correspond to the front surface of the electronic device EA, and may also correspond to the front surface of the window WM. Hereinafter, the display surface FS of the electronic device EA and the front surface FS of the window WM will use the same reference numerals.

[0063] According to one embodiment, the electronic device EA can sense external input TC applied from the outside. External input TC can include various forms of input such as force, pressure, temperature, or light. In this embodiment, external input TC is shown as a user's hand applied to the front of the electronic device EA. However, this is merely illustrative, and external input TC can include pen-based contact or input applied in a manner close to the electronic device EA, such as hovering.

[0064] An electronic device EA can sense user input through its front display surface FS and react to the sensed input signal. However, the area of ​​the electronic device EA that senses external input TC is not limited to the front of the electronic device EA, but can be varied depending on the design of the electronic device EA. For example, the electronic device EA can also sense user input applied to the side or back of the electronic device EA.

[0065] An electronic device (EA) may include: a window (WM), a display module (DM), an electronic module (ELM), a power supply module (PSM), and a housing (HAU). The window (WM) and the housing (HAU) can be combined to form the appearance of the electronic device (EA).

[0066] The window WM can be configured on the display module DM. The window WM covers the front IS of the display module DM and protects it from external impacts and scratches. The window WM can be bonded to the display module DM via an adhesive layer.

[0067] The window WM can contain an optically transparent insulating material. For example, the window WM can contain glass or synthetic resin as a base film. The window WM can have a single-layer or multi-layer structure. For example, a multi-layer window WM can include a synthetic resin film bonded by an adhesive, or a glass film bonded by an adhesive and a synthetic resin film. The window WM can also include functional layers such as an anti-fingerprint layer, a phase control layer, or a hard coating layer disposed on the transparent base film.

[0068] The front FS of the window WM can correspond to the front FS of the electronic device EA. The front FS of the window WM can include the transmissive area TA and the border area BZA.

[0069] The transmissive region TA can be an optically transparent area. The transmissive region TA allows the image IM provided by the display module DM to be transmitted. In this embodiment, although the transmissive region TA is shown as a quadrilateral shape, it is not limited to this, and the transmissive region TA can have various shapes.

[0070] The bezel area BZA can be a region whose light transmittance is lower than that of the transmissive area TA. The bezel area BZA can correspond to an area printed with a specified color. By preventing light transmission, the bezel area BZA prevents a structural element of the display module DM, which is configured to overlap with the bezel area BZA, from being visible from the outside.

[0071] The border region BZA may be adjacent to the transmission region TA. The shape of the transmission region TA may be substantially defined by the border region BZA. For example, the border region BZA may be configured outside and surround the transmission region TA. However, this is only illustrative; the border region BZA may be adjacent only to one side of the transmission region TA, or configured on the side of the electronic device EA instead of the front. Furthermore, the border region BZA may also be omitted.

[0072] The display module DM can be configured between the window WM and the housing HAU. The display module DM can display the image IM and sense external input TC. The image IM can be displayed on the front IS of the display module DM. The front IS of the display module DM can include an active area AA and a peripheral area NAA.

[0073] The active region AA can be a region activated by an electrical signal. For example, the active region AA can be a region for displaying an image IM and simultaneously a region for sensing an external input TC. The active region AA can overlap with at least a portion of the transmission region TA. Thus, a user can view the image IM or provide external input TC through the transmission region TA. However, this is only illustrative, and the region for displaying the image IM and the region for sensing the external input TC within the active region AA can be separated from each other, and is not limited to any particular embodiment.

[0074] The peripheral area NAA can be adjacent to the active area AA. For example, the peripheral area NAA can surround the active area AA. The peripheral area NAA can be configured with drive circuits or drive wiring for driving the active area AA. The peripheral area NAA can overlap with at least a portion of the frame area BZA, and the structural elements configured in the peripheral area NAA can be prevented from being seen from the outside by means of the frame area BZA.

[0075] The display module (DM) may include a display panel and an input sensing unit. The display panel can display an image (IM), and the input sensing unit can sense external inputs (TC). This will be described in detail later.

[0076] A portion of the display module DM can be bent around a bending axis extending along the first direction DR1. That is, the portion of the display module DM can be bent toward the back of the display module DM corresponding to the active region AA. A flexible circuit board FCB can be connected to the bent portion of the display module DM, thereby allowing the flexible circuit board FCB to overlap with the display module DM in a plane.

[0077] The flexible circuit board (FCB) can be electrically connected to one side of the display module (DM). The FCB can generate electrical signals supplied to the display module (DM) or receive signals generated from the display module (DM) to calculate result values ​​including the position or intensity information of the external input TC sensed.

[0078] The electronic module (ELM) and power supply module (PSM) can be configured below the display module (DM). The ELM and PSM can be electrically connected via a separate circuit board.

[0079] A power supply module (PSM) can provide the power required for the operation of an electronic device (EA). For example, a power supply module (PSM) may include a conventional battery module.

[0080] An electronic module (ELM) may include various functional modules for enabling an electronic device (EA) to operate. For example, an ELM may include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, an optical module, and an external interface module. An ELM may include a main circuit board, and the modules of the ELM may be mounted on the main circuit board or electrically connected to the main circuit board via another circuit board.

[0081] In the Electronic Module (ELM), the control module can control the overall operation of the Electronic Device (EA). For example, the control module can activate or deactivate the Display Module (DM) in response to user input. The control module may include at least one microprocessor. In the Electronic Module (ELM), the optical module may include a camera module, a proximity sensor, a biometric sensor that identifies a part of the user's body (e.g., fingerprint, iris, or face), or a light source.

[0082] The housing HAU can be integrated with the window WM and provide internal space for housing the display module DM, electronic module ELM, power module PSM, and flexible circuit board FCB. The housing HAU can contain materials with relatively high rigidity. For example, the housing HAU can contain glass, plastic, or metal, or include multiple frames and / or plates composed of combinations thereof. The housing HAU can absorb impacts applied from the outside or prevent the penetration of foreign matter / moisture, thereby protecting the structural components of the electronic device EA housed within the housing HAU.

[0083] Figure 3 This is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0084] Reference Figure 3 The display module DM may include a display panel DP and an input sensing unit ISP. The input sensing unit ISP may be configured on the display panel DP. For example, the input sensing unit ISP may be directly configured on the display panel DP. In this embodiment, "the input sensing unit ISP is directly configured on the display panel DP" means that the input sensing unit ISP is formed on the display panel DP through a continuous process, thereby bonding the input sensing unit ISP to the display panel DP without an additional adhesive layer. That is, the structural elements of the input sensing unit ISP can be formed on the substrate surface provided by the display panel DP.

[0085] The display panel (DP) can display images based on electrical signals. In one embodiment, the display panel (DP) can be a light-emitting display panel, but there are no particular limitations. For example, the display panel (DP) can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can contain organic light-emitting materials, and the light-emitting layer of an inorganic light-emitting display panel can contain inorganic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) will be described as an organic light-emitting display panel.

[0086] The display panel DP may include a substrate BS, a circuit element layer DP-CL, a light-emitting element layer DP-OL, and an encapsulation layer ECL, which are sequentially stacked along the third direction DR3.

[0087] The substrate BS can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. For example, the substrate BS can be a glass substrate, a metal substrate, or a polymer substrate. The substrate BS can provide a base surface for configuring the circuit element layer DP-CL.

[0088] The substrate BS may include inorganic layers, multiple layers, or composite material layers. The substrate BS may have a single-layer or multi-layer structure. For example, a multi-layer substrate BS may include synthetic resin layers and multiple or single-layer inorganic layers disposed between the synthetic resin layers. The synthetic resin layers may include acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, or perylene resins, but the material of the synthetic resin layers is not limited to these.

[0089] The DP-CL (Distributed Component Layer) can be disposed on a substrate BS. The DP-CL may include at least one insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer, semiconductor pattern, and conductive pattern included in the DP-CL can form driving elements such as transistors, signal lines, and pads.

[0090] The light-emitting element layer DP-OL can be disposed on the circuit element layer DP-CL. The light-emitting element layer DP-OL can include light-emitting elements that emit light individually. For example, the light-emitting elements can include organic light-emitting elements, inorganic light-emitting elements, micro LEDs, or nano LEDs. The light-emitting elements of the light-emitting element layer DP-OL can be electrically connected to the driving elements of the circuit element layer DP-CL and emit light according to the electrical signals provided by the driving elements.

[0091] An encapsulation layer (ECL) can be disposed on the light-emitting element layer (DP-OL) and seal the light-emitting element. The ECL may include at least one thin film for improving the optical efficiency of the DP-OL or for protecting the DP-OL. For example, the ECL may include at least one inorganic film and an organic film. The inorganic film of the ECL can protect the light-emitting element from moisture / oxygen. The organic film of the ECL can protect the light-emitting element from foreign matter such as dust particles.

[0092] The input sensing unit (ISP) can sense external input and provide an input signal including information related to the external input, so that the display panel (DP) can display an image corresponding to the external input. The input sensing unit (ISP) can be driven in various ways, such as capacitive, resistive, infrared, acoustic, or pressure-based methods. As long as external input can be sensed, the driving method of the input sensing unit (ISP) is not limited to any one method. In this embodiment, the input sensing unit (ISP) is described as an input sensing panel driven by a capacitive method.

[0093] The input sensing unit ISP may include a substrate layer IL1, a first sensing conductive layer CL1, a first sensing insulating layer IL2, a second sensing conductive layer CL2, and a second sensing insulating layer IL3, sequentially stacked along the third direction DR3. The substrate layer IL1 of the input sensing unit ISP may be in contact with the encapsulation layer ECL. However, the embodiment is not limited thereto, and at least one of the substrate layer IL1 and the second sensing insulating layer IL3 may be omitted.

[0094] The first sensing conductive layer CL1 and the second sensing conductive layer CL2 can each have a single-layer or multi-layer structure. The multi-layer conductive layer can include two or more of a transparent conductive layer and a metal layer. The multi-layer conductive layer can include metal layers containing different metals. The transparent conductive layer can include at least one of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), polyethylene dioxythiophene (PEDOT), metal nanowires, and graphene. The metal layer can include at least one of molybdenum, silver, titanium, copper, aluminum, and alloys thereof. For example, the first sensing conductive layer CL1 and the second sensing conductive layer CL2 can each have a two-layer structure, such as an ITO / copper two-layer structure, or not limited thereto, it can have a titanium / aluminum / titanium three-layer structure.

[0095] The first sensing conductive layer CL1 and the second sensing conductive layer CL2 may each include a sensing conductive pattern. The sensing conductive patterns of the first sensing conductive layer CL1 and the second sensing conductive layer CL2 can form the sensing electrodes constituting the input sensing unit ISP and the sensing lines connected thereto.

[0096] The substrate layer IL1, the first sensing insulating layer IL2, and the second sensing insulating layer IL3 may each include at least one inorganic film and an organic film. For example, the inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide, and the organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, ethylene resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin. However, the materials of the inorganic and organic films are not limited to the examples described. In one embodiment, the substrate layer IL1 may include an inorganic film, and the first sensing insulating layer IL2 and the second sensing insulating layer IL3 may include organic films, but the embodiment is not limited thereto.

[0097] Figure 4This is a top view of a display panel DP according to an embodiment of the present invention.

[0098] Reference Figure 4 The display panel DP may include: a substrate BS, a pixel PX, signal lines SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL, a scan driver SDV, an emission driver EDV, a data driver DDV, and a display pad D-PD.

[0099] The substrate BS can provide a base surface for configuring electrical components, lines, etc., of the display panel DP. The substrate BS may include a first base region AA1, a curved region BA, and a second base region AA2 defined in a second direction DR2. The curved region BA may extend from the first base region AA1 in the second direction DR2. The second base region AA2 may extend from the curved region BA in the second direction DR2. Therefore, the first base region AA1 and the second base region AA2 may be separated from each other by the curved region BA.

[0100] The first base region AA1 may include a display region DA. The display region DA may be a region for configuring the light-emitting elements of the pixel PX. Thus, the pixel PX can display an image through the display region DA. The display region DA may correspond to the display module DM (see reference). Figure 2 The active region AA (refer to) Figure 2 It can be used with Windows Mobile (see reference). Figure 2 The transmission region TA (reference) Figure 2 )overlapping.

[0101] The remaining first substrate region AA1, curved region BA, and second substrate region AA2, excluding the display region DA, can be defined as the non-display region NDA. The non-display region NDA can be an area adjacent to the display region DA that does not display an image. The non-display region NDA can surround the display region DA. The non-display region NDA can be configured with a scan driver unit SDV, a light-emitting driver unit EDV, a driver chip DDV, and display pads D-PD electrically connected to signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL for driving pixels PX. The signal lines SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL electrically connected to pixels PX can extend and be configured on the non-display region NDA.

[0102] The curved region BA can be a region that bends around a bending axis extending in the first direction DR1. That is, the curved region BA can bend toward the back of the display panel DP corresponding to the first base region AA1. The second base region AA2 extending from one side of the curved region BA can overlap with the first base region AA1 in a plane as the curved region BA bends. That is, the second base region AA2 can be disposed on the back of the display panel DP corresponding to the first base region AA1.

[0103] In the first direction DR1, the widths of both the bending region BA and the second base region AA2 can be smaller than the width of the first base region AA1. In a direction parallel to the bending axis, the bending region BA has a smaller width than the first base region AA1, thereby allowing the bending region BA to be easily bent. However, this is merely illustrative; in the first direction DR1, at least one of the widths of the bending region BA and the second base region AA2 can be the same as the width of the first base region AA1, and is not limited to any one of them.

[0104] The second base region AA2 may be a region located below the first base region AA1 and provided flat by bending through the bending region BA. The second base region AA2 may be a region used to configure the signal lines SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL that extend towards the display pad D-PD via the bending region BA and the driver chip DDV.

[0105] The area for configuring the display pad D-PD and the area for configuring the sensing pad I-PD (described later) (see reference) Figure 5 The area can be divided into the display pad area PD-A and the sensing pad area IPD-A. Figure 4 The illustration illustratively shows a scenario where the display pad region PD-A and the sensing pad region IPD-A are divided along a first direction DR1. For example, the sensing pad region IPD-A may be provided adjacent to both sides of the second substrate region AA2 along the first direction DR1, and the display pad region PD-A may be provided in the central portion. However, the embodiment is not necessarily limited to this; the display pad D-PD and the sensing pad I-PD (see reference 1) may also be used. Figure 5 The placement of the ) can be changed in many ways.

[0106] Flexible circuit board FCB (reference) Figure 2 It can be configured with display pads (D-PD) and sensing pads (I-PD) (see reference). Figure 5 On the second substrate region AA2, and with display pad D-PD and sensing pad I-PD (see reference). Figure 5Electrical connection. A flexible circuit board FCB (refer to) is disposed adjacent to the lower end of the second substrate region AA2. Figure 2 The second substrate region AA2 and the flexible circuit board FCB (see reference) can be located on the back of the display panel DP as the bending region BA bends. Figure 2 In electronic device EA (refer to) Figure 2 On the front side of the device, below the first base region AA1, the electronic device EA (refer to...) Figure 2 The border area of ​​) can be reduced.

[0107] Each pixel PX may include a pixel driving circuit consisting of transistors (e.g., switching transistors, driving transistors, etc.) and at least one capacitor, as well as a light-emitting element electrically connected to the pixel driving circuit. Each pixel PX can generate light in response to an electrical signal applied to it, and can display an image through the display area DA. According to an embodiment, a portion of the pixels PX may include transistors disposed in the non-display area NDA, and is not limited to any one type.

[0108] The scanning driver unit (SDV) and the light-emitting driver unit (EDV) can be configured in the non-display area NDA corresponding to the first substrate region AA1. The driver chip (DDV) can be configured in the non-display area NDA corresponding to the second substrate region AA2. In one embodiment, the driver chip (DDV) can be provided as an integrated circuit chip mounted in the non-display area NDA of the display panel DP. However, it is not limited to this; the driver chip (DDV) can also be mounted on the flexible circuit board FCB (see reference). Figure 2 )superior.

[0109] The signal lines SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, and PL may include: scan lines SL1~SLm, data lines DL1~DLn, light emission lines EL1~ELm, first control line CSL1 and second control line CSL2, and power line PL. Here, m and n represent natural numbers.

[0110] Data lines DL1 to DLn can be insulated from and cross scan lines SL1 to SLm and light-emitting lines EL1 to ELm. For example, scan lines SL1 to SLm can extend along the first direction DR1 and be electrically connected to the scan driver unit SDV. Data lines DL1 to DLn can extend along the second direction DR2 and be electrically connected to the driver chip DDV. Light-emitting lines EL1 to ELm can extend along the first direction DR1 and be electrically connected to the light-emitting driver unit EDV.

[0111] The power line PL may include a portion extending along a first direction DR1 and a portion extending along a second direction DR2. The portions extending along the first direction DR1 and the second direction DR2 of the power line PL may be configured on different layers or integrally configured on the same layer. In the power line PL, the portion extending along the first direction DR1 may be electrically connected to the pixel PX and the portion extending along the second direction DR2. In the power line PL, the portion extending along the second direction DR2 may be configured in the non-display area NDA and electrically connected from the first substrate area AA1 via the bending area BA and the second substrate area AA2 to the display pad D-PD. The power line PL may provide a first voltage to the pixel PX.

[0112] The first control line CSL1 can be electrically connected to the scan driver unit SDV, and extends towards the lower end of the second substrate region AA2 via the bending region BA. The second control line CSL2 can be electrically connected to the light emission driver unit EDV, and extends towards the lower end of the second substrate region AA2 via the bending region BA.

[0113] Display pads D-PD can be configured adjacent to the lower end of the second substrate region AA2. On the second substrate region AA2, display pads D-PD can be configured closer to the lower end of the substrate BS than the driver chip DDV. Display pads D-PD can be spaced apart from each other along the first direction DR1. Power line PL, first control line CSL1, and second control line CSL2 can be electrically connected to their corresponding display pads D-PD. Data lines DL1 to DLn can be electrically connected to their corresponding display pads D-PD via the driver chip DDV.

[0114] The D-PD pads can be bonded to the flexible circuit board FCB via an adhesive layer (see reference). Figure 2 Electrical connection from the flexible circuit board FCB (reference) Figure 2 The electrical signals provided can be transmitted to the display panel (DP) via the display pads (D-PD). However, the display pads (D-PD) and the flexible circuit board (FCB) (see reference) Figure 2 The connection method is not limited to this.

[0115] The scan drive unit (SDV) generates a scan signal in response to a scan control signal. The scan signal is applied to pixel PX via scan lines SL1 to SLm. The drive chip (DDV) generates a data voltage corresponding to the image signal in response to a data control signal. The data voltage is applied to pixel PX via data lines DL1 to DLn. The light emission drive unit (EDV) generates a light emission signal in response to a light emission control signal. The light emission signal is applied to pixel PX via light emission lines EL1 to Elm.

[0116] A pixel (PX) can receive data voltage in response to a scan signal. A pixel (PX) can generate an image by emitting light of a brightness corresponding to the data voltage in response to a light emission signal. The emission time of a pixel (PX) can be controlled by the light emission signal.

[0117] Figure 5 This is a top view of an input sensing unit (ISP) according to an embodiment of the present invention. For ease of explanation, Figure 5 The structural elements of the input sensing unit ISP disposed on the aforementioned substrate BS are briefly shown.

[0118] In one embodiment, the input sensing unit (ISP) can be driven in a mutual-capacitance manner. See also... Figure 5 The input sensing unit (ISP) may include: a first sensing electrode TEX (TEX1 to TEX6), a second sensing electrode TEY (TEY1 to TEY4), a first sensing line TLX1 to TLX6, a second sensing line TLY1 to TLY4, and a sensing pad I-PD. However, it is not limited to this, and the input sensing unit (ISP) may be driven in a self-capacitance manner.

[0119] Each of the first sensing electrodes TEX can extend along the first direction DR1, and the first sensing electrodes TEX are arranged along the second direction DR2. Figure 5 Six first sensing electrodes TEX1 to TEX6 are illustrated illustratively. However, the number of first sensing electrodes TEX included in the input sensing unit ISP is not limited to this. A first sensing electrode TEX may include a first sensing pattern SP1 arranged along a first direction DR1 and a first connection pattern BP1 for connecting these first sensing patterns SP1.

[0120] Each of the second sensing electrodes TEY can extend along the second direction DR2, and the second sensing electrodes TEY are arranged along the first direction DR1. Figure 5 Four second sensing electrodes TEY1 to TEY4 are illustrated. However, the number of second sensing electrodes TEY included in the input sensing unit ISP is not limited to this. A second sensing electrode TEY may include a second sensing pattern SP2 arranged along the second direction DR2 and a second connection pattern BP2 for connecting these second sensing patterns SP2.

[0121] The first sensing electrode TEX and the second sensing electrode TEY can be electrically isolated. The input sensing unit ISP can sense external input by the capacitance change between the first sensing electrode TEX and the second sensing electrode TEY. The first sensing electrode TEX and the second sensing electrode TEY can be configured in a region corresponding to the display area DA of the substrate BS. Thus, the electronic device EA (refer to...)Figure 1 It can sense external input applied to the display area DA while displaying the image.

[0122] The first sensing lines TLX1 to TLX6 can be configured on the non-display area NDA and electrically connected to the first sensing electrodes TEX1 to TEX6 respectively. A portion of the first sensing lines TLX1 to TLX6 can be configured on the left side of the non-display area NDA, and the remaining portion can be configured on the right side of the non-display area NDA. For example, the first sensing lines TLX1, TLX3, and TLX5 connected to the first sensing electrodes TEX1, TEX3, and TEX5 configured in odd-numbered rows can be connected to the left side of the first sensing electrodes TEX1, TEX3, and TEX5 respectively, and the first sensing lines TLX2, TLX4, and TLX6 connected to the first sensing electrodes TEX2, TEX4, and TEX6 configured in even-numbered rows can be connected to the right side of the first sensing electrodes TEX2, TEX4, and TEX6 respectively. However, the arrangement of the first sensing lines TLX1 to TLX6 is not limited to this. The first sensing lines TLX1 to TLX6 can also be arranged on the left side of the non-display area NDA, or the first sensing lines TLX1 to TLX6 can also be arranged on the right side of the non-display area NDA.

[0123] Each of the first sensing lines TLX1 to TLX6 can extend from the first substrate region AA1 through the bending region BA toward the second substrate region AA2. The first sensing lines TLX1 to TLX6 can be electrically connected to the sensing pads I-PD disposed on the second substrate region AA2.

[0124] The second sensing lines TLY1 to TLY4 can be disposed on the non-display area NDA and electrically connected to the second sensing electrodes TEY1 to TEY4 respectively. A portion of the second sensing lines TLY1 to TLY4 can be disposed adjacent to the left side of the non-display area NDA, and the remaining portion can be disposed adjacent to the right side of the non-display area NDA. For example, in the first direction DR1, the second sensing lines TLY1 and TLY2 electrically connected to the second sensing electrodes TEY1 and TEY2 disposed on the left side of the second sensing electrodes TEY1 to TEY4 can be disposed adjacent to the left side of the first substrate area AA1, and the second sensing lines TLY3 and TLY4 electrically connected to the second sensing electrodes TEY3 and TEY4 disposed on the right side of the second sensing electrodes TEY1 to TEY4 can be disposed adjacent to the right side of the first substrate area AA1. However, the arrangement of the second sensing lines TLY1 to TLY4 is not limited to this.

[0125] The second sensing lines TLY1 to TLY4 can each extend from the region adjacent to the lower end of the first base region AA1 towards the second base region AA2 via the bending region BA. The second sensing lines TLY1 to TLY4 can be electrically connected to the sensing pads I-PD disposed on the second base region AA2.

[0126] A portion of the sensing pads I-PD can be configured in the first direction DR1 in a region adjacent to the left side of the second base region AA2, while the remaining portion can be configured in a region adjacent to the right side of the second base region AA2. For example, the sensing pads I-PD can be divided into two groups separated from each other by the display pad region PD-A. However, the arrangement of the sensing pads I-PD is not limited to this.

[0127] The sensing pad I-PD can be used with the display pad D-PD (see reference). Figure 4 The sensing pad I-PD can be configured on the same layer as the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4, and connected through contact holes. However, this is not a limitation; the sensing pad I-PD can also be configured on a different layer than the display pad D-PD (see reference). Figure 4 They can be configured on different layers. For example, the sensing pad I-PD can be integrally formed on the same layer as the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4.

[0128] The first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can be arranged on the display panel DP (refer to) in the area corresponding to the non-display area NDA of the substrate BS. Figure 4 The structural elements are positioned higher up. Therefore, the first sensing lines TLX1~TLX6 and the second sensing lines TLY1~TLY4 can connect with the display panel DP (see reference) on the curved area BA and the second substrate area AA2. Figure 4 The structural elements overlap.

[0129] Figure 6 This is a cross-sectional view of a display module DM according to an embodiment of the present invention. Figure 6 The image illustrates, for example, the pixels PX configured in the display area DA (see reference). Figure 4 ) cross section.

[0130] Reference Figure 6 The display module DM may include a display panel DP and an input sensing unit ISP configured on the display panel DP. The foregoing description applies equally to each structural element.

[0131] like Figure 3As mentioned above, the display panel DP may include: a substrate BS, a circuit element layer DP-CL, a light-emitting element layer DP-OL, and an encapsulation layer ECL.

[0132] The substrate BS may be insulating and provide a base surface for configuring structural elements of the display module DM. The substrate BS may be flexible enough to be bent. As described above, the substrate BS may include a first base region AA1 (refer to...). Figure 4 ), bending region BA (refer to) Figure 4 ) and the second basal region AA2 (refer to Figure 4 The bending region BA of the substrate BS (refer to) Figure 4 It can be bent at a specified curvature.

[0133] The circuit element layer DP-CL may include: an insulating layer 10-60 disposed on the substrate BS, and a pixel PX (refer to...) Figure 4 The transistor TR, upper electrode UE, and connecting electrodes CN1 and CN2 are included. Insulating layers 10 to 60 may include a first insulating layer 10 to a sixth insulating layer 60 sequentially stacked on the substrate BS along the thickness direction. However, the embodiments of insulating layers 10 to 60 included in the circuit element layer DP-CL are not limited thereto, and may be varied according to the structural elements or manufacturing process of the circuit element layer DP-CL.

[0134] A first insulating layer 10 may be disposed on a substrate BS. The first insulating layer 10 may be provided as a barrier layer and / or a buffer layer to prevent foreign matter from entering from the outside. The first insulating layer 10 may improve the adhesion between the substrate BS and the semiconductor pattern SM and / or conductive pattern of the circuit element layer DP-CL. The first insulating layer 10 may include at least one of a silicon oxide layer and a silicon nitride layer. In one embodiment, the first insulating layer 10 may include alternating layers of silicon oxide and silicon nitride.

[0135] Pixel PX (reference) Figure 4 ) can be configured on the substrate BS. Pixel PX (refer to Figure 4 This can be configured corresponding to the display area DA. Pixel PX (refer to...) Figure 4 It can include transistors (TR) and light-emitting elements (OL).

[0136] The transistor TR may include a semiconductor pattern SM and a gate electrode GE. The semiconductor pattern SM may be disposed on the first insulating layer 10. The semiconductor pattern SM may include a channel S1, a source S2, and a drain S3. The semiconductor pattern SM may include silicon semiconductor, and may include single-crystal silicon semiconductor, polycrystalline silicon semiconductor, or amorphous silicon semiconductor. However, it is not limited to this, and the semiconductor pattern SM may also include oxide semiconductor. As long as the semiconductor pattern SM of an embodiment of the present invention has semiconductor properties, it can be formed from a variety of materials and is not limited to a certain embodiment.

[0137] A semiconductor pattern SM can include multiple regions with different electrical properties depending on whether it is doped or reduced. For example, a semiconductor pattern SM may include regions with high conductivity due to doping or reduction of the metal oxide; these highly conductive regions can function as electrodes or signal wiring in a transistor TR. This could correspond to the source S2 and drain S3 of a transistor TR. A semiconductor pattern SM may also include regions with relatively low conductivity due to being undoped; this could correspond to the channel S1 (or active) of a transistor TR.

[0138] The second insulating layer 20 can be disposed on the first insulating layer 10 and cover the semiconductor pattern SM. The gate electrode GE can be disposed on the second insulating layer 20. The second insulating layer 20 can be disposed between the semiconductor pattern SM and the gate electrode GE of the transistor TR. The gate electrode GE can overlap with the channel S1 of the semiconductor pattern SM in a planar plane. The gate electrode GE can act as a mask in the process of doping the semiconductor pattern SM. The gate electrode GE can contain heat-resistant molybdenum (Mo), molybdenum-containing alloys, titanium (Ti), titanium-containing alloys, etc., but is not limited to these.

[0139] Figure 6 The structure of the transistor TR shown is merely illustrative; the source S2 or drain S3 of the transistor TR can also be electrodes formed independently from the semiconductor pattern SM. In this case, the source S2 and drain S3 can be in contact with the semiconductor pattern SM, or penetrate the insulating layer and be connected to the semiconductor pattern SM. Furthermore, the gate electrode GE can also be disposed below the semiconductor pattern SM. The transistor TR of one embodiment of the present invention can be formed in various structures and is not limited to any one embodiment.

[0140] Additionally, the second insulating layer 20 and the third to sixth insulating layers 30 (described later) may include at least one inorganic layer and an organic layer. For example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins.

[0141] The third insulating layer 30 can be disposed on the second insulating layer 20 and cover the gate electrode GE. The upper electrode UE can be disposed on the third insulating layer 30. The upper electrode UE can overlap with the gate electrode GE in a plane, and the overlapping gate electrode GE and the upper electrode UE can form a capacitor.

[0142] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the upper electrode UE. Connecting electrodes CN1 and CN2 may include a first connecting electrode CN1 and a second connecting electrode CN2. The first connecting electrode CN1 may be disposed on the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the first connecting electrode CN1. The second connecting electrode CN2 may be disposed on the fifth insulating layer 50. A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover the second connecting electrode CN2. In one embodiment, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may include an organic layer that covers the steps disposed between the lower structural elements and provides a flat upper surface.

[0143] The first connecting electrode CN1 can be electrically connected to the semiconductor pattern SM through contact holes penetrating the second to fourth insulating layers 20-40. The second connecting electrode CN2 can be electrically connected to the first connecting electrode CN1 through contact holes penetrating the fifth insulating layer 50.

[0144] Both the first connecting electrode CN1 and the second connecting electrode CN2 may contain a conductive material. Each of the first connecting electrode CN1 and the second connecting electrode CN2 may contain gold, silver, copper, aluminum, platinum, molybdenum, titanium, or alloys thereof. At least one of the first connecting electrode CN1 and the second connecting electrode CN2 may include a multilayer conductive layer. For example, at least one of the first connecting electrode CN1 and the second connecting electrode CN2 may have a titanium / aluminum / titanium three-layer structure. However, the embodiments are not limited thereto.

[0145] According to an embodiment of the DP-CL circuit element layer, at least one of the first connection electrode CN1 and the second connection electrode CN2 can be omitted. Alternatively, according to an embodiment of the DP-CL circuit element layer, additional connection electrodes for connecting the transistor TR and the light-emitting element OL can also be configured. Depending on the number of insulating layers disposed between the light-emitting element OL and the transistor TR, the electrical connection method between the light-emitting element OL and the transistor TR can be varied and is not limited to a particular embodiment.

[0146] The light-emitting element layer DP-OL may include a light-emitting element OL and a pixel definition film PDL. The light-emitting element OL and the pixel definition film PDL may be disposed on the sixth insulating layer 60. The light-emitting element OL may include: a first electrode AE, a light-emitting layer EM, and a second electrode CE.

[0147] The first electrode AE ​​can be electrically connected to the second connecting electrode CN2 through a contact hole penetrating the sixth insulating layer 60. The first electrode AE ​​can be electrically connected to the transistor TR through the first connecting electrode CN1 and the second connecting electrode CN2.

[0148] The pixel definition film (PDL) may define a pixel opening (PX-OP) that exposes at least a portion of the first electrode (AE). An area of ​​the first electrode (AE) exposed from the PDL may correspond to a light-emitting area. The PDL may include an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the PDL may also include a black pigment or a black dye.

[0149] The light-emitting layer EM can be disposed on the first electrode AE. The light-emitting layer EM can provide light of a specified color. The light-emitting layer EM can be disposed corresponding to the pixel opening PX-OP defined on the pixel definition film PDL. Multiple light-emitting elements OL and pixel openings PX-OP can be provided, and the light-emitting layers EM of the light-emitting elements OL can be disposed corresponding to the pixel openings PX-OP respectively, and provided in a patterned form that is spaced apart from each other. However, it is not limited to this, the light-emitting layers EM of the light-emitting elements OL can also be formed as a single common layer.

[0150] The second electrode CE can be disposed on the light-emitting layer EM and the pixel definition film PDL. The second electrode CE can be provided as a common configuration on the pixel PX (see reference). Figure 4 ) common electrode.

[0151] Additionally, the light-emitting element OL may further include at least one of a hole control region disposed between the first electrode AE ​​and the light-emitting layer EM, and an electron control region disposed between the light-emitting layer EM and the second electrode CE. The hole control region may include at least one of a hole generation layer, a hole transport layer, and an electron blocking layer, and the electron control region may include at least one of an electron generation layer, an electron transport layer, and a hole blocking layer.

[0152] The encapsulation layer ECL can be disposed on the light-emitting element layer DP-OL. The encapsulation layer ECL can be disposed on the light-emitting element OL and the pixel definition film PDL and seal the light-emitting element OL. The encapsulation layer ECL can include at least one of inorganic film and organic film. In this embodiment, the encapsulation layer ECL can include: a first inorganic film EN1, a second inorganic film EN3, and an organic film EN2 disposed between the first inorganic film EN1 and the second inorganic film EN3. However, the structural elements of the encapsulation layer ECL are not limited to this as long as they can seal the light-emitting element OL.

[0153] A first inorganic film EN1 can be disposed on the second electrode CE. An organic film EN2 and a second inorganic film EN3 can be sequentially disposed on the first inorganic film EN1 in the thickness direction of the display panel DP. The first inorganic film EN1 and the second inorganic film EN3 can protect the light-emitting element OL from external moisture or oxygen. For example, each of the first inorganic film EN1 and the second inorganic film EN3 can contain at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. However, the materials of the first inorganic film EN1 and the second inorganic film EN3 are not limited to the examples described. An organic film EN2 can prevent foreign matter from entering the light-emitting element OL and can cover the steps of the structural elements disposed below the organic film EN2. For example, the organic film EN2 can contain acrylic organic compounds. However, the materials of the organic film EN2 are not limited to the examples described.

[0154] The input sensing unit (ISP) can be configured on the display panel (DP). The input sensing unit (ISP) may include a substrate layer IL1, a first sensing insulating layer IL2, a first sensing conductive layer CL1, and a second sensing conductive layer CL2. For example... Figure 3 As shown, the input sensing unit ISP may further include a second sensing insulating layer IL3 (see reference). Figure 3 The above description applies equally to all structural components.

[0155] The substrate layer IL1 can contact the uppermost layer of the encapsulation layer ECL. For example, the substrate layer IL1 can contact the second inorganic film EN3 of the encapsulation layer ECL. The substrate layer IL1 of the input sensing unit ISP can be formed directly on the substrate surface provided by the encapsulation layer ECL. However, it is not limited to this. According to an embodiment, the substrate layer IL1 can be omitted. In this case, the first sensing conductive layer CL1 of the input sensing unit ISP can contact the encapsulation layer ECL.

[0156] A first sensing conductive layer CL1 can be disposed on a substrate layer IL1, and a second sensing conductive layer CL2 can be disposed on a first sensing insulating layer IL2. The first sensing conductive layer CL1 and the second sensing conductive layer CL2 can constitute a sensing electrode TE. The sensing electrode TE can correspond to the aforementioned first sensing electrode TEX and second sensing electrode TEY (see reference). Figure 5 One of the following: For example, the first sensing conductive layer CL1 may include the connection pattern BP of the sensing electrode TE, and the second sensing conductive layer CL2 may include the sensing pattern SP of the sensing electrode TE. However, it is not limited to this; the first sensing conductive layer CL1 may include the sensing pattern SP, and the second sensing conductive layer CL2 may include the connection pattern BP.

[0157] The connection pattern BP can correspond to the first connection pattern BP1 mentioned above (see reference). Figure 5 ) or the second connecting pattern BP2 (refer to) Figure 5 The sensing pattern SP can correspond to the first sensing pattern SP1 mentioned above (refer to...). Figure 5 ) or the second sensing pattern SP2 (refer to) Figure 5 The connection pattern BP can be disposed on different layers from the sensing pattern SP and connected through a contact hole penetrating the first sensing insulating layer IL2. However, it is not limited to this; the connection pattern BP and the sensing pattern SP can also be disposed on the same layer and integrally formed.

[0158] The sensing electrode TE can be a mesh-shaped pattern and can be configured corresponding to an area where a pixel definition film (PDL) is disposed. However, it is not limited to this; the sensing electrode TE can be provided as a single-shaped pattern overlapping the light-emitting element OL, in which case the sensing electrode TE can contain a transparent conductive material.

[0159] Figure 7 This is a perspective view of an electronic device EA according to an embodiment of the present invention. Figure 7 The diagram briefly shows a portion of the structural elements of the electronic device EA, which are configured corresponding to the second base region AA2.

[0160] The second basal region AA2 is equivalent to the non-display region NDA (refer to...). Figure 4 A portion of the area. For example...Figure 7 As shown, the area in the non-display area NDA or the second substrate area AA2 where the driver chip DDV is bonded can be defined as the first pad area PA1, and the area where the flexible circuit board FCB is bonded is defined as the second pad area PA2.

[0161] The driver chip DDV can be bonded to the first pad region PA1 via the first adhesive layer CF1, and the flexible circuit board FCB can be bonded to the second pad region PA2 via the second adhesive layer CF2. Both the first adhesive layer CF1 and the second adhesive layer CF2 can comprise an adhesive synthetic resin. Both the first adhesive layer CF1 and the second adhesive layer CF2 can be non-conductive films (NCF). For example, both the first adhesive layer CF1 and the second adhesive layer CF2 can be adhesive resins that do not contain conductive particles.

[0162] However, this is not the only option. In one embodiment, one of the first adhesive layer CF1 and the second adhesive layer CF2 may be omitted. For example, the driver chip DDV and the flexible circuit board FCB may also be bonded to the first pad region PA1 and the second pad region PA2 using ultrasonic bonding, respectively.

[0163] The display panel (DP) may include multiple pads (PD). These pads (PD) may include a first signal pad (PD1), a second signal pad (PD2), and a display pad (D-PD). The first signal pad (PD1), the second signal pad (PD2), and the display pad (D-PD) may be pads configured on the signal transmission path.

[0164] The first signal pad PD1 can be configured corresponding to the output pad of the driver chip DDV and is an input pad that receives signals from the driver chip DDV. The second signal pad PD2 can be configured corresponding to the input pad of the driver chip DDV and is an output pad that outputs signals to the driver chip DDV. The display pad D-PD can be a panel input pad that receives signals from the flexible circuit board FCB.

[0165] Each of the first signal pads PD1 can be connected to the pixel PX of the display panel DP via signal lines (see reference). Figure 4 Electrical connection, and to pixel PX (reference) Figure 4 The second signal pad PD2 can be electrically connected to the corresponding display pad D-PD in the display pad D-PD through signal wiring. The display pad D-PD and the second signal pad PD2 that are electrically connected to each other can send and receive signals.

[0166] The first pad area PA1 may include a first sub-pad area PA1-1 and a second sub-pad area PA1-2. The first sub-pad area PA1-1 can be defined as the area for configuring the first signal pad PD1. The second sub-pad area PA1-2 can be defined as the area for configuring the second signal pad PD2.

[0167] The first signal pad PD1 can be arranged along the first direction DR1 and the second direction DR2 within the first sub-pad area PA1-1. The first signal pads PD1 arranged along the first direction DR1 can be defined as pad rows. Figure 7 The diagram illustrates, illustratively, the arrangement of five pad rows along the second direction DR2. The arrangement of the first signal pad PD1 is not limited to this.

[0168] The second signal pad PD2 can be arranged along the first direction DR1 within the second sub-pad area PA1-2. The second signal pad PD2 can be configured as a pad row. However, the arrangement of the second signal pad PD2 is not limited to this.

[0169] Figure 8A This is a top view of the pad areas PA1 / PA2 according to an embodiment of the present invention. Figure 8B and Figure 8C These are cross-sectional views of the pad areas PA1 / PA2 according to an embodiment of the present invention. Figure 8D This is a cross-sectional view of an electronic device EA according to an embodiment of the present invention.

[0170] Figure 8A This is a schematic top view of the pad areas PA1 / PA2 according to an embodiment of the present invention. Figure 8B Is with Figure 8A A cross-sectional view of the pad area PA1 / PA2 corresponding to line A-A'. Figure 8C Is with Figure 8A A cross-sectional view of the pad area PA1 / PA2 corresponding to the B-B' line. Figure 8D This is a cross-sectional view showing the bonding structure of the pad regions PA1 / PA2 of an electronic device EA according to an embodiment of the present invention. Figure 8D The example shows the target and Figure 8A The bonding structure of the electronic device EA in the pad area PA1 / PA2 corresponding to the A-A' line. The driver chip DDV may include a circuit board D-IC and bump electrodes BMP.

[0171] Figures 8A to 8D The signal pad PD shown can be a reference. Figure 7 The description includes one of the first signal pad PD1, the second signal pad PD2, and the display pad D-PD. Furthermore, although the data lines DL1 to DLn, including the terminal portion DL-E, are shown (see reference...),...Figure 4 This is one example of a signal line, but it is not limited to this. Signal lines can be data lines DL1 to DLn (see [reference]). Figure 4 Other signal lines besides ).

[0172] The following description uses data lines DL1 to DLn (refer to...) Figure 4 The first sub-pad area PA1-1 (refer to) Figure 7 The pad areas PA1 / PA2 will be described with the following as the center. In the second sub-pad area PA1-2, besides replacing data lines DL1~DLn (refer to...),... Figure 4 Apart from the connection signal lines, the rest can be applied to the first sub-pad area PA1-1 in the same way (refer to...). Figure 7 (Related explanations)

[0173] Reference Figures 8A to 8C The signal pad PD may include: a first conductive pattern CP1, a second conductive pattern CP2, a third conductive pattern CP3, a fourth conductive pattern CP4, and at least one insulating pattern PP. The signal pad PD may also include a first pad insulating layer IL1-P, a second pad insulating layer IL2-P, and a third pad insulating layer IL3-P. For ease of explanation, in... Figure 8A The top view only shows the contact holes OP1-C, OP2-C, and OP3-C defined on the pad insulation layers IL1-P, IL2-P, and IL3-P.

[0174] On a flat surface, the end portion DL-E of the data cable can have a shape extending along the second direction DR2. That is, the length or width of the end portion DL-E in the second direction DR2 can be greater than the length or width in the first direction DR1. The end portion DL-E of the data cable can be disposed in the aforementioned display area DA (refer to...). Figure 6 The transistor TR (reference) Figure 6 ) gate electrode GE (reference) Figure 6 The data cable termination DL-E can be disposed on the second insulating layer 20. The data cable termination DL-E can include components similar to the gate electrode GE (see reference GE). Figure 6 The same material. The end of the data cable, DL-E, can be connected to the gate electrode GE (see reference). Figure 6 The data line is formed in the same process step (e.g., patterning step). The end portion DL-E of the data line can have the same characteristics as the gate electrode GE (see reference). Figure 6 (Same thickness)

[0175] However, the position of the distal DL-E is not limited to this. The distal DL-E can also be combined with... Figure 6The upper electrode UE shown is disposed on the same layer, contains the same material, and has the same stack-up structure. Alternatively, it can be a portion of multiple signal lines connected to the gate electrode GE (see reference). Figure 6 Formed using the same process, another part is connected to the upper electrode UE (refer to...). Figure 6 They are formed through the same process.

[0176] Additionally, data cables DL1~DLn (refer to...) Figure 4 It can be configured on a single layer and have a unified shape, but is not limited to this. A data line DL1~DLn (refer to...) Figure 4 It can include multiple parts configured on different layers.

[0177] The first conductive pattern CP1 can be disposed on the end portion DL-E of the data line. In a planar plane, the first conductive pattern CP1 can overlap with the end portion DL-E of the data line. In a planar plane, the end portion DL-E of the data line can be disposed inside the first conductive pattern CP1, but is not limited thereto.

[0178] The first conductive pattern CP1 can be connected to the data lines DL1 to DLn (see reference) through at least one first contact hole OP1-C defined in the first pad insulating layer IL1-P. Figure 4 The terminal portion DL-E is connected to the first conductive pattern CP1. In this specification, the insulating layer disposed between the terminal portion DL-E and the first conductive pattern CP1 can be defined as the first pad insulating layer IL1-P. In this embodiment, the third insulating layer 30 and the fourth insulating layer 40 can be defined as the first pad insulating layer IL1-P. Furthermore, the stack-up structure of the first pad insulating layer IL1-P can be based on the circuit element layer DP-CL (refer to...). Figure 6 The stacked structure can be altered. In one embodiment, the first contact hole OP1-C can be defined by a greater number of insulating layers than the third insulating layer 30 and the fourth insulating layer 40, or it can be defined by a smaller number of insulating layers. The first conductive pattern CP1 and the end portion DL-E can be separated by a first pad insulating layer IL1-P (e.g., the third insulating layer 30 and the fourth insulating layer 40) disposed between them.

[0179] Figure 8AThe diagram illustratively illustrates a signal pad PD comprising three first contact holes OP1-C and six insulating patterns PP; the number of first contact holes OP1-C and insulating patterns PP is not limited thereto. In a planar plane, the first contact holes OP1-C may overlap with the end portion DL-E. In a planar plane, the first contact holes OP1-C may be defined inside the end portion DL-E. In a planar plane, the first contact holes OP1-C may be defined inside the first conductive pattern CP1. The first contact holes OP1-C may be arranged along a second direction DR2. The first contact holes OP1-C may be spaced apart from each other within the second direction DR2. In a planar plane, a portion of the first conductive pattern CP1 may overlap with the first contact holes OP1-C. A portion of the first conductive pattern CP1 overlapping with the first contact holes OP1-C may contact and be electrically connected to the end portion DL-E.

[0180] The first conductive pattern CP1 can be connected to the aforementioned display area DA (refer to...). Figure 6 The transistor TR (reference) Figure 6 The first connecting electrode CN1 (refer to) Figure 6 The first conductive pattern CP1 can be disposed on the fourth insulating layer 40. The first conductive pattern CP1 can include elements connected to the first connecting electrode CN1 (see reference 40). Figure 6 The same material. The first conductive pattern CP1 can be connected to the first connecting electrode CN1 (refer to...). Figure 6 The first conductive pattern CP1 is formed in the same process step. It can be a single-layer or multi-layer structure and can have an electrode CN1 (see reference 1). Figure 6 The first conductive pattern CP1 may have the same stacked structure as the first connecting electrode CN1 (see reference). Figure 6 The same thickness. The thickness of the first conductive pattern CP1 can be... to For example, the thickness of the first conductive pattern CP1 can be to

[0181] The second conductive pattern CP2 can be disposed on the first conductive pattern CP1. The second conductive pattern CP2 and the first conductive pattern CP1 can be distinguished by a boundary line on their cross-section, which is caused by the formation of the second conductive pattern CP2 and the first conductive pattern CP1 in different process steps. The second conductive pattern CP2 can contact and be electrically connected to the first conductive pattern CP1. In a plane, the second conductive pattern CP2 can overlap with the first conductive pattern CP1. In a plane, the first conductive pattern CP1 can be disposed inside the second conductive pattern CP2. However, this is not a limitation; for example, in a plane, the second conductive pattern CP2 can also be disposed inside the first conductive pattern CP1, or disposed at the same position as each other.

[0182] A portion of the second conductive pattern CP2 may be exposed via at least one second contact hole OP2-C defined in the second pad insulating layer IL2-P. The second conductive pattern CP2 may contact and be electrically connected to the third conductive pattern CP3 through the second contact hole OP2-C. Figure 8A The diagram illustratively shows a signal pad PD comprising three second contact holes OP2-C, but the number of second contact holes OP2-C is not limited thereto. In a plane, the second contact holes OP2-C can be defined inside the second conductive pattern CP2. In a plane, the second contact holes OP2-C can be defined inside the third conductive pattern CP3.

[0183] The second pad insulating layer IL2-P may contain the aforementioned input sensing unit ISP (see reference). Figure 6 The second pad insulating layer IL2-P is made of the same material as the base layer IL1. The second pad insulating layer IL2-P can be formed in the same process step as the base layer IL1. The second pad insulating layer IL2-P may include an inorganic film. For example, the inorganic film may contain at least one of aluminum oxide, titanium oxide, silicon nitride, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0184] The second conductive pattern CP2 can be connected to the aforementioned display area DA (see reference). Figure 6 The first connecting electrode CN1 (refer to) Figure 6 The second connecting electrode CN2 (refer to) Figure 6 The second conductive pattern CP2 may be configured on the same layer as the second connecting electrode CN2 (see reference). Figure 6 The same material. The second conductive pattern CP2 can be connected to the second connecting electrode CN2 (refer to...). Figure 6 The second conductive pattern CP2 is formed in the same process step. It can be a single-layer or multi-layer structure and can have a connection with the second connecting electrode CN2 (see reference). Figure 6 The second conductive pattern CP2 may have the same stacked structure as the second connecting electrode CN2 (see reference).Figure 6 The thickness of the second conductive pattern CP2 can be the same. to For example, the thickness of the second conductive pattern CP2 can be to

[0185] The third conductive pattern CP3 can be disposed on the second conductive pattern CP2. In a plane, the third conductive pattern CP3 can overlap with the second conductive pattern CP2. In a plane, the third conductive pattern CP3 can be disposed inside the second conductive pattern CP2, but is not limited thereto; the second conductive pattern CP2 can be disposed inside the third conductive pattern CP3, and they can also be disposed at the same position.

[0186] The third conductive pattern CP3 can be connected to the second conductive pattern CP2 via at least one second contact hole OP2-C defined in the second pad insulating layer IL2-P. The second contact hole OP2-C can be disposed inside the third conductive pattern CP3. The second contact hole OP2-C can overlap with the first contact hole OP1-C. However, this is not a limitation. For example, the first contact hole OP1-C and the second contact hole OP2-C can also overlap only partially, or not overlap at all.

[0187] The third conductive pattern CP3 may be included in the aforementioned display area DA (see reference). Figure 8D The first sensing conductive layer CL1 is made of the same material. The third conductive pattern CP3 can be formed in the same process step as the first sensing conductive layer CL1. The third conductive pattern CP3 can be a single layer or a multilayer structure, and can have the same stacked structure as the first sensing conductive layer CL1. The third conductive pattern CP3 can have the same thickness as the first sensing conductive layer CL1. The thickness of the third conductive pattern CP3 can be thinner than the thicknesses of both the first conductive pattern CP1 and the second conductive pattern CP2. The thickness of the third conductive pattern CP3 can be... to For example, the thickness of the third conductive pattern CP3 can be to Therefore, as Figure 8A As shown, compared to the case where the lower layer of the insulating pattern PP is thicker, when pressure is applied by the bump electrode (BMP), the bottom surface of the insulating pattern PP deforms less, and the pressure is concentrated on the top surface of the insulating pattern PP.

[0188] The fourth conductive pattern CP4 can be disposed on the third conductive pattern CP3. In a plane, the fourth conductive pattern CP4 can overlap with the third conductive pattern CP3. For ease of explanation, Figure 6The diagram shows the case where the third conductive pattern CP3 and the fourth conductive pattern CP4 are completely overlapped on the plane. However, the third conductive pattern CP3 can be disposed inside the fourth conductive pattern CP4, and the fourth conductive pattern CP4 can also be disposed inside the third conductive pattern CP3.

[0189] The fourth conductive pattern CP4 can be connected to the third conductive pattern CP3 via the third contact hole OP3-C defined in the third pad insulating layer IL3-P. In a planar plane, the third contact hole OP3-C can overlap with the third conductive pattern CP3. In a planar plane, the third contact hole OP3-C can be positioned inside the third conductive pattern CP3. In a planar plane, the third contact hole OP3-C can be positioned inside the fourth conductive pattern CP4. In a planar plane, the third contact hole OP3-C can overlap with the first contact hole OP1-C. In a planar plane, the third contact hole OP3-C can overlap with the second contact hole OP2-C. In a planar plane, the third contact hole OP3-C can overlap with the insulating pattern PP. In a planar plane, the insulating pattern PP can be positioned inside the third contact hole OP3-C.

[0190] The third pad insulating layer IL3-P may contain the aforementioned input sensing unit ISP (see reference). Figure 6 The first sensing insulating layer IL2 is made of the same material. The third pad insulating layer IL3-P can be formed in the same process step as the first sensing insulating layer IL2. The third pad insulating layer IL3-P can include an organic film. For example, the organic film can include at least one of acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0191] The fourth conductive pattern CP4 may be included in the aforementioned display area DA (see reference). Figure 8A The second conductive layer CL2 is made of the same material. The fourth conductive pattern CP4 can be formed in the same process step as the second conductive layer CL2. The fourth conductive pattern CP4 can be a multilayer structure and can have the same stacked structure as the second conductive layer CL2. The fourth conductive pattern CP4 can have the same thickness as the second conductive layer CL2. The thickness of the fourth conductive pattern CP4 can be thinner than the thicknesses of both the first conductive pattern CP1 and the second conductive pattern CP2. The thickness of the fourth conductive pattern CP4 can be... to For example, the thickness of the fourth conductive pattern CP4 can be to

[0192] The fourth conductive pattern CP4 may include: a first layer disposed on the third conductive pattern CP3, a second layer disposed on the first layer, and a third layer disposed on the second layer. The thickness of the second layer may be greater than the thickness of both the first and third layers. The second layer may have higher conductivity than the first and third layers. The first and third layers may contain the same material. The second layer may contain a different material than the first and third layers. For example, the first and third layers may contain titanium (Ti), and the second layer may contain aluminum (Al).

[0193] An insulating pattern PP can be positioned between a third conductive pattern CP3 and a fourth conductive pattern CP4. The lower surface of the insulating pattern PP can contact the third conductive pattern CP3, and the sides and upper surface of the insulating pattern PP can each be covered by the fourth conductive pattern CP4. The insulating pattern PP can form protrusions in the pad areas PA1 / PA2.

[0194] On a plane, the insulating pattern PP can overlap with both the third conductive pattern CP3 and the fourth conductive pattern CP4. On a plane, the insulating pattern PP can be spaced apart from the first contact hole OP1-C. In this embodiment, the insulating pattern PP can be arranged along the second direction DR2. The insulating patterns PP can be spaced apart from each other within the second direction DR2. On a plane, the insulating pattern PP can be disposed inside the third contact hole OP3-C and spaced apart from the third pad insulating layer IL3-P. The space between the insulating pattern PP and the third pad insulating layer IL3-P can be filled by the fourth conductive pattern CP4. The fourth conductive pattern CP4 disposed between the insulating pattern PP and the third pad insulating layer IL3-P can contact and be electrically connected to the third conductive pattern CP3.

[0195] The insulating pattern PP can be configured between adjacent first contact holes OP1-C. Figure 8A The illustration shows a case where three insulating patterns PP are arranged between each two adjacent first contact holes in the three first contact holes OP1-C, but the arrangement is not limited to this.

[0196] Figure 6 The illustration shows an example of an insulating pattern PP that is rectangular on a plane, but it is not limited to this. The shape of the insulating pattern PP on the plane can be changed to a polygon other than a rectangle, a circle, an ellipse, etc. Furthermore, the shapes of the insulating patterns PP are not limited to being the same as each other.

[0197] The insulating pattern PP can have a trapezoidal shape in cross-section. The insulating pattern PP can have inclined sides, and the inclination formed by the side with respect to the bottom surface can be an acute angle. However, it is not limited to this; the insulating pattern PP can also have a rectangular shape or an inverted trapezoidal shape in cross-section.

[0198] Insulating patterned PP can contain polymers. Insulating patterned PP can contain thermosetting polymers. However, it is not limited to this; insulating patterned PP can also contain thermoplastic polymers.

[0199] In one embodiment, the insulating pattern PP can be connected to the first sensing insulating layer IL2 of the input sensing unit ISP (refer to...). Figure 8D It is formed through the same process. Therefore, the additional process for forming the insulating pattern PP is not required.

[0200] Reference Figure 6 In one embodiment of the present invention, the signal pad PD can be configured with respect to the input sensing unit ISP (see reference 1). Figures 9A to 10C The first sensing conductive layer CL1 and the second sensing conductive layer CL2 are patterned between the third conductive pattern CP3 and the fourth conductive pattern CP4 in the same process step. Therefore, compared to the case where the insulating pattern PP is disposed between the first conductive pattern CP1 and the second conductive pattern CP2, the contact area between the signal pad PD and the bump electrode BMP is smaller, thus increasing the pressure per unit area of ​​the contact surface and improving bonding reliability in low-pressure processes. Specifically, the upper layer (e.g., the third layer) of the fourth conductive pattern CP4 of the signal pad PD in contact with the bump electrode BMP is stretched under pressure and forms a groove, exposing the highly conductive second layer (e.g., an aluminum layer), which can then contact and electrically connect with the bump electrode BMP. Furthermore, when the insulating pattern PP is disposed between the second conductive pattern CP2 and the third conductive pattern CP3, the second conductive pattern CP2, disposed at the lower part of the insulating pattern PP, is pressed downwards and deformed under pressure, thereby reducing the pressure applied to the signal pad PD in contact with the bump electrode BMP. The third conductive pattern CP3 is disposed on the second pad insulating layer IL2-P, which includes an inorganic film and supports the third conductive pattern CP3. The third conductive pattern CP3 can be formed to be thinner than both the first conductive pattern CP1 and the second conductive pattern CP2, thereby minimizing the deformation of the third conductive pattern CP3 due to pressure. In the case of the signal pad PD in one embodiment of the present invention, the deformation of the third conductive pattern CP3 disposed under the insulating pattern PP can be minimized, and the pressure is concentrated on the contact surface of the signal pad PD that contacts the bump electrode BMP, thereby improving the bonding reliability in low-pressure processes.

[0201] Figures 9A to 10C These are top views of the pad areas PA1 / PA2 according to an embodiment of the present invention. Figures 8A to 8D The same reference can be applied in the same way. Figure 9A The content of the explanation.

[0202] Figure 9B and Figure 8A This is an illustrative example showing the differences between... Figure 9A The diagram shows embodiments with different numbers, arrangements, or sizes of the second contact holes OP2-C. The number and arrangement of the insulating pattern PP can be varied depending on the arrangement of the second contact holes OP2-C.

[0203] Reference Figure 9B In a planar plane, the second contact hole OP2-C defined in the second pad insulating layer IL2-P may not overlap with the first contact hole OP1-C defined in the first pad insulating layer IL1-P. Furthermore, in a planar plane, the second contact hole OP2-C may not overlap with the insulating pattern PP. For example, in a planar plane, the second contact hole OP2-C may be positioned between two adjacent insulating patterns PP. The number of second contact holes OP2-C defined in a signal pad PD may differ from the number of first contact holes OP1-C. For example, in a signal pad PD, two second contact holes OP2-C may be defined.

[0204] Reference Figures 10A to 10C On a plane, the second contact hole OP2-C defined in the second pad insulating layer IL2-P may partially overlap with and partially not overlap with the first contact hole OP1-C defined in the first pad insulating layer IL1-P. Furthermore, on a plane, the second contact hole OP2-C may not overlap with the insulating pattern PP. One second contact hole OP2-C may be defined in a single signal pad PD.

[0205] Figure 8A This is an illustrative example showing the differences between... Figure 10A Figures showing embodiments with different numbers, arrangements, or planar shapes of insulating patterns PP during comparison.

[0206] Reference Figure 10C and Figure 10B The number of insulating patterns (PPs) can be four. On a plane, the spacing between the insulating patterns (PPs) can be different from each other. (See reference...) Figures 10A to 10C On a plane, the shape of the insulating pattern PP can be a rectangle whose length in the second direction DR2 is longer than the length in the first direction DR1. ​ In this process, the insulating pattern PP may not overlap with the first contact hole OP1-C and the second contact hole OP2-C.

[0207] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or of ordinary skill in the art that various modifications and alterations can be made to the invention without departing from the spirit and scope of the invention as set forth in the appended claims. Therefore, the scope of the invention should not be limited to the specific embodiments described in the specification, but should be defined by the appended claims.

Claims

1. A display panel, wherein, It includes a display area and a non-display area. The display area includes pixels, and the non-display area includes pad areas and is adjacent to the display area. Signal pads connected to the pixel via signal lines are configured in the pad area. The signal pads include: A first pad insulating layer is disposed on the end portion of the signal line and a first contact hole is defined to expose a portion of the end portion of the signal line. A first conductive pattern is disposed on the insulating layer of the first pad and connected to the end portion of the signal line through the first contact hole; The second conductive pattern is disposed on the first conductive pattern; A second pad insulating layer is disposed on the second conductive pattern and a second contact hole is defined to expose a portion of the second conductive pattern; The third conductive pattern is disposed on the second pad insulating layer and connected to the second conductive pattern through the second contact hole; A third pad insulating layer is disposed on the third conductive pattern and a third contact hole is defined to expose a portion of the third conductive pattern; A fourth conductive pattern is disposed on the insulating layer of the third pad and connected to the third conductive pattern through the third contact hole; and At least one insulating pattern is disposed between the third conductive pattern and the fourth conductive pattern.

2. The display panel according to claim 1, wherein, The display area includes a substrate layer, a circuit element layer, and a light-emitting element layer. The circuit element layer is disposed on the substrate layer, and the light-emitting element layer includes light-emitting elements and is disposed on the circuit element layer. The circuit element layer includes: transistor; A first connection electrode is connected to the transistor; and The second connecting electrode is connected to both the first connecting electrode and the light-emitting element. The first conductive pattern is disposed on the same layer as the first connecting electrode. The second conductive pattern is disposed on the same layer as the second connecting electrode.

3. The display panel according to claim 2, wherein, The transistor includes a semiconductor pattern and a gate electrode. The semiconductor pattern includes a channel, a source, and a drain. The gate electrode and the semiconductor pattern are disposed on different layers. The first connection electrode is connected to the source electrode or the drain electrode.

4. The display panel according to claim 1, wherein, The insulating pattern comprises polymers.

5. The display panel according to claim 1, wherein, On the plane, the insulating pattern is disposed inside the third contact hole. On a flat surface, the insulating pattern is spaced apart from the first contact hole.

6. The display panel according to claim 1, wherein, The fourth conductive pattern includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, wherein the first layer and the third layer respectively comprise titanium, and the second layer comprises aluminum.

7. The display panel according to claim 1, wherein, The non-display area includes a first area adjacent to the display area, a second area spaced apart from the first area, and a curved area disposed between the first area and the second area. The second region includes the pad region.

8. A display module, in, include: A display panel includes a display area and a non-display area. The display area includes pixels, and the non-display area includes a pad area and is adjacent to the display area. Signal pads connected to the pixels via signal lines are disposed in the pad area. The input sensing unit includes a first sensing conductive layer disposed on the display panel, a first sensing insulating layer disposed on the first sensing conductive layer, and a second sensing conductive layer disposed on the first sensing insulating layer. The signal pads include: A first conductive pattern is connected to the end of the signal line; The second conductive pattern is disposed on the first conductive pattern; A third conductive pattern is disposed on the second conductive pattern; A fourth conductive pattern is disposed on the third conductive pattern; and At least one insulating pattern is disposed between the third conductive pattern and the fourth conductive pattern. The third conductive pattern and the first sensing conductive layer contain the same material. The fourth conductive pattern and the second sensing conductive layer contain the same material.

9. The display module according to claim 8, wherein, The thickness of the third conductive pattern is the same as the thickness of the first sensing conductive layer. The thickness of the fourth conductive pattern is the same as the thickness of the second sensing conductive layer.

10. The display module according to claim 8, wherein, At least one of the first sensing conductive layer and the second sensing conductive layer includes a mesh opening.

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