Display module and electronic device including the same

Abstract

The invention relates to a display module and an electronic device. The display module may include a display panel, the display panel may include a display area and a non-display area disposed adjacent to the display area, in which a pad area is disposed in the non-display area, the display panel may include pixels disposed in a display area and signal pads connected to the pixels through signal lines and disposed in a pad area, the signal pad may include a first conductive pattern connected to a portion of the signal line, a second conductive pattern disposed on the first conductive pattern, a third conductive pattern disposed on the second conductive pattern, and an insulating pattern disposed between the second conductive pattern and the third conductive pattern, an opening may be provided in at least one of the first conductive pattern and the second conductive pattern, and the opening may overlap with the insulating pattern.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display module including a pad area and an electronic device. BACKGROUND

[0002] A multimedia electronic device such as a television, a mobile phone, a tablet computer, a navigation system, and a game console can include a display module configured to display an image and sense an external input.

[0003] The display module can be bonded and electrically connected to a driver chip that provides an electrical signal required to display an image. SUMMARY

[0004] The disclosure provides a display module and an electronic device that exhibit excellent bonding reliability.

[0005] An embodiment of the disclosure provides a display module including a display panel including a display area and a non-display area disposed adjacent to the display area, wherein a pad area is disposed in the non-display area, the display panel can include a pixel disposed in the display area and a signal pad connected to the pixel through a signal line and disposed in the pad area, the signal pad can include a first conductive pattern connected to a portion of the signal line, a second conductive pattern disposed on the first conductive pattern, a third conductive pattern disposed on the second conductive pattern, and an insulating pattern disposed between the second conductive pattern and the third conductive pattern, an opening can be disposed in at least one of the first conductive pattern and the second conductive pattern, and the opening can overlap the insulating pattern.

[0006] In an embodiment, the insulating pattern can include a central portion overlapping the opening, the insulating pattern can further include a side portion that can not overlap the opening, and the central portion can protrude further from at least one of the first conductive pattern and the second conductive pattern toward the third conductive pattern than the side portion.

[0007] In an embodiment, the side portion of the insulating pattern can overlap each of the first conductive pattern and the second conductive pattern.

[0008] In an embodiment, the insulating pattern can have a larger area than the opening in a plan view.

[0009] In an embodiment, the opening is disposed in the second conductive pattern, the insulating pattern can fill the opening, and the insulating pattern can be disposed directly on the first conductive pattern.

[0010] In an embodiment, the opening can include a first opening and a second opening, the first opening can be disposed in the first conductive pattern, the first opening can overlap the insulating pattern, and the second opening can be disposed in the second conductive pattern.

[0011] In an embodiment, the signal pad can further include a reinforcement pattern having a greater hardness than the insulating pattern, and the reinforcement pattern can overlap the opening in a plan view.

[0012] In an embodiment, the reinforcement pattern can include a metal.

[0013] In an embodiment, the reinforcement pattern can include molybdenum (Mo).

[0014] In an embodiment, the opening can be disposed in the second conductive pattern, the reinforcement pattern can be disposed directly under the first conductive pattern, and the insulating pattern can be disposed directly on the first conductive pattern.

[0015] In an embodiment, the second conductive pattern can have an opening defined therein, the reinforcement pattern can be disposed in the opening defined in the second conductive pattern, and the insulating pattern can be disposed directly on the reinforcement pattern.

[0016] In an embodiment, the opening can include a first opening and a second opening, the first opening can be disposed in the first conductive pattern, the second opening can be disposed in the second conductive pattern, the insulating pattern can overlap the first opening and the second opening, the reinforcement pattern can be disposed in the first opening, and the insulating pattern can be disposed directly on the reinforcement pattern.

[0017] In an embodiment, the opening can be disposed in the first conductive pattern, the reinforcement pattern can be disposed in the opening, and the insulating pattern can be disposed directly on the second conductive pattern.

[0018] In an embodiment, the display panel can include a base layer, a circuit element layer disposed on the base layer, and a light emitting element layer disposed on the circuit element layer in a display area, the light emitting element layer can include a light emitting element, the circuit element layer can include a transistor including a semiconductor pattern and a gate electrode, the semiconductor pattern including a channel, a source, and a drain, the semiconductor pattern and the gate electrode can be disposed at different layers from each other, a first connection electrode connected to the transistor, and a second connection electrode connected to the light emitting element, the first conductive pattern can be formed from the same layer as the first connection electrode, and the second conductive pattern can be formed from the same layer as the second connection electrode.

[0019] In an embodiment, the circuit element layer can further include an upper electrode overlapping the gate electrode in a plan view, a capacitor including the upper electrode and the gate electrode, the signal pad can further include a reinforcement pattern having a greater hardness than the insulating pattern, the reinforcement pattern can overlap the opening in a plan view, and the reinforcement pattern and the upper electrode can be formed from the same layer.

[0020] In an embodiment, the display module can further include an input sensing unit disposed on the display panel, wherein the input sensing unit can include a first sensing conductive layer, a first sensing insulating layer disposed on the first sensing conductive layer, and a second sensing conductive layer disposed on the first sensing insulating layer, and the third conductive pattern of the signal pad and at least one of the first sensing conductive layer and the second sensing conductive layer of the input sensing unit can be formed of the same layer.

[0021] In an embodiment, the insulating pattern can include a polymer.

[0022] In an embodiment, the first conductive pattern, the second conductive pattern, and the third conductive pattern can each include a first layer, a second layer, and a third layer, and the first layer and the third layer can have a smaller electrical conductivity than the second layer.

[0023] In an embodiment, the first layer and the third layer can each include titanium (Ti), and the second layer can include aluminum (Al).

[0024] In an embodiment of the present inventive concept, an electronic device can include a display module, the display module can include a display panel including a display area and a non-display area disposed adjacent to the display area, a pad area is disposed in the non-display area, the display panel can include a pixel disposed in the display area and a signal pad connected to the pixel through a signal line and disposed in the pad area, and an input sensing unit can be disposed on the display panel, the electronic device can include an electronic component including a bump electrode disposed in the pad area and an adhesive layer bonding the display panel and the electronic component, wherein the input sensing unit can include a first sensing conductive layer disposed on the display panel, a first sensing insulating layer disposed on the first sensing conductive layer, and a second sensing conductive layer disposed on the first sensing insulating layer, the signal pad can include a first conductive pattern connected to a portion of the signal line, a second conductive pattern disposed on the first conductive pattern, a third conductive pattern disposed on the second conductive pattern, and an insulating pattern disposed between the second conductive pattern and the third conductive pattern, wherein an opening can be disposed in at least one of the first conductive pattern and the second conductive pattern, the opening can overlap the insulating pattern, the insulating pattern can include a central portion overlapping the opening and a side portion which can not overlap the opening, and the central portion can protrude further from at least one of the first conductive pattern and the second conductive pattern toward the third conductive pattern than the side portion. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of the specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain principles of the present disclosure. In the drawings: Figure 1 is a combined schematic perspective view of an electronic device according to an embodiment of the present disclosure; Figure 2 is an exploded schematic perspective view of an electronic device according to an embodiment of the present disclosure; Figure 3 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure; Figure 4 is a schematic plan view of a display panel according to an embodiment of the present disclosure; Figure 5 is a schematic plan view of an input sensing unit according to an embodiment of the present disclosure; Figure 6 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure; Figure 7 is a schematic perspective view of an electronic device according to an embodiment of the present disclosure; Figure 8A is a schematic plan view of a pad area according to an embodiment of the present disclosure; Figure 8B is a schematic cross-sectional view of a pad area according to an embodiment of the present disclosure; Figures 9A to 9E Each is a schematic cross-sectional view of a pad area according to an embodiment of the present disclosure; and Figure 10A and Figure 10B Each is a schematic cross-sectional view of a pad area according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, the terms “embodiment” and “implementation” are interchangeable, and are non-limiting examples of apparatuses or methods disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the various embodiments.

[0027] Unless otherwise indicated, the embodiments shown are understood to provide features of the present disclosure. Thus, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter referred to as “elements”) can be combined, separated, interchanged, and / or rearranged, unless otherwise indicated, without departing from the present disclosure.

[0028] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. As such, the absence of cross-hatching or shading does not mean that a particular material, material property, dimension, ratio, commonality between elements, and / or any other characteristic, attribute, property, etc. is either preferred or required, unless specifically stated otherwise. Moreover, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When embodiments can be practiced differently, a particular sequence of processes can be performed other than as described. For example, two consecutively described processes can be executed substantially concurrently, or in the reverse order that is described. Also, the same reference numbers and / or reference designations can represent the same elements or features throughout the drawings.

[0029] When an element such as a layer, is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present. In this regard, the term "connected" can refer to physical or electrical and / or fluid connection with or without intervening elements. In addition, the X-axis, Y-axis and Z-axis can not be limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can be different directions that are not perpendicular to each other.

[0030] For the purposes of the present disclosure, "at least one of A and B" can be interpreted to be only A, only B, or any combination of A and B. Also, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to be only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0032] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper", "on", "over", "side" (e.g., as in "sidewall"), and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "having", "has", "united", "unites", "containing", "contains" or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising". Additionally, as used herein, the term "exemplary" is intended to mean "an example of." Also, as used herein, the term "about" is intended to mean approximately or nearly, for example, the term "about 5% is intended to mean approximately or nearly 5%. Also, as used herein, the term "substantially" is intended to mean largely or nearly, for example, the term "substantially enclosed" is intended to mean largely or nearly enclosed. Further, as used herein, the term "generally" is intended to mean roughly, approximately, around, or nearly, for example, the term "generally cylindrical" is intended to mean roughly cylindrical.

[0034] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations of schematic views of implementations and / or intermediate structures. It will be understood that modifications and / or additions are intended to be included within the scope of the various embodiments. The sections can be joined together to provide a total device, and each of the sections can be explicitly or implicitly shown by one or more of the drawings. Thus, for example, a section can be provided to show a single feature when the component or feature is used in multiple sections. Furthermore, structure formed by these components can be structural features that are not explicitly shown or described in the drawings. Thus, references to a particular feature or structure can include explicit showing of the structure and / or implicit showing of the structure based on the names and description given to the structure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein for the purpose of describing particular embodiments is not intended to be limiting of the disclosure. As used herein, the singular articles "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "including", and / or "having" as used herein, are specifically intended to be construed as open-ended terms (i.e., the terms do not allow for exclusion of any additional

[0035] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, portions, and / or modules. Those skilled in the art will understand that these blocks, portions, and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, portions, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, portion, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmable microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of this disclosure, each block, portion, and / or module in some embodiments may be physically separated into two or more interactive and discrete blocks, portions, and / or modules. Furthermore, without departing from the scope of this disclosure, blocks, portions and / or modules in some embodiments may be physically combined into more complex blocks, portions and / or modules.

[0036] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0037] Figure 1 This is a schematic perspective view of an electronic device EA according to an embodiment of the present disclosure. Figure 2 This is an exploded schematic perspective view of an electronic device EA according to an embodiment of the present disclosure.

[0038] refer to Figure 1 and Figure 2 An electronic device EA can be a device that is activated in response to an electrical signal, displays an image IM, and senses external input TC. For example, an electronic device EA may include devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. However, embodiments of the electronic device EA are presented as examples and are therefore not limited to any particular device without departing from this disclosure. In this embodiment, a mobile phone is shown as an example of an electronic device EA.

[0039] The electronic device EA can have a rectangular shape in a plan view, the rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. However, embodiments of the present disclosure are not limited thereto, and the electronic device EA can have various shapes such as a circular shape and a polygonal shape.

[0040] In an embodiment, the third direction DR3 can be a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. A front surface (or an upper surface) and a rear surface (or a lower surface) of each member constituting the electronic device EA can face each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3. A distance between the front surface and the rear surface defined in the third direction DR3 can correspond to a thickness of the member.

[0041] Here, "in a plan view" can be defined as a state observed in the third direction DR3 (or "in a plan view"). Here, "in a cross section" can be defined as a state observed in the first direction DR1 or the second direction DR2. Directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts, and thus can be changed to other directions.

[0042] The electronic device EA can be rigid or flexible. The term "flexible" indicates a bendable property, and can include all forms from a structure that can be completely folded to a structure that can be bent up to several nanometers. For example, the flexible electronic device EA can include a curved electronic device, a rollable electronic device, or a foldable electronic device.

[0043] The electronic device EA can display an image IM through a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM can include a still image as well as a dynamic image. Figure 1 A clock and an icon are illustrated as examples of the image IM.

[0044] For example, the display surface FS of the electronic device EA can include only a plane, or can further include a curved surface bent from at least one side of the plane. The display surface FS can correspond to a front surface of the electronic device EA, and can further correspond to a front surface of the window WM. Hereinafter, the same reference numeral will be given to the display surface FS of the electronic device EA and the front surface of the window WM.

[0045] The electronic device EA according to an embodiment can sense an external input TC applied from the outside. The external input TC can include various forms of input such as force, pressure, temperature, or light. In an embodiment, a user's hand applied to the front surface is shown as the external input TC. However, this is presented as an example, and the external input TC can include an input applied in proximity to the electronic device EA, such as hovering or contact of a pen.

[0046] The electronic device EA can sense a user input through a display surface FS defined in the front surface, and respond to the sensed input signal. However, the area of the electronic device EA for sensing the external input TC is not limited to the front surface of the electronic device EA, and can vary according to the design of the electronic device EA. For example, the electronic device EA can sense an input of a user applied to a side surface or a rear surface.

[0047] The electronic device EA can include a window WM, a display module DM, an electronic module ELM, a power supply module PSM, and a housing HAU. The window WM and the housing HAU can be joined to form the exterior of the electronic device EA.

[0048] The window WM can be disposed on the display module DM. The window WM can cover (or overlap) the front surface IS of the display module DM, and can protect the display module DM from external impact and scratches. The window WM can be joined to the display module DM through an adhesive layer.

[0049] The window WM can include an optically transparent insulating material. For example, the window WM can include glass or synthetic resin as a base film. The window WM can have a single layer structure or a multi-layer structure. For example, the window WM having a multi-layer structure can include synthetic resin joined through an adhesive, or include a glass film and a synthetic resin film joined through an adhesive. The window WM can further include a functional layer such as an anti-fingerprint layer, a phase control layer, or a hard coat layer disposed on the optically transparent base film.

[0050] The front surface of the window WM can correspond to the front surface FS of the electronic device EA. The front surface of the window WM can include a transmission area TA and a bezel area BZA.

[0051] The transmission area TA can be an optically transparent area. The transmission area TA can transmit an image IM provided from the display module DM. In an embodiment, the transmission area TA is shown to have a rectangular shape, but is not limited thereto, and the transmission area TA can have various shapes.

[0052] The bezel area BZA can be an area having a lower light transmittance than the transmissive area TA. The bezel area BZA can correspond to an area in which a material having a color is printed. The bezel area BZA can prevent the transmission of light, thereby preventing components of the display module DM disposed to overlap the bezel area BZA from being observed from the outside.

[0053] The bezel area BZA can be positioned adjacent to the transmissive area TA. The shape of the transmissive area TA can be substantially defined by the bezel area BZA. For example, the bezel area BZA can be disposed outside the transmissive area TA to surround the transmissive area TA. However, this is presented by way of example, and the bezel area BZA can be positioned adjacent to only one side of the transmissive area TA, or can not be disposed on the front surface FS of the electronic device EA but on a side surface of the electronic device EA. The bezel area BZA can not be disposed.

[0054] The display module DM can be disposed between the window WM and the housing HAU. The display module DM can display an image IM and sense an external input TC. The image IM can be displayed on a front surface IS of the display module DM. The front surface IS of the display module DM can include an active area AA and a non-active area NAA.

[0055] The active area AA can be an area activated in response to an electrical signal. For example, the active area AA can be an area in which an image IM is displayed and also senses an external input TC. The active area AA can overlap at least a portion of the transmissive area TA. Accordingly, a user can view the image IM or provide the external input TC through the transmissive area TA. However, this is presented by way of example, and in the active area AA, an area in which the image IM is displayed and an area in which the external input TC is sensed can be separated, and are not limited to embodiments.

[0056] The non-active area NAA can be positioned adjacent to the active area AA. For example, the non-active area NAA can surround the active area AA. A driving circuit, a driving line, etc. for driving the active area AA can be disposed in the non-active area NAA. The non-active area NAA can overlap at least a portion of the bezel area BZA, and can prevent components disposed in the non-active area NAA from being observed from the outside through the bezel area BZA.

[0057] The display module DM can include a display panel and an input sensing unit. The display panel can display an image IM, and the input sensing unit can sense an external input TC. Detailed descriptions thereof will be given later.

[0058] A portion of the display module DM can be bent about a bending axis extending in the first direction DR1. For example, the portion of the display module DM can be bent toward a rear surface of the display module DM corresponding to the active area AA. The flexible circuit board FCB can be connected to the bent portion of the display module DM, and thus, the flexible circuit board FCB can overlap the display module DM in a plan view.

[0059] The flexible circuit board FCB can be electrically connected to the display module DM on one side (e.g., a single side) of the display module DM. The flexible circuit board FCB can generate an electrical signal provided to the display module DM, or receive a signal generated from the display module DM, and calculate a result value including information about a position or intensity at which an external input TC is sensed.

[0060] The electronic module ELM and the power supply module PSM can be disposed under the display module DM. The electronic module ELM and the power supply module PSM can be electrically connected through separate circuit boards.

[0061] The power supply module PSM can supply power required for the operation of the electronic device EA. For example, the power supply module PSM can include a typical battery module.

[0062] The electronic module ELM can include various functional modules that enable the operation of the electronic device EA. For example, the electronic module ELM can include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, an optical module, and an external interface module. The electronic module ELM can include a main circuit board, and the modules of the electronic module ELM can be mounted on the main circuit board or electrically connected to the main circuit board through separate circuit boards.

[0063] In the electronic module ELM, the control module can control the overall operation of the electronic device EA. For example, the control module can activate or deactivate the display module DM according to a user input. The control module can include at least one microprocessor. In the electronic module ELM, the optical module can include a camera module, a proximity sensor, a biometric sensor for recognizing a part of a user's body (e.g., a fingerprint, an iris, or a face), or a light emitting lamp.

[0064] The housing HAU in combination with the window WM can provide an internal space that accommodates the display module DM, the electronic module ELM, the power supply module PSM, and the flexible circuit board FCB. The housing HAU can include a material having great rigidity. For example, the housing HAU can include a plurality of frames and / or plates including or formed of glass, plastic, or metal, or a combination thereof. The housing HAU can absorb an impact applied from the outside, or prevent foreign matter / moisture from penetrating from the outside, to protect the components of the electronic device EA accommodated in the housing HAU.

[0065] Figure 3 is a schematic cross-sectional view of a display module DM according to an embodiment of the disclosure.

[0066] Referring to Figure 3 , the display module DM can include a display panel DP and an input sensing unit ISP. The input sensing unit ISP can be disposed on the display panel DP. For example, the input sensing unit ISP can be disposed (e.g., directly disposed) on the display panel DP. In an embodiment, the phrase "the input sensing unit ISP is disposed (e.g., directly disposed) on the display panel DP" means that the input sensing unit ISP is formed on the display panel DP through a continuous process, and thus the input sensing unit ISP and the display panel DP are combined without a separate adhesive layer. For example, components of the input sensing unit ISP can be formed on a base surface provided by the display panel DP.

[0067] The display panel DP can display an image in response to an electrical signal. The display panel DP according to an embodiment can be a light-emitting display panel, and is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. An emission layer of the organic light-emitting display panel can include an organic light-emitting material, an emission layer of the inorganic light-emitting display panel can include an inorganic light-emitting material. An emission layer of the quantum dot light-emitting display panel can include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0068] The display panel DP can include a base substrate BS, a circuit element layer DP-CL, a light-emitting element layer DP-OL, and an encapsulation layer ECL, which are sequentially stacked with each other in a third direction DR3.

[0069] The base substrate BS can be a rigid substrate, or a flexible substrate that is bendable, foldable, rollable, or the like. For example, the base substrate BS can be a glass substrate, a metal substrate, or a polymer substrate. The base substrate BS can provide a base surface on which the circuit element layer DP-CL is disposed.

[0070] The base substrate BS can include an inorganic layer, an organic layer, or a composite material layer. The base substrate BS can have a single layer structure or a multi-layer structure. For example, the base substrate BS having a multi-layer structure can include synthetic resin layers and a multi-layer or single-layer inorganic layer disposed between the synthetic resin layers. The synthetic resin layer can include an acryl-based resin, a methacrylate-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, or a perylene-based resin, but the material of the synthetic resin layer is not limited thereto.

[0071] The circuit element layer DP-CL can be disposed on the base substrate BS. The circuit element layer DP-CL can include at least one insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer, the semiconductor pattern, and the conductive pattern included in the circuit element layer DP-CL can form driving elements such as transistors, signal lines, and pads.

[0072] The light emitting element layer DP-OL can be disposed on the circuit element layer DP-CL. The light emitting element layer DP-OL can include light emitting elements each emitting light. For example, the light emitting elements can be organic light emitting elements, inorganic light emitting elements, micro-LEDs, or nano-LEDs. The light emitting elements of the light emitting element layer DP-OL can be electrically connected to the driving elements of the circuit element layer DP-CL, and thus can emit light in response to an electrical signal provided by the driving elements.

[0073] The encapsulation layer ECL can be disposed on the light emitting element layer DP-OL to seal the light emitting elements. The encapsulation layer ECL can include at least one thin film for improving optical efficiency of the light emitting element layer DP-OL or protecting the light emitting element layer DP-OL. For example, the encapsulation layer ECL can include at least one of an inorganic film and an organic film. The inorganic film of the encapsulation layer ECL can protect the light emitting elements from moisture / oxygen. The organic film of the encapsulation layer ECL can protect the light emitting elements from foreign substances such as dust particles.

[0074] The input sensing unit ISP can sense an external input and provide an input signal including information about the external input, and thus the display panel DP can display an image corresponding to the external input. The input sensing unit ISP can be driven in various ways such as a capacitive method, a resistive method, an infrared method, a sound wave method, or a pressure method, and the driving method of the input sensing unit ISP is not limited to any one as long as it can sense an external input. In an embodiment, the input sensing unit ISP is described as an input sensing panel driven in a capacitive method.

[0075] The input sensing unit ISP can include a base layer IL1, a first sensing conductive layer CL1, a first sensing insulating layer IL2, a second sensing conductive layer CL2, and a second sensing insulating layer IL3, which are sequentially stacked with each other in the third direction DR3. The base layer IL1 of the input sensing unit ISP can be in contact with the encapsulation layer ECL. However, embodiments of the present disclosure are not limited thereto, and at least one of the base layer IL1 and the second sensing insulating layer IL3 can not be disposed.

[0076] The first and second sensing conductive layers CL1 and CL2 can each have a single layer structure or a multi-layer structure. The conductive layer having a multi-layer structure can include two or more layers of a transparent conductive layer and a metal layer. The conductive layer having a multi-layer structure can include metal layers having different metals. The transparent conductive layer can include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowire, and graphene. The metal layer can include at least one of molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. For example, the first and second sensing conductive layers CL1 and CL2 can each have a two-layer structure (e.g., a two-layer structure of ITO / copper) or a three-layer structure of titanium / aluminum / titanium, without limitation.

[0077] The first and second sensing conductive layers CL1 and CL2 can each include a sensing conductive pattern. The sensing conductive patterns of the first and second sensing conductive layers CL1 and CL2 can form a sensing electrode constituting the input sensing unit ISP and a sensing line connected to the sensing electrode.

[0078] The base layer IL1, the first and second sensing insulating layers IL2 and IL3 can each include at least one of an inorganic film and an organic film. For example, the inorganic film can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide, and the organic film can include at least one of an acryl-based resin, a methacrylic acid-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin. However, the materials of the inorganic film and the organic film are not limited to the above examples. In an embodiment, the base layer IL1 can include an inorganic film, and the first and second sensing insulating layers IL2 and IL3 can include an organic film, but embodiments of the disclosure are not limited thereto.

[0079] Figure 4 is a schematic plan view of a display panel DP according to an embodiment of the disclosure.

[0080] Referring to Figure 4 , the display panel DP can include a base substrate BS, pixels PX, signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL electrically connected to the pixels PX, a scan driver SDV, an emission driver EDV, a data driver DDV, and a display pad D-PD.

[0081] The base substrate BS can provide a base substrate surface on which electrical elements and lines of the display panel DP are disposed. The base substrate BS can include a first base area AA1, a bending area BA, and a second base area AA2 separated in the second direction DR2. The bending area BA can extend from the first base area AA1 in the second direction DR2. The second base area AA2 can extend from the bending area BA in the second direction DR2. Thus, the first base area AA1 and the second base area AA2 can be spaced apart from each other, and the bending area BA is between the first base area AA1 and the second base area AA2.

[0082] The first base area AA1 can include a display area DA. The display area DA can be an area in which light emitting elements of the pixels PX are disposed. Thus, the display area DA can display an image through the pixels PX. The display area DA can correspond to an active area AA (see Figure 2 ) of the display module DM (see Figure 2 ), and can overlap a transmissive area TA (see Figure 2 ) of the window WM (see Figure 2 ).

[0083] The first base area AA1, the bending area BA, and the second base area AA2 other than the display area DA can be defined as a non-display area NDA. The non-display area NDA can be an area adjacent to the display area DA and not displaying an image. The non-display area NDA can surround the display area DA. In the non-display area NDA, display pads D-PD electrically connected to the scan driver SDV, the emission driver EDV, the data driver DDV for driving the pixels PX, and signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL can be disposed. The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL electrically connected to the pixels PX can be disposed to extend in the non-display area NDA.

[0084] The bending area BA can be an area bent with respect to a bending axis extending in the first direction DR1. For example, the bending area BA can be bent toward a rear surface of the display panel DP corresponding to the first base area AA1. Due to the bending of the bending area BA, the second base area AA2 extending from one side (e.g., a single side) of the bending area BA can overlap the first base area AA1 in a plan view. For example, the second base area AA2 can be disposed on the rear surface of the display panel DP corresponding to the first base area AA1.

[0085] In the first direction DR1, the bending region BA and the second base region AA2 may each have a width smaller than that of the first base region AA1. The bending region BA has a smaller width than the first base region AA1 in the direction parallel to the bending axis, and therefore the bending region BA can be easily bent. However, this is shown as an example, and at least one of the widths of the bending region BA and the second base region AA2 in the first direction DR1 may be the same as the width of the first base region AA1, and the embodiments of this disclosure are not limited to any one of them.

[0086] Due to the curvature of the curved region BA, the second base region AA2 can be a region that is substantially flat and located below the first base region AA1. The second base region AA2 can be a region that houses the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL that extend from the curved region BA and the data driver DDV toward the display pad D-PD.

[0087] Configure the area for displaying pad D-PD and the area for sensing pad I-PD, which will be described later (see [link]). Figure 5 The area can be divided into the display pad area PD-A and the sensing pad area IPD-A. Figure 4 The illustration shows the division of a display pad area PD-A and a sensing pad area IPD-A on a first direction DR1. For example, the sensing pad area IPD-A can be arranged adjacent to both sides of the second base area AA2 on the first direction DR1, and the display pad area PD-A can be located in the center. However, the embodiments of this disclosure are not necessarily limited to this, and display pads D-PD and sensing pads I-PD can be arranged (see...). Figure 5 The position of ) can be changed in different ways.

[0088] Flexible circuit board FCB (see) Figure 2 You can configure the display pad D-PD and sensing pad I-PD here (see...) Figure 5 It is located in the second base area AA2 and can be electrically connected to the display pad D-PD and the sensing pad I-PD (see...). Figure 5 Due to the bending of the bending region BA, the flexible circuit board FCB (see [reference]) is disposed adjacent to the lower end of the second base region AA2. Figure 2 It can be positioned on the rear surface of the display panel DP. When the second base area AA2 and the flexible circuit board FCB (see...) Figure 2 ) is located in electronic device EA (see Figure 2 When the electronic device EA (see below the first base region AA1 on the positive surface of the surface) is below the first base region AA1, the electronic device EA (see below) Figure 2 The border area of ​​) can be reduced.

[0089] The pixels PX can each include a pixel driving circuit including transistors (e.g., a switching transistor, a driving transistor, etc.) and at least one capacitor, and a light emitting element electrically connected to the pixel driving circuit. The pixels PX can generate light in response to an electrical signal applied to each of the pixels PX, and display an image through the display area DA. According to an embodiment, some of the pixels PX can include a transistor disposed in the non-display area NDA, but embodiments of the disclosure are not limited to any one.

[0090] The scan driver SDV and the emission driver EDV can be disposed in the non-display area NDA corresponding to the first base area AA1. The data driver DDV can be disposed in the non-display area NDA corresponding to the second base area AA2. In an embodiment, the data driver DDV can be disposed in the form of an integrated circuit chip mounted in the non-display area NDA of the display panel DP. However, the data driver DDV is not limited thereto, and can also be mounted on a flexible circuit board FCB (see FIG. 1B). Figure 2

[0091] The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL can include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, and a power line PL, where m and n represent natural numbers greater than 1.

[0092] The data lines DL1 to DLn can be insulated from and cross the scan lines SL1 to SLm and the emission lines EL1 to ELm. For example, the scan lines SL1 to SLm can extend in the first direction DR1 and be electrically connected to the scan driver SDV. The data lines DL1 to DLn can extend in the second direction DR2 and be electrically connected to the data driver DDV. The emission lines EL1 to ELm can extend in the first direction DR1 and be electrically connected to the emission driver EDV.

[0093] The power line PL can include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. In the power line PL, the portion extending in the first direction DR1 and the portion extending in the second direction DR2 can be disposed at different layers, or can be integrated with each other at the same layer. The portion extending in the first direction DR1 of the power line PL can be electrically connected to the pixels PX and the portion extending in the second direction DR2 of the power line PL. The portion extending in the second direction DR2 of the power line PL can be disposed in the non-display area NDA, and can be electrically connected from the first base area AA1 to the display pad D-PD via the bending area BA and the second base area AA2. The power line PL can supply a first voltage to the pixels PX.​

[0094] The first control line CSL1 can be electrically connected to the scan driver SDV and can extend toward the lower end of the second base area AA2 via the bending area BA. The second control line CSL2 can be electrically connected to the emission driver EDV and can extend toward the lower end of the second base area AA2 via the bending area BA.

[0095] The display pad D-PD can be disposed adjacent to the lower end of the second base area AA2. In the second base area AA2, the display pad D-PD can be disposed closer to the lower end of the base substrate BS than the data driver DDV. The display pads D-PD can be spaced apart in the first direction DR1. The power line PL, the first control line CSL1, and the second control line CSL2 can each be electrically connected to a corresponding one of the display pads D-PD. The data lines DL1 to DLn can each be electrically connected to a corresponding one of the display pads D-PD via the data driver DDV.

[0096] The display pad D-PD can be electrically connected to the flexible circuit board FCB (see Figure 2 ) via an adhesive layer, and an electrical signal provided from the flexible circuit board FCB (see Figure 2 ) can be transmitted to the display panel DP via the display pad D-PD. However, the manner in which the display pad D-PD and the flexible circuit board FCB (see Figure 2 ) are connected is not limited thereto.

[0097] The scan driver SDV can generate a scan signal in response to a scan control signal. The scan signal can be applied to the pixel PX via the scan lines SL1 to SLm. The data driver DDV can generate a data voltage corresponding to an image signal in response to a data control signal. The data voltage can be applied to the pixel PX via the data lines DL1 to DLn. The emission driver EDV can generate an emission signal in response to an emission control signal. The emission signal can be applied to the pixel PX via the emission lines EL1 to ELm.

[0098] The data voltage can be supplied to the pixel PX in response to the scan signal. The pixel PX can generate an image by emitting light of a luminance corresponding to the data voltage in response to the emission signal. The emission duration of the pixel PX can be controlled by the emission signal.

[0099] Figure 5 is a schematic plan view of an input sensing unit ISP according to an embodiment of the present disclosure. For ease of description, Figure 5 components of the input sensing unit ISP disposed on the above-described base substrate BS are briefly shown.

[0100] In an embodiment, the input sensing unit ISP can be driven by a mutual capacitance type. Referring to Figure 5 , the input sensing unit ISP can include first sensing electrodes TEX: TEX1 to TEX6, second sensing electrodes TEY: TEY1 to TEY4, first sensing lines TLX1 to TLX6, second sensing lines TLY1 to TLY4, and a sensing pad I-PD. However, embodiments of the disclosure are not limited thereto, and the input sensing unit ISP can be driven by a self-capacitance type.

[0101] The first sensing electrodes TEX can each extend in the first direction DR1, and the first sensing electrodes TEX can be arranged (or disposed) in the second direction DR2. Figure 5 Six first sensing electrodes TEX1 to TEX6 are shown as an example. However, the number of the first sensing electrodes TEX included in the input sensing unit ISP is not limited thereto. The first sensing electrodes TEX (e.g., a single first sensing electrode TEX) can include a first sensing pattern SP1 disposed in the first direction DR1 and a first connection pattern BP1 connecting the first sensing pattern SP1.

[0102] The second sensing electrodes TEY can each extend in the second direction DR2, and the second sensing electrodes TEY can be arranged (or disposed) in the first direction DR1. Figure 5 Four second sensing electrodes TEY1 to TEY4 are shown as an example. However, the number of the second sensing electrodes TEY included in the input sensing unit ISP is not limited thereto. The second sensing electrodes TEY (e.g., a single second sensing electrode TEY) can include a second sensing pattern SP2 disposed in the second direction DR2 and a second connection pattern BP2 connecting the second sensing pattern SP2.

[0103] The first sensing electrodes TEX and the second sensing electrodes TEY can be electrically insulated. The input sensing unit ISP can sense an external input by a change in capacitance between the first sensing electrodes TEX and the second sensing electrodes TEY. The first sensing electrodes TEX and the second sensing electrodes TEY can be disposed in an area corresponding to a display area DA of the base substrate BS. Accordingly, the electronic device EA (see Figure 1 ) can display an image through the display area DA and can also sense an external input applied to the display area DA.

[0104] The first sensing lines TLX1 to TLX6 can be disposed in the non-display area NDA and electrically connected to the first sensing electrodes TEX1 to TEX6, respectively. Some of the first sensing lines TLX1 to TLX6 can be disposed on the left side of the non-display area NDA, and the rest can be disposed on the right side of the non-display area NDA. For example, the first sensing lines TLX1, TLX3, and TLX5 connected to the first sensing electrodes TEX1, TEX3, and TEX5 disposed in the odd-numbered rows can be connected to the left side of the first sensing electrodes TEX1, TEX3, and TEX5, respectively, and the first sensing lines TLX2, TLX4, and TLX6 connected to the first sensing electrodes TEX2, TEX4, and TEX6 disposed in the even-numbered rows can be connected to the right side of the first sensing electrodes TEX2, TEX4, and TEX6, respectively. However, the arrangement of the first sensing lines TLX1 to TLX6 is not limited thereto, and all of the first sensing lines TLX1 to TLX6 can be disposed on the left side of the non-display area NDA, or all of the first sensing lines TLX1 to TLX6 can be disposed on the right side of the non-display area NDA.

[0105] The first sensing lines TLX1 to TLX6 can each extend from the first base area AA1 toward the second base area AA2 via a bending area BA. The first sensing lines TLX1 to TLX6 can each be electrically connected to a sensing pad I-PD disposed in the second base area AA2.

[0106] The second sensing lines TLY1 to TLY4 can be disposed in the non-display area NDA and electrically connected to the second sensing electrodes TEY1 to TEY4, respectively. Some of the second sensing lines TLY1 to TLY4 can be disposed adjacent to the left side of the non-display area NDA, and the rest can be disposed adjacent to the right side of the non-display area NDA. For example, in the first direction DR1, the second sensing lines TLY1 and TLY2 electrically connected to the second sensing electrodes TEY1 and TEY2 disposed on the left side among the second sensing electrodes TEY1 to TEY4 can be disposed adjacent to the left side of the first base area AA1, and the second sensing lines TLY3 and TLY4 electrically connected to the second sensing electrodes TEY3 and TEY4 disposed on the right side can be disposed adjacent to the right side of the first base area AA1. However, the arrangement of the second sensing lines TLY1 to TLY4 is not limited thereto.

[0107] The second sensing lines TLY1 to TLY4 can each extend from an area adjacent to the lower end of the first base area AA1 toward the second base area AA2 via a bending area BA. The second sensing lines TLY1 to TLY4 can each be electrically connected to a sensing pad I-PD disposed in the second base area AA2.

[0108] Some of the sensing pads I-PD can be disposed in a region adjacent to the left side of the second base area AA2 in the first direction DR1, and the remaining ones can be disposed in a region adjacent to the right side of the second base area AA2. For example, the sensing pads I-PD can be divided into two groups spaced apart from each other, and the display pad region PD-A is between the two groups of sensing pads I-PD. However, the arrangement of the sensing pads I-PD is not limited thereto.

[0109] The sensing pads I-PD and the display pads D-PD (see Figure 4 ) can be disposed at the same layer. The sensing pads I-PD can be disposed at a different layer from the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4, and connected to the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 through contact holes. However, the embodiments of the disclosure are not limited thereto, and the sensing pads I-PD can also be disposed at a different layer from the display pads D-PD (see Figure 4 ). For example, the sensing pads I-PD and the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can be formed at the same layer, and can be integrated with each other.

[0110] The first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can be disposed on the upper part of the components of the display panel DP (see Figure 4 ) in a region corresponding to the non-display area NDA of the base substrate BS. Accordingly, the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can overlap the components of the display panel DP (see Figure 4 ) in the bending area BA and the second base area AA2.

[0111] Figure 6 is a schematic cross-sectional view of a display module DM according to an embodiment of the disclosure. As an example, Figure 6 a cross section of a pixel PX (see Figure 4 ) disposed in the display area DA is shown.

[0112] Referring to Figure 6 , the display module DM can include a display panel DP and an input sensing unit ISP disposed on the display panel DP. The above description is equally applicable to the corresponding components.

[0113] As described above in Figure 3 , the display panel DP can include a base substrate BS, a circuit element layer DP-CL, a light emitting element layer DP-OL, and an encapsulation layer ECL.

[0114] The base substrate BS has insulating properties and can provide a base substrate surface on which components of the display module DM are disposed. The base substrate BS can be flexible so as to be bendable. As described above, the base substrate BS can include a first base area AA1 (see Figure 4 ), a bend area BA (see Figure 4 ), and a second base area AA2 (see Figure 4 ), and the bend area BA (see Figure 4 ) of the base substrate BS can be bent with a certain curvature.

[0115] The circuit element layer DP-CL can include insulating layers 10 to 60 disposed on the base substrate BS, a transistor TR of a pixel PX (see Figure 4 ), an upper electrode UE, and connection electrodes CN1 and CN2. The insulating layers 10 to 60 can include first to sixth insulating layers 10 to 60 that are sequentially stacked in a thickness direction on the base substrate BS. However, the embodiment of the insulating layers 10 to 60 included in the circuit element layer DP-CL is not limited thereto and can vary according to the configuration of the circuit element layer DP-CL or a manufacturing process.

[0116] The first insulating layer 10 can be disposed on the base substrate BS. The first insulating layer 10 can be disposed as a barrier layer and / or a buffer layer to prevent foreign substances from entering from the outside. The first insulating layer 10 can enhance the bonding strength between the base substrate BS and the semiconductor pattern SM and / or the conductive pattern of the circuit element layer DP-CL. The first insulating layer 10 can include at least one of a silicon oxide layer and a silicon nitride layer. In an embodiment, the first insulating layer 10 can include the silicon oxide layer and the silicon nitride layer that are alternately stacked with each other.

[0117] The pixel PX (see Figure 4 ) can be disposed on the base substrate BS. The pixel PX (see Figure 4 ) can be disposed in correspondence with the display area DA. The pixel PX (see Figure 4 ) can include a transistor TR and a light emitting element OL.

[0118] The transistor TR can include a semiconductor pattern SM and a gate electrode GE. The semiconductor pattern SM can be disposed on the first insulating layer 10. The semiconductor pattern SM can include a channel S1, a source S2, and a drain S3. The semiconductor pattern SM can include a silicon semiconductor, and can include a single crystal silicon semiconductor, a polycrystal silicon semiconductor, or an amorphous silicon semiconductor. Embodiments of the present disclosure are not limited thereto, and the semiconductor pattern SM can include an oxide semiconductor. The semiconductor pattern SM according to the embodiments of the present disclosure can be formed of various materials as long as the materials have semiconductor properties, and is not limited to the embodiments.

[0119] The semiconductor pattern SM can include a plurality of regions having different electrical properties according to the presence or absence of doping or reduction. For example, the semiconductor pattern SM can include a region that is highly conductive due to doping or reduction of a metal oxide, and the highly conductive region can serve as an electrode or a signal line of the transistor TR. This can correspond to the source S2 and the drain S3 of the transistor TR. The semiconductor pattern SM can include a region that is less conductive due to the absence of doping, and this can correspond to the channel S1 (or active region) of the transistor TR.

[0120] The second insulating layer 20 can be disposed on the first insulating layer 10 and can cover (or overlap with) the semiconductor pattern SM. The gate electrode GE can be disposed on the second insulating layer 20. The second insulating layer 20 can be disposed between the semiconductor pattern SM and the gate electrode GE of the transistor TR. In a plan view, the gate electrode GE can overlap with the channel S1 of the semiconductor pattern SM. The gate electrode GE can serve as a mask in a doping process of the semiconductor pattern SM. The gate electrode GE can include molybdenum (Mo) that is resistant to heat, an alloy containing Mo, titanium (Ti), an alloy containing Ti, etc., but is not limited thereto.

[0121] Figure 6 The structure of the transistor TR shown in FIG. 1 is presented as an example, and the source S2 or the drain S3 of the transistor TR can be an electrode formed independently of the semiconductor pattern SM. The source S2 and the drain S3 can contact the semiconductor pattern SM or be connected to the semiconductor pattern SM through a contact hole formed in an insulating layer. The gate electrode GE can be disposed under the semiconductor pattern SM. The transistor TR according to the embodiment of the disclosure can be formed in various structures and is not limited to the embodiment.

[0122] The second insulating layer 20 and the third to sixth insulating layers 30 to 60 to be described later can include at least one of an inorganic layer and an organic layer. For example, the inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer can include at least one of an acryl-based resin, a methacrylate-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0123] The third insulating layer 30 can be disposed on the second insulating layer 20 and can cover (or overlap with) the gate electrode GE. The upper electrode UE can be disposed on the third insulating layer 30. The upper electrode UE can overlap with the gate electrode GE in a plan view, and the gate electrode GE and the upper electrode UE that overlap with each other can form a capacitor.

[0124] The fourth insulating layer 40 can be disposed on the third insulating layer 30 and can cover (or overlap with) the upper electrode UE. The connection electrodes CN1 and CN2 can include a first connection electrode CN1 and a second connection electrode CN2. The first connection electrode CN1 can be disposed on the fourth insulating layer 40. The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 and can cover (or overlap with) the first connection electrode CN1. The second connection electrode CN2 can be disposed on the fifth insulating layer 50. The sixth insulating layer 60 can be disposed on the fifth insulating layer 50 and can cover (or overlap with) the second connection electrode CN2. In an embodiment, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 can include an organic layer and can cover (or overlap with) a step between components disposed under at least one of the fifth insulating layer 50 and the sixth insulating layer 60 and provide a substantially flat upper surface.

[0125] The first connection electrode CN1 can be electrically connected to the semiconductor pattern SM through a contact hole passing through the second insulating layer 20 to the fourth insulating layer 40. The second connection electrode CN2 can be electrically connected to the first connection electrode CN1 through a contact hole passing through the fifth insulating layer 50.

[0126] The first connection electrode CN1 and the second connection electrode CN2 can each include a conductive material. The first connection electrode CN1 and the second connection electrode CN2 can each include gold, silver, copper, aluminum, platinum, molybdenum, titanium, or an alloy thereof. At least one of the first connection electrode CN1 and the second connection electrode CN2 can include a conductive layer having a multi-layer structure. For example, at least one of the first connection electrode CN1 and the second connection electrode CN2 can have a three-layer structure of titanium / aluminum / titanium. However, embodiments of the disclosure are not limited thereto.

[0127] According to an embodiment of the circuit element layer DP-CL, at least one of the first connection electrode CN1 and the second connection electrode CN2 can not be disposed. For example, according to an embodiment of the circuit element layer DP-CL, an additional connection electrode can be further disposed to connect the transistor TR and the light emitting element OL. According to the number of insulating layers disposed between the light emitting element OL and the transistor TR, a method of electrically connecting the light emitting element OL and the transistor TR can be variously changed, and the method is not limited to the embodiment.

[0128] The light emitting element layer DP-OL can include the light emitting element OL and the pixel definition film PDL. The light emitting element OL and the pixel definition film PDL can be disposed on the sixth insulating layer 60. The light emitting element OL can include a first electrode AE, an emission layer EM, and a second electrode CE.

[0129] The first electrode AE can be electrically connected to the second connection electrode CN2 through a contact hole passing through the sixth insulating layer 60. The first electrode AE can be electrically connected to the transistor TR through the first connection electrode CN1 and the second connection electrode CN2.

[0130] A pixel opening PX-OP exposing at least a portion of the first electrode AE can be defined in the pixel defining film PDL. The portion of the first electrode AE exposed from the pixel defining film PDL can correspond to a light emitting area. The pixel defining film PDL can include an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the pixel defining film PDL can further include a black pigment or a black dye.

[0131] An emission layer EM can be disposed on the first electrode AE. The emission layer EM can provide light of a color. The emission layer EM can be disposed in correspondence with the pixel opening PX-OP of the pixel defining film PDL. The light emitting element OL and the pixel opening PX-OP can be disposed in plural, and the emission layers EM of the light emitting elements OL can each be disposed in correspondence with the pixel opening PX-OP and spaced apart from each other in a pattern form. However, embodiments of the disclosure are not limited thereto, and the emission layers EM of the light emitting elements OL can be formed as a single common layer.

[0132] A second electrode CE can be disposed on the emission layer EM and the pixel defining film PDL. The second electrode CE can be disposed as a common electrode commonly disposed in the pixel PX (see Figure 4 ).

[0133] The light emitting element OL can further include at least one of a hole control region disposed between the first electrode AE and the emission layer EM and an electron control region disposed between the emission layer EM and the second electrode CE. The hole control region can include at least one of a hole generation layer, a hole transport layer, and an electron blocking layer, and the electron control region can include at least one of an electron generation layer, an electron transport layer, and a hole blocking layer.

[0134] An encapsulation layer ECL can be disposed on the light emitting element layer DP-OL. The encapsulation layer ECL can be disposed on the light emitting element OL and the pixel defining film PDL to seal the light emitting element OL. The encapsulation layer ECL can include at least one of an inorganic film and an organic film. In an embodiment, the encapsulation layer ECL can include a first inorganic film EN1, a second inorganic film EN3, and an organic film EN2 disposed between the first inorganic film EN1 and the second inorganic film EN3. However, the configuration of the encapsulation layer ECL is not limited thereto, as long as it can seal the light emitting element OL.

[0135] The first inorganic film EN1 can be provided on the second electrode CE, and the organic film EN2 and the second inorganic film EN3 can be sequentially provided on the first inorganic film EN1 in a thickness direction of the display panel DP. The first inorganic film EN1 and the second inorganic film EN3 can protect the light emitting element OL from moisture or oxygen entering from the outside. For example, the first inorganic film EN1 and the second inorganic film EN3 can each include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. However, the materials of the first inorganic film EN1 and the second inorganic film EN3 are not limited to the above examples. The organic film EN2 can prevent foreign matter from entering the light emitting element OL and cover a step between components provided below the organic film EN2 (or overlap with a step between components provided below the organic film EN2). For example, the organic film EN2 can include an acrylic-based organic material. However, the material of the organic film EN2 is not limited to the above example.

[0136] The input sensing unit ISP can be provided on the display panel DP. The input sensing unit ISP can include a base layer IL1, a first sensing insulating layer IL2, a first sensing conductive layer CL1, and a second sensing conductive layer CL2. As Figure 3 indicated in FIG. 1B, the input sensing unit ISP can further include a second sensing insulating layer IL3 (see Figure 3 ). The above description is equally applicable to the corresponding components.

[0137] The base layer IL1 can be in contact with an uppermost layer of the encapsulation layer ECL. For example, the base layer IL1 can be in contact with the second inorganic film EN3 of the encapsulation layer ECL. The base layer IL1 of the input sensing unit ISP can be formed on (e.g., directly on) a base surface provided by the encapsulation layer ECL. However, embodiments of the present disclosure are not limited thereto, and according to embodiments, the base layer IL1 can not be provided, in which case the first sensing conductive layer CL1 of the input sensing unit ISP can be in contact with the encapsulation layer ECL.

[0138] The first sensing conductive layer CL1 can be provided on the base layer IL1, and the second sensing conductive layer CL2 can be provided on the first sensing insulating layer IL2. The first sensing conductive layer CL1 and the second sensing conductive layer CL2 can form a sensing electrode TE. The sensing electrode TE can correspond to one of the above-described first sensing electrode TEX and second sensing electrode TEY (see Figure 5 ). For example, the first sensing conductive layer CL1 can include a connection pattern BP of the sensing electrode TE, and the second sensing conductive layer CL2 can include a sensing pattern SP of the sensing electrode TE. However, embodiments of the present disclosure are not limited thereto, and the first sensing conductive layer CL1 can include the sensing pattern SP, and the second sensing conductive layer CL2 can include the connection pattern BP.

[0139] The connection pattern BP can correspond to the first connection pattern BP1 (see Figure 5 ) or the second connection pattern BP2 (see Figure 5 ), and the sensing pattern SP can correspond to the first sensing pattern SP1 (see Figure 5 ) or the second sensing pattern SP2 (see Figure 5 ). The connection pattern BP can be provided at a different layer from the sensing pattern SP, and can be connected to the sensing pattern SP through a contact hole passing through the first sensing insulating layer IL2. However, embodiments of the present disclosure are not limited thereto, and the connection pattern BP and the sensing pattern SP can be provided at the same layer and formed as a single body (or integrated with each other).

[0140] The sensing electrode TE can be a mesh-shaped pattern, and can be provided in correspondence with an area in which the pixel definition film PDL is provided. However, embodiments of the present disclosure are not limited thereto, and the sensing electrode TE can be provided as a single-shaped pattern overlapping the light emitting element OL, and the sensing electrode TE can include a transparent conductive material.

[0141] Figure 7 is a schematic perspective view of an electronic device EA according to an embodiment of the present disclosure. Figure 7 Some components of the electronic device EA provided in correspondence with a second base area AA2 are briefly shown.

[0142] The second base area AA2 corresponds to a portion of a non-display area NDA (see Figure 4 ). As shown in Figure 7 , in the non-display area NDA or the second base area AA2, an area in which the data driver DDV is bonded can be defined as a first pad area PA1, and an area in which the flexible circuit board FCB is bonded can be defined as a second pad area PA2. In an embodiment, the data driver DDV and the flexible circuit board FCB can be collectively referred to as an electronic component, and the electronic component can include a bump electrode provided in the pad areas PA1 and PA2.

[0143] The data driver DDV can be bonded to the first pad area PA1 through a first adhesive layer CF1, and the flexible circuit board FCB can be bonded to the second pad area PA2 through a second adhesive layer CF2. The first adhesive layer CF1 and the second adhesive layer CF2 can each include a synthetic resin having adhesive properties. The first adhesive layer CF1 and the second adhesive layer CF2 can each be a non-conductive film (NCF). For example, the first adhesive layer CF1 and the second adhesive layer CF2 can each be an adhesive resin free of conductive particles.

[0144] However, embodiments of this disclosure are not limited thereto, and in some embodiments, at least one of the first adhesive layer CF1 and the second adhesive layer CF2 may not be provided. For example, the data driver DDV and the flexible circuit board FCB can be ultrasonically bonded to the first pad region PA1 and the second pad region PA2, respectively.

[0145] The display panel (DP) may include multiple pads (PD). Each pad (PD) may include a first signal pad (PD1), a second signal pad (PD2), and a display pad (D-PD). The first signal pad (PD1), the second signal pad (PD2), and the display pad (D-PD) may be pads positioned within the signal transmission path.

[0146] The first signal pad PD1 can be set to correspond to the output pad of the data driver DDV, and can also be an input pad that receives signals from the data driver DDV. The second signal pad PD2 can be set to correspond to the input pad of the data driver DDV, and can also be an output pad that outputs signals to the data driver DDV. The display pad D-PD can be a panel input pad that receives signals from the flexible circuit board FCB.

[0147] The first signal pad PD1 can be electrically connected to the pixel PX of the display panel DP via signal lines (see...). Figure 4 ), and can be directed to pixel PX (see Figure 4 ) Sending signals and from pixel PX (see Figure 4 The second signal pad PD2 can be electrically connected to the corresponding display pad D-PD in the display pad D-PD via signal lines, and the electrically connected display pad D-PD and the second signal pad PD2 can send and receive signals.

[0148] The first pad area PA1 may include a first sub-pad area PA1-1 and a second sub-pad area PA1-2. The first sub-pad area PA1-1 may be defined as the area where the first signal pad PD1 is set. The second sub-pad area PA1-2 may be defined as the area where the second signal pad PD2 is set.

[0149] The first signal pad PD1 can be arranged (or set) in the first sub-pad area PA1-1 on the first direction DR1 and the second direction DR2. Among the first signal pads PD1, the first signal pad PD1 arranged (or set) on the first direction DR1 can be defined as a pad row. As an example, Figure 7 The diagram shows five rows of pads arranged on DR2 in the second direction. The arrangement of the first signal pad PD1 is not limited to this.

[0150] The second signal pads PD2 can be arranged (or arranged) in the first direction DR1 in the second sub-pad region PA1-2. The second signal pads PD2 can be provided as a single pad row. However, the arrangement of the second signal pads PD2 is not limited thereto.

[0151] Figure 8A is a schematic plan view of the pad regions PA1 and PA2 according to an embodiment of the disclosure. Figure 8B is a cross-sectional view of the pad regions PA1 and PA2 according to an embodiment of the disclosure.

[0152] Figure 8A is a schematic plan view showing an enlarged portion of the pad regions PA1 and PA2 in which a signal pad PD (e.g., a single signal pad PD) is provided according to an embodiment of the disclosure. Figure 8B is a cross-sectional view of the pad regions PA1 and PA2 corresponding to Figure 8A line A-A' of

[0153] Figure 8A and Figure 8B The signal pads PD shown in Figure 7 may be one of the first signal pads PD1, the second signal pads PD2, and the display pads D-PD described with reference to Figure 4 Although the data lines DL1 to DLn including the end portion DL-E are shown as an example of the signal lines (see Figure 4 ), embodiments of the disclosure are not limited thereto. The signal lines can be another signal line other than the data lines DL1 to DLn (see

[0154] Hereinafter, the pad regions PA1 and PA2 will be described focusing on the first sub-pad region PA1-1 (see Figure 4 ) in which the data lines DL1 to DLn (see Figure 7 ) are provided. The description of the first sub-pad region PA1-1 (see Figure 7 ) can be equally applied to the second sub-pad region PA1-2, except that a connection signal line is provided instead of the data lines DL1 to DLn (see Figure 4 ).

[0155] With reference to Figure 8A and Figure 8B , the signal pads PD can include the first conductive pattern CP1, the second conductive pattern CP2, the third conductive pattern CP3, and at least one insulating pattern PP. As an example, Figure 8AA structure in which the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 are all placed at the same location with the same area size is shown. The signal pad PD can further include pad insulating layers IL1-PD and IL2-PD. For example, the signal pad PD can further include a first pad insulating layer IL1-PD and a second pad insulating layer IL2-PD. For ease of description, in Figure 8A the schematic plan view, the first pad insulating layer IL1-PD and the second pad insulating layer IL2-PD are not provided, and only a first insulating layer opening OP-IL1 defined in the first pad insulating layer IL1-PD is shown.

[0156] The signal pad PD can further include a reinforcement pattern RP. To show a structure in which the reinforcement pattern RP is disposed within the opening OP-CP2, in Figure 8A the reinforcement pattern RP is shown as being spaced apart from the opening OP-CP2 and having a smaller area than the opening OP-CP2, but in embodiments of the disclosure, as shown in Figure 8B the reinforcement pattern RP can be disposed to contact and fill the opening OP-CP2.

[0157] In Figure 8A the insulating pattern PP is shown as covering (or overlapping) the entire opening OP-CP2 in the plan view, but is not limited thereto, and a structure in which a portion covers (or partially overlaps) the opening OP-CP2 can be formed. At least a portion of the insulating pattern PP can not overlap the opening OP-CP2 to define a side portion S-PP which will be described later, and the pressure applied by the side portion S-PP in the bonding process is not dispersed but can be concentrated on the third conductive pattern CP3 disposed on the upper portion of the central portion C-PP of the insulating pattern PP.

[0158] The end portion DL-E of the data line can be disposed in the pad areas PA1 and PA2. Here, the end portion DL-E of the data line can be referred to as a portion of the signal line.

[0159] In the plan view, the end portion DL-E of the data line can be in the form of extending in the second direction DR2. For example, the end portion DL-E can have a length or width in the second direction DR2 that is greater than a length or width in the first direction DR1. The end portion DL-E of the data line and the gate electrode GE (see Figure 6 ) of the transistor TR (see Figure 6 ) disposed in the above-described display area DA (see Figure 6 ) can be disposed in the same layer.The data line can be formed from the same layer. For example, the end portion DL-E of the data line can be disposed on the second insulating layer 20. The end portion DL-E of the data line and the gate electrode GE (see...) Figure 6 The data cable can be made of the same material. For example, the terminal portion DL-E of the data cable can include molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), a titanium-containing alloy, or a combination thereof. The terminal portion DL-E of the data cable can be connected to the gate electrode GE (see [link to relevant documentation]). Figure 6 The data line is formed in the same process (e.g., patterning process). The terminal portion DL-E of the data line can have the same characteristics as the gate electrode GE (see...). Figure 6 (The same thickness)

[0160] However, the location of the end portion DL-E is not limited to this. End portion DL-E and Figure 6 The upper electrode UE shown can be formed from the same layer or formed on the same layer, can include the same material, and can have the same stacked structure. For example, some of the signal lines among multiple signal lines can be connected to the gate electrode GE (see [link to documentation]). Figure 6 It is formed using the same process, and other signal lines can be connected to the upper electrode UE (see...). Figure 6 Formed using the same process.

[0161] Data cables DL1 to DLn (see) Figure 4 These can be set on a layer (i.e., a single layer) and can be integrated with each other, but are not limited to this. Data lines DL1 to DLn (see...) Figure 4 One of them can include multiple parts set at different layers.

[0162] The first conductive pattern CP1 can be disposed on the end portion DL-E of the data line. In a plan view, the first conductive pattern CP1 can overlap with the end portion DL-E of the data line. In a plan view, the end portion DL-E of the data line can be disposed within the first conductive pattern CP1, but is not limited thereto.

[0163] The first conductive pattern CP1 can be connected to data lines DL1 to DLn through the first insulating layer opening OP-IL1 defined in the first pad insulating layer IL1-PD (see...). Figure 4 The terminal portion DL-E of the circuit element layer CP1 is defined as the first pad insulating layer IL1-PD. In this embodiment, the insulating layer disposed between the terminal portion DL-E and the first conductive pattern CP1 can be defined as the first pad insulating layer IL1-PD. In this embodiment, the third insulating layer 30 and the fourth insulating layer 40 can be defined as the first pad insulating layer IL1-PD. The stacking structure of the first pad insulating layer IL1-PD can be based on the circuit element layer DP-CL (see...). Figure 6The stack structure of the first insulating layer opening OP-IL1 can vary. In an embodiment, the first insulating layer opening OP-IL1 can be defined by a larger number of insulating layers than the third insulating layer 30 and the fourth insulating layer 40, or can be defined by a smaller number of insulating layers. The first conductive pattern CP1 and the end portion DL-E can be distinguished by the first pad insulating layer IL1-PD (e.g., the third insulating layer 30 and the fourth insulating layer 40) provided between the first conductive pattern CP1 and the end portion DL-E.

[0164] The first conductive pattern CP1 and the first connection electrode CN1 (see Figure 6 ) of the transistor TR (see Figure 6 ) connected to the above-described display region DA (see Figure 6 ) can be formed by the same layer or at the same layer. For example, the first conductive pattern CP1 can be provided on the fourth insulating layer 40. The first conductive pattern CP1 and the first connection electrode CN1 (see Figure 6 ) can include the same material. The first conductive pattern CP1 and the first connection electrode CN1 (see Figure 6 ) can be formed by the same process or from the same layer. The first conductive pattern CP1 can have a single-layer structure or a multi-layer structure, and can have the same stack structure as the first connection electrode CN1 (see Figure 6 ). For example, the first conductive pattern CP1 can have a three-layer structure of titanium / aluminum / titanium. The first conductive pattern CP1 can have the same thickness as the first connection electrode CN1 (see Figure 6 ). The first conductive pattern CP1 can have a thickness in the range of about 6000 to about 9000 . For example, the first conductive pattern CP1 can have a thickness in the range of about 7000 to about 8500 .

[0165] The second conductive pattern CP2 can be provided on the first conductive pattern CP1. The second conductive pattern CP2 and the first conductive pattern CP1 can be distinguished by a boundary line observed in a cross-section due to their formation in different processes. The second conductive pattern CP2 can contact the first conductive pattern CP1 and be electrically connected to the first conductive pattern CP1. In a plan view, the second conductive pattern CP2 can overlap the first conductive pattern CP1. In a plan view, the first conductive pattern CP1 can be provided within the second conductive pattern CP2. However, embodiments of the present disclosure are not limited thereto, and for example, in a plan view, the second conductive pattern CP2 can be provided within the first conductive pattern CP1, or can be provided at the same position as the first conductive pattern CP1.

[0166] The second conductive pattern CP2 and connected to the aforementioned display area DA (see...) Figure 6 The first connecting electrode CN1 (see) Figure 6 The second connecting electrode CN2 (see) Figure 6 The second conductive pattern CP2 and the second connecting electrode CN2 (see...) can be formed from the same layer or in the same layer. Figure 6 The second conductive pattern CP2 and the second connecting electrode CN2 (see...) can be made of the same material. Figure 6 The second conductive pattern CP2 can be formed using the same process or from the same layers. It can have a single-layer or multi-layer structure and can have a connection with the second connecting electrode CN2 (see...). Figure 6 The second conductive pattern CP2 may have the same stacked structure as the second connecting electrode CN2 (see [reference]). For example, the second conductive pattern CP2 may have a three-layer structure of titanium / aluminum / titanium. The second conductive pattern CP2 may have the same stacked structure as the second connecting electrode CN2 (see [reference]). Figure 6 The second conductive pattern CP2 can have the same thickness as the first, with a thickness of approximately 6000. To approximately 9000 The thickness can be within a certain range. For example, the second conductive pattern CP2 can have a thickness of approximately 7000. Approximately 8500 The thickness is within the range.

[0167] The signal pad PD may further include a pad insulating layer disposed between the first conductive pattern CP1 and the second conductive pattern CP2, and having an insulating layer opening therein that exposes the first conductive pattern CP1. For example, the pad insulating layer disposed between the first conductive pattern CP1 and the second conductive pattern CP2 may be a fifth insulating layer 50 of the aforementioned display area DA (see...). Figure 8A Set it to extend to the pad areas PA1 and PA2.

[0168] At least one of the first conductive pattern CP1 and the second conductive pattern CP2 may have an opening defined therein. As an example, Figure 8B and Figure 9C The structure in which the opening OP-CP2 is defined within the second conductive pattern CP2 is shown. The opening OP-CP2 defined within the second conductive pattern CP2 may be referred to as the second opening OP-CP2, to distinguish it from the opening OP-CP1 defined within the first conductive pattern CP1 (see [link to diagram]). Figure 6 ).

[0169] In the plan view, the opening OP-CP2 can be defined at the location overlapping the insulating pattern PP. In the plan view, the opening OP-CP2 can be defined to have an area smaller than that of the insulating pattern PP. The opening OP-CP2 overlapping the insulating pattern PP can be defined within the second conductive pattern CP2 disposed below the insulating pattern PP, and therefore, the problem of downward dispersion of pressure applied during the bonding process can be prevented when both the first conductive pattern CP1 and the second conductive pattern CP2 are disposed below and overlap the insulating pattern PP.

[0170] The signal pad PD may also include a reinforcing pattern RP disposed within the opening OP-CP2. The reinforcing pattern RP may be disposed below the insulating pattern PP. In a plan view, the reinforcing pattern RP may be configured to overlap with the insulating pattern PP. The reinforcing pattern RP may have a greater hardness than the insulating pattern PP. The reinforcing pattern RP may include a metal. For example, the reinforcing pattern RP may include molybdenum (Mo). The reinforcing pattern RP may be configured to overlap with the insulating pattern PP and thus firmly support the insulating pattern PP, preventing downward dispersion of pressure applied during the bonding process. The reinforcing pattern RP may not be configured to completely overlap with the conductive patterns CP1 and CP2 of the signal pad PD, but may be configured to correspond only to the portion where the insulating pattern PP is disposed, and thus firmly support the insulating pattern PP to prevent dispersion of pressure applied during the bonding process.

[0171] Enhanced pattern RP and display area DA (see Figure 6 The setting of transistor TR (see) Figure 6 ) and the first connecting electrode CN1 (see Figure 6 At least one electrode between the two electrodes can be formed using the same process or from the same layer. For example, reinforced patterned RP and Figure 6 The upper electrode UE can be formed using the same process or from the same layer. Therefore, the reinforcing pattern RP and Figure 8B The upper electrode UE can include the same material and can have the same thickness. The reinforcement pattern RP can be formed by modifying the mask pattern of a typical process without adding a separate mask process.

[0172] like Figure 6 As shown, if there is no defined opening in the first conductive pattern CP1, the reinforcing pattern RP can be disposed below the first conductive pattern CP1. Conversely, if there is an defined opening in the first conductive pattern CP1 and no defined opening in the second conductive pattern CP2, the reinforcing pattern RP can be disposed below the second conductive pattern CP2.

[0173] The second pad insulating layer IL2-PD and the base layer IL1 of the aforementioned input sensing unit ISP (see...) Figure 8A) can include the same material. The second pad insulating layer IL2-PD can be formed by the same process as or from the same layer as the base insulating layer IL1. The second pad insulating layer IL2-PD can include an inorganic film. For example, the inorganic film can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, or a combination thereof.

[0174] The second insulating layer opening OP-IL2 can be defined in the second pad insulating layer IL2-PD. The second insulating layer opening OP-IL2 can expose the second conductive pattern CP2. The third conductive pattern CP3 can be connected to the second conductive pattern CP2 through the second insulating layer opening OP-IL2.

[0175] The third conductive pattern CP3 can be disposed on the second conductive pattern CP2. In a plan view, the third conductive pattern CP3 can overlap the second conductive pattern CP2. In an embodiment, the third conductive pattern CP3 can be disposed within the second conductive pattern CP2, or the second conductive pattern CP2 can be disposed within the third conductive pattern CP3. Figure 6 In an embodiment, for convenience, the second conductive pattern CP2 and the third conductive pattern CP3 are illustrated as completely overlapping in a plan view, but the second conductive pattern CP2 can be disposed within the third conductive pattern CP3, or the third conductive pattern CP3 can be disposed within the second conductive pattern CP2.

[0176] The third conductive pattern CP3 and the first or second sensing conductive layer CL1 or CL2 of the above-described display area DA (see FIG. 1) can include the same material. For example, the third conductive pattern CP3 and the second sensing conductive layer CL2 of the above-described display area DA (see FIG. 1) can include the same material. Figure 6 ) can include the same material. For example, the third conductive pattern CP3 and the second sensing conductive layer CL2 of the above-described display area DA (see FIG. 1) can include the same material. Figure 8A ) can include the same material. For example, the third conductive pattern CP3 and the second sensing conductive layer CL2 of the above-described display area DA (see FIG. 1) can include the same material.

[0177] The third conductive pattern CP3 can include a first layer disposed on the second conductive pattern CP2, a second layer disposed on the first layer, and a third layer disposed on the second layer. The second layer can be thicker than each of the first layer and the third layer. The second layer can have a higher electrical conductivity than the first layer and the third layer. The first layer and the third layer can include the same material. The second layer can include a different material from the first layer and the third layer. For example, the first layer and the third layer can include titanium (Ti), and the second layer can include aluminum (Al). In an embodiment, the above-described first layer, second layer, and third layer can also be applied to the first conductive pattern CP1 and the second conductive pattern CP2. In the case where pressure is applied in a bonding process, the third layer disposed on the uppermost portion of the third conductive pattern CP3 is stretched and torn due to the pressure. This exposes the second layer, and then the second layer can be connected to the bump electrode of the electronic component.

[0178] The insulating pattern PP can be disposed between the second conductive pattern CP2 and the third conductive pattern CP3. A lower surface of the insulating pattern PP can be in contact with the first conductive pattern CP1 or the second conductive pattern CP2, and side surfaces and an upper surface of the insulating pattern PP can each be covered by (or overlap) the third conductive pattern CP3. The insulating pattern PP can form protrusions in the pad areas PA1 and PA2.

[0179] In a plan view, the insulating pattern PP can overlap each of the second conductive pattern CP2 and the third conductive pattern CP3. In an embodiment, the insulating pattern PP can be arranged (or disposed) in the second direction DR2. The insulating patterns PP can be spaced apart from each other in the second direction DR2. In a plan view, the insulating pattern PP can be disposed within the second insulating layer opening OP-IL2. The insulating pattern PP can be disposed to overlap the opening OP-CP2 defined in the second conductive pattern CP2.

[0180] In Figure 8B and Figure 8A In the above-described embodiments, a structure in which three insulating patterns PP are arranged in a row is illustrated as an example, but the number and arrangement of the insulating patterns PP are not limited thereto. In Figure 6 In the above-described embodiments, a structure in which the insulating pattern PP is square in shape in a plan view is illustrated as an example, but embodiments of the disclosure are not limited thereto. The shape of the insulating pattern PP in a plan view can be changed to a polygon other than a square, a circle, or an ellipse. The shapes of the insulating patterns PP are not limited to being the same.

[0181] An upper surface of the insulating pattern PP can include a stepped shape in a cross-section. For example, the insulating pattern PP can include a central portion C-PP overlapping the opening OP-CP2 and a side portion S-PP not overlapping the opening OP-CP2. The central portion C-PP has a greater thickness than the side portion S-PP. The central portion C-PP can protrude further than the side portion S-PP toward the third conductive pattern CP3 in the third direction DR3. In a plan view, the side portion S-PP can be adjacent to and surround at least a portion of the central portion C-PP. The side portion S-PP can overlap each of the first conductive pattern CP1 and the second conductive pattern CP2.

[0182] The insulating pattern PP according to the embodiment of the disclosure includes the side portion S-PP that protrudes less than the central portion C-PP, and thus, a pressure applied in a bonding process can not be dispersed but can be concentrated on the third conductive pattern CP3 disposed on the insulating pattern PP.

[0183] The insulating pattern PP can include a polymer. The insulating pattern PP can include a thermosetting polymer. However, the embodiment of the disclosure is not limited thereto, and the insulating pattern PP can also include a thermoplastic polymer.

[0184] In an embodiment, the insulating pattern PP can be formed through the same process as a first sensing insulating layer IL2 (see Figure 6 ) of an input sensing unit ISP (see Figures 9A to 9E ). Accordingly, an additional process for forming the insulating pattern PP can not be needed.

[0185] In an embodiment, the insulating pattern PP can have a height in a range of about 1 µm to about 2 µm. The height of the insulating pattern PP can indicate a length of the third direction DR3 of the insulating pattern PP. For example, the insulating pattern PP can have a height in a range of about 1.3 µm to about 1.7 µm. In an embodiment, the insulating pattern PP can have a width of about 2 µm or more. The width of the insulating pattern PP can indicate a length of the first direction DR1 or a length of the second direction DR2 of the insulating pattern PP. For example, the insulating pattern PP can have a width of about 3 µm or more.

[0186] Figure 10A Each is a schematic cross-sectional view of a pad area PA1 and PA2 according to an embodiment of the disclosure. Figure 10B and Figures 9A to 10B Each is a schematic cross-sectional view of a pad area PA1 and PA2 according to an embodiment of the disclosure.

[0187] Figure 8AEach illustrates other embodiments of a position corresponding to A-A' of FIG. 8 for the structure of the signal pad PD provided in the pad areas PA1 and PA2 according to embodiments of the disclosure. The description given above with reference to Figure 8B and Figures 9A to 10B the pad areas PA1 and PA2 applies equally to the pad areas PA1 and PA2 of Figure 9A .

[0188] With reference to Figure 9A , the reinforcing pattern RP-K can be provided on the first conductive pattern CP1. In the first conductive pattern CP1 and the second conductive pattern CP2, the opening OP-CP2 can be defined only in the second conductive pattern CP2, and the reinforcing pattern RP-K can be provided within the opening OP-CP2 defined in the second conductive pattern CP2 and above the first conductive pattern CP1. The reinforcing pattern RP-K can be provided (e.g., directly provided) under the insulating pattern PP to support the insulating pattern PP, thereby preventing dispersion of pressure applied in a bonding process.

[0189] Figure 6 The reinforcing pattern RP-K of Figure 6 may be a metal material. However, the reinforcing pattern RP-K is not limited to a metal material and can be any material having a greater hardness than the insulating pattern PP. Unlike the Figure 6 reinforcing pattern RP formed in the same process as any one of the electrodes provided between the transistor TR (see Figure 8B ) and the first connection electrode CN1 (see Figure 9B ) formed in the display area DA (see ), the reinforcing pattern RP-K can be formed by adding a separate process, thereby freely controlling the position and material for forming the reinforcing pattern RP-K. For example, a material having a desired hardness can be formed as the reinforcing pattern RP-K at a desired position by an inkjet process.

[0190] Figure 8B With reference to Figure 9A , in the first conductive pattern CP1 and the second conductive pattern CP2, the opening OP-CP2 can be defined only in the second conductive pattern CP2, and the insulating pattern PP can be provided (e.g., directly provided) on the first conductive pattern CP1, filling the inside of the opening OP-CP2 defined in the second conductive pattern CP2. The opening OP-CP2 of the second conductive pattern CP2 is defined at a position overlapping the insulating pattern PP, and thus, in the first conductive pattern CP1 and the second conductive pattern CP2, only the first conductive pattern CP1 is provided under the insulating pattern PP, and thus, the first conductive pattern CP1 can support the insulating pattern PP to prevent dispersion even in the absence of the reinforcing patterns RP and RP-K (see Figure 9CThis also prevents the dispersion of pressure applied during the bonding process.

[0191] refer to Figure 9D In the first conductive pattern CP1 and the second conductive pattern CP2, an opening OP-CP1 is defined only in the first conductive pattern CP1, and a reinforcing pattern RP can be disposed within the opening OP-CP1 of the first conductive pattern CP1. The reinforcing pattern RP can be configured to fill the opening OP-CP1 of the first conductive pattern CP1. The second conductive pattern CP2 can be disposed on the reinforcing pattern RP, and an insulating pattern PP can be disposed (e.g., directly disposed) on the second conductive pattern CP2. The reinforcing pattern RP can be disposed at a position overlapping with the insulating pattern PP, and the second conductive pattern CP2 can be disposed above the reinforcing pattern RP, and therefore, the second conductive pattern CP2 can support the insulating pattern PP to prevent the dispersion of pressure applied during the bonding process.

[0192] refer to Figure 9E and Figure 9E Openings OP-CP1 and OP-CP2 can be defined in the first conductive pattern CP1 and the second conductive pattern CP2, respectively. The opening OP-CP1 defined in the first conductive pattern CP1 can be referred to as the first opening, and the opening OP-CP2 defined in the second conductive pattern CP2 can be referred to as the second opening.

[0193] Openings OP-CP1 and OP-CP2 can be positioned at locations overlapping the insulating pattern PP, but they may not overlap with the first conductive pattern CP1 and the second conductive pattern CP2, and therefore, the pressure applied during the bonding process may not be dispersed. Figure 10A As shown, when the reinforcing pattern RP is positioned below the insulating pattern PP, the reinforcing pattern RP can more firmly support the insulating pattern PP.

[0194] refer to Figure 10B and Figure 8A The shapes of the openings OP-CP1 and OP-CP2 in at least one of the first conductive pattern CP1 and the second conductive pattern CP2 in the plan view are not limited to... Figure 10A The square shown can be a polygon, circle, or ellipse, other than a square. Figure 10B The diagram shows an example where the openings OP-CP1 and OP-CP2 are circular in shape in a plan view. Figure 8A The diagram shows a structure in which the openings OP-CP1 and OP-CP2 are rectangular in shape in the plan view as an example.

[0195] The shape of the enhanced pattern RP in the planar drawing is not limited to Figure 10AThe square shown can be a polygon, circle, or ellipse, other than a square. Figure 10B The image shows an example where the reinforcing pattern RP is circular in shape in a planar view. Figure 10A The diagram shows an example where the shape of the reinforcement pattern RP in the plan view is rectangular.

[0196] To illustrate the structure in which the reinforcing pattern RP is disposed within openings OP-CP1 and OP-CP2, Figure 10B and Figure 10A In the illustration, the reinforcing pattern RP is shown as being spaced apart from the openings OP-CP1 and OP-CP2 and having a smaller area than the openings OP-CP1 and OP-CP2. However, in embodiments of this disclosure, the reinforcing pattern RP may be configured to contact the openings OP-CP1 and OP-CP2 and fill the openings OP-CP1 and OP-CP2.

[0197] exist Figure 10B and Figure 8A In the diagram, the insulating pattern PP is shown as covering (or overlapping) the entire openings OP-CP1 and OP-CP2 in a plan view, but is not limited thereto, and can be formed in a structure in which partially covers (or partially overlaps) the openings OP-CP1 and OP-CP2. At least a portion of the insulating pattern PP may not overlap with the openings OP-CP1 and OP-CP2, and may include the above-mentioned features. Figure 8B and ​ The side portion S-PP described herein, and the pressure applied by the side portion S-PP during the bonding process is not dispersed, but can be concentrated on the third conductive pattern CP3 disposed on the upper portion of the insulating pattern PP.

[0198] A display module according to an embodiment of the present disclosure includes a signal pad having an opening in at least one of a first conductive pattern and a second conductive pattern, and thus preventing the dispersion of pressure applied during the bonding process. A display module according to an embodiment of the present disclosure includes a signal pad having a prominent central portion of an insulating pattern and less prominent side portions, and thus being better suited to withstand pressure applied during the bonding process. A signal pad of a display module according to an embodiment of the present disclosure may include a reinforcing pattern having a greater hardness than the insulating pattern, disposed below and corresponding to the insulating pattern, and thus being better suited to withstand pressure applied during the bonding process due to the reinforcing pattern.

[0199] An electronic device including a display module according to embodiments of the disclosure can have enhanced bonding reliability because pressure applied between the display module and an electronic component in a bonding process is not dispersed but is concentrated on a third conductive pattern disposed on an insulating pattern.

[0200] As described above, because an opening is defined in at least one conductive layer disposed below and corresponding to an insulating pattern of a signal pad, a display module according to embodiments of the disclosure can prevent pressure applied in a bonding process from being dispersed. The insulating pattern of the signal pad can include a protruding central portion that can overlap the opening and a side portion that does not overlap the opening, and thus has a structure capable of withstanding pressure. An enhancement pattern can be disposed corresponding to the insulating pattern, and thus, pressure applied in a bonding process can be effectively withstood.

[0201] Since pressure in a bonding process between a signal pad of a display module and an electronic component can be concentrated on a conductive layer disposed above an insulating pattern, an electronic device including a display module according to embodiments of the disclosure can exhibit excellent bonding reliability between the display module and the electronic component.

[0202] Although the disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments, but can be variously changed and modified by those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, the technical scope of the disclosure is not limited to the detailed description in the specification, but should be determined only by the claims.

Claims

1. Display module, including: A display panel includes a display area and a non-display area adjacent to the display area, wherein a pad area is provided in the non-display area. The display panel includes: Pixels, disposed in the display area; and Signal pads, connected to the pixel via signal lines and disposed in the pad area, wherein... The signal pads include: A first conductive pattern is connected to a portion of the signal line; A second conductive pattern is disposed on the first conductive pattern; A third conductive pattern is disposed on the second conductive pattern; and An insulating pattern is disposed between the second conductive pattern and the third conductive pattern. An opening is provided in at least one of the first conductive pattern and the second conductive pattern, and The opening overlaps with the insulating pattern.

2. The display module according to claim 1, wherein, The insulating pattern includes a central portion that overlaps with the opening. The insulating pattern also includes side portions that do not overlap with the opening, and The central portion protrudes further toward the third conductive pattern from at least one of the first and second conductive patterns than the side portions.

3. The display module according to claim 2, wherein, The side portion of the insulating pattern overlaps with each of the first conductive pattern and the second conductive pattern.

4. The display module according to claim 1, wherein, The insulating pattern has an area larger than the opening in the plan view.

5. The display module according to claim 1, wherein, The opening is disposed in the second conductive pattern. The insulating pattern fills the opening, and The insulating pattern is directly disposed on the first conductive pattern.

6. The display module according to claim 1, wherein, The opening includes a first opening and a second opening. The first opening is disposed in the first conductive pattern. The first opening overlaps with the insulating pattern. The second opening is disposed in the second conductive pattern, and The insulating pattern overlaps with the second opening and is disposed within the second opening.

7. The display module according to claim 1, wherein, The signal pads also include a reinforcing pattern having a higher hardness than the insulating pattern. The enhancement pattern overlaps with the opening in the plan view.

8. The display module according to claim 7, wherein, The reinforcing pattern includes metal.

9. The display module according to claim 7, wherein, The enhanced pattern includes molybdenum.

10. The display module according to claim 7, wherein, The opening is disposed in the second conductive pattern. The reinforcing pattern is directly disposed below the first conductive pattern, and The insulating pattern is directly disposed on the first conductive pattern.

11. The display module according to claim 7, wherein, The opening is disposed in the second conductive pattern. The reinforcing pattern is disposed in the opening, and The insulating pattern is directly disposed on the reinforcing pattern.

12. The display module according to claim 7, wherein, The opening includes a first opening and a second opening. The first opening is disposed in the first conductive pattern. The second opening is disposed in the second conductive pattern. The insulating pattern overlaps with the first opening and the second opening. The reinforcing pattern is disposed in the first opening, and The insulating pattern is directly disposed on the reinforcing pattern.

13. The display module according to claim 7, wherein, The opening is disposed in the first conductive pattern. The reinforcing pattern is disposed in the opening, and The insulating pattern is directly disposed on the second conductive pattern.

14. The display module according to claim 1, wherein, The display panel includes a base layer, a circuit element layer disposed on the base layer, and a light-emitting element layer disposed on the circuit element layer in the display area, wherein the light-emitting element layer includes light-emitting elements. The circuit element layer includes: A transistor includes a semiconductor pattern and a gate electrode, the semiconductor pattern including a channel, a source, and a drain, the semiconductor pattern and the gate electrode being disposed in different layers from each other; A first connection electrode is connected to the transistor; and The second connecting electrode is connected to the light-emitting element. The first conductive pattern and the first connecting electrode are formed from the same layer, and The second conductive pattern and the second connecting electrode are formed from the same layer.

15. The display module according to claim 14, wherein, The circuit element layer also includes an upper electrode that overlaps with the gate electrode in the plan view. The capacitor includes the upper electrode and the gate electrode. The signal pads also include a reinforcing pattern, which has a greater hardness than the insulating pattern. The enhancement pattern overlaps with the opening in the plan view, and The reinforcing pattern and the upper electrode are formed from the same layer.

16. The display module according to claim 1, further comprising: An input sensing unit is disposed on the display panel, wherein, The input sensing unit includes: First sensing conductive layer; A first sensing insulating layer is disposed on the first sensing conductive layer; and A second sensing conductive layer is disposed on the first sensing insulating layer, and The third conductive pattern of the signal pad and at least one of the first sensing conductive layer and the second sensing conductive layer of the input sensing unit are formed from the same layer.

17. The display module according to claim 1, wherein, The insulating pattern comprises a polymer.

18. The display module according to claim 1, wherein, The first conductive pattern, the second conductive pattern, and the third conductive pattern each include a first layer, a second layer, and a third layer, and The first layer and the third layer have lower electrical conductivity than the second layer.

19. The display module according to claim 18, wherein, The first layer and the third layer each comprise titanium, and The second layer comprises aluminum.

20. Electronic devices, including: The display module includes: A display panel includes a display area and a non-display area adjacent to the display area, wherein a pad area is provided in the non-display area. The display panel includes pixels disposed in the display area and signal pads connected to the pixels via signal lines and disposed in the pad area. An input sensing unit is disposed on the display panel; Electronic components, including raised electrodes disposed in the pad area; and An adhesive layer bonds the display panel and the electronic components. The input sensing unit includes: A first sensing conductive layer is disposed on the display panel; A first sensing insulating layer is disposed on the first sensing conductive layer; and The second sensing conductive layer is disposed on the first sensing insulating layer. The signal pads include: A first conductive pattern is connected to a portion of the signal line; A second conductive pattern is disposed on the first conductive pattern; A third conductive pattern is disposed on the second conductive pattern; and An insulating pattern is disposed between the second conductive pattern and the third conductive pattern. An opening is provided in at least one of the first conductive pattern and the second conductive pattern. The insulating pattern includes a central portion that overlaps with the opening and side portions that do not overlap with the opening, and The central portion protrudes further toward the third conductive pattern from at least one of the first and second conductive patterns than the side portions.

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