Wafer, chip and electronic equipment

Abstract

The invention provides a wafer, a chip and electronic equipment, which are used for solving the problem that a heat affected zone formed when an existing wafer is subjected to laser implicit cutting can cause adverse effects on the structure of the chip. The wafer provided by the invention comprises a first substrate layer, a doping layer and a functional layer which are stacked. Wherein the first substrate layer is located between the functional layer and the doped layer. According to the wafer provided by the invention, when the laser is emitted from one side, far away from the first substrate layer, of the doping layer and is focused on the first substrate layer to carry out laser implicit cutting on the wafer, the thermal conductivity of the wafer can be reduced by utilizing the doping layer, so that the extension length of a heat affected zone in the thickness direction of the wafer can be reduced, and the thermal conductivity of the wafer is improved in terms of angle. That is to say, the thickness of the first substrate layer can be greater than the length of the heat-affected zone, so that the heat-affected zone extends to the side, close to the doping layer, of the first substrate layer as much as possible, and the risk that the heat-affected zone is reversely diffused and extends to the functional layer to cause damage can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a wafer, chip, and electronic device. Background Technology

[0002] Chips are crucial components in electronic devices. Chip fabrication involves dicing wafers. Specifically, multiple chips are typically spaced apart on a wafer, and these chips are separated from each other through dicing and film spreading.

[0003] However, the heat-affected zone formed during laser dicing of existing wafers can adversely affect the chip structure. Summary of the Invention

[0004] This application provides a wafer, a chip, and an electronic device to address the problem that the heat-affected zone formed during laser dicing of existing wafers can adversely affect the structure of the chip.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a wafer comprising a first substrate layer, a doped layer, and a functional layer stacked together. The first substrate layer is located between the functional layer and the doped layer.

[0007] As the doping concentration of impurity elements in semiconductor materials increases, the lattice distortion of the semiconductor material intensifies, leading to increased phonon scattering and a decrease in phonon transport speed. Since phonons are the main carriers of heat transport in solids, the decrease in phonon transport speed will reduce the thermal conductivity of semiconductor materials.

[0008] In this way, when the wafer provided in the first aspect of this application is laser-cut, the laser beam enters from the side of the doped layer away from the first substrate layer and is focused in the first substrate layer to laser-cut the wafer. Since the impurity atoms in the doped layer can reduce the thermal conductivity of the wafer, and impurity clusters may be formed as the doping concentration increases, the thermal conductivity of the wafer will be further reduced. This can reduce the extension length of the heat-affected zone along the thickness direction of the wafer. In other words, it ensures that the thickness of the first substrate layer is greater than the length of the heat-affected zone, so that the heat-affected zone extends as close as possible to the side of the first substrate layer closer to the doped layer. This can reduce the risk of the heat-affected zone spreading backward to the functional layer (e.g., the functional layer is an active layer) and causing damage to it.

[0009] After laser slicing is completed, the doped layer can be removed by grinding. Then, the first substrate layer and the functional layer are cracked by a film expansion process to make multiple chips. The thickness of the obtained chips is further reduced compared to the existing technology.

[0010] In conjunction with the first aspect, in one possible implementation, the wafer further includes a dicing aid layer located on the side of the doped layer away from the first substrate layer. The dicing aid layer includes dicing bands and multiple non-dicing regions, the multiple non-dicing regions being spaced apart, with a dicing band formed between adjacent non-dicing regions. The dicing bands include a first region and a second region, the first region and the second region being distributed along the width direction of the dicing bands, and the doping concentration of the first region being greater than the doping concentration of the second region.

[0011] In this way, when laser dicing is performed on the wafer, the laser spot formed on the wafer surface is controlled to move along the dicing strip, thereby generating modified areas and controlled cracks at corresponding positions in the first substrate layer. This makes it easier to separate multiple chips by expanding the cracks in the subsequent film expansion process.

[0012] Furthermore, since the wavelength of the laser used in laser lithography is generally greater than 1100 nm, the energy of light with a wavelength greater than 1100 nm is insufficient to allow the bound electrons in the semiconductor material of the wafer to transition. Taking silicon as an example of the semiconductor material of the wafer, the band gap of silicon (i.e., the energy difference between the lowest energy level of the conduction band and the highest energy level of the valence band) is approximately 1.1 eV. The energy of light with a wavelength greater than 1100 nm is insufficient to allow the bound electrons in silicon to transition. However, when impurity elements are doped into silicon, the impurity atoms provide additional free electrons to silicon. These free electrons can raise the highest energy level of the valence band of silicon while keeping the lowest energy level of the conduction band unchanged, thereby narrowing the band gap of silicon to less than 1.1 eV. Alternatively, these free electrons can lower the lowest energy level of the conduction band of silicon while keeping the highest energy level of the valence band unchanged, thus also narrowing the band gap of silicon to less than 1.1 eV. At this point, the light energy with a wavelength greater than 1100nm is sufficient to cause the bound electrons in silicon to jump from the valence band to the conduction band. Since the doping concentration of the first region is greater than that of the second region, most of the laser light originally irradiating the surface of the first region will be absorbed by the first region, while only a very small portion of the laser light irradiating the surface of the second region will be absorbed by the second region. The vast majority will penetrate the second region to cut the wafer. That is, the cross-sectional area of ​​the laser beam entering the wafer is reduced in the physical dimension through the above structure (for ease of description, the diameter of the heat-affected zone in the cutting width direction will be referred to as its transverse diameter), thereby reducing the maximum transverse diameter of the heat-affected zone formed during laser slicing.

[0013] After wafer dicing, a dicing channel is formed that runs through the wafer along its thickness direction. At this time, the width of the dicing channel is actually equal to the maximum lateral diameter of the heat-affected zone. Therefore, reducing the maximum lateral diameter of the heat-affected zone also means reducing the width of the dicing channel. This allows the area ratio of the dicing channel on a single wafer to be reduced while keeping the wafer area unchanged, thereby increasing the chip area ratio and reducing the material cost per chip.

[0014] In conjunction with the first aspect, in another possible implementation, the doping concentration in the second region is zero. This ensures that a portion of the laser beam is absorbed only by the first region, while the remaining laser beam can pass entirely through the second region without being partially absorbed there, thus guaranteeing that all the energy of the remaining laser beam is used for wafer dicing.

[0015] In conjunction with the first aspect, in another possible implementation, the first region includes a first doped sub-region and a second doped sub-region, located on opposite sides of the second region along the width direction of the dicing strip. By positioning the first and second doped sub-regions on opposite sides of the second region, the thickness of the laser beam entering the wafer can be controlled by adjusting the width of the second region as needed, thus improving dicing accuracy.

[0016] In conjunction with the first aspect, another possible implementation involves the first region having the same doping type as the doped layer. Continuing with the example of silicon as the semiconductor material of the wafer, this way, the first region has the same doping type as the aforementioned doped layer (both are N-type or P-type doped). After wafer slicing, the doping of both the first region and the doped layer can be completed using the same or similar ion implanter, which simplifies the processing technology, improves production efficiency, and reduces processing costs.

[0017] In conjunction with the first aspect, in another possible implementation, the doping concentration of the first region is 10. 20 ~10 21 atoms / cm 3 In this way, by limiting the doping concentration of the first region to 10... 20 ~10 21 atoms / cm 3 This design ensures that the first region completely absorbs part of the laser light irradiating its surface, thereby reducing the size of the heat-affected zone in the width direction of the cutting strip, while also preventing excessively high impurity atom concentration from adversely affecting parameters such as the migration speed of photogenerated carriers in the semiconductor.

[0018] In conjunction with the first aspect, in another possible implementation, the doping concentration of the doped layer is 10. 14 ~10 15atoms / cm 3 In this way, by limiting the doping concentration of the doped layer to 10... 14 ~10 15 atoms / cm 3 This allows the doped layer to both reduce the extension length of the heat-affected zone from the laser focal point to the side of the wafer closer to the laser incident point during laser slicing, and also prevent the laser from being excessively absorbed when passing through the doped layer, thus ensuring that the laser still has enough energy to perform laser slicing on the first substrate layer after passing through the doped layer.

[0019] In conjunction with the first aspect, in another possible implementation, the wafer further includes a second substrate layer located on the side of the doped layer away from the first substrate layer. In this way, after slicing the cylindrical semiconductor material to obtain a wafer, an impurity element can be doped into the middle of the wafer via thermal diffusion or ion implantation to form a doped layer. The portions on either side of the doped layer that are not doped with pentavalent elements constitute the first and second substrate layers. Subsequently, during laser slicing of the wafer, the laser can enter from the side of the second substrate layer away from the doped layer and be focused onto the first doped layer, thereby creating modified regions and controlled cracks at corresponding locations in the first substrate layer.

[0020] In conjunction with the first aspect, in another possible implementation, along the thickness direction of the wafer, the thickness of the functional layer is h1, and the thickness of the dicing auxiliary layer is h3, where h3 ≥ h1. In this way, by making the thickness of the dicing auxiliary layer greater than or equal to the thickness of the functional layer, it is possible to ensure complete absorption of a portion of the laser in the first region, minimizing the possibility of a slight reduction in the maximum lateral diameter of the heat-affected zone due to laser transmission through the first region.

[0021] In conjunction with the first aspect, in another possible implementation, the thickness of the functional layer is h1 and the thickness of the doped layer is h2 along the thickness direction of the wafer, where h2 ≥ h1. In this way, by making the thickness of the doped layer greater than or equal to the thickness of the functional layer, the thickness of the first substrate layer can be minimized while keeping the total wafer thickness constant, thereby reducing the thickness of the final chip. Furthermore, the doped layer can still prevent the diffusion of the heat-affected zone along the wafer thickness direction.

[0022] Secondly, embodiments of this application provide another type of wafer, which includes a first substrate layer and a dicing auxiliary layer stacked together. The dicing auxiliary layer includes at least one dicing strip and a plurality of non-dicing regions, with adjacent non-dicing regions separated by the dicing strip. The dicing strip includes a first region and a second region distributed along its own width direction, and the doping concentration of the first region is greater than that of the second region.

[0023] The wafer provided in the second aspect of this application allows the laser to move along the cutting strip during laser dicing, thereby generating modified regions and controlled cracks at corresponding positions in the first substrate layer. This facilitates the separation of multiple chips by expanding the cracks through a subsequent film expansion process.

[0024] Furthermore, since the wavelength of the laser used in laser lithography is generally greater than 1100 nm, the energy of light with a wavelength greater than 1100 nm is insufficient to allow the bound electrons in the semiconductor material of the wafer to transition. Taking silicon as an example of the semiconductor material of the wafer, the band gap of silicon (i.e., the energy difference between the lowest energy level of the conduction band and the highest energy level of the valence band) is approximately 1.1 eV. The energy of light with a wavelength greater than 1100 nm is insufficient to allow the bound electrons in silicon to transition. However, when impurity elements are doped into silicon, the impurity atoms provide additional free electrons to silicon. These free electrons can raise the highest energy level of the valence band of silicon while keeping the lowest energy level of the conduction band unchanged, thereby narrowing the band gap of silicon to less than 1.1 eV. Alternatively, these free electrons can lower the lowest energy level of the conduction band of silicon while keeping the highest energy level of the valence band unchanged, thereby narrowing the band gap of silicon to less than 1.1 eV. At this point, the light energy with a wavelength greater than 1100nm is sufficient to cause the bound electrons in silicon to jump from the valence band to the conduction band. Since the doping concentration of the first region is greater than that of the second region, most of the laser light originally irradiating the surface of the first region will be absorbed by the first region, while only a very small portion of the laser light irradiating the surface of the second region will be absorbed by the second region. The vast majority will penetrate the second region to cut the wafer. That is, the cross-sectional area of ​​the laser beam entering the wafer is reduced in the physical dimension through the above structure (for ease of description, the diameter of the heat-affected zone in the cutting width direction will be referred to as its transverse diameter), thereby reducing the maximum transverse diameter of the heat-affected zone formed during laser slicing.

[0025] After wafer dicing, a dicing channel is formed that runs through the wafer along its thickness direction. At this time, the width of the dicing channel is actually equal to the maximum lateral diameter of the heat-affected zone. Therefore, reducing the maximum lateral diameter of the heat-affected zone also means reducing the width of the dicing channel. This allows the area ratio of the dicing channel on a single wafer to be reduced while keeping the wafer area unchanged, thereby increasing the chip area ratio and reducing the cost per chip.

[0026] In conjunction with the second aspect, in one possible implementation, the doping concentration in the second region is zero. This ensures that a portion of the laser beam is absorbed only by the first region, while the remaining laser beam can pass entirely through the second region without being partially absorbed there, thus guaranteeing that all the energy of the remaining laser beam is used for wafer dicing.

[0027] In conjunction with the second aspect, in another possible implementation, the first region includes a first doped sub-region and a second doped sub-region, located on opposite sides of the second region along the width direction of the dicing strip. By positioning the first and second doped sub-regions on opposite sides of the second region, the thickness of the laser beam entering the wafer can be controlled by adjusting the width of the second region as needed, thus improving dicing accuracy.

[0028] In conjunction with the second aspect, in another possible implementation, the doping concentration of the first region is 10. 20 ~10 21 atoms / cm 3 In this way, by limiting the doping concentration of the first region to 10... 20 ~10 21 atoms / cm 3 The design ensures that the first region can fully absorb part of the laser, thus reducing the lateral size of the heat-affected zone during laser slicing, while also preventing excessively high impurity atom concentration from adversely affecting parameters such as the migration speed of photogenerated carriers in the semiconductor.

[0029] In conjunction with the second aspect, in another possible implementation, the wafer also includes a functional layer located on the side of the first substrate layer away from the dicing aid layer. For example, the functional layer could be an active layer, facilitating the subsequent placement of various active devices within the chip on the active layer.

[0030] In conjunction with the second aspect, in another possible implementation, along the thickness direction of the wafer, the thickness of the functional layer is h1, and the thickness of the dicing auxiliary layer is h3, where h3 ≥ h1. In this way, by making the thickness of the dicing auxiliary layer greater than or equal to the thickness of the functional layer, it is possible to ensure complete absorption of a portion of the laser in the first region, minimizing the possibility of a slight reduction in the maximum lateral diameter of the heat-affected zone due to laser transmission through the first region.

[0031] Thirdly, embodiments of this application provide a chip, which is manufactured by cutting and expanding a wafer according to the first or second aspect described above.

[0032] Understandably, the beneficial effects that the chip described in the third aspect and any of its possible implementations can achieve can be referenced to the beneficial effects in the first aspect or the second aspect and any of its possible implementations, and will not be repeated here.

[0033] Fourthly, embodiments of this application provide an electronic device, which includes a substrate and the chip provided in the third aspect above, the chip being disposed on the substrate.

[0034] It is understood that the beneficial effects that the electronic device described in the fourth aspect and any possible implementation thereof can be referenced to the beneficial effects in the first aspect or the second aspect and any possible implementation thereof, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the overall structure of an electronic device provided in an embodiment of this application;

[0036] Figure 2 for Figure 1 Exploded view of the structure of electronic equipment in China;

[0037] Figure 3 A schematic cross-sectional view of a wafer provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of the heat-affected zone formed in the substrate during laser lithography.

[0039] Figure 5 A schematic cross-sectional view of another wafer provided in an embodiment of this application;

[0040] Figure 6 A schematic cross-sectional view of another wafer provided in an embodiment of this application;

[0041] Figure 7 The graph shows the relationship between laser transmittance and laser wavelength in monocrystalline silicon.

[0042] Figure 8 A schematic diagram of the heat-affected zone formed when a laser beam with a diameter of 10 μm is completely incident on a wafer;

[0043] Figure 9 A schematic cross-sectional view of another wafer provided in an embodiment of this application;

[0044] Figure 10 for Figure 9 A bottom view of the middle wafer;

[0045] Figure 11 A schematic diagram of the heat-affected zone after partial laser absorption in the first region;

[0046] Figure 12 for Figure 6 A bottom view of the wafer after it has been cut;

[0047] Figure 13 for Figure 9 A top view of the wafer after it has been cut;

[0048] Figure 14 This is a graph showing the relationship between doping concentration and the change in the bandgap of silicon.

[0049] Figure 15 A schematic cross-sectional view of another wafer provided in an embodiment of this application;

[0050] Figure 16 for Figure 15 A bottom view of the middle wafer;

[0051] Figure 17 For a laser beam with a diameter of 10μm Figure 15 A schematic diagram of the heat-affected zone formed during wafer dicing;

[0052] Figure 18 for Figure 15 A schematic diagram of the thickness of each layer in a wafer.

[0053] Figure label:

[0054] 01. Electronic device; 10. Display module; 20. Housing; 21. Back cover; 22. Mid-frame; 30. Camera module; 40. Circuit board; 50. Battery; 60a. Chip;

[0055] 60. Wafer; 601. Substrate; 602. Functional layer;

[0056] 61. First substrate layer; 62. Doped layer; 63. Second substrate layer;

[0057] 64. Cutting auxiliary layer; 64a. Cutting strip; 64b. Non-cutting region; 641. First region; 6411. First doped sub-region; 6412. Second doped sub-region; 642. Second region;

[0058] 100, Heat-affected zone; 101, First modified zone; 102, Second modified zone; 200, Cutting track; 300, Laser beam. Detailed Implementation

[0059] To make the purpose, technical solution, and advantages of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0060] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0061] In the description of the embodiments of this application, the term "at least one" refers to one or more, and "more than one" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, "joining" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the elements can rotate relative to each other after connection. "Sliding connection" refers to a connection where the elements can slide relative to each other after connection.

[0062] The directional terms mentioned in the embodiments of this application, such as "inner", "outer", "upper", "lower", "front", "rear", "left", "right", etc., are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0063] In the description of embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0064] This application provides an electronic device 01. Specifically, the electronic device 01 can be a portable electronic device or other types of electronic devices. For example, the electronic device can be a mobile phone, a tablet personal computer, a personal digital assistant (PDA), a monitor, a wearable device, etc. For ease of explanation, the following description uses a mobile phone as an example for the electronic device 01.

[0065] Please see Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of the overall structure of the electronic device 01 provided in the embodiments of this application. Figure 2 For the above Figure 1 An exploded view of the structure of electronic device 01. As described above, in this embodiment, electronic device 01 is a mobile phone, and electronic device 01 can have an approximately rectangular plate-like structure. Electronic device 01 may include a display module 10, a housing 20, a camera module 30, a circuit board 40, a battery 50, a chip 60a, and a substrate. It is understood that... Figure 1 and Figure 2 The electronic device 10 is shown only schematically, and the actual shape, size, location, and construction of these components are not subject to change. Figure 1 and Figure 2 Restrictions.

[0066] The aforementioned display module 10 is used to display images, videos, etc. The aforementioned camera module 30 is used to capture videos or images. The aforementioned housing 20 is used to protect the electronic components inside the electronic device 01. The housing 20 may include a back cover 21 and a middle frame 22, with the middle frame 22 located between the display module 10 and the back cover 21. The back cover 21 is fixed to the middle frame 22, and the display module 10 can be glued to the middle frame 22, so that the display module 10, the back cover 21, and the middle frame 22 form an internal accommodating space for the electronic device 01, within which the aforementioned circuit board 40, battery 50, camera module 30, chip 60a, and substrate are all disposed.

[0067] The aforementioned chip 60a is disposed on a substrate, wherein the substrate may be a packaging substrate, such as a wire bonding packaging substrate, a flip-chip packaging substrate, etc.

[0068] The aforementioned circuit board 40 is used to house the chip 60a, substrate, and other electronic components of the electronic device 01, and to realize electrical connections between various electronic components. The battery 50 is electrically connected to the circuit board 40 to supply power to the various electronic components. For example, the chip 60a can be a central processing unit (CPU), a system-on-chip (SOC), a graphics processing unit (GPU), etc.

[0069] Based on this, during the fabrication of the aforementioned chip 60a, the wafer 60 needs to be laser stealth dicing (hereinafter referred to as laser dicing) to separate the multiple chips 60a on the wafer 60. For ease of description below, an XYZ coordinate system is established, defining one radial direction of the wafer 60 as the X-axis direction, the other radial direction of the wafer 60 as the Y-axis direction, and the thickness direction of the wafer 60 as the Z-axis direction.

[0070] Please see Figure 3 and Figure 4 As shown, Figure 3 This is a schematic cross-sectional view (parallel to the XZ plane) of a wafer 60 provided in an embodiment of this application. Figure 4 This is a schematic diagram of the heat-affected zone 100 formed in the substrate 601 during laser lithography.

[0071] The wafer 60 may include a substrate 601 and a functional layer 602 stacked along the Z-axis. For example, the functional layer 602 may be an active layer used to house various active devices in the chip 60a. The following description uses the functional layer 602 as an example of an active layer.

[0072] The laser slicing process involves focusing a laser beam 300 onto a substrate 601 and then moving it along a specified path to create a modified region (the modified region refers to the area formed by significant changes in the structure and properties of the semiconductor material within the heat-affected zone 100 during laser slicing) and controlled cracks within the substrate 601, extending along the thickness direction of the wafer 60. The cracks are then expanded through a film expansion process to separate multiple chips 60a.

[0073] It is understood that the material of wafer 60 can be semiconductor materials such as germanium, single-crystal silicon, silicon carbide, and gallium nitride, and this application does not impose any special limitations on this. The following example uses silicon as the material of wafer 60 for illustration.

[0074] To achieve silicon modification, the local temperature of the substrate 601 of wafer 60 must reach at least the melting point of silicon, 1690 K. The heat-affected region 100 includes a first modification region 101 and a second modification region 102.

[0075] During laser concealment cutting, at the laser focal point ( Figure 4 A high-temperature region is formed around the midpoint A), with the temperature near the focal point reaching up to 20,000 K. At this temperature, some silicon near the focal point will evaporate instantly, forming tiny voids. This void region can be called the first modified region 101. Subsequently, the high-temperature region will extend and diffuse along the thickness direction of the wafer 60. Due to the characteristics of laser slicing, the high-temperature region will only extend a short distance towards the functional layer 602. The high-temperature region will mainly diffuse and extend a longer distance towards the side of the substrate 601 away from the functional layer 602. The silicon in the high-temperature region that has diffused away from the functional layer 602 will first melt and then recrystallize. This part of the substrate 601 that has melted and recrystallized can be called the second modified region 102.

[0076] Theoretically, silicon in regions with temperatures above the melting point of silicon will melt and recrystallize to form polycrystalline silicon. However, due to the excessive instantaneous temperature rise in the first modified region 101 (reaching 1000 K / s), a large temperature difference is generated before the formation of the second modified region 102, resulting in a compressive stress of 12 GPa. This stress inhibits the melting and recrystallization of silicon in the first modified region 101, so most of the structure in the first modified region 101 remains single-crystal. Subsequently, the compressive stress, along with the thermal shock generated by evaporation, propagates to the side away from the functional layer 602, forming a high-level polycrystalline structure in the second modified region 102.

[0077] Please continue reading Figure 4 As shown, taking a laser beam 300 with a diameter of 10 μm as an example, the longitudinal range (also known as the length L) of the heat-affected zone 100 formed during cutting extends approximately 30 μm along the Z-axis from the focal point away from the functional layer 602. The lateral range is a circular area with a maximum radius of 10 μm, centered on the focal point, within a cross-section parallel to the XY plane. Furthermore, along the Z-axis, the radius of the lateral range first increases and then decreases, meaning that the heat-affected zone 100 is generally elliptical or teardrop-shaped.

[0078] However, when the aforementioned wafer 60 is laser-cut, the heat-affected zone 100 formed is relatively large, which may have an adverse effect on the structure of the chip 60a.

[0079] For example, when the wafer 60 is laser-cut, the thickness H of the substrate 601 must be greater than the length L of the heat-affected zone 100. This results in a larger thickness of the manufactured chip 60a, which is not conducive to the miniaturization of the chip 60a. If the thickness H of the substrate 601 is less than or equal to the length L of the heat-affected zone, the heat-affected zone 100 may diffuse and extend along the thickness direction of the wafer 60 (parallel to the Z-axis) to the functional layer 602, causing damage to the function of the functional layer 602.

[0080] To address the aforementioned technical problems, this application provides another wafer 60, please refer to [link to relevant documentation]. Figure 5 As shown, Figure 5 This is a cross-sectional schematic diagram (parallel to the XZ plane) of another wafer 60 provided in an embodiment of this application. The wafer 60 includes a first substrate layer 61, a doped layer 62, and the aforementioned functional layer 602, which are stacked together. The first substrate layer 61 is located between the doped layer 62 and the functional layer 602.

[0081] It is understood that the doped layer 62 can be either P-type or N-type doped, and this application does not impose any special limitations on it. P-type doping refers to the addition of a small amount of trivalent elements (such as boron, aluminum, gallium, etc.) to the semiconductor material. N-type doping refers to the addition of a small amount of pentavalent elements (such as phosphorus, arsenic, etc.) to the semiconductor material. The doping element in the doped layer 62 can be one type or multiple types.

[0082] As the doping concentration of impurity elements in semiconductor materials increases, the lattice distortion of the semiconductor material intensifies, leading to increased phonon scattering and a decrease in phonon transport speed. Since phonons are the main carriers of heat transport in solids, the decrease in phonon transport speed will reduce the thermal conductivity (or thermal conductivity) of semiconductor materials.

[0083] In this way, when the wafer 60 provided in this embodiment undergoes laser dicing, the laser beam 300 enters from the side of the doped layer 62 away from the first substrate layer 61 and is focused in the first substrate layer 61 to perform laser dicing on the wafer 60. Since the impurity atoms in the doped layer 62 can reduce the thermal conductivity of the wafer 60, and impurity clusters may be formed as the doping concentration increases, the thermal conductivity of the wafer 60 is further reduced, thereby reducing the extension length of the heat-affected region 100 from the laser focal point towards the doped layer 62. In other words, it ensures that the thickness of the first substrate layer 61 is greater than the length L of the heat-affected region 100, so that the heat-affected region 100 extends as close as possible to the side of the first substrate layer 61 closer to the doped layer 62, thereby reducing the risk of the heat-affected region 100 diffusing backwards to the functional layer 602 and causing functional damage.

[0084] After laser slicing, the doped layer 62 can be removed by grinding. Then, a crack propagation process is used to extend the first substrate layer 61 and the functional layer 602 to fabricate multiple chips 60a. The thickness of the resulting chips 60a is compared to the above... Figure 4 The chip 60a in the middle is further thinned.

[0085] In some embodiments, the doping concentration of the doped layer 62 may be 10. 14 ~10 15 atoms / cm 3 For example, the doping concentration of doped layer 62 can be 1.0 × 10⁻⁶. 14 atoms / cm 3 1.1×10 14 atoms / cm 3 2.5×10 14 atoms / cm 3 5.0×10 14 atoms / cm 3 8.5×10 14 atoms / cm 3 9.9×10 14 atoms / cm 3 1.0×10 15 atoms / cm 3 wait.

[0086] In this way, by limiting the doping concentration of the doped layer 62 to 10 14 ~10 15 atoms / cm 3 This allows the doped layer 62 to both reduce the extension length L of the heat-affected zone 100 from the laser focal point to the doped layer 62 during laser slicing and prevent excessive absorption of the laser when passing through the doped layer 62, ensuring that the laser still has enough energy to perform laser slicing on the first substrate layer 61 after passing through the doped layer 62.

[0087] Further, please see Figure 6 As shown, Figure 6 This is a cross-sectional schematic diagram (parallel to the XZ plane) of another wafer 60 provided in an embodiment of this application. The wafer 60 may further include a second substrate layer 63. The second substrate layer 63 is located on the side of the doped layer 62 away from the first substrate layer 61. In this way, after the cylindrical semiconductor material is sliced ​​to obtain the wafer 60, an impurity element can be doped into the middle of the wafer 60 by thermal diffusion or ion implantation to form a doped layer 62. The portions on both sides of the doped layer 62 in the wafer 60 that are not doped with pentavalent elements are the first substrate layer 61 and the second substrate layer 63.

[0088] When performing laser slicing on wafer 60, laser beam 300 can be injected from the side of the second substrate layer 63 away from the doped layer 62 and focused on the first substrate layer 61, thereby generating modified regions and controlled cracks at corresponding positions in the first substrate layer 61. Subsequently, the doped layer is removed by grinding 62, and then the cracks are propagated in the first substrate layer 61 and the functional layer 602 through a film expansion process to fabricate multiple chips 60a.

[0089] Since the semiconductor material in 60-mesh wafers is generally single-crystal silicon, and the band gap of silicon (i.e., the energy difference between the lowest energy level of the conduction band and the highest energy level of the valence band) is approximately 1.1 eV, light with wavelengths greater than 1100 nm is insufficient to allow the bound electrons in silicon to undergo transitions. Please see [link to relevant documentation]. Figure 7 As shown, Figure 7 This is a graph showing the relationship between laser transmittance and laser wavelength in single-crystal silicon. The horizontal axis represents the laser wavelength, and the vertical axis represents transmittance. From... Figure 7 As can be seen, when the wavelength of the laser is greater than 1100nm, the transmittance of the laser in single-crystal silicon can reach more than 50%.

[0090] Furthermore, in laser concealed cutting technology, the minimum diameter of the laser beam generated by the laser source is generally only 10 μm. Please refer to [link / reference needed]. Figure 8 As shown, Figure 8This is a schematic diagram showing a 10μm diameter laser beam 300 completely penetrating the heat-affected zone 100 formed in the wafer 60. It can be seen that the maximum lateral diameter d of the heat-affected zone 100 formed by the 10μm diameter laser beam 300 in the wafer 60 is much larger than the diameter of the laser beam 300, typically reaching 20μm. However, after the wafer 60 is diced, a dicing channel 200 is formed that penetrates the wafer 60 along its thickness direction. At this point, the width of the dicing channel 200 is actually equal to the maximum lateral diameter d of the heat-affected zone 100. This results in the dicing channel 200 being too wide, occupying a large area on the wafer 60, leading to fewer chips 60a that can be manufactured from a single wafer 60, and higher material costs per chip 60a.

[0091] For the reasons mentioned above, please refer to Figure 9 and Figure 10 As shown, Figure 9 This is another cross-sectional schematic diagram of a wafer 60 provided in an embodiment of this application (parallel to the XZ plane). Figure 10 for Figure 9 Bottom view of wafer 60 (along the positive Z-axis).

[0092] The wafer 60 may further include a dicing aid layer 64. The dicing aid layer 64 is located on the side of the second substrate layer 63 away from the doped layer 62. The dicing aid layer 64 includes a dicing strip 64a and a plurality of non-dicing regions 64b, which are spaced apart, with a dicing strip 64a formed between adjacent non-dicing regions 64b. The dicing strip 64a includes a first region 641 and a second region 642 distributed along its width direction, and the doping concentration of the first region 641 is greater than the doping concentration of the second region 642.

[0093] It is understood that the aforementioned cutting strip 64a has a length direction, a width direction, and a thickness direction, with the length direction of the cutting strip 64a being its extension direction (i.e., in...). Figure 9 and Figure 10 (parallel to the Y-axis direction), the thickness direction of the dicing strip 64a is also the thickness direction of the wafer 60 (i.e., in...). Figure 9 and Figure 10 The width direction of the cutting strip 64a is perpendicular to its length and thickness directions (i.e., in the direction parallel to the Z-axis). Figure 9 and Figure 10 (Parallel to the X-axis direction).

[0094] The aforementioned cutting strip 64a can be set as one or more. The number of cutting strips 64a and their distribution position on the cutting auxiliary layer 64 can be specifically selected according to the required number, size and shape of chips 60a. This application does not make any special limitations in this regard.

[0095] In this way, when laser dicing is performed on wafer 60, the laser spot formed on the surface of wafer 60 is controlled to move along the dicing strip 64a, thereby generating modified regions and controlled cracks at corresponding positions in the first substrate layer 61. This facilitates the separation of multiple chips 60a by expanding the cracks in the subsequent film expansion process.

[0096] Furthermore, when impurity elements are doped into silicon, the impurity atoms provide additional free electrons to the silicon. These free electrons can raise the highest energy level of the valence band while keeping the lowest energy level of the conduction band unchanged, thus narrowing the band gap of silicon to less than 1.1 eV. Alternatively, these free electrons can lower the lowest energy level of the conduction band while keeping the highest energy level of the valence band unchanged, thus narrowing the band gap of silicon to less than 1.1 eV.

[0097] At this point, please continue to see Figure 10 , and in conjunction with see Figure 11 As shown, Figure 11 This is a schematic diagram of a heat-affected zone 100 formed after a laser beam 300 with a diameter of 10 μm is partially absorbed by the first region 641. The energy of light with a wavelength greater than 1100 nm is sufficient to cause bound electrons in silicon to transition from the valence band to the conduction band. Since the doping concentration of the first region 641 is greater than that of the second region 642, most of the laser light originally irradiating the surface of the first region 641 will be absorbed by the first region 641, while only a very small portion of the laser light irradiating the surface of the second region 642 will be absorbed by the second region 642. The vast majority will penetrate the second region 642 to cut the wafer 60. That is, the cross-sectional area of ​​the laser beam 300 entering the wafer 60 is reduced in the physical dimension by the above structure (i.e., the maximum cross-sectional size of the laser beam 300 in the wafer 60 can be less than 10 μm), thereby reducing the maximum lateral diameter d of the heat-affected zone 100 formed during laser dicing to less than 20 μm in the X-axis direction. Figure 10 The shaded area in the image represents the laser beam 300 remaining after being partially absorbed by the first region 641. It can be seen that after absorption by the first region 641, the maximum size of the laser beam 300 entering the wafer 60 in the X-axis direction is only about half of the original size.

[0098] After wafer 60 is cut, a dicing channel 200 is formed that runs through wafer 60 along its thickness direction. At this time, the width of the dicing channel 200 is actually equal to the maximum lateral diameter d of the heat-affected zone 100. Therefore, the reduction of the maximum lateral diameter d of the heat-affected zone 100 also means the reduction of the width of the dicing channel 200. This allows the area ratio of the dicing channel 200 on a single wafer 60 to be reduced while keeping the area of ​​wafer 60 unchanged, thereby increasing the area ratio of chip 60a and reducing the cost of a single chip 60a.

[0099] Furthermore, while ensuring that the doping concentration of the first region 641 is greater than that of the second region 642, the doping concentration of the second region 642 should be as small as possible. Ideally, the doping concentration of the second region 642 should be zero. This ensures that a portion of the laser beam 300 is absorbed only by the first region 641, while the remaining laser beam 300 can pass entirely through the second region 642 without being partially absorbed thereafter. In other words, it ensures that all the energy of the remaining laser beam 300 is used to dicing the wafer 60.

[0100] Understandably, in actual production, the total thickness of the wafer 60 remains unchanged before the doped layer 62 and the second substrate layer 63 are removed by grinding. The aforementioned dicing auxiliary layer 64 was originally part of the second substrate layer 63. The dicing auxiliary layer 64 can be formed by injecting impurity ions into a designated position of the second substrate layer 63.

[0101] For example, please see Figure 12 As shown, Figure 12 for Figure 6 The image shows a bottom view (along the positive Z-axis) of wafer 60 after dicing. It can be seen that without the dicing aid layer 64 on wafer 60, the resulting dicing channel 200 is relatively wide, and its area on wafer 60 accounts for a large proportion of the total area. Figure 12 The wafer 60 can ultimately be cut into 4 rectangular chips 60a with the required area.

[0102] Please see Figure 13 As shown, Figure 13 for Figure 9 The image shows a bottom view (along the positive Z-axis) of wafer 60 after dicing. It can be seen that after adding the dicing aid layer 64 to wafer 60, the width of the dicing path 200 formed after dicing is significantly reduced. Figure 13 The wafer 60 can ultimately be cut into six rectangular chips 60a with the required area, i.e. Figure 13 The material cost of a single 60a chip is only Figure 12 Two-thirds of the size of a single 60a chip.

[0103] Please see Figure 14 The above, Figure 14 This is a graph showing the relationship between doping concentration and the change in silicon bandgap. The horizontal axis represents the doping concentration, and the vertical axis represents the change in silicon bandgap ΔE. G ΔE G Specifically, it refers to the difference between the band gap of silicon before and after doping. From... Figure 14 As can be seen from this, as the doping concentration increases to 10... 20 ~10 21 atoms / cm 3 ΔEG The bandgap of silicon was increased from 50 meV to 200 meV, meaning that the bandgap of silicon decreased from 1.1 eV to 0.9 eV after doping, thus enabling the absorption of laser light with a wavelength of 1100 nm.

[0104] Therefore, in this embodiment, the doping concentration of the first region 641 can be 10. 20 ~10 21 atoms / cm 3 For example, the doping concentration of the first region 641 can be 1.0 × 10⁻⁶. 20 atoms / cm 3 1.1×10 20 atoms / cm 3 2.5×10 20 atoms / cm 3 5.0×10 20 atoms / cm 3 8.5×10 20 atoms / cm 3 9.9×10 20 atoms / cm 3 1.0×10 21 atoms / cm 3 wait.

[0105] In this way, by limiting the doping concentration of the first region 641 to 10 20 ~10 21 atoms / cm 3 This design ensures that the first region 641 completely absorbs part of the laser light irradiating its surface, thereby reducing the size of the heat-affected zone 100 in the width direction of the cutting strip 64a, while also preventing excessively high impurity atom concentration from adversely affecting parameters such as the migration speed of photogenerated carriers in the semiconductor.

[0106] It should be noted that the first region 641 in the aforementioned cutting auxiliary layer 64 can be either N-type doped or P-type doped. That is, the first region 641 can be doped with pentavalent elements (such as phosphorus, arsenic, etc.) or trivalent elements (such as boron, aluminum, gallium, etc.). Provided that the doping concentration is within the aforementioned range, both N-type doping and P-type doping can achieve partial absorption of laser light; therefore, this application does not impose any special limitations on this.

[0107] When the first region 641 has the same doping type as the doped layer 62, after the wafer 60 is sliced, the doping of the first region 641 in the doped layer 62 and the dicing auxiliary layer 64 can be completed by the same or similar ion implanter, which helps to simplify the processing technology, improve production efficiency and reduce processing costs.

[0108] Please see Figure 15 and Figure 16 As shown, Figure 15 This is another cross-sectional schematic diagram of a wafer 60 provided in an embodiment of this application (parallel to the XZ plane). Figure 16 for Figure 15 A bottom view of the middle wafer 60 (along the positive Z-axis). The first region 641 may include a first doped sub-region 6411 and a second doped sub-region 6412. Along a direction parallel to the X-axis, the first doped sub-region 6411 and the second doped sub-region 6412 are located on opposite sides of the second region 642.

[0109] In this way, the first doped sub-region 6411 and the second doped sub-region 6412 are respectively set on both sides of the second region 642. Thus, the thickness of the laser beam 300 entering the wafer 60 can be controlled by adjusting the width of the second region 642 along the X-axis direction, which is beneficial to improving the cutting accuracy. Figure 16 The shaded area in the image represents the laser beam 300 remaining after being partially absorbed by the first doped sub-region 6411 and the second doped sub-region 6412. It can be seen that after absorption by the first doped sub-region 6411 and the second doped sub-region 6412, the maximum size of the laser beam 300 entering the wafer 60 in the X-axis direction is only about one-third of the original size.

[0110] It is understood that the width of the first doped sub-region 6411 and the width of the second doped sub-region 6412 can be the same (i.e., the width of the first doped sub-region 6411 and the width of the second doped sub-region 6412 are symmetrically arranged about the second region 642) or different along the direction parallel to the X-axis. This application does not make any special limitation in this regard.

[0111] The first doped sub-region 6411 and the second doped sub-region 6412 can both be N-type doped or both be P-type doped. Alternatively, the first doped sub-region 6411 can be N-type doped and the second doped sub-region 6412 can be P-type doped. Or, the first doped sub-region 6411 can be P-type doped and the second doped sub-region 6412 can be N-type doped. Therefore, this application does not impose any special limitations in this regard.

[0112] The doping concentrations of the first doped sub-region 6411 and the second doped sub-region 6412 can be the same or different, as long as the doping concentrations of the first doped sub-region 6411 and the second doped sub-region 6412 are respectively within the doping concentration range of the aforementioned first region 641.

[0113] In addition, when the doping type of the first doped sub-region 6411 and the second doped sub-region 6412 is the same, the same-valent impurity elements contained in the first doped sub-region 6411 and the second doped sub-region 6412 may be the same or different, and this application does not make any special limitation in this regard.

[0114] For example, please refer to [link to previous page]. Figure 15 As shown, Figure 15 In the wafer 60 shown, the doped layer 62 and the first doped sub-region 6411 and the second doped sub-region 6412 in the auxiliary dicing layer are both N-type doped, and the doped impurity element is phosphorus. The doping concentration of the doped layer 62 is 8.5 × 10¹⁴ atoms / cm². 3 The doping concentration of both the first doped sub-region 6411 and the second doped sub-region 6412 is 5.0 × 10¹⁴ atoms / cm². 3 .

[0115] Please see Figure 17 As shown, Figure 17 300 pairs of laser beams with a diameter of 10 μm Figure 15 A schematic diagram of the heat-affected zone 100 formed during the dicing of the wafer 60. By utilizing the absorption of laser light by the first doped sub-region 6411 and the second doped sub-region 6412, the width of the dicing track 200 (i.e., the maximum lateral diameter d of the heat-affected zone 100) can be reduced to 10 μm.

[0116] In some embodiments, see Figure 18 As shown, Figure 18 for Figure 15 A schematic diagram of the thicknesses of each layer in wafer 60. Along the thickness direction of wafer 60 (parallel to the Z-axis), the thickness of the functional layer 602 is h1, and the thickness of the doped layer 62 is h2, where h2 ≥ h1. In this way, by making the thickness of the doped layer 62 greater than or equal to the thickness of the functional layer 602, the thickness of the first substrate layer 61 can be minimized while keeping the total thickness of wafer 60 constant, thereby reducing the thickness of the final chip 60a. Furthermore, the doped layer 62 can still prevent the diffusion of the heat-affected zone 100 along the thickness direction of wafer 60.

[0117] Furthermore, along the thickness direction of wafer 60 (parallel to the Z-axis), the thickness of the aforementioned dicing auxiliary layer 64 is h3, where h3 ≥ h1. The thickness h3 of the dicing auxiliary layer 64 and the thickness h2 of the doped layer 62 may or may not be equal.

[0118] In this way, by making the thickness of the cutting auxiliary layer 64 greater than or equal to the thickness of the functional layer 602, it is possible to ensure that the first region 641 completely absorbs part of the laser, and to avoid the situation where the maximum lateral diameter of the heat-affected zone 100 is not significantly reduced due to the laser passing through the first region 641.

[0119] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer, characterized in that, It includes a first substrate layer, a doped layer, and a functional layer stacked together; The first substrate layer is located between the functional layer and the doped layer.

2. The wafer according to claim 1, characterized in that, The wafer further includes a dicing aid layer, which is located on the side of the doped layer away from the first substrate layer; The cutting auxiliary layer includes a cutting strip and multiple non-cutting areas, the multiple non-cutting areas are spaced apart, and the cutting strip is formed between two adjacent non-cutting areas; The dicing strip includes a first region and a second region, which are distributed along the width direction of the dicing strip, and the doping concentration of the first region is greater than that of the second region.

3. The wafer according to claim 2, characterized in that, The doping concentration in the second region is zero.

4. The wafer according to claim 2 or 3, characterized in that, The first region includes a first doped sub-region and a second doped sub-region, and the first doped sub-region and the second doped sub-region are located on both sides of the second region along the width direction of the cut strip.

5. The wafer according to any one of claims 2 to 4, characterized in that, The first region has the same doping type as the doped layer.

6. The wafer according to any one of claims 2 to 5, characterized in that, The doping concentration of the first region is 10. 20 ~10 21 atoms / cm 3 .

7. The wafer according to any one of claims 1 to 6, characterized in that, The doping concentration of the doped layer is 10. 14 ~10 15 atoms / cm 3 .

8. The wafer according to any one of claims 1 to 7, characterized in that, The wafer also includes a second substrate layer located on the side of the doped layer away from the first substrate layer.

9. The wafer according to any one of claims 2 to 8, characterized in that, Along the thickness direction of the wafer, the thickness of the functional layer is h1, and the thickness of the dicing auxiliary layer is h3, wherein h3 ≥ h1.

10. The wafer according to any one of claims 1 to 9, characterized in that, Along the thickness direction of the wafer, the thickness of the functional layer is h1, and the thickness of the doped layer is h2, wherein h2 ≥ h1.

11. A wafer, characterized in that, It includes a first substrate layer and a dicing aid layer stacked together; The cutting auxiliary layer includes a cutting strip and multiple non-cutting areas, the multiple non-cutting areas are spaced apart, and the cutting strip is formed between two adjacent non-cutting areas; The cut strip includes a first region and a second region distributed along its own width direction, and the doping concentration of the first region is greater than that of the second region.

12. The wafer according to claim 11, characterized in that, The doping concentration in the second region is zero.

13. The wafer according to claim 11 or 12, characterized in that, The first region includes a first doped sub-region and a second doped sub-region, and the first doped sub-region and the second doped sub-region are located on both sides of the second region along the width direction of the cut strip.

14. The wafer according to any one of claims 11 to 13, characterized in that, The doping concentration of the first region is 10. 20 ~10 21 atoms / cm 3 .

15. The wafer according to any one of claims 11 to 14, characterized in that, The wafer also includes a functional layer located on the side of the first substrate layer away from the dicing aid layer.

16. The wafer according to claim 15, characterized in that, Along the thickness direction of the wafer, the thickness of the functional layer is h1, and the thickness of the dicing auxiliary layer is h3, wherein h3 ≥ h1.

17. A chip, characterized in that, The chip is manufactured by wafer cutting and film expansion as described in any one of claims 1 to 16.

18. An electronic device, characterized in that, The electronic device includes a substrate and the chip of claim 17, wherein the chip is disposed on the substrate.

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