Semiconductor package including detection pattern and method of manufacturing same

Abstract

A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package may include: a first semiconductor wafer having a first width; a second semiconductor wafer on the first semiconductor wafer, the second semiconductor wafer having a second width less than the first width; and a molding layer at least partially covering a side surface of the second semiconductor wafer and a top surface of the first semiconductor wafer, where the first semiconductor wafer includes at least one first detection pattern on the top surface of the first semiconductor wafer and in contact with a bottom surface of the molding layer.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0106013, filed on August 8, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least some example embodiments relate to a semiconductor package including a pattern detection method and / or a method of manufacturing the semiconductor package. Background Technology

[0004] Semiconductor packages are configured to facilitate the use of integrated circuit chips as components in electronic products. Traditionally, a semiconductor package may include a printed circuit board (PCB) and a semiconductor chip wafer mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, much research is underway to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] At least some exemplary embodiments of the present invention relate to a semiconductor package with improved reliability.

[0006] At least some exemplary embodiments of the present invention relate to a method for increasing yield in a process for manufacturing semiconductor packages.

[0007] According to some exemplary embodiments of the present invention, a semiconductor package may include:

[0008] A first semiconductor wafer having a first width; a second semiconductor wafer located on the first semiconductor wafer, the second semiconductor wafer having a second width less than the first width; and a molding layer that at least partially covers the side surface of the second semiconductor wafer and the top surface of the first semiconductor wafer, wherein the first semiconductor wafer includes at least one first detection pattern located on the top surface of the first semiconductor wafer and in contact with the bottom surface of the molding layer.

[0009] According to some exemplary embodiments of the present invention, a semiconductor package may include: a first semiconductor wafer having a first width; a second semiconductor wafer located on the first semiconductor wafer, the second semiconductor wafer having a second width less than the first width; and a molding layer that at least partially covers the side surface of the second semiconductor wafer and the top surface of the first semiconductor wafer, wherein the second semiconductor wafer includes at least one detection pattern located on the top surface of the second semiconductor wafer.

[0010] According to some example embodiments of the inventive concept, a semiconductor package can include a first semiconductor die having a first width and including first connection pads located at an upper portion of the first semiconductor die, external connection terminals bonded to a bottom surface of the first semiconductor die, a second semiconductor die located on the first semiconductor die, the second semiconductor die having a second width smaller than the first width and including second connection pads located at a lower end of the second semiconductor die and respectively in contact with the first connection pads, and a molding layer at least partially covering side surfaces of the second semiconductor die and a top surface of the first semiconductor die, wherein the first semiconductor die includes at least one first detection pattern located on the top surface of the first semiconductor die and in contact with a bottom surface of the molding layer, a reflectivity of the first detection pattern is different from a reflectivity of the top surface of the first semiconductor die, and the first detection pattern has a triangular, trapezoidal, or rectangular cross-section.

[0011] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor package can include manufacturing a wafer including device regions and separation regions between the device regions, bonding first semiconductor dies to the device regions of the wafer, forming detection patterns in the separation regions and in at least one of the first semiconductor dies, forming a molding layer at least partially covering the wafer and the first semiconductor dies, performing a chemical mechanical polishing (CMP) process on the molding layer and the first semiconductor dies to partially remove the molding layer and the first semiconductor dies, and performing a singulation process to remove the separation regions and the molding layer on the separation regions, wherein the CMP process is performed using a CMP apparatus, and the CMP apparatus is configured to detect an end point using the detection patterns. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1A-1C is a plan view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0013] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1A .

[0014] Figure 3A and Figure 4A are enlarged cross-sectional views illustrating a portion "P1" of Figure 2 .

[0015] Figure 3B and Figure 4B are enlarged cross-sectional views illustrating a portion "P2" of Figure 2 .

[0016] Figures 5A-5G are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package of Figure 2 .

[0017] Figure 6 is a diagram illustrating a CMP apparatus according to some example embodiments of the inventive concepts.

[0018] Figure 7A is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0019] Figure 7B is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to some example embodiments of the inventive concepts. Figure 7A

[0020] Figure 8A is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0021] Figure 8B is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to some example embodiments of the inventive concepts. Figure 8A

[0022] Figure 9A is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0023] Figure 9B is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to some example embodiments of the inventive concepts. Figure 9A

[0024] Figure 10 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0025] Figure 11 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0026] Figure 12 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0027] Figure 13 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0028] Figure 14 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0029] Figure 15 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts.

[0030] Figure 16 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0031] ​​​Example embodiments of the present inventive concepts will now be described more fully with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements throughout the various drawings. Like numbers also indicate general consistency in positioning of members throughout the several embodiments of the structures described. It will be understood that, although the terms first, second, etc. can be used herein to describe various elements / regions / components, these elements / regions / components should not be limited by these terms since such elements / regions / components should be understood as being capable of comprising, consisting of or consisting essentially of several members, regions or components. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting.

[0032] Figures 1A-1C is a plan view showing a semiconductor package according to some example embodiments of the present inventive concepts. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1A .

[0033] Referring to Figure 1A and Figure 2 , a semiconductor package 1000 according to some example embodiments can include a first semiconductor wafer 100, a second semiconductor wafer 200, and a molding layer MD. In this specification, the term "semiconductor wafer" can be referred to as "semiconductor chip". The first semiconductor wafer 100 can have a first width W1 in a first direction X1. The second semiconductor wafer 200 can have a second width W2 smaller than the first width W1 in the first direction X1.

[0034] The first semiconductor wafer 100 can be or include a logic circuit chip, an application specific integrated circuit (ASIC) chip, and / or a memory chip (e.g., a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip). The first semiconductor wafer 100 can include a first substrate 10, a first interlayer insulating layer IL1, a back surface insulating layer 12, first interconnection lines 5, first bonding pads 7, first connection pads CP1, a through-via member TV, a via insulating layer TL, and a first detection pattern DP1. The first substrate 10 can be or include a semiconductor wafer formed of a semiconductor material (e.g., silicon), a silicon-on-insulator (SOI) wafer, and / or an insulating wafer. The first substrate 10 can include a front surface 10a and a back surface 10b opposite to each other. Although not shown, a plurality of first transistors can be disposed on the front surface 10a of the first substrate 10.

[0035] The first interlayer insulating layer IL1 can be disposed on the front surface 10a of the first substrate 10. The first interlayer insulating layer IL1 can be formed of silicon oxide, silicon nitride, silicon oxynitride, SiOCH, and SiCN

[0036] The first interconnection line 5 can be formed of at least one of doped polysilicon and metal materials (e.g., aluminum, tungsten, titanium, and copper) and can have, for example, a single layer or a multi-layer structure. The first interconnection line 5 having a multi-layer structure can be disposed in the first interlayer insulating layer IL1. The first interconnection line 5 can be formed of at least one of doped polysilicon and metal materials (e.g., aluminum, tungsten, titanium, and copper). The first interconnection line 5 and the first transistor can be used to constitute various circuits.

[0037] The first bonding pad 7 can be disposed at a lower portion of the first interlayer insulating layer IL1. The first bonding pad 7 can be connected to the first interconnection line 5. The first bonding pad 7 can be formed of at least one of metal materials (e.g., aluminum, tungsten, titanium, and copper). The outer connection terminal OB can be bonded to the first bonding pad 7, respectively. The outer connection terminal OB can include at least one of a conductive bump and a solder ball. The outer connection terminal OB can be formed of or include at least one of metal materials (e.g., copper, nickel, tin, and silver).

[0038] The back surface 10b of the first substrate 10 can be covered or at least partially covered by a back surface insulating layer 12. The back surface insulating layer 12 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and SiCN and can have a single layer or a multi-layer structure. The first connection pad CP1 can be disposed at an upper portion of the back surface insulating layer 12. The first connection pad CP1 can be formed of or include at least one of metal materials (e.g., copper).

[0039] A through-via member TV can be disposed to penetrate (e.g., at least partially extend through) the first substrate 10, a portion of the first interlayer insulating layer IL1, and a portion of the back surface insulating layer 12 to connect the first connection pad CP1 to some of the first interconnection line 5. The through-via member TV can be formed of or include at least one of metal materials (e.g., copper, tungsten, and titanium). A via insulating layer TL can be interposed between the through-via member TV and the first substrate 10. The via insulating layer TL can be formed of, for example, silicon oxide.

[0040] Referring to Figure 1AAt least one first detection pattern DP1 can be provided at the edge and / or the corner of the first semiconductor wafer 100. The first detection pattern DP1 can have the same shape and size, or can have different shapes and sizes. The first detection pattern DP1 can include a 1st a detection pattern DP1(a) and a 1st b detection pattern DP1(b). The 1st a detection pattern DP1(a) can be provided at the corner of the first semiconductor wafer 100, respectively. The 1st b detection pattern DP1(b) can be provided between the corners of the first semiconductor wafer 100. The planar and / or cross-sectional shape of the 1st a detection pattern DP1(a) and the 1st b detection pattern DP1(b) can be different. For example, the 1st a detection pattern DP1(a) can have an arc shape or a sector shape when viewed in a plan view. The 1st b detection pattern DP1(b) can have a semicircular shape when viewed in a plan view. At least one of the 1st a detection pattern DP1(a) can have a third width W3 in the first direction X1. At least one of the 1st b detection pattern DP1(b) can have a fourth width W4 in the first direction X1. The fourth width W4 can be different from the third width W3. For example, the fourth width W4 can be greater than the third width W3.

[0041] Referring to Figure 1B and Figure 1C , the first detection pattern DP1 can be provided only at the corner of the first semiconductor wafer 100. The first detection pattern DP1 can have an arc shape or a sector shape when viewed in a plan view, as shown in Figure 1B . Alternatively, the first detection pattern DP1 can have a rectangular shape when viewed in a plan view, as shown in Figure 1C . However, example embodiments are not limited thereto.

[0042] Figure 3A and Figure 4A are enlarged cross-sectional views showing a portion "P1" of Figure 2 .

[0043] Referring to Figure 2 , Figure 3A and Figure 4AThe top surface DP1_U of the first detection pattern DP1 can be in contact with the molding layer MD. The top surface DP1_U of the first detection pattern DP1 can be coplanar with the top surface 100_U of the first semiconductor wafer 100. The first detection pattern DP1 can be disposed to penetrate (e.g., at least partially extend through) the backside insulating layer 12 of the first semiconductor wafer 100. The first detection pattern DP1 can further extend and can be inserted into the first substrate 10. The first detection pattern DP1 can be placed in the first trench TC1 formed in (e.g., at least partially defined by) the side surface of the first semiconductor wafer 100. The inner surface of the first trench TC1 can be inclined at an angle. The first detection pattern DP1 can have a triangular cross-section. The width of the first detection pattern DP1 can decrease as the vertical level decreases. The side surface DP1_S of the first detection pattern DP1 can be vertically aligned (e.g., coplanar) with the side surface MD_S of the molding layer MD. The side surface DP1_S of the first detection pattern DP1 can be vertically aligned (e.g., coplanar) with the side surface 100_S of the first semiconductor wafer 100.

[0044] The reflectivity of the top surface DP1_U of the first detection pattern DP1 can be different from the reflectivity of the top surface 100_U of the first semiconductor wafer 100. In some example embodiments, the characteristics of the top surface DP1_U of the first detection pattern DP1 can be different from the characteristics of the top surface 100_U of the first semiconductor wafer 100. For example, the top surface DP1_U of the first detection pattern DP1 can have a hydrophobic characteristic (e.g., be hydrophobic or substantially hydrophobic), and the top surface 100_U of the first semiconductor wafer 100 can have a hydrophilic characteristic (e.g., be hydrophilic or substantially hydrophilic). The coefficient of friction of the top surface DP1_U of the first detection pattern DP1 can be different from the coefficient of friction of the top surface 100_U of the first semiconductor wafer 100.

[0045] In Figure 3A example embodiments, the first detection pattern DP1 can be formed of or include a material different from the backside insulating layer 12. The first detection pattern DP1 can include, for example, a resin layer or a polymer layer. As Figure 4A indicated, the first detection pattern DP1 can include a first insulating pattern 11, a first diffusion protection pattern 13, and a first metal pattern 15, which are sequentially stacked. The first insulating pattern 11 can be formed of or include, for example, silicon oxide. The diffusion protection pattern 13 can be formed of at least one of Ti, TiN, Ta, and TaN. The first metal pattern 15 can be formed of at least one of a metal material (e.g., aluminum, copper, or tungsten). The first diffusion protection pattern 13 can also be referred to as a “first diffusion prevention pattern” 13 or a “first diffusion reduction pattern” 13, but the function of the pattern 13 should be understood as not being limited thereto.

[0046] Referring back to Figure 1A and Figure 2 , the second semiconductor wafer 200 can be a logic circuit chip, an application specific integrated circuit (ASIC) chip, or a memory chip (e.g., a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip). The second semiconductor wafer 200 can include a second substrate 20, a second interlayer insulating layer IL2, and at least one second detection pattern DP2. The second substrate 20 can be or include a semiconductor wafer formed of or including a semiconductor material (e.g., silicon), a silicon-on-insulator (SOI) wafer, and / or an insulating wafer. The second substrate 20 can include a front surface 20a and a back surface 20b opposite to each other.

[0047] Figure 3B and Figure 4B is an enlarged cross-sectional view showing a portion "P2" of Figure 2 .

[0048] Referring to Figure 2 and Figure 3B , a plurality of second transistors TR can be disposed on the front surface 20a of the second substrate 20. A device isolation portion STI can be disposed in the front surface 20a of the second substrate 20 to define an active region of the second transistor TR. The device isolation portion STI can be formed of or include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and can have a single layer or a multi-layer structure. The second interlayer insulating layer IL2 can be disposed on the front surface 20a of the second substrate 20. The second interlayer insulating layer IL2 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, SiOCH, and SiCN, and can have a single layer or a multi-layer structure. The second interconnection line 22 having a multi-layer structure can be disposed in the second interlayer insulating layer IL2. The second interconnection line 22 can be formed of or can include at least one of doped polysilicon and a metal material (e.g., aluminum, tungsten, titanium, and copper). The second interconnection line 22 and the second transistor can be used to constitute various circuits.

[0049] The second connection pads CP2 can be disposed at the bottom of the second interlayer insulating layer IL2. The second connection pads CP2 can be formed of or include at least one of metal materials (e.g., copper). The second connection pads CP2 can be connected to some of the second interconnection lines 22. The second connection pads CP2 can be in contact with the first connection pads CP1, respectively. In case that the second connection pads CP2 and the first connection pads CP1 are formed of the same material, there can be no interface therebetween, but example embodiments are not limited thereto.

[0050] At least one second detection pattern DP2 can be disposed at the top of the second semiconductor wafer 200. The second detection patterns DP2 can have the same shape and size, or can have different shapes and sizes. In some example embodiments, a plurality of second detection patterns DP2 can be disposed, and the plurality of second detection patterns DP2 can be spaced apart from each other, as shown in Figures 1A-1C When viewed in a plan view, the second detection patterns DP2 can have a circular shape, as shown in Figure 1A and Figure 1B , or can have a rectangular shape, as shown in Figure 1C , but example embodiments are not limited thereto. The second detection patterns DP2 can have a fifth width W5 in the first direction X1. The fifth width W5 can be different from the third width W3 and / or the fourth width W4. For example, the fifth width W5 can be smaller than the third width W3 and / or the fourth width W4.

[0051] Referring to Figure 2 , Figure 3B and Figure 4B , the second detection patterns DP2 can be disposed in the second substrate 20 of the second semiconductor wafer 200. A top surface DP2_U of the second detection patterns DP2 can be coplanar or substantially coplanar with a back surface 20b of the second substrate 20. The back surface 20b of the second substrate 20 can correspond to a top surface of the second semiconductor wafer 200. The second detection patterns DP2 can be placed in a second trench TC2 formed in the back surface 20b of the second substrate 20. An inner surface of the second trench TC2 can be inclined at an angle. The second detection patterns DP2 can have a triangular cross-section. The width of the second detection patterns DP2 can decrease as the vertical level decreases. However, example embodiments are not limited thereto.

[0052] The reflectivity of the top surface DP2_U of the second detection pattern DP2 may differ from the reflectivity of the rear surface 20b of the second substrate 20. In some example embodiments, the characteristics of the top surface DP2_U of the second detection pattern DP2 may differ from the characteristics of the rear surface 20b of the second substrate 20. For example, the top surface DP2_U of the second detection pattern DP2 may be hydrophobic, and the rear surface 20b of the second substrate 20 may be hydrophilic. The coefficient of friction of the top surface DP2_U of the second detection pattern DP2 may differ from the coefficient of friction of the rear surface 20b of the second substrate 20.

[0053] exist Figure 3B In some embodiments, the second detection pattern DP2 may include, for example, a resin layer or a polymer layer. In some example embodiments, such as... Figure 4B As shown, the second detection pattern DP2 may include a second insulating pattern 21, a second diffusion protection pattern 23, and a second metal pattern 25 stacked sequentially. The second insulating pattern 21 may be formed of silicon oxide. The second diffusion protection pattern 23 may be formed of at least one material (e.g., Ti, TiN, Ta, and TaN), or may include at least one material (e.g., Ti, TiN, Ta, and TaN). The second metal pattern 25 may be formed of at least one metallic material (e.g., aluminum, copper, or tungsten). The second diffusion protection pattern 23 may also be referred to as a "second diffusion prevention pattern" 23 or a "second diffusion reduction pattern" 23, but the function of pattern 23 should be understood to be limited thereto.

[0054] The molding layer MD can be formed of a material with high light transmittance. For example, the molding layer MD can be formed of or include, for example, silicon oxide. In some example embodiments, the molding layer MD may include an insulating resin (e.g., epoxy molding compound (EMC)). The molding layer MD may also include fillers dispersed in the insulating resin. The fillers can be formed of or include, for example, silicon oxide (SiO2), but the example embodiments are not limited thereto.

[0055] In some example embodiments, since the semiconductor package 1000 includes a first detection pattern DP1 and / or a second detection pattern DP2, the endpoint of the chemical mechanical polishing (CMP) process on the second substrate 20 and the molding layer MD can be detected during the manufacturing process of the semiconductor package 1000. Therefore, the semiconductor package 1000 can be manufactured with a desired thickness. This reduces the thickness variation of the semiconductor package 1000 and improves its reliability.

[0056] Figures 5A-5G The manufacturing process is shown sequentially. Figure 2 A cross-sectional view of a method for developing semiconductor packaging components. Figure 6 This is a diagram illustrating some example embodiments of a CMP device according to the present invention.

[0057] Referring to Figure 5A A first wafer WF1 can be prepared. The first wafer WF1 can include a plurality of device regions DR and separation regions SR between the device regions DR. In each of the device regions DR, the first wafer WF1 can have the same or similar structure as the first semiconductor wafer 100 described with reference to Figure 1A and Figure 2 The first wafer WF1 can include the first substrate 10, the first interlayer insulating layer IL1, the back surface insulating layer 12, the first interconnection line 5, the first bonding pad 7, the first connection pad CP1, the through-via member TV, and the via insulating layer TL. The outer connection terminal OB can be bonded to the first bonding pad 7. The first wafer WF1 can be attached to the first carrier substrate CR1 using a sacrificial adhesive layer AL1 interposed between the first wafer WF1 and the first carrier substrate CR1. The sacrificial adhesive layer AL1 can be formed of or include a thermosetting resin or a photocurable resin, for example, but example embodiments are not limited thereto.

[0058] Referring to Figure 5A and Figure 5B A second semiconductor wafer 200 can be prepared. Each of the second semiconductor wafers 200 can include the second substrate 20, the second interlayer insulating layer IL2, and the second connection pad CP2. Here, the second substrate 20 can have the first thickness TH1. The second semiconductor wafers 200 can be placed on the device regions DR of the first wafer WF1, respectively, and then, a thermal compression process can be performed to bond the second semiconductor wafers 200 to the device regions DR of the first wafer WF1, respectively. Accordingly, the first connection pad CP1 can be bonded to the second connection pad CP2, respectively. The top surface of the back surface insulating layer 12 can be bonded to the bottom surface of the second interlayer insulating layer IL2.

[0059] Referring to Figure 5C A first etching process can be performed to form (e.g., define) first trenches TC1 in the top surface of the first wafer WF1. A second etching process can be performed to form (e.g., define) second trenches TC2 in the back surface of the second substrate 20. The first etching process and the second etching process can be performed simultaneously or sequentially. The first trenches TC1 and the second trenches TC2 can be formed to have the same shape and the same depth. Alternatively, the first trenches TC1 and the second trenches TC2 can be formed to have different shapes and different depths from each other. The first trenches TC1 can be formed on the separation regions SR.

[0060] Referring to Figure 5D First detection patterns DP1 can be formed in the first trenches TC1, respectively, and second detection patterns DP2 can be formed in the second trenches TC2, respectively. As in the first semiconductor wafer 100 described with reference to Figure 3A and Figure 3BIn some embodiments related thereto, the first and second detection patterns DP1 and DP2 can be formed of or include a resin and / or a polymer layer. Alternatively, as in the embodiments related to Figure 4A and Figure 4B In example embodiments related thereto, the first and second detection patterns DP1 and DP2 can be formed to include at least one of the insulating patterns 11 and 21, the diffusion protection patterns 13 and 23, and the metal patterns 15 and 25. The first and second detection patterns DP1 and DP2 can differ from adjacent patterns in optical reflection or surface characteristics (e.g., hydrophobicity, hydrophilicity, friction coefficient, etc.).

[0061] Referring to Figure 5E and Figure 6 A molding layer MD can be formed on the first wafer WF1. The molding layer MD can be formed of silicon oxide or an epoxy molding compound. The first wafer WF1 covered with or at least partially covered with the molding layer MD can be referred to as a wafer structure WS. A CMP process can be performed to remove a portion of the molding layer MD and a portion of the second substrate 20. Accordingly, the second substrate 20 can have a second thickness TH2. The second thickness TH2 can be less than Figure 5A the first thickness TH1. The CMP process can include loading the wafer structure WS on a CMP device 2000.

[0062] Referring to Figure 5E and Figure 6 The CMP device 2000 can include a rotation unit 1600 for supporting and compressing the wafer structure WS, a polishing pad 1500 in contact with a surface of the wafer structure WS, a rotation plate 1520 configured to rotate together with the polishing pad 1500 attached thereto, a conditioner 1800 for restoring a surface state of the polishing pad 1500, and a slurry supply nozzle 1700 configured to supply a CMP slurry to the polishing pad 1500. The CMP device 2000 can include a motor 1610 that transmits a rotational power to the rotation unit 1600 and a first controller 1620 that senses and controls a driving state of the motor 1610. An optical waveguide 1502 can be disposed in the polishing pad 1500 and can be configured to allow transmission of light L1 and L2. An optical generation / sensing sensor 1501 can be disposed in the rotation plate 1520 and can be configured to generate the first light L1 and transmit the first light L1 to the wafer structure WS through the optical waveguide 1502, and sense the second light L2 reflected from the wafer structure WS. A second controller 1510 can be disposed in the rotation plate 1520 and can be used to control the optical generation / sensing sensor 1501.

[0063] Referring to Figure 5EThe first and second detection patterns DP1 and DP2 described can be provided in the wafer structure WS. The wafer structure WS can be flipped and can be fixed to a bottom surface of the rotation unit 1600, and then a CMP process can be performed on a surface of the wafer structure WS by bringing the surface of the wafer structure WS into close contact with the polishing pad 1500, rotating the rotation unit 1600 and the rotation plate 1520, and supplying a CMP slurry through the slurry supply nozzle 1700. In the CMP process, the detection patterns DP1 and DP2 can be used as an endpoint of the CMP process.

[0064] For example, during the CMP process, the first light L1 generated by the light generation / sensing sensor 1501 can be reflected from the surface of the detection patterns DP1 and DP2, and a portion of the first light L1 can be returned as the second light L2. As the thickness of the mold layer MD is reduced by the CMP process, the light transmittance of the mold layer MD can be increased. Accordingly, the intensity of the second light L2 reflected by the first detection pattern DP1 can be increased, which can make it possible to accurately measure the thickness of the mold layer MD. Accordingly, the endpoint of the CMP process can be detected and determined.

[0065] In some example embodiments, as a portion of the second substrate 20 is gradually removed by the polishing or grinding process, the second detection pattern DP2 can also be gradually removed. Accordingly, the upper surface area of the second detection pattern DP2 can be reduced, and thus the amount of the second light L2 reflected by the top surface of the second detection pattern DP2 can be gradually reduced. Accordingly, the remaining thickness of the second substrate 20 can be estimated (e.g., accurately estimated). Accordingly, the endpoint of the CMP process can be detected and determined.

[0066] In some example embodiments, the top surface of the second detection pattern DP2 can have a hydrophobic property, and the second substrate 20 can have a hydrophilic property. Here, when both the second detection pattern DP2 and the second substrate 20 are polished, as the second detection pattern DP2 can be gradually removed during the polishing process, the top surface of the second semiconductor wafer 200 can have only the hydrophilic property, and this can result in a change in the amount of current of the electric motor 1610 that rotates the rotation unit 1600. For example, in the case where the top surface of the second semiconductor wafer 200 has the hydrophobic property, the amount of current of the electric motor 1610 that rotates the rotation unit 1600 can relatively increase to normally perform the polishing process. In contrast, in the case where the top surface of the second semiconductor wafer 200 has the hydrophilic property, the amount of current of the electric motor 1610 that rotates the rotation unit 1600 can relatively decrease. By sensing the change in the amount of current of the electric motor 1610, the endpoint of the CMP process can be detected and determined.

[0067] Referring to Figure 5E and Figure 5FAs described above, the difference in surface reflection or surface state between the first detection pattern DP1 and the second detection pattern DP2 can be used to detect and determine the endpoint of the CMP process. Therefore, the CMP process can be... Figure 5E It terminates precisely at the first level LV1. In this case, as... Figure 5F As shown, a significant portion of the second detection pattern DP2 can be removed, leaving only a portion. In other example embodiments, the CMP process can... Figure 5E The detection terminates at the second level LV2. In this case, the second detection pattern DP2 can be completely removed and may not be left behind.

[0068] Reference Figure 5G The first wafer WF1 can be separated from the sacrificial adhesive layer AL1 and the first carrier substrate CR1. Then, a monolithic process can be performed to cut the separation region SR of the first wafer WF1 and the molding layer MD thereon. Thus, semiconductor packages 1000 and 1005 can be manufactured. The first detection pattern DP1 can also be cut by the monolithic process. The first detection pattern DP1 can remain partially within the semiconductor packages 1000 and 1005.

[0069] In a method for manufacturing a semiconductor package according to some exemplary embodiments of the present invention, the second substrate 20 may be manufactured to have a uniform and desired thickness (e.g., TH2), and thus the total thickness of semiconductor packages 1000 and 1005 may be controlled to have a uniform value, or substantially a uniform value. Therefore, process defects and / or yield may be reduced.

[0070] Figure 7A This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention.

[0071] Reference Figures 1A-4B In a semiconductor package 1001 according to some exemplary embodiments of the present invention, the first detection pattern DP1 and the second detection pattern DP2 may have trapezoidal shapes that are different from each other. Each of the first detection pattern DP1 and the second detection pattern DP2 may have a width that decreases as the vertical level decreases. The height of the first detection pattern DP1 may be greater than the height of the second detection pattern DP2. In addition to the features described above, the semiconductor package may be configured to have a reference shape. Figure 7B The semiconductor package described has the same, substantially the same, or similar features as one of the semiconductor packages.

[0072] Figure 7A It shows the manufacturing process. Figure 7B A cross-sectional view of the process of a semiconductor package.

[0073] Reference Figure 5D In reference Figure 5EIn the process described above, the first detection pattern DP1 and the second detection pattern DP2 can be formed to have the same trapezoidal shape. Next, the reference Figure 5F CMP process in the process described above. Then, subsequent processes of Figure 5G and Figure 7A may be performed to manufacture the semiconductor package of Figure 8A .

[0074] Figures 1A-4B is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0075] Referring to Figure 8B , in the semiconductor package 1002 according to some example embodiments of the inventive concept, the first detection pattern DP1 and the second detection pattern DP2 can have different rectangular shapes from each other. The height of the first detection pattern DP1 can be greater than the height of the second detection pattern DP2. The width of the first detection pattern DP1 can be greater than the width of the second detection pattern DP2. Except for the above features, the semiconductor package can be configured to have the same, substantially the same, or similar features to one of the semiconductor packages described with reference to Figure 8A .

[0076] Figure 8B is a cross-sectional view illustrating a process of manufacturing a semiconductor package of Figure 5D .

[0077] Referring to Figure 5E , in the process described above with reference to Figure 5F , the first detection pattern DP1 and the second detection pattern DP2 can be formed to have the same rectangular shape. Next, the reference Figure 5G CMP process in the process described above. Then, subsequent processes of Figure 8A and Figure 9A may be performed to manufacture the semiconductor package of Figure 2 .

[0078] Figure 9B is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0079] Referring to Figure 9A , according to some example embodiments of the inventive concept, the first detection pattern DP1 can be omitted in the semiconductor package 1003. The semiconductor package 1003 can include only one second detection pattern DP2. Except for the above features, the semiconductor package can be configured to have the same, substantially the same, or similar features to one of the semiconductor packages described with reference to Figure 9B .

[0080] Figure 5Dis a cross-sectional view illustrating a process of manufacturing a semiconductor package. Figure 5E

[0081] Referring to Figure 5F , in the process described with reference to Figure 5G , the second semiconductor wafer 200 can be formed to include the second detection pattern DP2 and the third detection pattern DP3 spaced apart from each other. The second detection pattern DP2 and the third detection pattern DP3 can be formed to have shapes and heights different from each other. For example, the second detection pattern DP2 can have a triangular cross-section, and the third detection pattern DP3 can have a trapezoidal shape. A fourth level LV4 of a bottom end of the second detection pattern DP2 can be lower than a fifth level LV5 of a bottom end of the third detection pattern DP3. Next, the CMP process in the process described with reference to Figure 9A may be terminated at a first level LV1. The first level LV1 can be higher than the fourth level LV4, and can be lower than the fifth level LV5. In this case, as a result of the CMP process, the third detection pattern DP3 can be completely removed, and a portion of the second detection pattern DP2 can be left. Then, subsequent processes of Figure 10 and Figure 10 may be performed to manufacture the semiconductor package Figures 1A-4B .

[0082] Figure 5E is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0083] Referring to Figure 10 , the semiconductor package 1004 according to some example embodiments of the inventive concept can include the first detection pattern DP1, and the second detection pattern DP2 can be omitted from the semiconductor package 1004. Except for the above-described features, the semiconductor package can be configured to have features identical, substantially identical, or similar to one of the semiconductor packages described with reference to Figure 11 . When the CMP process in the steps of Figure 11 stops at the second level LV2, the semiconductor package 1004 can be manufactured. Figures 1A-4B

[0084] Figure 5F is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0085] Referring to Figure 5G , the semiconductor package 1005 according to some example embodiments of the inventive concept can include one first detection pattern DP1 and two second detection patterns DP2. Except for the above-described features, the semiconductor package can be configured to have features substantially identical or similar to one of the semiconductor packages described with reference to Figure 11 . After the singulation process, the two second detection patterns DP2 can be located at a first side of the semiconductor package 1005, and the first detection pattern DP1 can be located at a second side of the semiconductor package 1005.​​Figure 12 and Figure 12 the device region DR at the edge of the first wafer WF1 can be used as Figures 1A-4B the semiconductor package 1005.

[0086] Figure 13 is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0087] Referring to Figure 13 , the semiconductor package 1006 according to some example embodiments of the inventive concept can include only one first detection pattern DP1. Except for the above-mentioned features, the semiconductor package can be configured to have the same, substantially the same, or similar features to one of the semiconductor packages described with reference to Figure 12 .

[0088] Figure 5G is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0089] Referring to Figure 13 , the semiconductor package 1007 according to some example embodiments of the inventive concept can have the same or substantially the same structure as the semiconductor package 1006 of Figure 14 except that the first detection pattern DP1 is not present. In this case, the first trench TC1 can be formed in the upper side surface of the first semiconductor wafer 100. The first trench TC1 can be formed to expose the bottom surface of the molding layer MD. When the first detection pattern DP1 is separated from the first semiconductor wafer 100 in the singulation process of Figure 14 , the semiconductor package 1007 of Figure 2 can be manufactured.

[0090] Figures 1A-4B is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0091] Referring to Figure 15 , the semiconductor package 1008 according to some example embodiments of the inventive concept can have substantially the same structure as the semiconductor package 1000 of Figure 15 except that the first detection pattern DP1 is absent. Except for the above-mentioned features, the semiconductor package can be configured to have the same, substantially the same, or similar features to one of the semiconductor packages described with reference to Figure 2 .

[0092] Figures 1A-4B is a cross-sectional view illustrating a semiconductor package according to some example embodiments of the inventive concept.

[0093] Referring to Figures 1A-4BThe semiconductor package 1009, according to some exemplary embodiments of the present invention, may have the same characteristics as... Figures 1A-4B The semiconductor package 1000 has the same or substantially the same structure as the package substrate PB, except that the package substrate PB is located in the position of the first semiconductor wafer 100. The package substrate PB can be a double-sided or multilayer printed circuit board or a redistributed substrate. The package substrate PB may include a substrate body portion 300, an upper photo-imaging insulating layer 320, and a lower photo-imaging insulating layer 310. When the package substrate PB is a printed circuit board, the substrate body portion 300 may be formed or include at least one of thermosetting resin (e.g., epoxy resin), thermoplastic resin (e.g., polyimide), and composite material (e.g., prepreg), in which reinforcing elements (e.g., glass fiber and / or inorganic filler) are pre-impregnated with a thermoplastic resin matrix or a thermosetting resin matrix, or a photocurable resin, but the inventive concept is not limited to these examples. The upper photo-imaging insulating layer 320 and the lower photo-imaging insulating layer 310 may be formed of photoresist (PSR) material. When the packaging substrate PB is a redistributed substrate or includes a redistributed substrate, the substrate body portion 300, the upper light imaging insulating layer 320, and the lower light imaging insulating layer 310 may be formed of a photoimaging dielectric (PID) material, but the example embodiment is not limited thereto.

[0094] The package substrate PB may further include an upper substrate pattern 317, a lower substrate pattern 307, an internal interconnect line IT, and a first detection pattern DP1. The internal interconnect line IT connects the upper substrate pattern 317 to the lower substrate pattern 307. The upper substrate pattern 317, the lower substrate pattern 307, and the internal interconnect line IT may be formed of at least one metallic material (e.g., copper). An external connection terminal OB may be coupled to the lower substrate pattern 307. The first detection pattern DP1 may be configured to have a reference... Figure 16 The features in the described example embodiments are substantially the same or similar. The first detection pattern DP1 may be disposed along the edge and / or one or more corners of the package substrate PB.

[0095] The second semiconductor wafer 200 can be mounted on the package substrate PB. The second semiconductor wafer 200 can be configured to have the same characteristics as the reference. Figure 16Features in the described embodiments are substantially the same or similar to features in one of the described semiconductor packages. The internal connection members IB can be inserted between the second connection pads CP2 of the second semiconductor wafer 200 and the upper substrate pattern 317 of the package substrate PB. The internal connection members IB can be or include conductive bumps and / or solder balls. The internal connection members IB can be formed of, for example, SnAg, but example embodiments are not limited thereto. The space between the package substrate PB and the second semiconductor wafer 200 can be filled with an underfill layer UF. The underfill layer UF can include a thermosetting resin or a photo-curable resin. In addition, the underfill layer UF can further include an organic filler or an inorganic filler. In addition to the above features, the semiconductor package can be configured to have features substantially the same as or similar to those of the semiconductor package described with reference to Figures 1A-14 Features in the described semiconductor package are substantially the same or similar to features in one of the described semiconductor packages.

[0096] Figures 1A-16 is a cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concepts.

[0097] Referring to ​ A semiconductor package 1010 according to some example embodiments of the inventive concepts can include second to fifth semiconductor wafers 200a, 200b, 200c, and 200d and first to fourth mold layers MD1 to MD4 sequentially stacked on a first semiconductor wafer 100. The width of the first semiconductor wafer 100 can be greater than the width of each of the second to fifth semiconductor wafers 200a, 200b, 200c, and 200d. The side surfaces of the second to fifth semiconductor wafers 200a, 200b, 200c, and 200d can be aligned with each other (e.g., coplanar).

[0098] The first semiconductor wafer 100 can be a different type of chip from the second to fifth semiconductor wafers 200a, 200b, 200c, and 200d. The first semiconductor wafer 100 can be, for example, a logic circuit chip or a buffer wafer. The second to fifth semiconductor wafers 200a, 200b, 200c, and 200d can be or include the same type of memory chip, but example embodiments are not limited thereto. The memory chip can be, for example, one of a DRAM, a NAND flash, an SRAM, an MRAM, a PRAM, and an RRAM chip. The present drawing illustrates a structure in which one logic circuit chip and four memory chips are stacked, but the number of stacked logic circuit chips and memory chips is not limited thereto and can vary differently. The first semiconductor wafer 100 can be wider than the second to fifth semiconductor wafers 200a, 200b, 200c, and 200d. The semiconductor package 1010 can be a high bandwidth memory (HBM) chip.

[0099] The first to fourth molding layers MD1 to MD4 can cover the top surface of the first semiconductor wafer 100 and the side surfaces of the second to fifth semiconductor wafers 200a, 200b, 200c, and 200d. A top surface of the fourth molding layer MD4 can be coplanar with a back surface of the fifth semiconductor wafer 200d.

[0100] The first semiconductor wafer 100 can include a first substrate 10, a first interlayer insulating layer IL1, first interconnection lines 5, a first bonding pad 7, a third connection pad CP3, a through-via member TV, a via insulating layer TL, and a first detection pattern DP1. A back surface of the first substrate 10 can be covered or at least partially covered by a first back surface insulating layer OL1. The third connection pad CP3 can be disposed in the first back surface insulating layer OL1. The first back surface insulating layer OL1 can cover an entire back surface of the first substrate 10.

[0101] The second semiconductor wafer 200a and the first molding layer MD1 can be disposed on the first semiconductor wafer 100. The second semiconductor wafer 200a can include a second substrate 20, a second interlayer insulating layer IL2, second interconnection lines 22, a fourth connection pad CP4, the third connection pad CP3, the through-via member TV, the via insulating layer TL, and a second detection pattern DP2. The fourth connection pad CP4 can be located at a bottom of the second interlayer insulating layer IL2. A back surface 20b of the second substrate 20 of the second semiconductor wafer 200a can be covered or at least partially covered by a second back surface insulating layer OL2. The third connection pad CP3 can be disposed in the second back surface insulating layer OL2. The second back surface insulating layer OL2 can extend to cover a top surface of the first molding layer MD1.

[0102] The third semiconductor wafer 200b and the second molding layer MD2 can be disposed on the second back surface insulating layer OL2. The third semiconductor wafer 200b can include the second substrate 20, the second interlayer insulating layer IL2, the second interconnection lines 22, the fourth connection pad CP4, the third connection pad CP3, the through-via member TV, the via insulating layer TL, and the second detection pattern DP2. The fourth connection pad CP4 can be located at a bottom of the second interlayer insulating layer IL2. A back surface 20b of the second substrate 20 of the third semiconductor wafer 200b can be covered or at least partially covered by a third back surface insulating layer OL3. The third connection pad CP3 can be disposed in the second back surface insulating layer OL2. The third back surface insulating layer OL3 can extend to cover a top surface of the second molding layer MD2.

[0103] A fourth semiconductor wafer 200c and a third molding layer MD3 can be disposed on a third back surface insulation layer OL3. The fourth semiconductor wafer 200c can include a second substrate 20, a second interlayer insulation layer IL2, a second interconnection line 22, a fourth connection pad CP4, a third connection pad CP3, a through-via member TV, a via insulation layer TL, and a second detection pattern DP2. The fourth connection pad CP4 can be located in a bottom of the second interlayer insulation layer IL2. A back surface 20b of the second substrate 20 of the fourth semiconductor wafer 200c can be covered or at least partially covered by a fourth back surface insulation layer OL4. The third connection pad CP3 can be disposed in the second back surface insulation layer OL2. The fourth back surface insulation layer OL4 can extend to cover a top surface of the third molding layer MD3.

[0104] A fifth semiconductor wafer 200d and a fourth molding layer MD4 can be disposed on the fourth back surface insulation layer OL4. The fifth semiconductor wafer 200d can include the second substrate 20, the second interlayer insulation layer IL2, the second interconnection line 22, the fourth connection pad CP4, and a third detection pattern DP3. The fourth connection pad CP4 can be located in a bottom of the second interlayer insulation layer IL2.

[0105] The first detection pattern DP1, the second detection pattern DP2, and the third detection pattern DP3 can have different shapes and sizes. For example, the first detection pattern DP1 can have a different shape from the second detection pattern DP2 and the third detection pattern DP3. A width and a height of the third detection pattern DP3 can be greater than a width and a height of the first detection pattern DP1 and the second detection pattern DP2.

[0106] Each of the first back surface insulation layer OL1 to the fourth back surface insulation layer OL4 can be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and SiCN, and can have a single layer or a multi-layer structure. Each of the first back surface insulation layer OL1 to the fourth molding layer MD4 can be formed of or include silicon oxide and / or an epoxy resin molding compound, but example embodiments are not limited thereto. In a case where the first back surface insulation layer OL1 to the fourth back surface insulation layer OL4 and the first molding layer MD1 to the fourth molding layer MD4 are formed of the same material (e.g., silicon oxide), an interface therebetween can not be visible or observable, and they can be observed as a single object, but example embodiments are not limited thereto. In addition to the above-described features, the semiconductor package can be configured to have the same, substantially the same features as one of the semiconductor packages described with reference to FIGS. 1 to 6. ​ The semiconductor package described with reference to FIGS. 7 to 10 can have the same, substantially the same features as one of the semiconductor packages described with reference to FIGS. 1 to 6.

[0107] In the semiconductor package and the method of manufacturing a semiconductor package according to some example embodiments of the inventive concept, a detection pattern can be provided in at least one of a wafer and a semiconductor wafer, and can be used to detect (e.g., accurately detect) an endpoint of a chemical mechanical polishing (CMP) process, which can be performed on the semiconductor wafer and a molding layer in a manufacturing process of the semiconductor package. Accordingly, the semiconductor package can be manufactured to have a desired thickness. Thus, a thickness variation of the semiconductor package can be reduced and reliability of the semiconductor package can be improved. Further, process failure can be reduced and / or yield in the manufacturing process can be improved.

[0108] Although example embodiments of the inventive concept have been specifically illustrated and described herein, it will be appreciated that changes can be made in form and detail without departing from the spirit and scope of the appended claims. ​ Embodiments of the inventive concept can be combined to realize the inventive concept.

[0109] Singular expressions can include plural expressions, unless the context clearly indicates otherwise. Terms such as "comprising" or "having" can be interpreted to add the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification.

[0110] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", "attached to", or "contacting" another element or layer, it can be directly on, connected, coupled, attached, or contacting the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to", "directly attached to", or "directly contacting" another element or layer, there are no intervening elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0111] When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Further, when the words "approximately" and "substantially" are used in connection with a geometric shape, it is intended that the precision of the geometric shape is not essential, but that the degrees of freedom of the shape are within the scope of the present disclosure. Further, whether or not a numerical value or a shape is modified by "about" or "substantially", it will be understood that these values and shapes are to be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values therebetween, such as in increments of 0.1%.

[0112] It will be understood that elements and / or properties recited in this document as “same as” or “identical to” other elements can also be understood to be “same as,” “identical to,” or “equivalent to” other elements and / or properties recited in this document as “same as,” “identical to,” or “equivalent to” other elements and / or properties. Elements and / or properties recited in this document as “same as,” “identical to,” or “equivalent to” other elements and / or properties can be “same as,” “identical to,” or “equivalent to” other elements and / or properties in structure, in function, and / or in composition.

[0113] For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” and the like, can be used herein with reference to the position of an element or feature as shown in the drawings. Such relative terms can be used to describe the position of an element or feature relative to another element or feature as shown in the drawings. However, it will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if the device in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Claims

1. A semiconductor package, comprising: A first semiconductor wafer having a first width; A second semiconductor wafer is located on the first semiconductor wafer, and the second semiconductor wafer has a second width that is smaller than the first width; as well as A molding layer that at least partially covers the side surface of the second semiconductor wafer and the top surface of the first semiconductor wafer. The first semiconductor wafer includes at least one first detection pattern, which is located on the top surface of the first semiconductor wafer and in contact with the bottom surface of the molding layer.

2. The semiconductor package as claimed in claim 1, wherein, The first detection pattern has a triangular, trapezoidal, or rectangular cross-section.

3. The semiconductor package as claimed in claim 1, wherein, When viewed in a planar view, the first detection pattern has an arc, semi-circular, or rectangular shape.

4. The semiconductor package as claimed in claim 1, wherein, The molding layer includes at least one of oxide materials and epoxy molding compounds.

5. The semiconductor package as claimed in claim 1, wherein, The reflectivity of the first detection pattern is different from the reflectivity of the top surface of the first semiconductor wafer.

6. The semiconductor package of claim 1, wherein, The first detection pattern includes at least one of metal, polymer, and resin.

7. The semiconductor package of claim 1, wherein, The second semiconductor wafer includes at least one second detection pattern located on the top surface of the second semiconductor wafer and spaced apart from the molding layer.

8. The semiconductor package of claim 7, wherein, The second detection pattern has a triangular, trapezoidal, or rectangular cross-section.

9. The semiconductor package of claim 7, wherein, The reflectivity of the second detection pattern is different from the reflectivity of the top surface of the second semiconductor wafer.

10. The semiconductor package of claim 7, wherein, The top surface of the second detection pattern is hydrophobic, and the top surface of the second semiconductor wafer is hydrophilic.

11. The semiconductor package of claim 7, wherein, The second detection pattern includes at least one of metal, polymer, and resin.

12. The semiconductor package of claim 7, wherein, The first detection pattern has a first height, and the second detection pattern has a second height that is different from the first height.

13. The semiconductor package of claim 1, wherein, The first detection pattern is located on at least one of the edges and corners of the first semiconductor wafer.

14. The semiconductor package of claim 1, wherein, The side surface of the first detection pattern is coplanar with the side surface of the molding layer.

15. The semiconductor package of claim 1, further comprising: The third semiconductor wafer located on the second semiconductor wafer, The third semiconductor wafer includes at least one second detection pattern located on the top surface of the third semiconductor wafer.

16. A semiconductor package, comprising: A first semiconductor wafer having a first width; A second semiconductor wafer is located on the first semiconductor wafer, and the second semiconductor wafer has a second width that is smaller than the first width; as well as A molding layer that at least partially covers the side surface of the second semiconductor wafer and the top surface of the first semiconductor wafer. The second semiconductor wafer includes at least one detection pattern located on the top surface of the second semiconductor wafer.

17. The semiconductor package of claim 16, wherein, The detection pattern has a triangular, trapezoidal, or rectangular cross-section.

18. The semiconductor package of claim 16, wherein, The reflectivity of the detection pattern is different from the reflectivity of the top surface of the second semiconductor wafer.

19. A semiconductor package, comprising: A first semiconductor wafer having a first width and including a first connection pad located in the upper part of the first semiconductor wafer; External connection terminals are attached to the bottom surface of the first semiconductor wafer; A second semiconductor wafer, located on top of the first semiconductor wafer, has a second width smaller than the first width and includes second connection pads located at the lower end of the second semiconductor wafer and respectively contacting the first connection pads; and A molding layer that at least partially covers the side surface of the second semiconductor wafer and the top surface of the first semiconductor wafer. The first semiconductor wafer includes at least one first detection pattern, which is located on the top surface of the first semiconductor wafer and in contact with the bottom surface of the molding layer. The reflectivity of the first detection pattern is different from the reflectivity of the top surface of the first semiconductor wafer, and The first detection pattern has a triangular, trapezoidal, or rectangular cross-section.

20. The semiconductor package of claim 19, wherein, The second semiconductor wafer includes at least one second detection pattern located on the top surface of the second semiconductor wafer and spaced apart from the molding layer.

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