Method, apparatus and system for producing polycrystalline silicon layer, and semiconductor structure

Abstract

The invention provides a method, a device and a system for producing a polycrystalline silicon layer, and a semiconductor structure. The method comprises the following steps: acquiring a grain image of a first polycrystalline silicon layer deposited on the surface of a first wafer through a charged particle beam imaging mode; counting statistical parameters of the grain size of the first polycrystalline silicon layer based on the grain image; obtaining an incidence relation between the statistical parameters and the process parameters; and based on the association relationship and the target parameter value, determining a process parameter of depositing a second polycrystalline silicon layer on the surface of the second wafer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a method, apparatus and system for producing polycrystalline silicon layers, as well as semiconductor structures. Background Technology

[0002] On the surface of a substrate made of semiconductor material (such as a single-crystal silicon wafer), a layer of polycrystalline semiconductor material (such as polycrystalline silicon) is usually deposited. Taking the polycrystalline silicon layer as an example, the polycrystalline silicon layer can not only attract metal elements during the semiconductor device manufacturing process, but also capture charge carriers generated in the buried oxide (BOX) layer due to the parasitic surface conduction (PSC) effect.

[0003] The two functions of the polycrystalline silicon layer mentioned above both stem from the fact that grain boundaries and dislocations in the polycrystalline silicon material form traps for gettering and capturing charge carriers. A higher grain boundary density indicates a higher trap density, which in turn enhances the polycrystalline silicon layer's ability to attract and capture metals and charge carriers. However, grain boundary density is typically not directly measurable or calculable; it is characterized by grain size. Specifically, smaller grain sizes result in higher grain boundary density, stronger metal gettering and charge carrier capture capabilities, and higher quality polycrystalline silicon layers.

[0004] Therefore, it is currently necessary to improve the quality of polysilicon layers during the production process. Summary of the Invention

[0005] This disclosure provides a method, apparatus, and system for producing polycrystalline silicon layers, as well as a semiconductor structure; it enables the quantitative acquisition of statistical parameters of the grain size in the polycrystalline silicon layer, and guides the production process of the polycrystalline silicon layer based on these statistical parameters, thereby achieving closed-loop, automatic, and precise control of the production process of the polycrystalline silicon layer to improve the quality of the polycrystalline silicon layer.

[0006] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a method for producing a polycrystalline silicon layer, the method comprising: Grain images of the first polycrystalline silicon layer deposited on the surface of the first wafer were acquired using charged particle beam imaging. Statistical parameters of the grain size of the first polycrystalline silicon layer were obtained based on grain images; Obtain the correlation between statistical parameters and process parameters; Based on the correlation and target parameter values, the process parameters for depositing the second polysilicon layer on the surface of the second wafer are determined.

[0007] Secondly, this disclosure provides a grain size detection device, which includes: a collection unit, a statistics unit, an acquisition unit, and a determination unit, wherein, The acquisition unit is configured to acquire images of the grains of the first polysilicon layer deposited on the surface of the first wafer using charged particle beam imaging. The statistics unit is configured to statistically analyze the grain size of the first polysilicon layer based on the grain image. The acquisition unit is configured to acquire the correlation between statistical parameters and process parameters; The determining unit is configured to determine the process parameters for depositing a second polysilicon layer on the surface of the second wafer based on the correlation and the target parameter value.

[0008] Thirdly, this disclosure provides a system for producing polycrystalline silicon layers, the system comprising: The imaging device is configured to acquire grain images of the first polysilicon layer deposited on the surface of the first wafer via charged particle beam imaging. A controller, communicatively coupled to the imaging device, includes a processor and a memory, wherein... The memory contains instructions; The processor is configured to execute instructions to: Statistical parameters of the grain size of the first polycrystalline silicon layer were obtained based on grain images; Obtain the correlation between statistical parameters and process parameters; Based on the correlation and target parameter values, the process parameters for depositing the second polysilicon layer on the surface of the second wafer are determined.

[0009] Fourthly, this disclosure provides a semiconductor structure, including: Substrate; A polycrystalline material layer deposited on a substrate; and, Buried oxide layer covering polycrystalline material layer; The average size of the grains in the polycrystalline material layer is 230 nm, the average diameter uniformity of all grains in the polycrystalline material layer is 2.8%, and the roughness of the polycrystalline material layer is less than or equal to 50.

[0010] This disclosure provides a method, apparatus, and system for producing polycrystalline silicon layers, as well as a semiconductor structure. The method involves imaging the polycrystalline silicon layer using charged particle beam imaging to obtain a high-resolution grain image. Based on the grain image, statistical parameters of the grain size of the first polycrystalline silicon layer are statistically analyzed. These statistical parameters are then used to establish a correlation between the statistical parameters and process parameters. Subsequently, based on this correlation, process parameters for depositing a second polycrystalline silicon layer on the surface of a second wafer are obtained, and these process parameters guide the production process of the second polycrystalline silicon layer. Based on the technical solution of this disclosure, statistical parameters of the grain size in the polycrystalline silicon layer can be quantitatively obtained, and the production process of the polycrystalline silicon layer can be guided based on these statistical parameters. This achieves closed-loop, automated, and precise control of the polycrystalline silicon layer production process, thereby improving the quality of the polycrystalline silicon layer. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the semiconductor structure provided in this disclosure.

[0012] Figure 2 This is a schematic diagram of a method for producing a polycrystalline silicon layer provided in this disclosure.

[0013] Figure 3 A grain image provided in this disclosure.

[0014] Figure 4 This is a preprocessed image of the grains with enhanced contrast provided in this disclosure.

[0015] Figure 5 This is a schematic diagram comparing the average size of the grains provided in this disclosure.

[0016] Figure 6 This is a schematic diagram illustrating the relationship between the average grain size and deposition temperature provided in this disclosure.

[0017] Figure 7 This is a schematic diagram illustrating the relationship between the average grain size and annealing temperature provided in this disclosure.

[0018] Figure 8 This is a comparative schematic diagram of the grain diameter uniformity provided in this disclosure.

[0019] Figure 9 This is a comparative schematic diagram of the roughness of the polycrystalline silicon layer provided in this disclosure.

[0020] Figure 10 This is a schematic diagram of the process for obtaining statistical parameters of grain size provided in this disclosure.

[0021] Figure 11 This is a schematic diagram of the process for obtaining grain contours using an edge detection algorithm, as provided in this disclosure.

[0022] Figure 12 This disclosure provides a binarized contour map.

[0023] Figure 13 This disclosure provides a grain profile image.

[0024] Figure 14 This is a flowchart illustrating the statistical parameters for determining the grain size in the first polycrystalline silicon layer based on the grain profile, as provided in this disclosure.

[0025] Figure 15 This is a schematic diagram of the composition of an apparatus for producing polycrystalline silicon layers provided in this disclosure.

[0026] Figure 16 This is a schematic diagram of a system structure for producing polycrystalline silicon layers provided in this disclosure. Detailed Implementation

[0027] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0028] See Figure 1 This is a schematic diagram of an exemplary semiconductor structure provided in this disclosure. Figure 1 In the semiconductor structure 1, there are: a substrate 11, a polycrystalline material layer 12 deposited on the substrate 11, and a buried oxide (BOX) layer 13 covering the polycrystalline material layer 12.

[0029] exist Figure 1 In this process, the substrate 11 can be made of single-crystal silicon. For example, after cutting a single-crystal silicon ingot grown by the Czochralski (CZ) method or the Float Zone (FZ) method to obtain a single-crystal silicon wafer, a polished wafer formed by applying grinding, etching, polishing, and other processes to the single-crystal silicon wafer can be used as a substrate. Figure 1 The substrate 11 shown is optional. Alternatively, the epitaxial wafer formed by further epitaxial processing of the polished wafer can also be used as... Figure 1 The substrate 11 shown is optionally made of other materials besides single-crystal silicon, such as sapphire, silicon carbide, etc., which will not be described in detail in this disclosure.

[0030] exist Figure 1 In this process, the polycrystalline material layer 12 can be made of a polycrystalline semiconductor material, which can be represented as a material with small crystals having random crystal orientation. For example, polycrystalline semiconductor materials include polycrystalline silicon (Poly-Si), polycrystalline silicon germanide (SiGe), polycrystalline silicon carbide (SiC), and polycrystalline germanium (Ge).

[0031] For the above-exemplary polycrystalline semiconductor materials, a polycrystalline material layer 12 can be formed by vapor deposition on the surface of the substrate 11. This vapor deposition method includes chemical or physical vapor deposition, such as metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), remote plasma chemical vapor deposition (RPCVD), or plasma-enhanced chemical vapor deposition (PECVD), etc.

[0032] exist Figure 1 In this process, the material of the BOX layer 13 may include semiconductor oxides, semiconductor nitrides, or semiconductor oxide oxynitrides, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). These materials can also be deposited on the polycrystalline material layer 12 using vapor deposition to form one or more insulating layers, which form... Figure 1 BOX layer 13 in the middle.

[0033] To clearly and concisely illustrate the technical solution of this disclosure, this disclosure takes polycrystalline silicon as an example, where the polycrystalline silicon layer 12 is made of polycrystalline silicon. The grains of the polycrystalline silicon layer form numerous grain boundaries, and the dangling bonds, dislocations, and vacancies at these grain boundaries act as traps for metal element gettering and for capturing charge carriers (e.g., electrons or holes). Taking charge carrier capture as an example, once a charge carrier is trapped, it cannot migrate freely, thus suppressing the formation of the parasitic surface conduction (PSC) layer. Based on the above explanation of charge carrier capture in the polycrystalline material layer, it can be seen that when the grain density in the polycrystalline silicon layer increases, the density of the aforementioned defect states acting as traps also increases accordingly, and the polycrystalline silicon layer's ability to perform metal gettering and capture charge carriers also improves. Furthermore, there is a negative correlation between grain density and grain size; that is, the smaller the grain size, the more grains are present per unit area, resulting in a corresponding increase in grain density.

[0034] Based on the above relationships, it can be seen that grain boundary density can be used to directly evaluate the metal gettering ability and charge carrier trapping ability of polycrystalline silicon layers. However, since grain boundary density cannot be directly measured or calculated and needs to be characterized by grain size, grain size is usually used as an indirect indicator to evaluate the metal gettering ability and charge carrier trapping ability of polycrystalline silicon layers. That is, the smaller the grain size, the higher the grain boundary density, and the higher the quality of the polycrystalline silicon layer.

[0035] Currently, most solutions rely on manual experience for process adjustments during the production of polycrystalline silicon layers. These solutions suffer from problems such as slow response, low precision, and unstable results, making it difficult to meet the increasingly stringent process control requirements of advanced technologies.

[0036] Based on this, this disclosure achieves closed-loop, automatic, and precise control of the polycrystalline silicon layer production process by quantitatively characterizing the grain size and adjusting the production process of the polycrystalline silicon layer based on the grain size feedback, thereby improving the quality of the polycrystalline silicon layer. Figure 2 This disclosure provides a method flow for producing a polycrystalline silicon layer, which may include steps S201 to S203.

[0037] S201: Acquire grain images of the first polycrystalline silicon layer deposited on the surface of the first wafer using charged particle beam imaging.

[0038] In this disclosure, the charged particle beam includes an electron beam and an ion beam. The interaction of these charged particles with the polycrystalline silicon layer generates secondary electrons or secondary ions. By collecting these secondary electron or secondary ion signals, an image of the polycrystalline silicon layer can be formed. Because the electrons or ions are small in size, the image resolution is extremely high, reaching several nanometers and sub-nanometer levels. Such a high-resolution image can more finely resolve details within the polycrystalline silicon layer, such as grains with sizes ranging from tens to hundreds of nanometers. Thus, by scanning the polycrystalline silicon layer with a charged particle beam, high-resolution grain images can be obtained.

[0039] In some examples, charged particle beam imaging methods include scanning electron microscopy (SEM) and transmission electron microscopy (TEM). These imaging methods can achieve resolutions on the order of several nanometers, and some (such as TEM) can even reach sub-nanometer levels. Such high resolution is more suitable for detecting grains with sizes currently in the tens of nanometer range compared to optical detection methods, thus improving the accuracy of grain size detection.

[0040] In this disclosure, taking SEM imaging as an example, the grain image can be obtained by scanning the polycrystalline silicon layer with an in-line SEM and acquiring SEM images of the surface area of ​​the polycrystalline silicon layer at exemplary dimensions (5µm × 5µm or 5µm × 3µm). It is understood that SEM imaging can obtain high-resolution images reflecting the morphology and boundaries of polycrystalline silicon grains without damaging the wafer sample.

[0041] For a single polycrystalline silicon layer on a wafer, SEM imaging can acquire grain images of one or more regions. Each grain image shows the grains within the corresponding region, such as... Figure 3 As shown, this is a grain image of a region measuring 5µm × 3µm on the surface of a polycrystalline silicon layer. This grain image can be a grayscale image. Figure 3 In the grain image shown, multiple grains can be visually observed within the 5µm×3µm region.

[0042] In some examples, the corresponding region of the aforementioned grain image may include all regions covering the entire polysilicon layer, or a sampled region obtained by sampling the polysilicon layer at predetermined dimensional intervals, or one or more specifically selected regions within the polysilicon layer. In this disclosure, each of the grain images of all the aforementioned regions presents multiple grains.

[0043] S202: Statistical parameters of the grain size of the first polycrystalline silicon layer based on grain image statistics.

[0044] In this disclosure, Figure 3 Taking the grain image shown as an example, visual observation reveals that the boundary line between adjacent grains (i.e., the edge of the grain) differs significantly in grayscale or contrast from the grain itself. Therefore, the grain outline can be obtained by detecting the grain edge. After obtaining the grain outline, all grains in the image can be identified and the size of each grain can be determined based on the outline, thereby obtaining the statistical parameters of the grain size of all grains in the first polysilicon layer.

[0045] Specifically, grain size refers to the physical dimensions used to characterize grain size, such as the grain's diameter, radius, or area. These physical dimensions can all be represented by the grain's radius / diameter. Furthermore, the grain's diameter can be determined by the diameter of the grain outline in a grain image. For example, Figure 3 The region shown has dimensions of 5µm × 3µm on the surface of the polysilicon layer, and this Figure 3 The image of the grain shown is 200 pixels × 120 pixels. When a grain is in Figure 3When the outline diameter presented in the image is 10 pixels, the actual physical diameter of the grain is 10×5um / 200=0.25um=250nm.

[0046] Furthermore, after obtaining the grain size, the dimensions of all grains in the polysilicon layer can be statistically analyzed to obtain statistical parameters, such as the average diameter of the grains in the polysilicon layer, the uniformity of grain diameter, and the ratio of the number of grains of different sizes. Specifically, the average diameter of the grains in the polysilicon layer can be the average of the diameters of all grains in all grain images of the polysilicon layer. The uniformity of grain diameter can be the ratio of the difference between the largest and smallest diameters of all grains in all grain images to twice the average diameter. The ratio of the number of grains of different sizes is the ratio of the number of grains with a diameter greater than the average diameter to the number of grains with a diameter less than the average diameter.

[0047] Specifically, to increase the contrast between the grain edges and the grain itself to improve edge detection accuracy, the grain image can be preprocessed before step S202 to increase its contrast. This preprocessing increases the contrast of the grain image, making the grayscale difference between the grains and grain boundaries more obvious, providing a clearer grain image for the edge detection algorithm, thereby improving the accuracy of edge recognition. In some examples, after acquiring the original grain image via SEM, the contrast-enhancing preprocessing can be performed using graphics processing software. Figure 3 Taking the original grain image shown as an example, the grain image after preprocessing to enhance contrast is as follows: Figure 4 As shown, through comparison Figure 3 and Figure 4 It can be observed intuitively. Figure 4 The grayscale difference between grain boundaries and grains in Figure 3 The grayscale differences should be obvious.

[0048] S203: Obtain the correlation between statistical parameters and process parameters.

[0049] During the deposition of polycrystalline silicon layers, process parameters influence grain growth, thereby affecting grain size. For example, the temperature values ​​during deposition and heat treatment affect grain size, and the temperature distribution during deposition can result in different grain sizes at different locations within the polycrystalline silicon layer. Once statistical parameters of grain size are obtained, a correlation can be established between these parameters and process parameters, and these correlations can be used to characterize the aforementioned effects.

[0050] S204: Based on the correlation and target parameter values, determine the process parameters for depositing the second polysilicon layer on the surface of the second wafer.

[0051] Having established the aforementioned correlation, when it is necessary to deposit a second polysilicon layer on the surface of the second wafer, the process parameters used for depositing the second polysilicon layer can be determined based on the desired grain size requirement (i.e., the target parameter value) for the second polysilicon layer. In this way, by controlling the process parameters, a second polysilicon layer with the desired grain size can be deposited on the surface of the second wafer.

[0052] Through the above Figure 2 The technical solution shown in this disclosure uses charged particle beam imaging to image the polysilicon layer and obtain a high-resolution grain image. Then, based on the grain image, statistical parameters of the grain size of the first polysilicon layer are calculated, and a correlation between these statistical parameters and process parameters is constructed. Subsequently, based on this correlation, process parameters for depositing the second polysilicon layer on the surface of the second wafer are obtained, and the production process of the second polysilicon layer is guided according to these process parameters.

[0053] In some possible implementations, statistical parameters include the average size of all grains in the first polysilicon layer, such as the average diameter. This average diameter is related to the growth temperature during the grain growth process, which in this disclosure includes a deposition process and a heat treatment process, and correspondingly, the growth temperature includes a deposition temperature and an annealing temperature. Specifically, the deposition process of the polysilicon layer begins with the formation of nuclei on the wafer surface, which then gradually grow and come into contact with each other to form a continuous thin film. Temperature is a key factor affecting the nucleation rate and growth rate. During deposition, higher deposition temperatures provide greater atomic migration energy. This means that atoms deposited on the surface have more energy to migrate on the surface and have a greater chance of reaching lower-energy lattice sites, such as the edges or steps of existing nuclei, thus promoting the growth of existing grains rather than forming new nuclei. This tends to result in larger but fewer grains. If the temperature is too low, the atomic migration ability is insufficient, and a large number of small nuclei easily form at arbitrary locations, resulting in fine grains. Annealing is a heat treatment process performed after deposition, which provides additional thermal energy to promote atomic diffusion and grain boundary migration. This can lead to smaller grains being swallowed by larger grains due to the Ostwald ripening effect, or grains growing through remodeling and recrystallization, thereby reducing the overall interfacial energy of the system. Therefore, annealing typically increases the average grain size. Based on the above, the higher the growth temperature, the larger the average grain size. This disclosure, by controlling the deposition temperature and the annealing temperature during annealing, can regulate the surface migration of atoms and the crystal rearrangement process, thereby affecting the average diameter of the final polycrystalline silicon layer grains.

[0054] Based on this, this disclosure provides three examples of process growth condition combinations with different deposition temperatures and annealing conditions. In condition combination one, the deposition temperature is 980°C and the annealing temperature is 1000°C. Under this condition combination, the thickness of the first polysilicon layer deposited is 2µm. The grain diameter of the first polysilicon layer is detected to be in the range of 300nm to 350nm, with an average diameter of 340nm. In condition combination two, the deposition temperature is in the range of 980°C to 950°C, without annealing. Under this condition combination, the thickness of the first polysilicon layer deposited is 2µm. The grain diameter of the first polysilicon layer is detected to be in the range of 250nm to 300nm, with an average diameter of 280nm. In condition combination three, the deposition temperature is 950°C and the annealing temperature is 1080°C. Under this condition combination, the thickness of the first polysilicon layer deposited is 2µm. The grain diameter of the first polysilicon layer is detected to be in the range of 200nm to 250nm, with an average diameter of 230nm. The grain diameter range obtained by the above three combinations of conditions can be compared using a box plot, for example. Figure 5 As shown in the figure, the lower the growth temperature, the smaller the average diameter of the grains.

[0055] Furthermore, this disclosure considers the effects of deposition temperature and annealing temperature on the average grain diameter, as follows: Figure 6 and Figure 7 As shown, from Figure 6 As can be seen, in the four deposition temperature ranges of 700-800 degrees Celsius, 800-900 degrees Celsius, 900-1000 degrees Celsius, and 1000-1100 degrees Celsius, the average grain size increases with increasing deposition temperature. Figure 6 The dashed line in the figure illustrates a linear positive correlation between deposition temperature and average grain size. Figure 7 In the four annealing temperature ranges of 1000-1050 degrees Celsius, 1050-1100 degrees Celsius, 1100-1150 degrees Celsius, and 1150-1200 degrees Celsius, the average grain size increases with increasing annealing temperature. Figure 7 The dashed line in the figure shows a linear positive correlation between annealing temperature and average grain size.

[0056] according to Figure 6 and Figure 7 The relationships shown can determine the process parameters for subsequently depositing a second polysilicon layer on the second wafer surface. Specifically, when depositing the second polysilicon layer on the second wafer surface, if the target average size of the grains in the second polysilicon layer is greater than the average size of the grains in the first polysilicon layer, the deposition temperature and / or annealing temperature for depositing the second polysilicon layer on the second wafer surface should be increased compared to the deposition temperature and / or annealing temperature when depositing the first polysilicon layer on the first wafer surface. When the target average size of the grains of the second polysilicon layer is smaller than the average size of the grains of the first polysilicon layer, the deposition temperature and / or annealing temperature of the second polysilicon layer on the second wafer surface is reduced compared to the deposition temperature and / or annealing temperature when the first polysilicon layer is deposited on the first wafer surface.

[0057] In some possible implementations, statistical parameters include the diameter uniformity of all grains in the first polysilicon layer. In this disclosure, diameter uniformity can be characterized by the ratio of the difference between the largest and smallest diameters among all grains in the first polysilicon layer to twice the average diameter. Understandably, the smaller this value, the more uniform the grain size distribution in the first polysilicon layer, the more uniform the growth of all grains, and the better the diameter uniformity of all grains. During the deposition of the polysilicon layer, upper and lower heaters (taking a lampshade as an example) heat the reaction chamber. The power ratio of the upper and lower lampshades directly affects the temperature distribution within the reaction chamber and on the wafer surface. If the wafer surface temperature is uneven, the atomic mobility, nucleation rate, and growth rate will differ in different regions, resulting in the formation of grains of different sizes at different locations on the wafer, thus worsening the grain diameter uniformity. Based on the above explanation, by optimizing the power ratio of the heating system to improve the temperature uniformity of the wafer surface, the nucleation and growth conditions of polycrystalline silicon on the entire wafer can be made as consistent as possible, ultimately resulting in a polycrystalline silicon layer with good diameter uniformity.

[0058] Based on this, this disclosure provides examples of three power ratio conditions. In ratio condition one, the upper lampshade accounts for 70% of the power and the lower lampshade accounts for 17%. Under this ratio condition, the uniformity of the grain diameter of the polycrystalline silicon layer deposited, as detected by the aforementioned grain size detection method, ranges from 0% to 5%, and the average diameter uniformity is 2.8%. In ratio condition two, the upper lampshade accounts for 72% of the power and the lower lampshade accounts for 17.5%. Under this ratio condition, the uniformity of the grain diameter of the polycrystalline silicon layer deposited, as detected by the aforementioned grain size detection method, ranges from 5% to 10%, and the average diameter uniformity is 8%. In ratio condition three, the upper lampshade accounts for 74% of the power and the lower lampshade accounts for 18%. Under this ratio condition, the uniformity of the grain diameter of the polycrystalline silicon layer deposited, as detected by the aforementioned grain size detection method, ranges from 10% to 15%, and the average diameter uniformity is 13%. The uniformity range of grain diameter obtained under the above three ratio conditions is compared using a box plot. Figure 8 As shown, it can be seen that the larger the power ratio of the upper and lower lamp covers, the larger the diameter uniformity index value, and the worse the diameter uniformity of the grains. In other words, the power ratio of the upper and lower lamp covers is positively correlated with the diameter uniformity index and negatively correlated with the diameter uniformity.

[0059] Based on the above correlation, the process parameters for depositing a second polysilicon layer on the second wafer surface can be determined. Specifically, when depositing the second polysilicon layer on the second wafer surface, if the target diameter uniformity index of the second polysilicon layer grains is greater than that of the first polysilicon layer grains, the power ratio of the upper and lower heaters during the deposition of the second polysilicon layer on the second wafer surface should be increased compared to the power ratio during the deposition of the first polysilicon layer on the first wafer surface. When the target diameter uniformity index of the second polysilicon layer is less than that of the first polysilicon layer, the power ratio of the upper and lower heaters when depositing the second polysilicon layer on the second wafer surface is reduced compared to the power ratio when depositing the first polysilicon layer on the first wafer surface.

[0060] In addition to the correlation between statistical parameters and process parameters described in the two implementation methods above, the statistical parameters of grain size are also related to the quality parameters of the polycrystalline silicon layer. Specifically, among all the grains in the polycrystalline silicon layer, the ratio of the number of first grains with a diameter greater than the average diameter to the number of second grains with a diameter less than or equal to the average diameter is related to the surface roughness of the polycrystalline silicon layer. More specifically, the surface roughness of the polycrystalline silicon layer is mainly caused by the difference in the top surface height of the individual grains constituting the layer and the preferred orientation of the grains. If the polycrystalline silicon layer is composed of grains with very uneven sizes, then grains of different sizes may have different growth rates in the vertical growth direction, or larger grains may form higher protrusions on the surface, while smaller grains fill the spaces between them, resulting in large surface height fluctuations, i.e., high surface roughness. Conversely, if the grain size distribution is relatively concentrated, and the size of most grains is close to the average value, then the top surface height of each grain will be more consistent, resulting in a relatively smooth film surface with lower surface roughness.

[0061] Based on this, this disclosure provides three examples of ratios for different grain sizes. In ratio example one, the ratio (i.e., N1:N2) of the number of first grains (N1) with diameters greater than the average diameter to the number of second grains (N2) with diameters less than the average diameter in the first polysilicon layer ranges from 0.5 to 1. Under this ratio condition, the surface roughness Ra of the polysilicon layer is greater than 50, and the range of Ra is 50 to 60. In ratio example two, the range of N1:N2 is from 0 to 0.5. Under this ratio condition, the surface roughness Ra of the polysilicon layer is less than 50, and the range of Ra is 38 to 50. The relationship between the above N1:N2 ratio and roughness is as follows: Figure 9 As shown, from Figure 9 As can be seen, the ratio of N1 to N2 has a linear relationship with Ra, that is, the smaller the ratio of N1 to N2, the smaller the Ra value, which indicates that the surface of the polycrystalline silicon layer is less rough.

[0062] Based on the correlation between the ratio of N1 to N2 and Ra, after depositing the first polysilicon layer on the surface of the first wafer and / or depositing the second polysilicon layer on the surface of the second wafer, the ratio of the number of first grains N1 to the number of second grains N2 in all grains of the first polysilicon layer and / or the second polysilicon layer is calculated, and the roughness of the first polysilicon layer and / or the second polysilicon layer is determined based on this ratio.

[0063] Combination Figures 5 to 9 As shown, this disclosure, by adjusting the deposition temperature and annealing temperature, power ratio, and based on the ratio of the number of grains of different sizes, can obtain a polycrystalline silicon layer that meets the following indicators: the average grain size in the polycrystalline material layer is 230 nm, the average diameter uniformity of all grains in the polycrystalline material layer is 2.8%, and the roughness of the polycrystalline material layer is less than or equal to 50. Further, the grain size in the polycrystalline silicon layer is greater than or equal to 200 nm and less than or equal to 250 nm; the diameter uniformity of all grains in the polycrystalline material layer is greater than or equal to 0% and less than or equal to 5%; and the roughness of the polycrystalline material layer is greater than or equal to 38 and less than or equal to 50.

[0064] for Figure 2 The technical solution shown is for obtaining the statistical parameters described in the above implementation method, such as... Figure 10 As shown, step S202, which involves calculating the statistical parameters of the grain size of the first polysilicon layer based on the grain image, may include: S2021: obtaining the grain contour in the grain image based on an edge detection algorithm; and S2022: determining the statistical parameters of the grain size in the first polysilicon layer based on the grain contour.

[0065] exist Figure 10 In the illustrated process, the edge detection algorithm includes the Canny edge detection algorithm. Specifically, the process of obtaining the grain contour in step S2021 is as follows: Figure 11 As shown, it may include: S1101: Perform smoothing filtering on the grain image to remove noise from the grain image.

[0066] In this disclosure, a two-dimensional Gaussian filter function can be used for the above-mentioned smoothing filtering process. Specifically, the grain image is... Figure 3 or Figure 4 The grayscale image shown is... This indicates that the two-dimensional Gaussian filter function σ represents the smoothness level. It's worth noting that during implementation, a larger σ can produce a stronger smoothing effect and remove more noise. However, edges, as high-frequency components, may also have subtle, real edges smoothed or blurred. Therefore, the value of σ should not be too large to eliminate too many edges, nor too small to reduce noise reduction capabilities. Regarding the above... as well as The image after noise removal can be obtained by performing smoothing filtering using the following formula. :

[0067] In the above formula, This represents the convolution operator.

[0068] S1102: Obtain the gradient magnitude and gradient direction of the noise-removed image.

[0069] In this step, for the noise-removed image, the gradient magnitude and direction of each pixel can be calculated using first-order partial derivatives. In specific implementation, for the noise-removed image... The gradient values ​​of each pixel in the horizontal (x-direction) and vertical (y-direction) directions are obtained by using the first derivative of the one-dimensional Gaussian filter function.

[0070] In detail, for the one-dimensional Gaussian filter function in the x and y directions and Their first derivatives are respectively and Using the noise-removed image through respectively as well as Obtain the gradient value of each pixel in the x-direction. gradient value in the y direction ,in, This represents the convolution operator.

[0071] After obtaining the gradient value of each pixel in the x-direction gradient value in the y direction Then, it can be calculated using the formula. as well as Obtain the gradient magnitude of each pixel. and gradient direction .

[0072] S1103: In the gradient direction, non-maximum suppression is performed based on the gradient magnitude to obtain the initial edge image.

[0073] In this disclosure, the gradient magnitude of each pixel is obtained. and gradient direction Then, retain the gradient magnitude of the pixel with the largest gradient magnitude in the same gradient direction, and set the gradient magnitude of other pixels in the same gradient direction to 0, thus obtaining the initial edge image.

[0074] In one exemplary implementation, step S1103 may include: First, iterate through each pixel and, during the iteration, obtain the gradient direction for the currently iterated pixel.

[0075] Next, the gradient magnitude of the currently traversed pixel is compared with the gradient magnitude of its two adjacent pixels in the gradient direction.

[0076] It should be noted that when the gradient direction is horizontal, two adjacent pixels are the left and right neighbors of the currently traversed pixel. When the gradient direction is vertical, two adjacent pixels are the top and bottom neighbors of the currently traversed pixel. When the gradient direction is slanted, the gradient magnitude of two adjacent pixels can be calculated by interpolation within the neighborhood of the currently traversed pixel. In this disclosure, the size of the neighborhood can be 3×3.

[0077] If the gradient magnitude of the currently traversed pixel is greater than the gradient magnitudes of its two adjacent pixels along the gradient direction, then the gradient magnitude of the currently traversed pixel is retained. Otherwise, the gradient magnitude of the currently traversed pixel is set to 0.

[0078] Through the above implementation process, after traversing all pixels, the pixels that retain the gradient magnitude ultimately form the initial edge image.

[0079] S1104: Edge suppression is performed using dual thresholds to filter candidate edge images from the initial edge image.

[0080] After obtaining the initial edge image, it is necessary to filter the pixels that retain gradient magnitudes to determine whether they are grain edges. In this disclosure, a dual-threshold method is used for filtering. Specifically, a higher gradient magnitude threshold (high threshold) Th and a lower gradient magnitude threshold (low threshold) Tl are set. For example, Th can be 100 and Tl can be 50, or Th can be 200 and Tl can be 100. The settings of Th and Tl can be determined according to the polarity of the actual scene, which will not be elaborated in this disclosure.

[0081] After determining the high threshold Th and the low threshold Tl, the gradient magnitude of each pixel in the candidate edge image that retains a gradient magnitude is compared with both the high threshold Th and the low threshold Tl. If the gradient magnitude of a pixel is greater than or equal to the high threshold Th, the pixel is identified as a strong edge and retained. If the gradient magnitude of a pixel is less than the low threshold Tl, the pixel is identified as a non-edge, and non-edge pixels are suppressed, such as being discarded or having their gradient magnitude set to zero. If the gradient magnitude of a pixel is less than the high threshold Th but greater than or equal to the low threshold Tl, the pixel is identified as a false edge.

[0082] Through the above-described dual-threshold edge suppression process, candidate edge images composed of strong edges and false edges can be selected from the initial edge image.

[0083] S1105: Perform edge linking based on candidate edge images to form a binarized contour map.

[0084] In this disclosure, the candidate edge image includes strong edges and virtual edges. Virtual edges require further determination to determine whether they are edges of a grain. Specifically, if a pixel of a virtual edge is connected to a pixel of a strong edge, then the pixel of the virtual edge can be identified as a grain edge; otherwise, the pixel of the virtual edge is suppressed, for example, discarded or its gradient magnitude is set to zero. This process of further determining virtual edges utilizes the continuity of grain edges, which helps to connect broken edges and remove isolated edge points caused by noise.

[0085] After completing step S1105, an edge image in the grain image can be formed. This edge image is specifically a binarized contour image, such as... Figure 12 As shown by the white line in the image. Figure 12 The white line in the middle and Figure 3 By combining the grain images shown, it can be seen that the edge images in the grain images can clearly mark the identified grain boundaries, which provides a direct basis for subsequent quantitative determination and statistical analysis of grain size in polycrystalline silicon layers.

[0086] S1106: Extract candidate contours from the binarized contour map.

[0087] In this step, all independent, continuous edge pixel segments are identified and extracted from the binarized contour image; these pixel segments constitute the candidate contours. During extraction, the outermost contour of the binarized contour image can be searched. For the grain, this avoids extracting contours of potential holes inside the grain, ensuring that the extracted candidate contours represent the outer boundary of the grain. Furthermore, during extraction, horizontal, vertical, and diagonal pixel segments can be compressed, retaining only their endpoints. This effectively reduces redundant points in the candidate contours while maintaining the basic shape of the contour, saving storage space and accelerating subsequent processing.

[0088] In practical implementation, taking the Python programming language as an example, the above extraction process can be represented by the following pseudocode: contours,_=cv2.findContours(edges,cv2.RETR_EXTERNAL,cv2.CHAIN_APPROX_SIMPLE).

[0089] In the pseudocode above, edges represents the aforementioned Figure 6 The illustrated technical solution uses the Canny edge detection algorithm to obtain a binarized contour image. `cv2.RETR_EXTERNAL` indicates that the outermost contour of the binarized contour image is retrieved. `cv2.CHAIN_APPROX_SIMPLE` indicates that the horizontal, vertical, and diagonal pixel segments are compressed, retaining only their endpoints. `cv2.findContours` represents the function for extracting candidate contours, and `contours` represents the list returned by the function. Each element in this list is an independent candidate contour; that is, `contours` represents the list of candidate contours extracted in step S801. Furthermore, each candidate contour (i.e., an element in the list) is itself an array containing the coordinates of the pixels that make up that candidate contour.

[0090] S1107: Select grain contours from candidate contours according to at least one of the following: area threshold, closure, and shape concavity / convexity.

[0091] After obtaining candidate contours, contours that do not conform to the characteristics of real grains need to be removed from the candidate contours in order to filter out valid grain contours. In this disclosure, the filtering criteria may, exemplarily, include at least one of area, whether the contour is closed, and whether the contour shape is a convex polygon.

[0092] In some examples, small contours are caused by noise or image artifacts. This disclosure sets an area threshold, such as 100 pixel units, to distinguish whether a contour area is small. Specifically, each candidate contour is traversed, and the area of ​​the currently traversed candidate contour is compared with the area threshold. If it is less than the threshold, the currently traversed candidate contour is discarded; otherwise, the currently traversed candidate contour is considered a valid grain contour and is retained.

[0093] In practical implementation, taking the Python programming language as an example, the filtering process illustrated in this example can be represented by the following pseudocode: filtered_contours = [cnt for cnt in contours if cv2.contourArea(cnt)≥ 100] In the pseudocode above, each candidate contour `cnt` in the candidate contour list `contours` is traversed, and the area of ​​each traversed candidate contour is calculated using the function `cv2.contourArea(cnt)`. If the calculated contour area is greater than or equal to the area threshold (set to 100 in this disclosure), then the candidate contour is considered valid and is retained in a new contour list `filtered_contours`. Contours with a calculated contour area less than 100 are discarded and not retained in `filtered_contours`.

[0094] In some examples, the grain contours are all closed. Based on the closure of the grain contours, valid grain contours can also be selected from the candidate contours. In detail, each candidate contour is traversed, and it is determined whether the currently traversed candidate contour is closed. If it is, the currently traversed candidate contour is considered a valid grain contour and is retained; otherwise, the currently traversed candidate contour is discarded.

[0095] In the specific implementation process, each candidate contour cnt in the candidate contour list contours is traversed, and the closure of each traversed candidate contour is determined by the function cv.iscsContourConvex(cnt). If the function returns 1, it means that the currently traversed candidate contour is valid and is retained; otherwise, it is discarded and not retained.

[0096] In some examples, the grain profile is a convex polygon without any depressions. Based on the convexity of the grain profile shape, other or irregularly shaped profiles can also be excluded from the candidate profiles, thus filtering out the valid grain profiles. In detail, each candidate profile is traversed, and it is determined whether the shape of the currently traversed candidate profile is convex. If it is, the currently traversed candidate profile is considered a valid grain profile and is retained; otherwise, the currently traversed candidate profile is discarded.

[0097] In the specific implementation process, each candidate contour cnt in the candidate contour list contours is traversed, and the convexity of the shape of each traversed candidate contour is determined by the function cv2.iscsContourConvex(cnt). If the function returns 1, it means that the currently traversed candidate contour is valid and is retained; otherwise, it is discarded and not retained.

[0098] For the examples of the three filtering conditions mentioned above, either one can be implemented individually to filter out the grain contours in the grain image, or two or three of the above filtering conditions can be combined to filter out the grain contours in the grain image. In the process of combining implementations, the order of the filtering conditions can be arranged according to the specific situation, which will not be elaborated in this disclosure.

[0099] In some examples, targeting Figure 12 The white lines in the image represent the binarized profiles. The grain profiles selected based on two criteria—area and whether the profile is closed—are as follows: Figure 13 As shown, these grain profiles can serve as the basis for subsequently determining grain size parameters.

[0100] In some possible implementations, after obtaining the grain profile, the actual physical size of the grain can be obtained by analyzing the dimensions of the grain profile in the image. For example... Figure 14 As shown, the statistical parameters for determining the grain size in the first polysilicon layer based on the grain profile, as described in step S2022, may include: S1401: Obtain the minimum circumcircle corresponding to each grain profile.

[0101] S1402: Use the physical dimension parameters of each minimum circumcircle as the physical dimension parameters of the corresponding grain profile.

[0102] Regarding steps S1401 and S1402 above, it should be noted that the present disclosure exemplarily uses the minimum circumcircle of each grain profile as the fitting of the grain profile shape, which can reduce the difficulty of obtaining the physical size parameters of the grain and improve the computational efficiency and processing speed while ensuring that the error is small.

[0103] Specifically, for a single grain image, each grain contour `cnt` in the grain contour list is traversed. Then, the center coordinates and radius of the minimum circumcircle of each traversed grain contour are calculated using the function `minEnclosingCircle(cnt)`. After obtaining the center coordinates and radius of the minimum circumcircle of each traversed grain contour, the center coordinates of the minimum circumcircle are used as the position coordinates of the corresponding grain contour, and the radius of the minimum circumcircle is used as the radius of the corresponding grain contour. After obtaining the radius of each traversed grain contour, the area and diameter of each traversed grain contour can be obtained based on its radius.

[0104] It should be noted that the radius, area, and diameter of the grain profile obtained above are calculated from the image and are not the actual physical size parameters of the grain. This disclosure can calculate the corresponding actual physical size parameters of the grain using the radius, area, and diameter of the grain profile based on the ratio of the size of the grain image to the region size in the corresponding first polysilicon layer. Specifically, it still uses... Figure 3 Taking the grain image shown as an example, its image size is 200 pixels × 120 pixels, and the corresponding area has a size of 5µm × 3µm in the first polysilicon layer. That is to say, in Figure 3 In this context, the actual physical length corresponding to one pixel is 5µm / 200 = 0.025µm = 25nm. Based on this ratio, taking diameter as an example, when the diameter of the grain outline is 10 pixels, the actual physical diameter of the grain is 250nm. Of course, the actual physical radius and physical area of ​​the grain can also be obtained based on this ratio, which will not be elaborated upon in this disclosure.

[0105] S1403: Based on the physical size parameters of all grain profiles in all grain images, calculate the statistical parameters of the grain size in the first polysilicon layer.

[0106] In this disclosure, the statistical parameters of the grain size in the first polysilicon layer may include: the average diameter of the grains in the first polysilicon layer, the uniformity of the grain diameter, and the ratio of the number of grains of different sizes. Specifically, the average diameter of the grains in the first polysilicon layer can be the average of the diameters of all grains in all grain images. The uniformity of the grain diameter can be the ratio of the difference between the largest and smallest diameters in all grains in all grain images to twice the average diameter. The ratio of the number of grains of different sizes is the ratio of the number of grains with a diameter greater than the average diameter to the number of grains with a diameter less than the average diameter.

[0107] Based on the same inventive concept as the aforementioned technical solutions, this disclosure provides an apparatus for producing polycrystalline silicon layers, such as... Figure 15As shown, the device 150 includes: a data acquisition unit 151, a statistics unit 152, an acquisition unit 153, and a determination unit 154, wherein, The acquisition unit 151 is configured to acquire grain images of the first polysilicon layer deposited on the surface of the first wafer by a charged particle beam imaging method. The statistics unit 152 is configured to calculate statistical parameters of the grain size of the first polysilicon layer based on the grain image. The acquisition unit 153 is configured to acquire the correlation between the statistical parameters and the process parameters; The determining unit 154 is configured to determine the process parameters for depositing a second polysilicon layer on the surface of the second wafer based on the correlation and the target parameter value.

[0108] In some examples, the statistical parameters include the average size of the grains, and the process parameter is the growth temperature, where a higher growth temperature results in a larger average grain size.

[0109] In some examples, the determining unit 154 is configured to: When the target average size of the grains is greater than the average size of the grains in the first polysilicon layer, the deposition temperature and / or annealing temperature for depositing the second polysilicon layer on the second wafer surface is increased compared to the deposition temperature and / or annealing temperature when depositing the first polysilicon layer on the first wafer surface. When the target average size is smaller than the average size of the grains of the first polysilicon layer, the deposition temperature and / or annealing temperature for depositing the second polysilicon layer on the second wafer surface is reduced compared to the deposition temperature and / or annealing temperature when depositing the first polysilicon layer on the first wafer surface.

[0110] In some examples, the statistical parameters include the grain diameter uniformity index, and the process parameters are the power ratio of the upper and lower heaters. The larger the power ratio of the upper and lower heaters, the larger the grain diameter uniformity index.

[0111] In some examples, the determining unit 154 is configured to: When the target diameter uniformity index is greater than the diameter uniformity index of the first polysilicon layer, the ratio of the power ratio of the upper and lower heaters when depositing the second polysilicon layer on the second wafer surface is increased compared to the power ratio when depositing the first polysilicon layer on the first wafer surface. When the target diameter uniformity index is less than the diameter uniformity index of the first polysilicon layer, the power ratio of the upper and lower heaters is reduced when depositing the second polysilicon layer on the second wafer surface, compared to the power ratio when depositing the first polysilicon layer on the first wafer surface.

[0112] In some examples, the statistical parameter includes the ratio of the number of first grains with a diameter greater than the average diameter to the number of second grains with a diameter less than or equal to the average diameter in the first and / or second polysilicon layers, and the determining unit 154 is further configured to: The roughness of the first polysilicon layer and / or the second polysilicon layer is determined based on the ratio.

[0113] In some examples, the statistics unit 152 is configured to: The grain contours in the grain image are obtained using an edge detection algorithm; Statistical parameters for determining the grain size in the first polycrystalline silicon layer based on the grain profile.

[0114] In some examples, the statistics unit 152 is configured to: Obtain the minimum circumcircle corresponding to each grain profile; The physical dimension parameters of each smallest circumcircle are used as the physical dimension parameters of the corresponding grain profile; Based on the physical size parameters of all grain contours in all grain images, statistical parameters of the grain size in the first polycrystalline silicon layer are calculated.

[0115] Please refer to Figure 16 The illustration shows a system 160 for producing polycrystalline silicon layers, which may include an imaging device 161 and a controller 162 communicatively coupled to the imaging device 161.

[0116] Imaging device 161 can be implemented as a charged particle beam imaging device, such as scanning electron microscopy (SEM) imaging and transmission electron microscopy (TEM) imaging.

[0117] The controller 162 may include one or more of the following components: processor 1621 and memory 1622.

[0118] Optionally, the processor 1621 connects to various parts within the controller 161 using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1622, and by calling data stored in the memory 1622. Optionally, the processor 1621 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1621 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for the touchscreen display; the NPU implements Artificial Intelligence (AI) functions; and the baseband chip handles wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1621, but may be implemented as a separate chip.

[0119] The memory 1622 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1622 may include a non-transitory computer-readable storage medium. The memory 1622 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1622 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the controller 162, etc.

[0120] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the method for producing a polysilicon layer as described in the various embodiments above.

[0121] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the method for producing a polycrystalline silicon layer as described in the various embodiments above.

[0122] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0123] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for producing a polycrystalline silicon layer, characterized in that, The method includes: Grain images of the first polycrystalline silicon layer deposited on the surface of the first wafer were acquired using charged particle beam imaging. Statistical parameters of the grain size of the first polycrystalline silicon layer were calculated based on the grain image. Obtain the correlation between the statistical parameters and the process parameters; Based on the aforementioned correlation and target parameter values, the process parameters for depositing a second polysilicon layer on the surface of the second wafer are determined.

2. The method for producing a polycrystalline silicon layer according to claim 1, characterized in that, The statistical parameters include the average size of the grains, and the process parameter is the growth temperature. The higher the growth temperature, the larger the average size of the grains.

3. The method for producing a polycrystalline silicon layer according to claim 2, characterized in that, The process parameters for depositing a second polysilicon layer on the surface of the second wafer are determined based on the correlation and the target parameter value, including: When the target average size of the grains is greater than the average size of the grains in the first polysilicon layer, the deposition temperature and / or annealing temperature for depositing the second polysilicon layer on the second wafer surface is increased compared to the deposition temperature and / or annealing temperature when depositing the first polysilicon layer on the first wafer surface. When the target average size is smaller than the average size of the grains of the first polysilicon layer, the deposition temperature and / or annealing temperature for depositing the second polysilicon layer on the second wafer surface is reduced compared to the deposition temperature and / or annealing temperature when depositing the first polysilicon layer on the first wafer surface.

4. The method for producing a polycrystalline silicon layer according to claim 1, characterized in that, The statistical parameters include the grain diameter uniformity index, and the process parameters are the power ratio of the upper and lower heaters. The larger the power ratio of the upper and lower heaters, the larger the grain diameter uniformity index.

5. The method for producing a polycrystalline silicon layer according to claim 4, characterized in that, The process parameters for depositing a second polysilicon layer on the surface of the second wafer are determined based on the correlation and the target parameter value, including: When the target diameter uniformity index is greater than the diameter uniformity index of the first polysilicon layer, the ratio of the power ratio of the upper and lower heaters when depositing the second polysilicon layer on the second wafer surface is increased compared to the power ratio when depositing the first polysilicon layer on the first wafer surface. When the target diameter uniformity index is less than the diameter uniformity index of the first polysilicon layer, the power ratio of the upper and lower heaters is reduced when depositing the second polysilicon layer on the second wafer surface, compared to the power ratio when depositing the first polysilicon layer on the first wafer surface.

6. The method for producing a polycrystalline silicon layer according to claim 1, characterized in that, The statistical parameters include the ratio of the number of first grains with a diameter greater than the average diameter to the number of second grains with a diameter less than or equal to the average diameter in the first and / or second polycrystalline silicon layers. The method further includes: The roughness of the first polysilicon layer and / or the second polysilicon layer is determined based on the ratio.

7. The method for producing a polycrystalline silicon layer according to claim 1, characterized in that, The statistical parameters for calculating the grain size of the first polycrystalline silicon layer based on the grain image include: The grain contours in the grain image are obtained using an edge detection algorithm; Statistical parameters for determining the grain size in the first polycrystalline silicon layer based on the grain profile.

8. The method for producing a polycrystalline silicon layer according to claim 7, characterized in that, The statistical parameters for determining the grain size in the first polysilicon layer based on the grain profile include: Obtain the minimum circumcircle corresponding to each grain profile; The physical dimension parameters of each smallest circumcircle are used as the physical dimension parameters of the corresponding grain profile; Based on the physical size parameters of all grain contours in all grain images, statistical parameters of the grain size in the first polycrystalline silicon layer are calculated.

9. An apparatus for producing polycrystalline silicon layers, characterized in that, The device includes: a data acquisition unit, a statistics unit, an acquisition unit, and a determination unit, wherein, The acquisition unit is configured to acquire grain images of the first polysilicon layer deposited on the surface of the first wafer by a charged particle beam imaging method. The statistics unit is configured to calculate statistical parameters of the grain size of the first polysilicon layer based on the grain image; The acquisition unit is configured to acquire the correlation between the statistical parameters and the process parameters; The determining unit is configured to determine the process parameters for depositing a second polysilicon layer on the surface of the second wafer based on the correlation and the target parameter value.

10. A system for producing polycrystalline silicon layers, characterized in that, The system includes: The imaging device is configured to acquire grain images of the first polysilicon layer deposited on the surface of the first wafer via charged particle beam imaging. A controller, communicatively coupled to the imaging device, includes a processor and a memory, wherein... The memory stores instructions; The processor is configured to execute the instructions to: Statistical parameters of the grain size of the first polycrystalline silicon layer were calculated based on the grain image. Obtain the correlation between the statistical parameters and the process parameters; Based on the aforementioned correlation and target parameter values, the process parameters for depositing a second polysilicon layer on the surface of the second wafer are determined.

11. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; A polycrystalline material layer deposited on the substrate; and, A buried oxide layer covering the polycrystalline material layer; The average size of the grains in the polycrystalline material layer is 230 nm, the average diameter uniformity of all grains in the polycrystalline material layer is 2.8%, and the roughness of the polycrystalline material layer is less than or equal to 50.

12. The semiconductor structure according to claim 11, characterized in that, The grain size in the polycrystalline material layer is greater than or equal to 200 nm and less than or equal to 250 nm; the diameter uniformity of all grains in the polycrystalline material layer is greater than or equal to 0% and less than or equal to 5%; the roughness of the polycrystalline material layer is greater than or equal to 38 and less than or equal to 50.

Images