Wafer offset detection method, system, electronic device and storage medium

Abstract

The application provides a wafer offset detection method, a system, an electronic device and a storage medium. The wafer offset detection method provided by the application utilizes a test device to test each chip on a target wafer to obtain a wafer map of the target wafer; the edge yield of each preset edge in the wafer map is calculated, the distance between the center of the wafer map and the center of the target wafer is calculated, and the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer are combined to determine whether the target wafer has an offset, so that the wafer offset can be accurately detected, and the error of picking and placing chips and the abnormal mixing of materials can be avoided.

Description

Wafer offset detection methods, systems, electronic devices and storage media Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a wafer offset detection method, system, electronic device, and storage medium. Background Technology

[0002] In semiconductor manufacturing, testing, grinding, and dicing processes, wafer alignment is a crucial step. Optical positioning systems, along with positioning edges and slots and the wafer's characteristic patterns, guide equipment to precisely position and align the wafer, establishing a corresponding reference coordinate system to identify chips using X and Y coordinates. Precise positioning and the establishment of this reference coordinate system allow each chip to be represented in coordinates within the various stages of the semiconductor process chain. During chip picking and packaging, any alignment misalignment (X or Y coordinate shift) can cause overall wafer misalignment, leading to misplacement and mixed-material issues during final chip picking. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a wafer offset detection method, system, electronic device and storage medium to solve the above-mentioned technical problems.

[0004] To achieve the above objectives, the first aspect of this application provides a wafer offset detection method, comprising:

[0005] Each chip on the target wafer is tested using testing equipment to obtain a wafer map of the target wafer;

[0006] Calculate the edge yield of each preset edge in the wafer diagram;

[0007] Calculate the distance between the center of the wafer pattern and the center of the target wafer;

[0008] The edge yield of each preset edge in the wafer diagram and the distance between the center of the wafer diagram and the center of the target wafer are used to determine whether the target wafer has an offset.

[0009] In one embodiment, determining whether the target wafer has an offset involves combining the edge yield of each preset edge in the wafer pattern and the distance between the center of the wafer pattern and the center of the target wafer, including:

[0010] When the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size, it is determined that the target wafer has no offset.

[0011] When the edge yield of each preset edge in the wafer diagram is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer diagram and the center of the target wafer is less than half the size of the chip, it is determined that the target wafer has no offset.

[0012] When the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size, it is determined that the target wafer has an offset.

[0013] When the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip, it is determined that the target wafer has an offset.

[0014] In one embodiment, the step of determining whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer pattern and the distance between the center of the wafer pattern and the center of the target wafer, further includes:

[0015] When it is determined that the target wafer is offset, an alarm is triggered to notify the staff to handle the anomaly.

[0016] In one embodiment, the preset edges include: an upper edge, a lower edge, a left edge, a right edge, an upper left edge, an upper right edge, a lower left edge, and a lower right edge; wherein the yield thresholds corresponding to different preset edges may be different.

[0017] In one embodiment, the step of testing each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer further includes:

[0018] The target wafer is fixed on the vacuum chuck of the probe station. The notch or flat edge features of the target wafer are identified by the automatic alignment system. The center of the target wafer is located and calibrated. A rectangular coordinate system is established with the center of the target wafer as the origin.

[0019] The calculation of the distance between the center of the wafer pattern and the center of the target wafer includes:

[0020] Calculate the average of the coordinates of all chips in the wafer diagram, and use it as the center coordinate of the wafer diagram;

[0021] Calculate the distance between the center coordinates of the wafer image and the origin, and use this distance as the distance between the center of the wafer image and the center of the target wafer.

[0022] Based on the same inventive concept, a second aspect of this application provides a wafer offset detection system, comprising:

[0023] The testing module is used to test each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer;

[0024] The first calculation module is used to calculate the edge yield of each preset edge in the wafer diagram;

[0025] The second calculation module is used to calculate the distance between the center of the wafer pattern and the center of the target wafer;

[0026] The offset determination module is used to determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0027] In one embodiment, the offset determination module is used to determine that the target wafer has no offset when the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the size of the chip.

[0028] The offset determination module is used to determine that the target wafer has no offset when the edge yield of each preset edge in the wafer diagram is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer diagram and the center of the target wafer is less than half the size of the chip.

[0029] The offset determination module is used to determine that the target wafer has an offset when the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size.

[0030] The offset determination module is used to determine that the target wafer has an offset when the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip.

[0031] In one embodiment, it further includes:

[0032] The alarm module is used to notify staff to handle the abnormality when it is determined that the target wafer is offset.

[0033] Based on the same inventive concept, a third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer offset detection method described in the first aspect above.

[0034] Based on the same inventive concept, a fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the wafer offset detection method described in the first aspect.

[0035] As can be seen from the above, the wafer offset detection method provided in this application calculates the edge yield of each preset edge in the wafer diagram, calculates the distance between the center of the wafer diagram and the center of the target wafer, and combines the edge yield of each preset edge in the wafer diagram with the distance between the center of the wafer diagram and the center of the target wafer to determine whether the target wafer is offset. This method can accurately detect wafer offset and avoid misplacement and mixing of chips during chip picking. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 is a flowchart of a wafer offset detection method provided in an embodiment of this application;

[0038] Figure 2 is a schematic diagram of a wafer offset to the right provided in another embodiment of this application;

[0039] Figure 3 is a wafer diagram provided in another embodiment of this application;

[0040] Figure 4 is a schematic diagram of the center of the target wafer and the center of the wafer pattern provided in another embodiment of this application;

[0041] Figure 5 is a schematic diagram of a wafer offset detection system provided in another embodiment of this application;

[0042] Figure 6 is a schematic diagram of an electronic device provided in another embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0044] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] Referring to Figure 1, an embodiment of this application provides a wafer offset detection method, which includes the following steps:

[0046] Step S10: Use testing equipment to test each chip on the target wafer to obtain a wafer map of the target wafer;

[0047] Step S20: Calculate the edge yield of each preset edge in the wafer diagram; wherein, the edge yield of each preset edge is the ratio of the number of defective chips in that preset edge to the total number of chips in that preset edge.

[0048] Step S30: Calculate the distance between the center of the wafer pattern and the center of the target wafer;

[0049] Step S40: Combine the edge yield of each preset edge in the wafer map with the distance between the center of the wafer map and the center of the target wafer to determine whether there is an offset in the target wafer.

[0050] The wafer offset detection method provided in this embodiment calculates the edge yield of each preset edge in the wafer diagram, calculates the distance between the center of the wafer diagram and the center of the target wafer, and combines the edge yield of each preset edge in the wafer diagram with the distance between the center of the wafer diagram and the center of the target wafer to determine whether the target wafer is offset. This method can accurately detect wafer offset and avoid misplacement and mixing of chips during chip picking.

[0051] Furthermore, prior to step S10, the following steps are also included:

[0052] Step S01: Fix the target wafer on the vacuum chuck of the probe station. Use the automatic alignment system to identify the notch or flat edge features of the target wafer, locate and calibrate the center of the target wafer, and establish a Cartesian coordinate system with the center of the target wafer as the origin. At the same time, complete the signal calibration between the probe tip and the automatic testing equipment.

[0053] Specifically, step S10 includes: the probe station generates the coordinates of each chip based on the wafer chip array parameters, drives the X / Y axis unit to move the probe card, and makes the probes accurately contact the chip test pads; then, the automatic test equipment applies test signals to the chips according to a preset program, collects and analyzes the chip response data, determines whether the chip is good, defective, or marked as an invalid chip to be skipped, and simultaneously records the coordinates of each valid chip in the Cartesian coordinate system and the test results. After the entire wafer is tested, the valid data is screened and verified, the chips are mapped according to coordinates and assigned different colors according to the test results (e.g., green represents good, red represents defective), and finally a visualized wafer map containing wafer number, test time, chip distribution and status is generated.

[0054] In one embodiment, step S40, determining whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer, includes the following steps:

[0055] Step S41: When the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size, it is determined that the target wafer has no offset.

[0056] Step S42: When the edge yield of each preset edge in the wafer diagram is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer diagram and the center of the target wafer is less than half the size of the chip, it is determined that the target wafer has no offset.

[0057] Step S43: When the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size, it is determined that the target wafer has an offset.

[0058] Step S44: When the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip, it is determined that the target wafer has an offset.

[0059] Specifically, by combining the edge yield of each preset edge in the wafer map with the distance between the center of the wafer map and the center of the target wafer, it is possible to determine whether the target wafer is offset. This allows for precise detection of wafer offset and reduces the risk of false positives. The chip size is defined as the length between the diagonals of the chip.

[0060] In one embodiment, step S40, which combines the edge yield of each preset edge in the wafer map with the distance between the center of the wafer map and the center of the target wafer to determine whether the target wafer has an offset, further includes the following steps:

[0061] Step S50: When it is determined that the target wafer is offset, an alarm is triggered to notify staff to handle the anomaly and allow for timely manual intervention.

[0062] In one embodiment, the preset edges include: top edge, bottom edge, left edge, right edge, top left edge, top right edge, bottom left edge, and bottom right edge; wherein, the yield thresholds corresponding to different preset edges may be different.

[0063] In this embodiment, considering the differences between edges in different directions (e.g., top edge and top left edge) of different wafers, the preset edges are divided into top edge, bottom edge, left edge, right edge, top left edge, top right edge, bottom left edge, and bottom right edge to calculate the edge yield in eight directions. Furthermore, the yield thresholds corresponding to different preset edges can be different, thereby more accurately detecting whether there is a shift in the target wafer and reducing the risk of misjudgment.

[0064] Specifically, the yield thresholds corresponding to different preset edges can be determined based on historical data in the database, such as 80%, 85%, 90%, etc. For example, the yield threshold for the top edge is 85%, and the yield threshold for the top left edge is 80%. In other embodiments, for ease of calculation, the yield thresholds corresponding to different preset edges can be the same.

[0065] Referring to Figure 2, a schematic diagram of a wafer offset to the right is shown. The resulting wafer image is shown in Figure 3. The chips are assigned different colors based on the test results: gray represents good products, and black represents defective products. As can be seen from the figure, there are more defective products on the right edge.

[0066] In one embodiment, step S30, calculating the distance between the center of the wafer pattern and the center of the target wafer, includes the following steps:

[0067] Step S31: Calculate the average value of the coordinates of all chips in the wafer diagram, and use it as the center coordinate of the wafer diagram;

[0068] Step S32: Calculate the distance between the center coordinates of the wafer image and the origin, which is used as the distance between the center of the wafer image and the center of the target wafer.

[0069] Specifically, as discussed above, when obtaining the wafer map in step S10, the coordinates of each chip in a Cartesian coordinate system established with the center of the target wafer as the origin have already been recorded. Therefore, here, the average value of the coordinates of all chips in the wafer map can be calculated as the center coordinates of the wafer map. Referring to Figure 4, point A is the center of the target wafer, and point B is the center of the wafer map. The coordinates of point A are (0,0), and the coordinates of point B are (x,y). Therefore, the distance between the center of the wafer map and the center of the target wafer is... .

[0070] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method.

[0071] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0072] Based on the same inventive concept, corresponding to any of the methods in the above embodiments, this application also provides a wafer offset detection system. Referring to FIG5, the system includes the following modules:

[0073] The testing module is used to test each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer. Specifically, the target wafer is fixed on the vacuum chuck of the probe station, and the automatic alignment system identifies the notch or flat edge features of the target wafer, locates and calibrates the center of the target wafer, and establishes a Cartesian coordinate system with the center of the target wafer as the origin.

[0074] The first calculation module is used to calculate the edge yield of each preset edge in the wafer diagram; wherein, the edge yield of each preset edge is the ratio of the number of defective chips at that preset edge to the total number of chips at that preset edge. Optionally, the preset edges include: top edge, bottom edge, left edge, right edge, top-left edge, top-right edge, bottom-left edge, and bottom-right edge; wherein, the yield thresholds corresponding to different preset edges may be different.

[0075] The second calculation module is used to calculate the distance between the center of the wafer pattern and the center of the target wafer.

[0076] The offset determination module is used to determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0077] The wafer offset detection system provided in this embodiment calculates the edge yield of each preset edge in the wafer diagram, calculates the distance between the center of the wafer diagram and the center of the target wafer, and combines the edge yield of each preset edge in the wafer diagram with the distance between the center of the wafer diagram and the center of the target wafer to determine whether the target wafer is offset. It can accurately detect wafer offset and avoid misplacement and mixing of chips during chip picking.

[0078] In one embodiment, the offset determination module is used to determine that the target wafer has no offset when the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size.

[0079] The offset determination module is used to determine that the target wafer has no offset when the edge yield of each preset edge in the wafer map is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is less than half the size of the chip.

[0080] The offset determination module is used to determine that the target wafer has an offset when the edge yield of at least one preset edge in the wafer map is less than the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size.

[0081] The offset determination module is used to determine that there is an offset in the target wafer when the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip.

[0082] In one embodiment, the wafer offset detection system further includes an alarm module, which is used to notify staff to handle the abnormality when it is determined that the target wafer is offset.

[0083] In one embodiment, the second computing module includes:

[0084] The first calculation submodule is used to calculate the average value of the coordinates of all chips in the wafer diagram, which is used as the center coordinate of the wafer diagram.

[0085] The second calculation submodule is used to calculate the distance between the center coordinates of the wafer image and the origin, which is used as the distance between the center of the wafer image and the center of the target wafer.

[0086] The wafer offset detection system in this embodiment has the beneficial effects of the above-described method embodiments, which will not be repeated here.

[0087] Based on the same inventive concept, corresponding to any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer offset detection method of any of the above embodiments.

[0088] Figure 6 shows a more specific hardware structure diagram of an electronic device provided in this embodiment. The device may include: a processor 1101, a memory 1102, an input / output interface 1103, a communication interface 1104, and a bus 1105. The processor 1101, memory 1102, input / output interface 1103, and communication interface 1104 are interconnected within the device via the bus 1105.

[0089] The processor 1101 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0090] The memory 1102 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1102 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1102 and is called and executed by the processor 1101.

[0091] Input / output interface 1103 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0092] The communication interface 1104 is used to connect the communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0093] Bus 1105 includes a pathway for transmitting information between various components of the device, such as processor 1101, memory 1102, input / output interface 1103, and communication interface 1104.

[0094] It should be noted that although the above-described device only shows the processor 1101, memory 1102, input / output interface 1103, communication interface 1104, and bus 1105, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0095] The electronic devices described above are used to implement the corresponding wafer offset detection methods in any of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0096] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the wafer offset detection method as described in any of the above embodiments.

[0097] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0098] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the wafer offset detection method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0099] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0100] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0101] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0102] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A wafer offset detection method, characterized in that, include: Each chip on the target wafer is tested using testing equipment to obtain a wafer map of the target wafer; Calculate the edge yield of each preset edge in the wafer diagram; Calculate the distance between the center of the wafer pattern and the center of the target wafer; determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer pattern and the distance between the center of the wafer pattern and the center of the target wafer; determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer pattern and the distance between the center of the wafer pattern and the center of the target wafer, including: when the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size, determine that the target wafer has no offset; when the edge yield of each preset edge in the wafer pattern is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than one-quarter of the chip size, determine that the target wafer has no offset. When the size is half of the target wafer, it is determined that the target wafer has no offset; when the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is greater than one-quarter of the chip size and less than half of the chip size, it is determined that the target wafer has an offset; when the distance between the center of the wafer image and the center of the target wafer is greater than or equal to half of the chip size, it is determined that the target wafer has an offset; the step of testing each chip on the target wafer with testing equipment to obtain the wafer image of the target wafer also includes: fixing the target wafer on the vacuum chuck of the probe station, identifying the notch or flat edge features of the target wafer through an automatic alignment system, locating and calibrating the center of the target wafer, and establishing a rectangular coordinate system with the center of the target wafer as the origin.

2. The wafer offset detection method according to claim 1, characterized in that, The method involves determining whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer diagram and the distance between the center of the wafer diagram and the center of the target wafer. The method further includes: when it is determined that the target wafer has an offset, an alarm is triggered to notify the staff to handle the abnormality.

3. The wafer offset detection method according to claim 1, characterized in that, The preset edges include: top edge, bottom edge, left edge, right edge, top left edge, top right edge, bottom left edge, and bottom right edge; wherein, the yield thresholds corresponding to different preset edges may be different.

4. The wafer offset detection method according to claim 1, characterized in that, The calculation of the distance between the center of the wafer pattern and the center of the target wafer includes: calculating the average value of the coordinates of all chips in the wafer pattern as the center coordinates of the wafer pattern; and calculating the distance between the center coordinates of the wafer pattern and the origin as the distance between the center of the wafer pattern and the center of the target wafer.

5. A wafer offset detection system, characterized in that, include: The testing module is used to test each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer; The first calculation module is used to calculate the edge yield of each preset edge in the wafer diagram; The second calculation module is used to calculate the distance between the center of the wafer pattern and the center of the target wafer. The target wafer is fixed on the vacuum chuck of the probe station, and an automatic alignment system identifies the notch or flat edge features of the target wafer to locate and calibrate its center. A Cartesian coordinate system is established with the center of the target wafer as the origin. The offset determination module is used to determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer pattern and the distance between the center of the wafer pattern and the center of the target wafer. The offset determination module determines that the target wafer is not offset when the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size. An offset exists; the offset determination module is used to determine that the target wafer has no offset when the edge yield of each preset edge in the wafer image is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is less than half the size of the chip; the offset determination module is used to determine that the target wafer has an offset when the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is greater than one-quarter of the size of the chip and less than half the size of the chip; the offset determination module is used to determine that the target wafer has an offset when the distance between the center of the wafer image and the center of the target wafer is greater than or equal to half the size of the chip.

6. The wafer offset detection system according to claim 5, characterized in that, Also includes: The alarm module is used to notify staff to handle the abnormality when it is determined that the target wafer is offset.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the wafer offset detection method as described in any one of claims 1 to 4.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the wafer offset detection method according to any one of claims 1 to 4.

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