Devices including exposed conductive layers and methods of making same

Abstract

The invention relates to a device including an exposed conductive layer and a method of manufacturing the device. An electronic system includes a first device and a second device bonded to the first device. A first device includes: a semiconductor substrate having an opening; a stack having a metal layer and a conductive via; and a conductive layer including aluminum, the conductive layer having a first face in contact with the stack and a second face opposite the first face partially exposed through the opening. The stacked metal layers and conductive vias are made of a conductive material different from aluminum.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. FR2408751, filed on 7 August 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices including exposed conductive layers and methods of manufacturing such devices. Background Technology

[0004] For the manufacture of electronic devices, bonding one chip to another expands design possibilities. However, the design and manufacturing process of connection pads accessible to other electronic devices still presents some challenges. In particular, where the pads are used for testing purposes, it is often desirable for the pads to allow testing of devices formed as part of one of the chips before assembly, and to allow testing of devices formed on both chips after assembly.

[0005] The drawback of existing solutions is that they do not offer the possibility of testing the devices in one of the wafers before assembly. Furthermore, they require numerous photolithography steps and / or the use of a large number of masks, which increases manufacturing costs.

[0006] Therefore, there is a need in this field for cost-effective solutions to address the aforementioned drawbacks. Summary of the Invention

[0007] According to one aspect, an electronic system is provided, comprising a first device including: a semiconductor substrate having an opening; a stack including a plurality of metal layers and conductive vias; and a conductive layer including aluminum having a first side in contact with the stack and a second side opposite to the first side, the second side being partially exposed through the opening, wherein the stacked metal layers and conductive vias are made of a conductive material different from aluminum.

[0008] According to one embodiment, the system further includes a second device, wherein the second device contacts the stack of the first device at a connection interface opposite to the semiconductor substrate.

[0009] According to one embodiment, the conductive layer is at least partially embedded in the semiconductor substrate.

[0010] According to one embodiment, the conductive layer is separated from the semiconductor substrate by one or more stacked conductive layers.

[0011] According to one embodiment, the conductive material of the stacked metal layers and the conductive vias is copper.

[0012] According to one embodiment, the conductive layer includes a central layer made of aluminum, as well as a top layer and a bottom layer.

[0013] According to one embodiment, the bottom layer is made of a material comprising tantalum, preferably tantalum nitride.

[0014] According to one embodiment, the top layer is formed of at least one of titanium nitride, silicon nitride, and tantalum nitride.

[0015] According to one embodiment, the conductive layer has a thickness ranging from 1 μm to 2 μm, and preferably from 1.5 μm to 2 μm.

[0016] According to another aspect, a method for manufacturing an electronic system is provided, the electronic device including a first device, the method comprising: providing a semiconductor substrate; forming a conductive module on a first surface of the semiconductor substrate, the conductive module including i) a stack comprising a plurality of metal layers and conductive vias, and ii) a conductive layer comprising aluminum and a first surface in contact with the stack, wherein the stacked metal layers and conductive vias are made of a conductive material different from aluminum; and etching the semiconductor substrate on a second surface opposite to the first surface to create an opening to partially expose the second surface of the conductive layer opposite to the first surface.

[0017] According to one embodiment, the method further includes: providing a second device; and attaching the second device to the stack of the first device at a connection interface opposite to the semiconductor substrate.

[0018] According to one embodiment, forming a conductive module includes forming a conductive layer by: etching trenches within a semiconductor substrate to a depth less than or equal to the thickness of the conductive layer; and growing an aluminum layer to fill the trenches.

[0019] According to one embodiment, forming the conductive layer further includes etching a portion of the aluminum layer to obtain the conductive layer.

[0020] According to one embodiment, forming the conductive module further includes forming the stack, wherein forming the conductive layer is performed prior to forming the stack.

[0021] According to another aspect, an image sensor or memory unit including the above-described system is provided. Attached Figure Description

[0022] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation with reference to the accompanying drawings, wherein:

[0023] Figure 1A This is a cross-sectional view illustrating an apparatus according to an embodiment of the present disclosure;

[0024] Figure 1B This is a cross-sectional view illustrating an apparatus according to an embodiment of the present disclosure, the apparatus including components that engage with another apparatus. Figure 1A The device;

[0025] Figure 2 This is a cross-sectional view of an apparatus according to an embodiment of the present disclosure, the apparatus including a first device (e.g., forming part of a first wafer) coupled to another device (e.g., forming part of a second wafer);

[0026] Figure 3 This is a cross-sectional view of an apparatus according to another embodiment of the present disclosure, the apparatus including a first device (e.g., forming part of a first wafer), the first device being coupled to another device (e.g., forming part of a second wafer); and

[0027] Figures 4A to 4O yes Figure 1A A cross-sectional view of the successive steps in the manufacturing process of the device. Detailed Implementation

[0028] In the various figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0029] For clarity, only operations and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, the process steps involved in the manufacture of electronic devices (such as photolithography, etching, and material deposition) are known to those skilled in the art and are not described in detail.

[0030] Unless otherwise indicated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than the conductor, while when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0031] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as the terms "above", "below", "higher", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), the orientation shown in the figure is used.

[0032] In this disclosure, unless otherwise specified, the expressions “approximately,” “about,” “substantially,” and “around” indicate within 10%, and preferably within 5%.

[0033] In this disclosure, unless otherwise specified, whenever an example range is given, the limit values ​​of that range are considered to be included in that range.

[0034] Figure 1A This is a cross-sectional view illustrating an apparatus 100 (e.g., forming part of a first wafer) according to an exemplary embodiment of the present disclosure.

[0035] The device 100 includes a substrate 130. The substrate 130 is, for example, a semiconductor substrate, such as a substrate formed of silicon or including silicon.

[0036] Device 100 includes, for example, an interconnect layer forming a stack 140. Stack 140 includes, for example, one or more metal layers 158, 159 (e.g., made of copper), and includes, for example, conductive vias connected to the one or more metal layers and passing through one or more dielectric layers. The one or more metal layers and conductive vias are formed, for example, of a conductive material different from aluminum.

[0037] The device 100 also includes a conductive layer 120 comprising aluminum. For example, as... Figure 1A As shown, the conductive layer 120 may include an aluminum sublayer 125 sandwiched between additional sublayers 126 and 127 formed of other conductive materials. For example, the sublayer 126 formed on the underside of the aluminum sublayer 125 is formed of tantalum, tantalum nitride, or other tantalum-containing materials. The sublayer 127 formed on the top surface of the aluminum sublayer 125 is formed of, for example, titanium nitride, silicon nitride, or tantalum nitride.

[0038] One advantage of having a conductive layer 120 containing aluminum and one or more metal layers 158, 159 and conductive vias of a stack 140 made of a different conductive material (e.g., copper) is that the conductive layer 120 can be positioned at any depth of the device 100, thereby simplifying the manufacturing process. Because the conductive layer is made of a different conductive material than the metal layers 158, 159 and the conductive vias, they are fabricated in two separate process steps, allowing for easier provision of all the features that enable these components to perform their respective functions in the device.

[0039] according to Figure 1A In one embodiment shown, the conductive layer 120 is located at the interface between the substrate 130 and the stack 140. For example, the conductive layer 120 is at least partially embedded within the substrate 130.

[0040] It will be noted that only a portion (less than all) of the surface of the conductive layer 120 is exposed and accessible through the opening 135 in the substrate 130, and is configured, for example, to connect to an external device. Figure 1A (Not shown in the diagram). For example, the central portion of the surface is exposed, while the peripheral portion of the surface (around the central portion) is covered. In particular, the conductive layer 120 is, for example, the connection pad of the device 100. Figure 1AIt is not drawn to scale. For example, in practice, the width W of opening 135 is 5 to 10 times the height H of opening 135. For example, the width W is in the range of 40 μm to 60 μm, and the height H is in the range of 4 μm to 12 μm.

[0041] according to Figure 1A In one embodiment shown, the conductive layer 120 is formed in a layer closer to the substrate 130 than the first metal layer 159 of the stack 140.

[0042] According to one embodiment, the device 100 further includes a connection interface 150 located on a first surface of the device 100. This first surface is, for example, the surface of the stack 140 opposite to the surface that contacts the substrate 130. The connection interface 150 includes one or more metal contacts, labeled 15A to 15I and collectively referred to as 155, and the connection interface 150 is configured to connect a first wafer to a second wafer. Figure 1A (Not shown in the image). Metal contacts 155 are connected, for example, to at least one of one or more metal layers of the stack 140 via conductive vias, and at least one metal contact 155 is connected to the conductive layer 120, for example, via one or more conductive vias 156 and one or more metal layers 158, 159. Figure 1A In the example, metal contacts 15A to 15D are connected to metal layer 158, and five metal contacts 15E to 15I are connected to conductive layer 120 using conductive vias 156 and metal layers 158 and 159. While five metal contacts 15E to 15I are presented, in alternative embodiments, there may be more or fewer conductive contacts 155 connected to conductive layer 120. Metal contacts 155 are configured for connection to another device. Figure 1A The corresponding metal contact (not shown in the image).

[0043] For example, the conductive layer 120 is connected only to one or more metal contacts 155 of the connection interface 150, and not to other components of the device 100. In other words, the conductive layer 120 is (specifically) used to contact other devices connected to the metal contacts 155.

[0044] Device 100 includes, for example, one or more isolation rings 160 within substrate 130, the isolation rings 160 being configured to isolate device 100 from charge buildup near opening 135 and to isolate lead engagement from any erroneous contact of the portion of substrate 130 located within one or more isolation rings 160.

[0045] Figure 1B This is a cross-sectional view of a system 170 according to an exemplary embodiment of the present disclosure, the system 170 including... Figure 1A The device 100 is coupled to another device 180, for example, forming part of a second wafer.

[0046] According to one embodiment, the connection interface 150 of the first wafer of the device 100 is bonded to the connection interface of the second wafer using, for example, hybrid bonding (HB) technology, such that the first and second wafers are stacked face-to-face. Metal contacts 155 of the connection interface 150 are connected, for example, to one or more metal contacts 190 of the connection interface of the second wafer. The positioning of the metal contacts 155 of the first wafer, for example, matches the positioning of the metal contacts of the second wafer, such that they are aligned and form an electrical contact.

[0047] Advantageously, the device 100 including the conductive layer 120 is positioned on top of another device 180. For example, the other device 180 does not include a corresponding conductive layer. One advantage of positioning the device 100 including the conductive layer 120 on top is that a deep etching step is not required to create an opening 135 for contacting the conductive layer 120. For example, the distance between the conductive layer 120 and the top surface of the device 100 is small enough to avoid a deep etching step. In other words, the conductive layer placed in the top device is close to the free surface of the system where the etching process is performed.

[0048] Another advantage of positioning the device 100, including the conductive layer 120, on top is that the fabrication of the stack of device 100 and the additional device 180 is simplified because there are few (or no) constraints on the construction of the metal layers 158, 159 and the conductive vias. For example, the portion of system 170 located between the conductive layer 120 and the substrate 130 (in which the opening 135 is fabricated) should not contain any metal layers and conductive vias. By placing the conductive layer 120 in the top device, such constraints are reduced or avoided.

[0049] The second wafer includes, for example, a substrate 192 covered by a stack 194, which includes, for example, one or more metal layers (e.g., made of copper) and, for example, conductive vias connected to the one or more metal layers and passing through one or more dielectric layers. The second wafer includes, for example, conductive layers and electronic components connected to the device 100 and / or connected to the conductive layer 120 via metal contacts 155, 190.

[0050] One advantage of having the conductive layer 120 in contact with the substrate 130 is that the opening 135 exposes only the conductive layer 120, while the stack 140 is not exposed by the opening 135. This reduces the risk of electrostatic charge buildup during the process step that creates the opening 135, especially since this process step occurs towards the end of the manufacturing process. Figure 1A and Figure 1B Another advantage of this embodiment is that the stack 140 is not exposed to the environment and moisture, which increases reliability. For example, the use of sealing rings to protect the exposed surfaces of the stack 140 can be avoided.

[0051] Although Figure 1A and Figure 1B The figure shows a single device 100 of the first wafer and a single device 180 of the second wafer, but the first wafer and the second wafer may each include multiple similar devices, such as hundreds or thousands of devices, which will be separated, for example, during a dicing operation to form discrete two-tier devices.

[0052] Figure 2 This is a cross-sectional view of an apparatus 200 according to another exemplary embodiment of the present disclosure, the apparatus 200 including a first device 210 (e.g., forming part of a first wafer) which is coupled to another device 280 (e.g., forming part of a second wafer).

[0053] Device 200 and Figure 1B The device 170 is similar to that of the device 200, and similar features are referenced by the same reference numerals. The difference between the device 170 and the device 200 is that, in the device 200, the conductive layer 120 does not contact the substrate 130.

[0054] According to one embodiment, the conductive layer 120 is located in a dedicated conductive layer of the first device 210 and is separated from the substrate 130 by one or more intermediate layers. For example, the intermediate layers correspond to the metal levels of the device, each metal level including metal tracks and separated from adjacent metal levels by a corresponding dielectric layer. For example, the conductive layer 120 is only connected to the connection interface 150 of the first wafer. For example, the conductive layer 120 is formed at the same level (e.g., within the metal level) of the first device 210 that is furthest from the substrate 130 (or in other words, closest to the connection interface 150). In particular, the conductive layer 120 does not directly contact the substrate, but rather a portion of a stack 140 is inserted between the conductive layer and the substrate.

[0055] exist Figure 2 In one example, a long hybrid bonding via (HBV) is formed to connect the connection interface 150 to a metal layer of the stack 140, for example, the metal layer being positioned closer to the substrate 130 than the conductive layer 120.

[0056] Figure 2 One advantage of this embodiment is that it can be implemented with relatively few modifications to standard manufacturing processes, such as adding a single photolithography step.

[0057] Figure 3 This is a cross-sectional view of a device 200' according to another exemplary embodiment of the present disclosure, the device 200' including a first device 210' (e.g., forming part of a first wafer), the first device 210' being coupled to another device 280' (e.g., forming part of a second wafer).

[0058] Device 200' and Figure 2 The device is similar to 200, except that the conductive layer 120 is implemented in a metal layer of the device, which includes additional metal tracks for providing additional interconnections within the stack 140. These metal tracks are formed, for example, during the same process steps as the conductive layer 120, and are therefore formed of one or more metals that are the same as the conductive layer 120.

[0059] exist Figure 3 In the example, in addition to the conductive layer 120 being connected to the connection interface 150, the conductive layer 120 is also connected to other metal layers of the first device 210'.

[0060] and Figure 1B Device 170 and Figure 2 Compared to device 200, device 200' can be fabricated using at least one less photolithography step and one less mask because the formation of conductive layer 120 can be performed simultaneously with other structures of device 200'. This reduces costs.

[0061] For example, the conductive layer 120 is formed in the metal layer of the first device 210' that is furthest from the substrate 130 (i.e., closest to the connection interface 150). In particular, the conductive layer 120 does not directly contact the substrate, but rather a portion of the stack 140 is inserted between the conductive layer and the substrate.

[0062] Figures 4A to 4O This is an example embodiment based on the present disclosure. Figure 1A A cross-sectional view of the successive steps of the manufacturing process of the device 100.

[0063] Figures 4A to 4O Some components and Figure 1A The components are the same. These components are labeled with the same reference numerals and will not be described in detail again.

[0064] Figure 4A The diagram illustrates the relationship with Figure 1A The example starting point of the manufacturing process of device 100 corresponds to device 400.

[0065] The device 400 includes a substrate 130, for example, corresponding to a portion of a first wafer.

[0066] According to one embodiment, device 400 includes a dielectric layer 405 covering a substrate 130. The dielectric layer 405 includes a sublayer formed, for example, of silicon carbonitride (SiCN), which is optionally covered by a sublayer formed of a dielectric. For example, the dielectric is a dielectric having an ultra-low dielectric constant (e.g., below 2.5). As an example, the dielectric is a composite of silicon dioxide and organosilicon glass, such as SiCOH. The dielectric layer 405 is deposited, for example, using chemical vapor deposition. The thickness of the SiCN sublayer is, for example, in the range of 10 nm to 30 nm, while the thickness of the dielectric layer is, for example, in the range of 35 nm to 55 nm. The dielectric layer 405 has a thickness, for example, in the range of 400 nm to 500 nm.

[0067] Device 400 includes, for example, a contact 407 that passes through dielectric layer 405, and is made of tungsten.

[0068] Figure 4B The diagram illustrates the process after the photolithography step. Figure 4A Device 400.

[0069] For example, a first mask layer 410 is formed on the surface of the dielectric layer 405 using photolithography. The first mask layer 410 includes an opening 415 that exposes the surface of the dielectric layer 405.

[0070] Figure 4C The illustration shows the process after the optional etching step. Figure 4B The device.

[0071] In embodiments where the substrate 130 is covered by a dielectric layer 405, the dielectric layer 405 is etched at the location of the opening 415, for example, using dry etching. In the presence of multiple dielectric layers, this process can be repeated. Figure 4C The steps involve successively etching the dielectric layer until the substrate layer 130 is exposed.

[0072] In other embodiments not illustrated, Figure 4A The device 400 does not include a dielectric layer 405. A first mask layer 410 is formed on the surface of the substrate 130 and includes an opening 415 to expose the surface of the substrate 130. Therefore, it can be omitted. Figure 4C The etching steps are shown in the figure.

[0073] Figure 4D The illustration shows the process after the etching step. Figure 4C The device.

[0074] The substrate layer 130 is etched through the opening 415, for example, using wet etching. For example, a cavity 417 with a height L1 is formed in the substrate layer 130, the height L1 being less than the thickness L2 of the substrate layer 130. The height L1 is, for example, in the range of 1 μm to 2 μm, such as in the range of 1.2 μm to 1.8 μm.

[0075] Figure 4E The illustration shows the effect after removing the first mask layer 410. Figure 4D The device.

[0076] For example, the first mask layer 410 is stripped off.

[0077] Figure 4F The illustration shows the process following one or more optional deposition steps. Figure 4E The device.

[0078] According to one embodiment, a dielectric layer (not shown) is deposited to cover the surface of the device. For example, an oxide layer, such as tetraethyl orthosilicate (TEOS), is deposited. The thickness of the dielectric layer is, for example, in the range of 5 nm to 20 nm.

[0079] According to one embodiment, Figure 1A The conductive sublayer 127 of the conductive layer 120 is deposited on the surface of the dielectric layer, or directly deposited to cover it. Figure 4E The surface of the device. For example, a first sublayer formed of titanium nitride or silicon nitride is deposited, with a thickness, for example, in the range of 15 nm to 35 nm. For example, a second sublayer formed of tantalum nitride is deposited, with a thickness, for example, in the range of 10 nm to 30 nm.

[0080] Figure 4G The illustration shows the deposition Figure 1A After the aluminum sublayer 125 (e.g., using sputtering) Figure 4F The device. Aluminum sublayer 125 is deposited on... Figure 4F The thickness of the aluminum sublayer 125 is, for example, in the range of 1 μm to 2 μm and, for example, 1.4 μm to 1.5 μm.

[0081] In some embodiments, the thickness of the aluminum sublayer 125 is greater than the height L1 of the cavity formed in the substrate layer 130.

[0082] exist Figure 4F One advantage of depositing the optional dielectric and conductive sublayer 127 at the steps shown is that they prevent direct contact between the substrate layer 130 and the aluminum sublayer 125. These layers, for example, form diffusion barrier layers, etch stop barrier layers, or both, to protect the aluminum sublayer 125.

[0083] In some embodiments, the following is omitted Figure 4F The steps shown are performed, and the aluminum sublayer 125 is directly deposited on the surface of the substrate layer 130.

[0084] Figure 4H The illustration shows the process following one or more optional deposition steps. Figure 4G The device.

[0085] According to one embodiment, a conductive sublayer 126 is deposited on the surface of an aluminum sublayer 125. For example, a first sublayer formed of tantalum is deposited, with a thickness in the range of 5 nm to 15 nm. For example, a second sublayer formed of tantalum nitride is deposited on the surface of the first tantalum sublayer, with a thickness in the range of 150 nm to 170 nm.

[0086] exist Figure 4F , Figure 4G and Figure 4H The sublayers 127, 125, and 126 deposited in the steps shown are formed together. Figure 1A The conductive layer 120. For example, this is achieved using a damascene process.

[0087] Figure 4I The diagram illustrates the process after the photolithography step. Figure 4H The device.

[0088] For example, using photolithography in Figure 4H On the surface of the device or directly on Figure 4G A second mask layer 430 is formed on the surface of the device. The second mask layer 430 is positioned above the cavity 417 and is, for example, wider than the opening 415 of the first mask layer 410.

[0089] Figure 4J The illustration shows the result after one or more etching steps. Figure 4I The device.

[0090] One or more etching steps (e.g., dry etching) are used to etch the conductive layer and / or dielectric layer covering the dielectric layer 405 to expose the dielectric layer 405 outside the area covered by the second mask layer 430.

[0091] exist Figure 4A In embodiments of the device 400 that do not include the dielectric layer 405, the substrate layer 130 is exposed outside the area covered by the second mask layer 430.

[0092] Figure 4K The illustration shows the result after removing the second mask layer 430. Figure 4J The device.

[0093] For example, the second mask layer 430 is stripped off.

[0094] Figure 4L The diagram illustrates the process after the thinning step. Figure 4K The apparatus described herein includes a thinning step for removing excess material from the conductive layer 120 to obtain a flat surface, for example, flush with the dielectric layer 405. Thinning may involve, for example, chemical mechanical polishing.

[0095] Figure 4M The diagram illustrates the process after several deposition steps. Figure 4L The device.

[0096] For example, formed through successive depositional steps Figure 1A The stack 140 of one or more conductive and / or dielectric layers as described herein.

[0097] According to one embodiment, metal vias are formed, for example, by electroplating, to connect the conductive layer 120 to the connection interface 150. Alternatively, other metal vias are formed to connect metal tracks to the connection interface 150.

[0098] Figure 4N The image shows the flipped Figure 4M The device is such that the substrate layer 130 faces upward.

[0099] Figure 4O The illustration shows the process after the etching step. Figure 4N The device.

[0100] According to some embodiments, a photolithography step is performed to... Figure 1A A third mask layer (not shown) with an opening is deposited at the location of opening 135.

[0101] The substrate layer 130 is etched (e.g., using wet etching) to create an opening 135 to expose the conductive layer 120. In embodiments where the conductive layer 120 includes a sublayer 127, the sublayer 127 is exposed, for example. The sublayer 127 includes, for example, an etched stop barrier layer to protect the aluminum sublayer 125. The sublayer 127 is, for example, harder than aluminum and helps absorb and disperse the forces generated by applying a probe tip to the surface of the sublayer 127 to measure or apply current or voltage during subsequent testing of the device.

[0102] Then, the third mask layer is removed after the etching step.

[0103] The opening 135 has a width, for example, in the range of 40 μm to 100 μm and a height in the range of 3 μm to 15 μm.

[0104] In the embodiment where the aluminum sublayer 125 is deposited directly on the surface of the substrate layer 130, Figure 4O Etching of the middle substrate layer 130 exposes the aluminum sublayer 125.

[0105] According to Figure 4O The device generated by the steps described above and Figure 1A The device 100 corresponds to this.

[0106] In the embodiments described herein, conductive layer 120 comprises, for example, aluminum, but not copper. One advantage of using aluminum instead of copper for sublayer 125 is that a copper-free region is obtained at the location of opening 135, thereby simplifying the process steps. Another advantage of using aluminum instead of copper is that aluminum provides passivation and does not diffuse oxygen.

[0107] One advantage of having a conductive layer 120 on the first wafer, including the opening 135, is that the device 100 of the first wafer can be tested independently of the device 180 of the second wafer without being bonded to the second wafer. This results in a reduction in unit production cost compared to having one or more conductive layers 120 formed within the second device 180.

[0108] Furthermore, the embodiments described herein require relatively few photolithography steps and masks, resulting in relatively low manufacturing costs. Additionally, the described manufacturing process is compatible with the formation of planar surfaces compatible with the formation of optical lenses.

[0109] Devices 100, 170, 200, 200' are, for example, image sensors (e.g., 3D stacked back-illuminated (BSI) image sensors), memory units, or processors.

[0110] Devices 100, 170, 200, 200' are included, for example, in 3D stacking devices involving wafer-to-wafer bonding or die-to-wafer bonding.

[0111] Devices 100, 170, 200, 200' include, for example, components implemented in electronic devices (such as telephones, computers, cameras, or displays), for example, in the telecommunications or automotive industries.

[0112] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. In particular, while a first wafer configured to be bonded to a second wafer has been described, in alternative embodiments, a die-on-wafer process can be used, wherein the first wafer is separated into individual devices, which are individually bonded to the second wafer.

[0113] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. An electronic system comprising a first device, wherein the first device comprises: A semiconductor substrate with an opening; It includes a stack of multiple metal layers and conductive vias; as well as The conductive layer includes an aluminum layer having a first side in contact with the stack and a second side opposite the first side, wherein less than a portion of the second side is exposed through an opening. The stacked metal layers and conductive vias are made of a conductive material different from aluminum.

2. The system of claim 1 further includes a second device that contacts the stack of the first device at a connection interface opposite to the semiconductor substrate.

3. The system of claim 2, wherein the second device comprises a corresponding semiconductor substrate covered by a corresponding stack, the corresponding stack comprising one or more corresponding metal layers and corresponding conductive vias connected to the one or more corresponding metal layers and passing through the one or more corresponding dielectric layers.

4. The system of claim 2, wherein the first device and the second device include corresponding metal contacts, wherein the metal contacts of the first device are connected to the metal contacts of the second device at the connection interface.

5. The system of claim 1, wherein the conductive layer is at least partially embedded in the semiconductor substrate.

6. The system of claim 1, wherein the conductive layer is separated from the semiconductor substrate by the stacked one or more conductive layers.

7. The system of claim 1, wherein the conductive material of the stacked metal layers and the conductive vias is copper.

8. The system of claim 1, wherein the conductive layer comprises a central layer made of aluminum, as well as a top layer and a bottom layer.

9. The system of claim 8, wherein the bottom layer is made of a material comprising tantalum, preferably tantalum nitride.

10. The system of claim 8, wherein the top layer is formed of at least one of titanium nitride, silicon nitride, and tantalum nitride.

11. The system of claim 1, wherein the conductive layer has a thickness ranging from 1 μm to 2 μm.

12. The system of claim 1, wherein the opening has a width in the range of 40 μm to 60 μm and a height in the range of 4 μm to 12 μm.

13. The system of claim 1, further comprising an external device electrically connected to the first device via a conductive layer.

14. The system of claim 1, wherein the portion of the second surface exposed through the opening is the central portion of the second surface, while the peripheral portion of the second surface is covered.

15. A 3D stacked back-illuminated image sensor, comprising the system of claim 1.

16. A method for manufacturing an electronic system, the electronic system comprising a first apparatus, the method comprising: Provide semiconductor substrates; A conductive module is formed on a first surface of a semiconductor substrate, the conductive module comprising: i) a stack including a plurality of metal layers and conductive vias, and ii) a conductive layer including aluminum and a first surface in contact with the stack, wherein the stacked metal layers and conductive vias are made of a conductive material different from aluminum; as well as The semiconductor substrate is etched on the second surface opposite to the first surface to create an opening, exposing only a portion of the conductive layer on the second surface opposite to the first surface.

17. The method of claim 16, further comprising: Provide a second device; as well as The second device is attached to the stack of the first device at a connection interface opposite to the semiconductor substrate.

18. The method of claim 17, wherein the second device comprises a corresponding semiconductor substrate covered by a corresponding stack, the corresponding stack comprising one or more corresponding metal layers and corresponding conductive vias connected to the one or more corresponding metal layers and passing through the one or more corresponding dielectric layers, and wherein the first device and the second device comprise corresponding metal contacts, wherein the metal contacts of the first device are connected to the metal contacts of the second device at a connection interface.

19. The method of claim 16, wherein forming the conductive module comprises forming the conductive layer by: Trenches are etched within the semiconductor substrate to a depth less than or equal to the thickness of the conductive layer; and An aluminum layer is grown to fill the trench.

20. The method of claim 19, wherein forming the conductive layer further comprises etching a portion of the aluminum layer to obtain the conductive layer.

21. The method of claim 19, wherein forming the conductive module further comprises forming the stack, and wherein forming the conductive layer is performed prior to forming the stack.

22. The method of claim 16, wherein etching creates an opening that exposes the central portion of the second surface, while the peripheral portion of the second surface remains covered.

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