Substrate

Abstract

A substrate includes: a core layer including an active region in which a semiconductor chip is mounted and a dummy region surrounding the active region; a plurality of through vias disposed in the active region and passing through the core layer; a plurality of dummy through-vias disposed in the dummy region and passing through the core layer; a plurality of upper connection pads disposed on an upper surface of the core layer in the active region, each of the plurality of upper connection pads being electrically connected to a respective one of the plurality of through vias; a plurality of upper support pads disposed on an upper surface of the core layer in the dummy region, each of the plurality of upper support pads being in contact with a corresponding one of the plurality of dummy through vias; and a plurality of lower support pads disposed on a lower surface of the core layer in the dummy region, each of the plurality of lower support pads being in contact with a respective one of the plurality of dummy through-vias.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to a substrate including a dummy through-via. BACKGROUND

[0002] As the demand for implementation of high performance, high speed, and / or multifunctionalization of semiconductor devices increases, the integration degree of semiconductor devices has been increasing. In manufacturing semiconductor devices having a fine pattern corresponding to the high integration trend of semiconductor devices, it is necessary to implement a pattern having a fine width or a fine separation distance. Accordingly, a substrate on which a semiconductor chip is mounted continues to decrease in thickness. Therefore, a technology for preventing damage or warping of the substrate during a semiconductor package manufacturing process is required. SUMMARY

[0003] An aspect of the present inventive concept provides a substrate including a dummy through-via disposed in a dummy area and upper and lower support pads connected thereto.

[0004] According to an aspect of the present inventive concept, there is provided a substrate including: a core layer including an active area in which a semiconductor chip is mounted and a dummy area surrounding the active area; a plurality of through-vias disposed in the active area and passing through the core layer; a plurality of dummy through-vias disposed in the dummy area and passing through the core layer; a plurality of upper connection pads disposed on an upper surface of the core layer in the active area, each of the plurality of upper connection pads being electrically connected to a respective one of the plurality of through-vias; a plurality of upper support pads disposed on the upper surface of the core layer in the dummy area, each of the plurality of upper support pads being in contact with a respective one of the plurality of dummy through-vias; and a plurality of lower support pads disposed on a lower surface of the core layer in the dummy area, each of the plurality of lower support pads being in contact with a respective one of the plurality of dummy through-vias.

[0005] According to another aspect of the inventive concepts, a substrate is provided that includes a core layer including an active region in which a semiconductor chip is mounted and a dummy region surrounding the active region, a plurality of through-vias disposed in the active region and passing through the core layer, a plurality of dummy through-vias disposed in the dummy region and passing through the core layer, an upper structure disposed on an upper surface of the core layer, and a lower structure disposed on a lower surface of the core layer. The upper structure can include a plurality of upper connection pads each of which is in contact with a respective one of the plurality of through-vias and an upper support structure in contact with the plurality of dummy through-vias. The lower structure can include a lower support structure in contact with the plurality of dummy through-vias.

[0006] According to another aspect of the inventive concepts, a substrate is provided that includes a core layer including an active region in which a semiconductor chip is mounted and a dummy region surrounding the active region, a plurality of through-vias disposed in the active region and passing through the core layer, a plurality of dummy through-vias disposed in the dummy region and passing through the core layer, a plurality of upper connection pads disposed in an upper surface of the core layer in the active region, each of the plurality of upper connection pads being electrically connected to a respective one of the plurality of through-vias, a plurality of upper support pads disposed in the upper surface of the core layer in the dummy region, each of the plurality of upper support pads being in contact with a respective one of the plurality of dummy through-vias, and a plurality of lower support pads disposed on a lower surface of the core layer in the dummy region, each of the plurality of lower support pads being in contact with a respective one of the plurality of dummy through-vias. The core layer can include a plurality of dummy through-holes passing through the core layer in the dummy region. Each of the plurality of dummy through-vias can fill a respective one of the plurality of dummy through-holes. The plurality of dummy through-vias can have a first width at a first vertical height, a second width greater than the first width at a second vertical height higher than the first vertical height, and a third width greater than the first width at a third vertical height lower than the first vertical height. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a top view of a substrate according to an example embodiment; Figure 2 is Figure 1 is an enlarged partial view of the substrate shown; Figure 3 is Figure 2a vertical cross-sectional view of the substrate taken along line I-I'; Figure 4 is Figure 1 an enlarged partial view of the substrate shown; Figure 5 is Figure 4 a vertical cross-sectional view of the substrate taken along line II-II'; Figure 6 is Figure 5 a top view of the substrate shown; Figure 7A is a top view of a substrate according to an example embodiment; Figure 7B is Figure 7A a vertical cross-sectional view of the substrate taken along line II-II'; Figure 7C is Figure 7B a top view of the substrate shown; Figures 8 to 10 is a top view of a substrate according to an example embodiment; Figures 11 to 12 is a vertical cross-sectional view of a substrate according to an example embodiment; Figures 13A to 13D is a diagram illustrating a method of manufacturing a semiconductor package according to an example embodiment. DETAILED DESCRIPTION

[0008] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. It should also be noted that the disclosure provides numerous alternative or equivalent examples, but that this list of alternatives is not exhaustive. In addition, any consistency in the details between various examples should not be construed as requiring such details. In determining the requirements of the present invention, the language of the claims should be referenced.

[0009] As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function (e.g., conveying information) in the operation of the circuit. The "dummy" element can exist in the device only as a pattern. In some cases, the "dummy" element can be electrically floating, or can be connected to various voltage sources, but otherwise does not provide the same functionality of the non-dummy element it represents.

[0010] Throughout the specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that, unless the context dictates otherwise, the component can only be formed of that element or group of elements, or that element or group of elements can be combined with additional elements to form the component. On the other hand, the term "consisting of means that the component is formed only of the listed elements.

[0011] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. That is, if a first element is directly connected or coupled to a second element, then there is no intervening element present, that directly connects or couples the first element to the second element.

[0012] As used herein, components described as being "electrically connected" are configured such that an electrical signal can be transferred from one component to another (although such an electrical signal can attenuate in strength as it is transferred and can be selectively transferred). Further, components that are "directly electrically connected" form a common electrical node by electrical connection of one or more conductors such as, for example, a wire, a pad, an internal electrical line, a through via, etc. Thus, components that are directly electrically connected do not include components that are electrically connected by active elements such as transistors or diodes.

[0013] As used herein, terms such as "same," "identical," and the like, when referring to features such as orientation, layout, position, shape, size, composition, amount, or other measure, do not necessarily mean that the features are exactly the same, but are intended to encompass features that are nearly the same, with typical variations that can occur as a result of conventional manufacturing processes. The term "substantially" can be used herein to emphasize this meaning.

[0014] Ordinants such as "first," "second," "third," etc. can simply be used as labels to certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms described in the specification without use of "first," "second," etc. can still be called "first" or "second" in the claims. In addition, terms referenced in a particular claim with a particular ordinal number (e.g., "first") can be described in the specification or another claim with a different ordinal number (e.g., "second"). Items described herein in the singular can be provided in plural, as can be seen, for example, in the drawings. Thus, unless the context indicates otherwise, a description of a single item should be understood to apply to a plurality of items, as well.

[0015] Figure 1 is a top view of a substrate according to an example embodiment. Figure 2 is Figure 1 is a magnified view of a portion of the substrate shown. Figure 2 may correspond to Figure 1 the area "A" shown. Figure 3 is Figure 2 is a vertical cross-sectional view of the substrate shown taken along line I-I'.

[0016] Referring to Figures 1 to 3 , the substrate 100 according to example embodiments of the inventive concept can be a printed circuit board (PCB). The term "substrate" can mean a bulk substrate (e.g., an initial semiconductor substrate such as a bulk semiconductor substrate (e.g., formed of crystalline silicon), a silicon-on-insulator (SOI) substrate, etc. that forms a bulk of a wafer in a final wafer product), or a stack structure including such a bulk substrate and layers formed on the substrate. For example, the substrate 100 can be a PCB for mold underfill (MUF). In example embodiments, the substrate 100 can have a strip structure extending in a horizontal direction (X direction). The core layer 110 of the substrate 100 can include an active area R1, a dummy area R2, and a peripheral area R3.

[0017] The active area R1 can be an area in which semiconductor chips are mounted. A plurality of semiconductor chips can be mounted in the active area R1. After a molding process is performed, the active area R1 can be individualized along a scribe lane SL to manufacture semiconductor packages (e.g., the active area R1 can be cut along the scribe lane to separate the active area R1 into individual semiconductor packages).

[0018] The dummy area R2 can surround the active area R1. Semiconductor chips can not be mounted in the dummy area R2 (e.g., the dummy area R2 can be an area in which semiconductor chips are not mounted). The active area R1 and the dummy area R2 can be sealed with an encapsulant in a molding process. In Figure 1 In a top view, the active area R1 and the dummy area R2 are shown to have a rectangular shape, but the inventive concept is not limited thereto.

[0019] Bonding areas R1a, each of which is a region of a semiconductor in which a plurality of semiconductor chips are mounted, can be disposed in the active area R1. In Figure 1 In the above-described example embodiment, the bonding areas R1a can be indicated by dotted lines in the active area R1. The scribe lanes SL can be indicated by solid lines and can form a solid rectangular shape. The solid rectangular shape can each correspond to a single semiconductor package including semiconductor chips that can be formed after a molding process. The scribe lanes SL can correspond to lines in which cutting is performed in a sawing / picking process so as to individualize the semiconductor chips into each semiconductor package after a molding process for sealing the semiconductor chips with an encapsulant. For example, the active area R1 can be an area that remains as part of a separate semiconductor package after completion of the semiconductor package, and the dummy area R2 can be an area in which no semiconductor package is formed.

[0020] The peripheral region R3 can surround the dummy region R2. In the peripheral region R3, a mark indicating information about a semiconductor chip to be mounted, a guide used in a subsequent process, a mark for PCB alignment, and a guide hole can be provided. The guide hole can be used as an identification mark during a molding process, and can also be used as an alignment device during movement. A unit alignment mark, which can be a reference point of the scribe lane SL, can be provided in the active region R1.

[0021] Figure 2 and Figure 3 is a top view and a vertical cross-sectional view of the substrate 100 in the active region R1.

[0022] Further referring to Figure 2 and Figure 3 , the substrate 100 can include a core layer 110, an upper structure US, and a lower structure LS. In an example embodiment, the substrate 100 can be a substrate for a semiconductor package, such as a PCB, an interposer substrate, a ceramic substrate, a tape interconnect substrate, etc. In an example embodiment, the substrate 100 can be a PCB. For example, the core layer 110 of the substrate 100 can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a photosensitive insulating layer. Specifically, the core layer 110 can include a material such as a prepreg, an anisotropic build-up film (ABF), FR-4, a bismaleimide triazine (BT), and a photoimageable dielectric (PID) resin. The substrate 100 can be formed using, for example, a copper-clad laminate (CCL), a non-copper-clad laminate, a glass substrate, a ceramic substrate, etc.

[0023] In the active region R1, the core layer 110 can include a through-hole H1. The through-hole H1 can pass through the upper surface and the lower surface of the core layer 110 and extend vertically from the upper surface to the lower surface. The substrate 100 can further include a through-via V1 disposed in the through-hole H1.

[0024] In an example embodiment, the through-hole H1 can have an hourglass shape. For example, the horizontal width of the through-hole H1 can decrease and then increase from the upper surface to the lower surface of the core layer 110.

[0025] In an example embodiment, the through-via V1 can completely fill the through-hole H1. For example, the through-via V1 can have an hourglass shape (e.g., the through-via V1 can have a shape complementary to that of the through-hole H1). The horizontal width of the through-via V1 can decrease and then increase along the length from the upper surface to the lower surface of the core layer 110. The upper surface and the lower surface of the through-via V1 can be coplanar with the upper surface and the lower surface of the core layer 110, respectively.

[0026] The through-vias V1 can include an electrically conductive material. The through-vias V1 can include, for example, a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0027] The upper structure US can be disposed on the upper surface of the core layer 110. In the active region R1, the upper structure US can include the upper connection pads 120 and the upper protective layer 130. The upper connection pads 120 can be in contact with the upper surface of the core layer 110 and can be electrically connected to the corresponding through-vias V1. In an example embodiment, at least one of the upper connection pads 120 can have an interconnection structure extending in a horizontal direction from the upper surface of the core layer 110. Figure 2 The shape, arrangement, and number of the illustrated upper connection pads 120 are examples and are not limited thereto.

[0028] The upper connection pads 120 can include an electrically conductive material. The upper connection pads 120 can include, for example, a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In an example embodiment, the upper connection pads 120 can be formed simultaneously with the through-vias V1 and can include the same material as the material of the through-vias V1.

[0029] The upper protective layer 130 can partially cover the upper surface of the core layer 110 and can cover at least one of the upper connection pads 120. As described above, the substrate 100 can be a PCB for an MUF, and an encapsulant such as an EMC can be disposed between a semiconductor chip mounted on the substrate 100 and the substrate 100, or a bottom filler can be omitted. That is, in a molding process, an encapsulant can cover the semiconductor chip and the substrate 100 and can flow into a space between the semiconductor chip and the substrate 100. The upper connection pads 120 in contact with the semiconductor chip can not be covered by the upper protective layer 130 so that the encapsulant can smoothly flow into the space between the semiconductor chip and the substrate 100, and the upper surface and the side surface of the upper connection pads 120 can be completely exposed. For example, as illustrated, the upper protective layer 130 can include a bonding region R1a exposing the upper connection pads 120. Figure 3 The upper protective layer 130 can include a bonding region R1a exposing the upper connection pads 120. The bonding region R1a can be located on a central portion of each semiconductor package after a process of manufacturing a semiconductor package is completed, and the upper protective layer 130 can extend along an edge of each semiconductor package. The upper protective layer 130 can include, for example, a solder resist (SR).

[0030] A lower structure LS can be disposed on a lower surface of the core layer 110. In the active area R1, the lower structure LS can include lower connection pads 140 and a lower protection layer 150. The lower connection pads 140 can be in contact with the lower surface of the core layer 110, and can be electrically connected to the corresponding via V1. In an example embodiment, at least one of the lower connection pads 140 can have an interconnection structure extending in a horizontal direction from the lower surface of the core layer 110.

[0031] The lower connection pads 140 can include a conductive material. The lower connection pads 140 can include, for example, a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. In an example embodiment, the lower connection pads 140 can be formed at the same time as the via V1 and the upper connection pads 120, and can include the same material as the material of the via V1 and the upper connection pads 120 (e.g., the lower connection pads 140 can be formed in the same process as the via V1 and the upper connection pads 120). In an example, the via V1, the upper connection pads 120, and the lower connection pads 140 can include copper (Cu).

[0032] The lower protection layer 150 can partially cover the lower surface of the core layer 110, and can cover at least one of the lower connection pads 140. In an example embodiment, a volume of the lower protection layer 150 can be greater than a volume of the upper protection layer 130. In an example embodiment, an area of the lower protection layer 150 can be greater than an area of the upper protection layer 130 in a top view. For example, the substrate 100 according to an example embodiment of the inventive concept can be a PCB for a MUF, and the upper protection layer 130 can be a relatively small area such that an encapsulant flows into a space between the substrate 100 and a semiconductor chip. For example, an area of the upper protection layer 130 can be in a range of about 20% to about 30% of an area of a semiconductor package after the semiconductor package is manufactured.

[0033] An upper surface of the upper protection layer 130, the core layer 110, and the upper connection pads 120 exposed by the upper protection layer 130 can form a front surface FS of the substrate 100. A lower surface of the lower protection layer 150, the core layer 110, and the lower connection pads 140 exposed by the lower protection layer 150 can form a back surface BS of the substrate 100.

[0034] Figure 3 The illustrated upper structure US and lower structure LS are examples, and are not limited thereto. In an example embodiment, the upper connection pads 120 can be formed of a plurality of layers, and the lower connection pads 140 can be formed of a plurality of layers.

[0035] Figure 4 is Figure 1An enlarged view of a portion of the substrate shown. Figure 4 may correspond to Figure 1 the region "B" shown, and shows the front surface of the substrate. Figure 5 is Figure 4 a vertical cross-sectional view of the substrate shown taken along the line II-II'.

[0036] With reference to Figure 4 and Figure 5 , the upper structure US can be disposed on the core layer 110 in the dummy region R2, and the lower structure LS can be disposed below the core layer 110.

[0037] In the dummy region R2, the core layer 110 can include a dummy via hole H2. The dummy via hole H2 can pass through the upper surface and the lower surface of the core layer 110 and extend vertically between the upper surface and the lower surface. The substrate 100 can further include a dummy via V2 disposed in the dummy via hole H2.

[0038] In an example embodiment, the dummy via hole H2 can have a shape that is the same as or similar to that of the via hole H1, and can have an hourglass shape. For example, the horizontal width of the dummy via hole H2 can decrease and then increase from the upper surface to the lower surface of the core layer 110. The dummy via hole H2 can have a first width W1, i.e., a minimum value, at a first vertical height between the upper surface and the lower surface of the core layer 110. The dummy via hole H2 can have a second width W2 greater than the first width W1 at a second vertical height higher than the first vertical height, and can have a third width W3 greater than the first width W1 at a third vertical height lower than the first vertical height.

[0039] In an example embodiment, the dummy via V2 can have a structure that is the same as or similar to that of the via V1, and can completely fill the dummy via hole H2 (e.g., the shape of the dummy via V2 can be complementary to that of the dummy via hole H2). For example, the dummy via V2 can have an hourglass shape. The dummy via V2 can have a first width W1, i.e., a minimum value, at a first vertical height between the upper surface and the lower surface of the core layer 110. The dummy via V2 can have a second width W2 greater than the first width W1 at a second vertical height higher than the first vertical height, and can have a third width W3 greater than the first width W1 at a third vertical height lower than the first vertical height. The upper surface and the lower surface of the dummy via V2 can be coplanar with the upper surface and the lower surface of the core layer 110, respectively.

[0040] The dummy via V2 can include an electrically conductive material. The dummy via V2 can include, for example, a metallic material including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0041] In the present specification, the active region R1 and the dummy region R2 can be referred to as a first region and a second region, respectively. The via V1 and the dummy via V2 can be referred to as a first via and a second via, respectively. The hole H1 and the dummy hole H2 can also be referred to as a first hole and a second hole, respectively.

[0042] In the dummy region R2, the upper structure US can include an upper support structure. In an example embodiment, the upper support structure can include upper support pads 122 and upper support patterns 124. The upper support pads 122 can be in contact with the upper surface of the core layer 110, and at least one of the upper support pads 122 can be in contact with and connected to a corresponding dummy via V2. In an example embodiment, the upper support patterns 124 can be disposed between the upper support pads 122, and can connect adjacent upper support pads 122 to each other. At least one of the upper support patterns 124 can have an interconnection structure extending in a horizontal direction from the upper surface of the core layer 110.

[0043] In an example embodiment, the upper support pads 122 can be disposed in a grid pattern, and the upper support patterns 124 can extend between the upper support pads 122. Figure 4 The shapes, arrangement structures, and numbers of the illustrated upper support pads 122 and upper support patterns 124 are examples, and are not limited thereto. In an example embodiment, the upper support pads 122 can have a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape. For ease of description, the upper support pads 122 and the upper support patterns 124 are illustrated in Figure 4 However, as Figure 5 The upper support pads 122 and the upper support patterns 124 can be completely covered by the upper protection layer 130, as illustrated.

[0044] The upper support pad 122 and the upper support pattern 124 may comprise, for example, a metallic material, including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. In an example embodiment, the upper support pad 122 and the upper support pattern 124 may be formed simultaneously with the dummy through-path V2, and may comprise the same material as the dummy through-path V2 (e.g., the upper support pad 122 and the upper support pattern 124 may be formed in the same process as the dummy through-path V2). In an example embodiment, the upper support pad 122 and the upper support pattern 124 may have a thickness substantially equal to the thickness of the upper connecting pad 120.

[0045] In the dummy region R2, the upper protective layer 130 can completely cover the upper surface of the core layer 110 and the upper support pad 122. In the dummy region R2, the upper surface of the core layer 110 and the upper support pad 122 can be left unexposed.

[0046] Figure 6 yes Figure 5 Top view of the substrate shown. Figure 6 Show Figure 5 The back surface BS of the substrate shown.

[0047] Further reference Figure 6 In the dummy region R2, the lower structure LS may further include a lower support pad 142. At least one of the lower support pads 142 may contact and connect to a corresponding dummy through-path V2. In an example embodiment, the lower support pad 142 may be arranged in a grid pattern. In an example embodiment, the lower support pad 142 may have a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape. For ease of description, in Figure 6 The lower support pad 142 is shown. However, as... Figure 5 As shown, the lower support pad 142 can be completely covered by the lower protective layer 150.

[0048] The lower support pad 122 may comprise, for example, a metallic material, including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. In an example embodiment, the lower support pad 142 may be formed simultaneously with the dummy through-path V2 and may comprise the same material as the dummy through-path V2 (e.g., the lower support pad 142 may be formed in the same process as the dummy through-path V2). In an example embodiment, the lower support pad 142 may have a thickness substantially equal to the thickness of the lower connecting pad 140. The lower support pad 142 may be referred to as a lower support structure.

[0049] As described above, in the PCB for the MUF, the area of the upper protective layer 130 (or the volume of the upper protective layer 130) can be formed to be relatively smaller than the area of the lower protective layer 150 (or the volume of the lower protective layer 150), and thus the coefficient of thermal expansion (CTE) of the upper structure US and the coefficient of thermal expansion of the lower structure LS can be different from each other. Accordingly, when the different coefficients of thermal expansion are not compensated for, the substrate 100 can be bent due to the upper structure US and the lower structure LS having different coefficients of thermal expansion.

[0050] However, as Figures 4 to 6 indicated, the core layer 110 of the substrate 100 according to an example embodiment of the inventive concept can include a dummy via V2 in the dummy area R2, and can include an upper support pad 122 and a lower support pad 142 connected to the dummy via V2. The dummy via V2 can be connected to both the upper support pad 122 of the upper structure US and the lower support pad 142 of the lower structure LS, such that even when the coefficient of thermal expansion of the upper structure US and the coefficient of thermal expansion of the lower structure LS are different, bending of the substrate 100 can be prevented or reduced.

[0051] In addition, according to an example embodiment of the inventive concept, in the dummy area R2, the pattern density of the upper structure US can be greater than the pattern density of the lower structure US. Here, the pattern density of the upper structure US can refer to the ratio of the area of the upper support pad 122 and the upper support pattern 124 to the total area (e.g., the area of the core layer 110 or the upper protective layer 130) in a plan view (see Figure 4 ). The pattern density of the lower structure US can refer to the ratio of the area of the lower support pad 142 to the total area (e.g., the area of the core layer 110 or the lower protective layer 150) in a plan view (see Figure 6 ). That is, the upper support pad 122 and the upper support pattern 124 can be more densely disposed than the lower support pad 142.

[0052] In an example embodiment, the pattern density of the upper structure US in the dummy area R2 can be greater than the pattern density of the upper structure US in the active area R1. The pattern density of the upper structure US in the active area R1 can refer to the ratio of the area of the upper connection pad 120 to the total area (e.g., the area of the core layer 110) in a plan view (see Figure 2 ).

[0053] In example embodiments, the upper support pads 122 can be larger than the upper connection pads 120. For example, the horizontal width Wb of the upper support pads 122 can be larger than the horizontal width Wa of the upper connection pads 120. In example embodiments, the upper support pads 122 can be larger than the lower support pads 142. For example, the horizontal width Wb of the upper support pads 122 can be larger than the horizontal width Wc of the lower support pads 142. In example embodiments, the horizontal width Wc of the lower support pads 142 can be smaller than the horizontal width Wa of the upper connection pads 120. The horizontal width Wb of the upper support pads 122 and the horizontal width Wc of the lower support pads 142 can be larger than the horizontal width of the dummy via V2. The horizontal width of the upper support pattern 124 can be smaller than the horizontal width Wb of the upper support pads 122. The distance Wd between the upper support pads 122 can be smaller than the distance We between the lower support pads 142.

[0054] In example embodiments, the horizontal width Wb of the upper support pads 122 can be in a range from about 150 μm to about 400 μm. The horizontal width Wc of the lower support pads 142 can be in a range from about 100 μm to about 150 μm. The distance Wd between the upper support pads 122 can be in a range from about 100 μm to about 350 μm. The distance We between the lower support pads 142 can be in a range from about 350 μm to about 400 μm.

[0055] As described above, the pattern density of the upper structure US in the dummy region R2 can be formed to be larger than the pattern density of the upper structure US in the active region Rl, and the pattern density of the upper structure US in the dummy region R2 can be formed to be larger than the pattern density of the lower structure LS in the dummy region R2, thereby reducing the difference between the coefficient of thermal expansion of the upper structure US and the coefficient of thermal expansion of the lower structure LS of the entire substrate 100, and preventing or reducing the warpage of the substrate 100.

[0056] As described above, the area of the upper protective layer 130 can be formed to be relatively smaller than the area of the lower protective layer 150, and the coefficient of thermal expansion of the upper structure US can be different from the coefficient of thermal expansion of the lower structure LS. However, according to example embodiments of the inventive concept, the upper support pads 122 can be connected to each other by the upper support pattern 124, thereby preventing or reducing the warpage of the upper structure US.

[0057] Figure 7A is a top view of a substrate according to an example embodiment. Figure 7B is Figure 7A is a vertical sectional view of the substrate shown in FIG. 2A, taken along line II-II'. Figure 7C is Figure 7B is a top view of a substrate according to an example embodiment. Figure 7A shows Figure 7BThe front surface FS of the substrate is shown, and Figure 7C The front surface FS of the substrate is shown, and Figure 7B The back surface BS of the substrate is shown.

[0058] Referring to Figures 7A to 7C The dummy through-vias V2 can be omitted between the upper support pads 122 and the lower support pads 142 in the dummy area R2 in an example embodiment. For example, at least one of the upper support pads 122 or at least one of the lower support pads 142 can not be in contact with the dummy through-vias V2. For example, the upper support pads 122 and the lower support pads 142 can include first upper support pads 122 and second upper support pads 122', and first lower support pads 142 and second lower support pads 142', respectively. The first upper support pads 122 and the first lower support pads 142 can be connected to each other by the dummy through-vias V2, while the second upper support pads 122' can not be connected to the second lower support pads 142'. The core layer 110 can be inserted between the second upper support pads 122' and the second lower support pads 142'. Figure 7A The arrangement of the dummy through-vias V2 shown is an example, and is not limited thereto.

[0059] Figures 8 to 10 is a top view of a substrate according to an example embodiment.

[0060] Referring to Figure 8 The substrate 100b can include the upper support pads 122 and the upper support patterns 124a and 124b disposed in the dummy area R2. In an example embodiment, a plurality of upper support patterns 124a and 124b can be connected to each upper support pad 122. For example, the upper support pads 122 adjacent to each other can be connected by the first upper support patterns 124a and the second upper support patterns 124b.

[0061] Figure 9 is a front surface of a substrate according to an example embodiment.

[0062] Referring to Figure 9 The upper structure US of the substrate 100c can include an upper support structure 124c. The upper support structure 124c can be an example in which the arrangement is modified such that Figure 4 The upper support pads 122 and the upper support patterns 124 shown have an example embodiment in which the widths are equal. The upper support structure 124c can have a lattice shape, and can extend in the horizontal direction.

[0063] In an example embodiment, the back surface BS of the substrate 100c can also have a structure similar or identical to that of the front surface FS. For example, the lower support pads 142 of the lower structure LS can have a lattice shape, and can extend in the horizontal direction.

[0064] Figure 10 A front surface of a substrate according to an example embodiment is shown.

[0065] Referring to Figure 10 The lower structure LS of the substrate 100d can include a lower support structure. The lower support structure can include lower support pads 142 and lower support patterns 144. For example, the lower support patterns 144 can extend in a horizontal direction between the lower support pads 142 and can connect adjacent lower support pads 142 to each other. A horizontal width of the lower support patterns 144 can be less than or equal to a horizontal width of the lower support pads 142. The horizontal width of the lower support patterns 144 can be less than or equal to a horizontal width of the upper support patterns 124.

[0066] Figure 11 , Figure 12 and Figures 13A to 13D A vertical cross-sectional view of a substrate according to an example embodiment is shown.

[0067] Referring to Figure 11 The lower structure LS of the substrate 100e can include a lower protection layer 150 covering a lower surface of the core layer 110. In an example embodiment, the lower protection layer 150 can have an opening OP in the dummy area R2. For example, the opening OP can expose the lower surface of the core layer 110 and / or the lower support pads 142.

[0068] In a structure of a PCB for a MUF, when the opening OP is formed in a lower surface of the lower protection layer 150 in the dummy area R2 to compensate for the area of the upper protection layer 130 in the active area R1 being formed relatively smaller than the area of the lower protection layer 150 in the active area R1, a difference between a coefficient of thermal expansion of the upper structure US and a coefficient of thermal expansion of the lower structure LS can be reduced, and a bending of the substrate 100e can be prevented or reduced.

[0069] Figure 12 and Figures 13A to 13D A vertical cross-sectional view of a substrate in a dummy area R2 according to an example embodiment is shown.

[0070] Referring to Figure 12The substrate 100f can include an upper structure US and a lower structure LS disposed on the upper and lower surfaces of the core layer 110. In example embodiments, the upper structure US and the lower structure LS can be formed of a plurality of layers. For example, in the dummy region R2, the upper structure US can include a first upper support pad 122f1, a second upper support pad 122f2, a connection via 123, an upper protective layer 130f, and an insulating layer 132f. The first upper support pad 122f1 can be in contact with the dummy through via V2, and the second upper support pad 122f2 can be disposed on the first upper support pad 122f1. The connection via 123 can connect the first upper support pad 122f1 and the second upper support pad 122f2 to each other.

[0071] In example embodiments, the first upper support pad 122f1 and / or the second upper support pad 122f2 can have the same arrangement and / or structure as that shown in FIGS. 1A and 1B. Figure 4 or Figure 9 The first upper support pad 122f1, the second upper support pad 122f2, and the connection via 123 can include the same material as that of the dummy through via V2.

[0072] The insulating layer 132f can cover the upper surface of the core layer 110, and can cover the first upper support pad 122f1 and the connection via 123. The upper protective layer 130f can be disposed on the insulating layer 132f, and can cover the second upper support pad 122f2.

[0073] The insulating layer 132f can include an insulating resin and an inorganic filler. For example, the insulating layer 132f can include ABF, but the inventive concept is not limited thereto, and the insulating layer 132f can include a photosensitive insulating material (PID) or an insulating polymer, such as a photosensitive polyimide (PSPI). The upper protective layer 130f can include a solder resist.

[0074] Figure 12 The structure of the upper structure US shown is an example, and is not limited thereto. For example, the upper structure US can include a plurality of insulating layers 132f located between the core layer 110 and the upper protective layer 130f, and each insulating layer 132f can cover an upper support pad.

[0075] In example embodiments, the lower structure LS can include a lower protective layer 150f and an insulating layer 152f in the dummy region R2. The insulating layer 152f can cover the lower surface of the core layer 110, and can cover a lower support pad 142. The lower protective layer 150f can be disposed below the insulating layer 152f. The lower protective layer 150f and the insulating layer 152f can include the same materials as those of the upper protective layer 130f and the insulating layer 132f, respectively.

[0076] AsFigure 12 As shown, the upper structure US can include first and second upper support pads 122f1 and 122f2, forming multiple layers, while the lower structure LS can include a single layer of lower support pads 142, compensating for the area of the upper passivation layer 130 in the active area R1 being formed relatively smaller than the area of the lower passivation layer 150 in the active area R1, reducing the difference between the coefficient of thermal expansion of the upper structure US and the coefficient of thermal expansion of the lower structure LS, and preventing or reducing the warpage of the substrate 100f. In example embodiments, the lower support pads 142 of the lower structure LS can form multiple layers. For example, the number of lower support pads 142 can be equal to or less than the number of upper support pads of the upper structure US. In an example, the number of layers of lower support pads 142 can be equal to or less than the number of layers of upper support pads of the upper structure US.

[0077] Figures 13A to 13D FIG. 1 is a diagram illustrating a method of manufacturing a semiconductor package according to an example embodiment. Figures 13A to 13D An active area of a substrate is illustrated.

[0078] Referring to Figure 13A A semiconductor chip 160 can be mounted on the substrate 100. The semiconductor chip 160 can be electrically connected to the substrate 100 through a bump structure 162. For example, the semiconductor chip 160 can include chip pads 161 connected to the bump structure 162. The chip pads 161 can be disposed on a lower surface of the semiconductor chip 160 and can be in contact with corresponding bump structures 162. For example, the bump structure 162 can have a solder ball, a conductive bump, or a flip chip connection structure having a grid array such as a pin grid array, a ball grid array, or a land grid array.

[0079] The bump structure 162 can include a first portion 162a in contact with the chip pads 161 and a second portion 162b connecting the first portion 162a and the upper connection pads 120 to each other. For example, the first portion 162a can be a metal pillar portion, and the second portion 162b can be a solder portion including a low melting point metal, but the inventive concept is not limited thereto. In some example embodiments, the bump structure 162 can include only the second portion 162b. The low melting point metal can include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy thereof (e.g., Sn-Ag-Cu).

[0080] The semiconductor chip 160 can be a logic chip or a memory chip. The logic chip can include a microprocessor, an analog device, or a digital signal processor. The memory chip can include a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0081] Referring to Figure 13B and Figure 13C , the mold molding can include a lower mold 10 and an upper mold 20. A port 50 for supplying a molding material M can be provided in a central portion of the lower mold 10. A molding space MS can be defined between the lower mold 10 and the upper mold 20. The molding space MS can be provided on opposite sides of the port 50 and can extend in a horizontal direction.

[0082] The molding material M can be supplied to the molding space MS through the gate G by vertical reciprocating motion of a plunger 30 provided in the port 50. The molding process can be simultaneously performed in the molding spaces MS provided on opposite sides of the port 50.

[0083] The substrate 100 on which the semiconductor chip 160 is mounted can be provided in the molding space MS. The molding material M supplied through the gate G can cover the substrate 100 and the semiconductor chip 160. The molding material M can be cured to form Figure 13C the encapsulant 170 as shown.

[0084] The encapsulant 170 can cover the substrate 100 and the semiconductor chip 160. The encapsulant 170 can be a resin including an epoxy resin, a polyimide, or the like. For example, the resin can include a bisphenol-based epoxy resin, a polycyclic aromatic epoxy resin, an o-cresol novolac epoxy resin, a biphenyl epoxy resin, or a naphthyl epoxy resin.

[0085] Referring to Figure 13D , external connection terminals 180 can be formed under the substrate 100, and the semiconductor package 1 can be manufactured by performing a sawing process. The external connection terminals 180 can be in contact with the lower connection pads 140. A ground voltage Vss or a power supply voltage Vdd can be applied to the lower connection pads 140. The external connection terminals 180 can be electrically connected to an external device such as a main board or the like. The external connection terminals 180 can include a conductive material and can be in the form of a ball, a pin, or a lead. For example, the external connection terminals 180 can be solder balls.

[0086] The semiconductor package 1 can further include a passive device 190 and a connection terminal 192 disposed under the substrate 100. The passive device 190 can be electrically connected to a corresponding one of the lower connection pads 140 through the connection terminal 192. The passive device 190 can include, for example, a capacitor such as a multilayer ceramic capacitor (MLCC) or a low inductance chip capacitor (LICC), an inductor, a magnetic bead, etc. In an example embodiment, the passive device 190 can be a landing side capacitor (LSC). However, the inventive concept is not limited thereto. In some example embodiments, the passive device 190 can be a die side capacitor (DSC) mounted on the upper surface of the substrate 100 or an embedded capacitor embedded in the substrate 100.

[0087] The sawing process can be performed by cutting the substrate 100 along the scribe lane SL shown, and each active region R1 can be individualized to form the semiconductor package 1. Figure 1

[0088] According to example embodiments of the inventive concept, a dummy through via and upper and lower support pads connected thereto can be provided in a dummy region, thereby reducing a difference in a coefficient of thermal expansion between an upper structure and a lower structure of the substrate and preventing warping of the substrate.

[0089] While example embodiments have been illustrated and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.​

Claims

1. A substrate comprising: a core layer including an active area in which a semiconductor chip is mounted and a dummy area surrounding the active area; a plurality of through-vias provided in the active area and passing through the core layer; a plurality of dummy through-vias provided in the dummy area and passing through the core layer; a plurality of upper connection pads provided on an upper surface of the core layer in the active area, each of the plurality of upper connection pads being electrically connected to a respective one of the plurality of through-vias; a plurality of upper support pads provided on the upper surface of the core layer in the dummy area, each of the plurality of upper support pads being in contact with a respective one of the plurality of dummy through-vias; and a plurality of lower support pads provided on a lower surface of the core layer in the dummy area, each of the plurality of lower support pads being in contact with a respective one of the plurality of dummy through-vias.

2. The substrate of claim 1, further comprising: a plurality of upper support patterns in the dummy area, each of the plurality of upper support patterns connecting adjacent ones of the plurality of upper support pads to each other. a size of each of the plurality of upper support pads is greater than a size of each of the plurality of lower support pads.

3. The substrate of claim 1, wherein, a size of each of the plurality of lower support pads is smaller than a size of each of the plurality of upper connection pads.

4. The substrate of claim 1, wherein, a distance between adjacent ones of the plurality of upper support pads is smaller than a distance between adjacent ones of the plurality of lower support pads.

5. The substrate of claim 1, wherein, 6. The substrate of claim 1, further comprising: an upper protective layer provided on the upper surface of the core layer, wherein the upper protective layer partially covers the active area and completely covers the dummy area, and at least one of the plurality of upper connection pads is exposed by the upper protective layer.

7. The substrate of claim 1, further comprising: a lower protective layer provided on the lower surface of the core layer, wherein the lower protective layer partially covers the active area and completely covers the dummy area.

8. The substrate of claim 7, further comprising: a plurality of lower connection pads provided on the lower surface of the core layer in the active area, each of the plurality of lower connection pads being electrically connected to a respective one of the plurality of through-vias, and at least one of the plurality of lower connection pads is exposed by an opening in the lower protective layer. a pattern density of the plurality of upper support pads is greater than a pattern density of the plurality of lower support pads.

9. The substrate of claim 1, wherein, ​ 10. The substrate of claim 1, wherein, A pattern density of the plurality of upper connection pads is smaller than a pattern density of the plurality of upper support pads and larger than a pattern density of the plurality of lower support pads.

11. The substrate of claim 1, wherein, At least one of the plurality of upper support pads is not in contact with any of the plurality of dummy through-vias.

12. The substrate of claim 1, further comprising: a plurality of lower support patterns in the dummy area, each of the plurality of lower support patterns connecting adjacent ones of the plurality of lower support pads to each other.

13. The substrate of claim 1, wherein a horizontal width of each of the plurality of upper support pads is in a range of 150 μm to 400 μm, and a horizontal width of each of the plurality of lower support pads is in a range of 100 μm to 150 μm.

14. The substrate of claim 1, wherein a distance between adjacent ones of the plurality of upper support pads is in a range of 100 μm to 350 μm, and a distance between adjacent ones of the plurality of lower support pads is in a range of 350 μm to 400 μm.

15. The substrate of claim 1, further comprising: a lower protection layer disposed on the lower surface of the core layer, wherein the lower protection layer exposes at least one of the plurality of lower support pads.

16. The substrate of claim 1, wherein at least one of the plurality of upper support pads includes a first upper support pad in contact with a corresponding one of the plurality of dummy through-vias and a second upper support pad on the first upper support pad, and the substrate further comprises a connection via connecting the first upper support pad and the second upper support pad to each other.

17. A substrate, comprising: a core layer including an active area in which a semiconductor chip is mounted and a dummy area surrounding the active area; a plurality of through-vias disposed in the active area and passing through the core layer; a plurality of dummy through-vias disposed in the dummy area and passing through the core layer; an upper structure disposed on an upper surface of the core layer; and a lower structure disposed on a lower surface of the core layer, wherein the upper structure includes a plurality of upper connection pads each in contact with a corresponding one of the plurality of through-vias and an upper support structure in contact with the dummy through-vias, and the lower structure includes a lower support structure in contact with the plurality of dummy through-vias.

18. The substrate of claim 17, wherein, the upper support structure includes a plurality of upper support pads each in contact with a corresponding one of the plurality of dummy through-vias and a plurality of upper support patterns connecting the plurality of upper support pads to each other.

19. The substrate of claim 17, wherein, the upper support structure has a lattice shape.

20. A substrate comprising: a core layer including an active area in which a semiconductor chip is mounted and a dummy area surrounding the active area; a plurality of through-vias disposed in the active area and passing through the core layer; a plurality of dummy through-vias disposed in the dummy area and passing through the core layer; a plurality of upper connection pads disposed on an upper surface of the core layer in the active area, each of the plurality of upper connection pads being electrically connected to a respective one of the plurality of through-vias; a plurality of upper support pads disposed on the upper surface of the core layer in the dummy area, each of the plurality of upper support pads being in contact with a respective one of the plurality of dummy through-vias; and a plurality of lower support pads disposed on a lower surface of the core layer in the dummy area, each of the plurality of lower support pads being in contact with a respective one of the plurality of dummy through-vias, wherein the core layer includes a plurality of dummy through-holes passing through the core layer in the dummy area, each of the plurality of dummy through-vias fills a respective one of the plurality of dummy through-holes, and the plurality of dummy through-vias has a first width at a first vertical height, a second width greater than the first width at a second vertical height higher than the first vertical height, and a third width greater than the first width at a third vertical height lower than the first vertical height. ​

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