Packaging method and packaging structure of multi-layer stacked memory
By using a multi-layer stacked memory packaging method, the electrical connection and stacking bonding between silicon interposer chips and memory chips are utilized to solve the yield and cost problems caused by through-silicon via (TSV) technology in DRAM wafer manufacturing, and to achieve a packaging structure with high connection density and small package size.
Patent Information
- Application Number
- CN202511695340.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-13
AI Technical Summary
In the DRAM wafer manufacturing process, if through-silicon via (TSV) technology is not used, the yield is low; if TSV technology is used, the process is complex, which further reduces the yield and increases the cost.
The multi-layer stacked memory packaging method uses silicon interposer chips and memory chips to be laid flat, and electrical connection is achieved by forming a molding layer and a wiring layer. After being cut into independent modules, they are stacked and bonded in sequence, and finally wrapped with a second molding layer.
Simplify the manufacturing process, avoid losses caused by through-silicon via (TSV) yield issues, reduce DRAM wafer costs, increase interconnect density, and reduce package size.
Smart Images
Figure CN121532035A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked memory packaging method and packaging structure. BACKGROUND
[0002] In the DRAM wafer manufacturing process, if the through silicon via process is not used, the DRAM wafer manufacturing yield is low; if the through silicon via process is used, due to the complexity of the through silicon via process, the DRAM wafer yield is further reduced, resulting in an increase in wafer cost.
[0003] In view of the above problems, it is necessary to provide a multi-layer stacked memory packaging method and packaging structure which are reasonable in design and effective in solving the above problems. SUMMARY
[0004] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a multi-layer stacked memory packaging method and packaging structure.
[0005] An aspect of the embodiment of the present disclosure provides a multi-layer stacked memory packaging method, which comprises: providing a plurality of silicon adapter chips and a plurality of memory chips, wherein the silicon adapter chips are provided with a plurality of through silicon vias penetrating the thickness thereof; tiledly arranging the plurality of silicon adapter chips and the plurality of memory chips; forming a first plastic encapsulation layer wrapping the silicon adapter chips and the memory chips; forming a first wiring layer electrically connected to the silicon adapter chips and the memory chips respectively on a first surface of the first plastic encapsulation layer; forming a second wiring layer electrically connected to the silicon adapter chips on a second surface of the first plastic encapsulation layer; forming a plurality of independent memory chip modules by cutting, and sequentially stacking and bonding the plurality of memory chip modules; forming a second plastic encapsulation layer wrapping the plurality of memory chip modules.
[0006] Optionally, the tiledly arranging the plurality of silicon adapter chips and the plurality of memory chips comprises: providing a first temporary carrier, and tiledly fixing a first surface of the plurality of silicon adapter chips and a front surface of the plurality of memory chips to the first temporary carrier; After the first plastic encapsulation layer is formed, the method further comprises: removing the first temporary carrier.
[0007] Optionally, the forming the first wiring layer electrically connected to the silicon adapter chips and the memory chips respectively on the first surface of the first plastic encapsulation layer comprises: The first surface of the first plastic sealing layer, the first surface of the silicon adapter chip and the front surface of the memory chip form the first wiring layer; A second wiring layer electrically connected with the silicon adapter chip is formed on the second surface of the first plastic sealing layer, comprising: The second surface of the first plastic sealing layer is thinned to expose the through silicon via of the second surface of the silicon adapter chip; The second wiring layer is formed on the second surface of the first plastic sealing layer and the second surface of the silicon adapter chip.
[0008] Optionally, a plurality of the silicon adapter chips and a plurality of the memory chip modules are arranged in a tiled manner, further comprising: A second temporary carrier is provided, and the first surfaces of the plurality of silicon adapter chips and the back surfaces of the memory chip modules are fixed to the second temporary carrier, wherein the front surfaces of the memory chip modules are provided with conductive bumps; After the first plastic sealing layer is formed, the method further comprises: thinning the first surface of the first plastic sealing layer to expose the conductive bumps on the first surfaces of the silicon adapter chips and the front surfaces of the memory chip modules.
[0009] Optionally, a first wiring layer electrically connected with the silicon adapter chip and the memory chip respectively is formed on the first surface of the first plastic sealing layer, further comprising: The first wiring layer is formed on the first surface of the thinned first plastic sealing layer, the second surface of the silicon adapter chip and the front surface of the memory chip; A second wiring layer electrically connected with the silicon adapter chip is formed on the second surface of the first plastic sealing layer, further comprising: The second temporary carrier is removed; The second wiring layer is formed on the second surface of the first plastic sealing layer and the first surface of the silicon adapter chip.
[0010] Optionally, in the two adjacent memory chip modules, the memory chips in the upper memory chip module correspond one-to-one to the memory chips in the lower memory chip module; The silicon adapter chips in the upper memory chip module are distributed one-to-one corresponding to the silicon adapter chips in the lower memory chip module.
[0011] Optionally, a plurality of the memory chip modules are sequentially stacked and bonded, comprising: In the two adjacent memory chip modules, the front surfaces of the memory chips in the upper memory chip module are bonded to the back surfaces of the memory chips in the lower memory chip module; or, The front surface of the memory chip in the upper memory chip module is bonded to the front surface of the memory chip in the lower memory chip module in the two adjacent memory chip modules.
[0012] Optionally, the memory chips in the upper memory chip module and the memory chips in the lower memory chip module are staggered in the two adjacent memory chip modules. The silicon conversion chips in the upper memory chip module and the silicon conversion chips in the lower memory chip module are staggered.
[0013] Optionally, the plurality of memory chip modules are sequentially stacked and bonded, comprising: The front surface of the memory chip in the upper memory chip module is bonded to the back surface of the memory chip in the lower memory chip module in the two adjacent memory chip modules; or, The front surface of the memory chip in the upper memory chip module is bonded to the front surface of the memory chip in the lower memory chip module in the two adjacent memory chip modules.
[0014] Another aspect of the embodiments of the present disclosure provides a multi-layer stacked memory package structure, which is packaged by using the multi-layer stacked memory packaging method described above.
[0015] The multi-layer stacked memory packaging method and structure of the embodiments of the present disclosure, in the packaging method, the independent silicon conversion chip is provided to realize the connection of the upper and lower memory chip modules, the manufacturing process is simple, and meanwhile, since the silicon conversion chip provided with the through silicon via is integrated with the DRAM wafer after completing the circuit test, the yield problem of the through silicon via will not cause the loss of the chip, thereby reducing the cost of the DRAM wafer; the connection density of the silicon conversion chip is higher, and the corresponding packaging size can be made smaller under the same connection requirement. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 A flowchart of a multi-layer stacked memory packaging method in an embodiment of the embodiments of the present disclosure; Figures 2 to 21 A process flowchart of a multi-layer stacked memory packaging method in another embodiment of the embodiments of the present disclosure. DETAILED DESCRIPTION
[0017] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.
[0018] As Figure 1As shown, one aspect of the embodiments of the present disclosure provides a multi-layer stacked memory packaging method S100, which can specifically include: S110, providing a plurality of silicon adapter chips and a plurality of memory chips, wherein the silicon adapter chips are provided with a plurality of through-silicon vias.
[0019] S120, arranging the plurality of silicon adapter chips and the plurality of memory chips in a flat manner.
[0020] S130, forming a first plastic encapsulation layer wrapping the silicon adapter chips and the memory chips.
[0021] S140, forming a first wiring layer respectively electrically connected to the silicon adapter chips and the memory chips on a first surface of the first plastic encapsulation layer.
[0022] S150, forming a second wiring layer electrically connected to the silicon adapter chips on a second surface of the first plastic encapsulation layer.
[0023] S160, forming a plurality of independent memory chip modules by cutting, and sequentially stacking and bonding the plurality of memory chip modules.
[0024] S170, forming a second plastic encapsulation layer wrapping the plurality of memory chip modules.
[0025] In an embodiment, step S110 can specifically include: As shown, a plurality of silicon adapter chips 110 and a plurality of memory chips 120 are provided, wherein the silicon adapter chips 110 are provided with a plurality of through-silicon vias 130. Figure 2 In step S120, the plurality of silicon adapter chips and the plurality of memory chips are arranged in a flat manner, which can specifically include:
[0026] As shown, a first temporary carrier 141 is provided, and a first surface of the plurality of silicon adapter chips 110 and a front surface of the plurality of memory chips 120 are fixed to the first temporary carrier 141 in a flat manner. Figure 2 In step S130, the first plastic encapsulation layer wrapping the silicon adapter chips and the memory chips is formed, which can specifically include: as shown, a first plastic encapsulation layer 150 wrapping the silicon adapter chips and the memory chips is formed on a surface of the first temporary carrier 141.
[0027] As shown, after the first plastic encapsulation layer 150 is formed, the method further includes: removing the first temporary carrier 141. Figure 3
[0028] As shown, after the first plastic encapsulation layer 150 is formed, the method further includes: removing the first temporary carrier 141. Figure 4 As shown, after the first plastic encapsulation layer 150 is formed, the method further includes: removing the first temporary carrier 141.
[0029] In step S140, a first wiring layer 160 is formed on the first surface of the first encapsulation layer 150 and electrically connected to the silicon conversion chip 110 and the memory chip 120 respectively. Specifically, the step S140 can include the following steps: As shown in Figure 5 After the first temporary carrier 141 is removed, the first wiring layer 160 is formed on the first surface of the first encapsulation layer 150, the first surface of the silicon conversion chip 110 and the front surface of the memory chip 120.
[0030] As shown in Figure 5 The specific process of forming the first wiring layer 160 can be as follows: A first dielectric layer 161 is formed on the first surface of the first encapsulation layer 150, the first surface of the silicon conversion chip 110 and the front surface of the memory chip 120. The first dielectric layer 161 can be a PI layer.
[0031] The first dielectric layer 161 is patterned by using photolithography and etching processes, so as to form a plurality of first openings on the first dielectric layer 161.
[0032] A first metal layer 162 is formed in the first openings by using electroplating process, and the first metal layer 162 is electrically connected to the front surface of the memory chip 120 and the silicon through hole 130 of the silicon conversion chip 110 respectively.
[0033] A dielectric layer 163 is formed on the first metal layer 162, and the dielectric layer 163 is patterned by using photolithography and etching processes, so as to form a plurality of openings on the dielectric layer 163.
[0034] A plurality of solder balls 164 are formed in the openings and electrically connected to the first metal layer 162.
[0035] In step S150, a second wiring layer 170 is formed on the second surface of the first encapsulation layer 150 and electrically connected to the silicon conversion chip 110. Specifically, the step S150 can include the following steps: As shown in Figure 6 The first wiring layer 160 is fixed to the temporary carrier 143 by the protective adhesive layer 142.
[0036] As shown in Figure 7 The second surface of the first encapsulation layer 150 is thinned by using grinding process, so as to expose the silicon through hole 130 of the second surface of the silicon conversion chip 110. In this embodiment, the back surface of the memory chip 120 is not exposed.
[0037] As shown in Figure 7 The second wiring layer 170 is formed on the second surface of the first encapsulation layer 150 and the second surface of the silicon conversion chip 110.
[0038] As shown in Figure 7 The specific process of forming the second wiring layer 170 can be as follows: A second dielectric layer 171 is formed on the second surface of the first encapsulation layer 150 and the second surface of the silicon adapter chip 110; the second dielectric layer 171 can be formed by a coating process, and the second dielectric layer 171 can be a PI layer.
[0039] The second dielectric layer 171 is patterned by photolithography and etching processes to form a plurality of second openings on the second dielectric layer 171.
[0040] A second metal layer 172 is formed in the second openings by electroplating or the like, and the second metal layer 172 is electrically connected to the silicon through hole 130 of the silicon adapter chip 110.
[0041] In step S160, a plurality of independent memory chip modules are formed by cutting, and a plurality of the memory chip modules are sequentially stacked and bonded, including: As shown in Figure 8 A plurality of independent memory chip modules A are formed by a cutting process, as shown in Figure 9 The plurality of memory chip modules A are sequentially stacked and bonded by a hot-press bonding process. The memory chip module B at the top layer does not have a silicon adapter chip 110, and the base memory chip module C at the bottom layer can be fixed to a temporary carrier to facilitate the stacking of the plurality of memory chip modules A.
[0042] In step S170, a second encapsulation layer is formed to wrap the plurality of memory chip modules, which can specifically include: As shown in Figure 10 A second encapsulation layer 180 is formed to wrap the plurality of memory chip modules A, and the second encapsulation layer 180 protects the plurality of memory chip modules A.
[0043] In another embodiment, step S110 can specifically include: As shown in Figure 11 A plurality of silicon adapter chips 110 and a plurality of memory chips 120 are provided, wherein the silicon adapter chip 110 is provided with a plurality of silicon through holes 130 penetrating the thickness thereof. The front surface of the memory chip 120 is provided with a conductive bump 121.
[0044] In step S120, the plurality of silicon adapter chips and the plurality of memory chips are arranged in a flat manner, which can specifically include: As shown in Figure 11As shown, a second temporary carrier board 142 is provided to fix the first surfaces of the plurality of silicon interposer chips 110 and the back surface of the memory chip 120 to the second temporary carrier board 142.
[0045] Step S130, which involves forming a first molding compound 150 encapsulating the silicon interposer chip 110 and the memory chip 120, may specifically include: like Figure 12 As shown, a first molding compound 150 is formed on the surface of the second temporary carrier 142, and the first molding compound 150 protects the silicon interposer chip 110 and the memory chip 120.
[0046] The method further includes, after forming the first molding layer 150, the following steps: Figure 13 As shown, the first surface of the first molding layer 150 is thinned to expose the first surface of the silicon adapter chip 110 and the conductive bumps 121 on the front side of the memory chip 120.
[0047] In step S140, a first wiring layer 160 is formed on the first surface of the first molding compound 150, which is electrically connected to the silicon interposer chip 110 and the memory chip 120 respectively. Specifically, this may include: like Figure 14 As shown, the first wiring layer 160 is formed on the first surface of the thinned first molding compound 150, the second surface of the silicon interposer chip 110, and the front side of the memory chip 120. The specific steps for forming the first wiring layer 160 can be found in the above embodiments and will not be repeated here.
[0048] Step S150, which involves forming a second wiring layer electrically connected to the silicon interposer chip 110 on the second surface of the first molding compound 150, may further include: like Figure 15 As shown, the second temporary carrier board 142 is removed, and the first wiring layer 160 is fixed to the temporary carrier board 143 by the protective adhesive layer 142.
[0049] like Figure 16 As shown, a second wiring layer 170 is formed on the second surface of the first molding compound 150 and the first surface of the silicon interposer chip 110. The specific process for forming the second wiring layer 170 can be referred to the above embodiment, and will not be repeated here.
[0050] Step S160 involves cutting to form multiple independent memory chip modules, and then stacking and bonding the multiple memory chip modules sequentially, including: like Figure 17 As shown, multiple independent memory chip modules A are formed through a cutting process, such as... Figure 18As shown, multiple memory chip modules A are sequentially stacked and bonded together using a thermo-press bonding process. The top-level memory chip module B does not have a silicon adapter chip 110, and the bottom-level basic memory chip module C can be fixed to a temporary carrier board, facilitating the stacking of multiple memory chip modules A.
[0051] Each memory chip module A includes a silicon interposer chip 110 and a memory chip 120 laid flat, a first molding compound 150 encapsulating the silicon interposer chip 110 and the memory chip 120, a first wiring layer 160 disposed on the first surface of the first molding compound 150 and the front surface of the memory chip 120, and a second wiring layer 170 disposed on the second surface of the first molding compound 150.
[0052] Step S170, which involves forming a second molding layer encapsulating the plurality of memory chip modules, may specifically include: like Figure 19 As shown, a second molding compound 180 is formed, comprising multiple memory chip modules A, which protects the multiple memory chip modules A.
[0053] For example, such as Figure 20 As shown, in two adjacent memory chip modules A, the memory chip 120 in the upper memory chip module A corresponds one-to-one with the memory chip 120 in the lower memory chip module A; the silicon adapter chip 110 in the upper memory chip module A corresponds one-to-one with the silicon adapter chip 110 in the lower memory chip module A.
[0054] like Figure 20 As shown, in another embodiment, with memory chips 120 and silicon interconnect chips 110 in the upper and lower memory chip modules A corresponding one-to-one, multiple memory chip modules A are stacked and bonded together sequentially. Specifically, this may include: in two adjacent memory chip modules A, the front side of the memory chip 120 in the upper memory chip module A is bonded to the back side of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in two adjacent chip modules A are connected face-to-back (FTB).
[0055] Specifically, in two adjacent memory chip modules A, the first wiring layer 160 located on the front side of the memory chip 120 in the upper memory chip module A is thermally bonded to the second wiring layer 170 located on the back side of the memory chip 120 in the lower memory chip module A.
[0056] In another embodiment, provided that the memory chips 120 and silicon interposer chips 110 in the upper and lower memory chip modules A are in one-to-one correspondence, multiple memory chip modules A are stacked and bonded together sequentially. Specifically, this may include: in two adjacent memory chip modules A, the front side of the memory chip 120 in the upper memory chip module A is bonded to the front side of the memory chip 120 in the lower memory chip module A. That is, the chips in two adjacent chip modules A are connected face-to-face (FTF) or back-to-back (BTB).
[0057] Specifically, in two adjacent memory chip modules A, the first wiring layer 160 on the front of the memory chip 120 in the upper memory chip module A is thermally bonded to the first wiring layer 160 on the front of the memory chip 120 in the lower memory chip module A.
[0058] For example, such as Figure 21 As shown, in two adjacent memory chip modules A, the memory chip 120 in the upper memory chip module A and the memory chip 120 in the lower memory chip module A are staggered; the silicon adapter chip 110 in the upper memory chip module A and the silicon adapter chip 110 in the lower memory chip module A are staggered.
[0059] like Figure 21 As shown, in another embodiment, with the memory chips 120 and silicon interconnect chips 110 in the upper and lower memory chip modules A being staggered vertically, multiple memory chip modules A are sequentially stacked and bonded together. Specifically, this may include: in two adjacent memory chip modules A, the front side of the memory chip 120 in the upper memory chip module A is bonded to the back side of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in two adjacent chip modules A are connected face-to-back (FTB).
[0060] Specifically, in two adjacent memory chip modules A, the first wiring layer 160 located on the front side of the memory chip 120 in the upper memory chip module A is thermally bonded to the second wiring layer 170 located on the back side of the memory chip 120 in the lower memory chip module A.
[0061] In another embodiment, under the premise that the memory chips 120 and the silicon interposer chips 110 are staggered in the upper and lower memory chip module A, a plurality of the memory chip module A are sequentially stacked and bonded. Specifically, the front surface of the memory chip 120 in the upper memory chip module A is bonded to the front surface of the memory chip 120 in the lower memory chip module A. That is, the chips in the adjacent two chip modules A are connected face-to-face (FTF) or back-to-back (BTB).
[0062] Specifically, the first wiring layer 160 on the front surface of the memory chip 120 in the upper memory chip module A is thermocompression bonded to the first wiring layer 160 on the front surface of the memory chip 120 in the lower memory chip module A.
[0063] The multi-layer stacked memory packaging method of the embodiments of the present disclosure provides a separate silicon interposer chip to connect the upper and lower memory chip modules, and the manufacturing process is simple. Since the silicon interposer chip with a through silicon via is integrated with the DRAM wafer after the circuit test is completed, the yield problem of the through silicon via will not cause the loss of the chip, thereby reducing the cost of the DRAM wafer. The connection density of the silicon interposer chip is higher, and the corresponding packaging size can be smaller under the same connection requirement.
[0064] As shown in FIGS. 1, 2 and 3, Figure 20 and 21 Another aspect of the embodiments of the present disclosure provides a multi-layer stacked memory packaging structure 100, which is packaged by using the multi-layer stacked memory packaging method S100 described above. The specific process of the multi-layer stacked memory packaging method S100 has been described in detail above, and will not be described here.
[0065] The multi-layer stacked memory packaging structure 100 includes a plurality of stacked memory chip modules A and a second plastic encapsulation layer 180 wrapping the plurality of chip modules A. Each memory chip module A includes a silicon interposer chip 110 and a memory chip 120 arranged in a tile, a first plastic encapsulation layer 150 wrapping the silicon interposer chip 110 and the memory chip 120, a first wiring layer 160 arranged on the first surface of the first plastic encapsulation layer 150 and the front surface of the memory chip 120, and a second wiring layer 170 arranged on the second surface of the first plastic encapsulation layer 150. The chip module at the topmost layer does not have a silicon interposer chip 110.
[0066] For example, as shown in FIGS. 1, 2 and 3, Figure 20As shown, in the two adjacent memory chip module A, the front surface of the memory chip 120 in the upper memory chip module A is bonded to the back surface of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in the adjacent two chip modules A are connected face-to-back (FTB).
[0067] As shown, in an embodiment, under the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are one-to-one corresponding, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include that in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded to the back surface of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in the adjacent two chip modules A are connected face-to-back (FTB). Figure 20
[0068] Specifically, in the two adjacent memory chip modules A, the first wiring layer 160 located at the front surface of the memory chip 120 in the upper memory chip module A is thermocompression bonded to the second wiring layer 170 located at the back surface of the memory chip 120 in the lower memory chip module A.
[0069] In another embodiment, under the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are one-to-one corresponding, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include that in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded to the front surface of the memory chip 120 in the lower memory chip module A. That is, the chips in the adjacent two chip modules A are connected face-to-face (FTF) or back-to-back (BTB).
[0070] Specifically, in the two adjacent memory chip modules A, the first wiring layer 160 located at the front surface of the memory chip 120 in the upper memory chip module A is thermocompression bonded to the first wiring layer 160 located at the front surface of the memory chip 120 in the lower memory chip module A.
[0071] As shown, in an embodiment, under the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are one-to-one corresponding, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include that in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded to the back surface of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in the adjacent two chip modules A are connected face-to-back (FTB). Figure 21 As shown, in the two adjacent memory chip module A, the memory chip 120 in the upper memory chip module A and the memory chip 120 in the lower memory chip module A are staggered distribution; the silicon conversion chip 110 in the upper memory chip module A and the silicon conversion chip 110 in the lower memory chip module A are staggered distribution.
[0072] As shown, in an embodiment, on the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are staggered distribution, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include: in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded with the back surface of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in the two adjacent chip modules A are connected face-to-back (FTB). Figure 21 As shown, in an embodiment, on the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are staggered distribution, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include: in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded with the back surface of the memory chip 120 in the lower memory chip module A. That is, the two memory chips 120 in the two adjacent chip modules A are connected face-to-back (FTB).
[0073] Specifically, in the two adjacent memory chip modules A, the first wiring layer 160 located at the front surface of the memory chip 120 in the upper memory chip module A is thermocompression bonded with the second wiring layer 170 located at the back surface of the memory chip 120 in the lower memory chip module A.
[0074] In another embodiment, on the premise that the memory chip 120 and the silicon conversion chip 110 in the upper and lower memory chip module A are staggered distribution, the plurality of memory chip modules A are sequentially stacked and bonded, which can specifically include: in the two adjacent memory chip modules A, the front surface of the memory chip 120 in the upper memory chip module A is bonded with the front surface of the memory chip 120 in the lower memory chip module A. That is, the chips in the two adjacent chip modules A are connected face-to-face (FTF) or back-to-back (BTB).
[0075] Specifically, in the two adjacent memory chip modules A, the first wiring layer 160 located at the front surface of the memory chip 120 in the upper memory chip module A is thermocompression bonded with the first wiring layer 160 located at the front surface of the memory chip 120 in the lower memory chip module A.
[0076] The multi-layer stacked memory package structure of the embodiments of the present disclosure realizes the connection of the upper and lower memory chip modules through the silicon conversion chip arranged in a flat manner with the memory chips, the manufacturing process is simple, and meanwhile, since the silicon conversion chip provided with the through silicon via is integrated with the DRAM wafer after the circuit test is completed, the yield problem of the through silicon via will not cause the loss of the chip, thereby reducing the cost of the DRAM wafer; the connection density of the silicon conversion chip is higher, and the corresponding package size can be made smaller under the same connection requirement.
[0077] It can be understood that the above implementation is only an exemplary implementation for illustrating the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered as the protection scope of the embodiments of the present disclosure.
Claims
1. A method for packaging multi-layer stacked memory, characterized in that, The method includes: Multiple silicon interposer chips and multiple memory chips are provided, wherein the silicon interposer chips are provided with multiple through-silicon vias penetrating their thickness; The silicon adapter chips and the memory chips are arranged in a flat layout; A first molding layer is formed to encapsulate the silicon interconnect chip and the memory chip; A first wiring layer is formed on the first surface of the first molding layer, which is electrically connected to the silicon interposer chip and the memory chip respectively; A second wiring layer electrically connected to the silicon interposer chip is formed on the second surface of the first molding layer; Multiple independent memory chip modules are formed by cutting, and the multiple memory chip modules are stacked and bonded together in sequence. A second molding compound is formed to encapsulate the multiple memory chip modules.
2. The method according to claim 1, characterized in that, The plurality of silicon interposer chips and the plurality of memory chips are arranged in a flat configuration, including: A first temporary carrier board is provided, on which the first surfaces of the plurality of silicon interposer chips and the front surfaces of the plurality of memory chips are laid flat and fixed; After forming the first molding layer, the method further includes: removing the first temporary carrier plate.
3. The method according to claim 2, characterized in that, A first wiring layer is formed on the first surface of the first molding layer, which is electrically connected to the silicon interposer chip and the memory chip, respectively, including: The first wiring layer is formed on the first surface of the first molding layer, the first surface of the silicon interposer chip, and the front side of the memory chip; A second wiring layer electrically connected to the silicon interposer chip is formed on the second surface of the first molding layer, including: The second surface of the first molding layer is thinned to expose the through-silicon vias on the second surface of the silicon adapter chip; The second wiring layer is formed on the second surface of the first molding layer and the second surface of the silicon interposer chip.
4. The method according to claim 1, characterized in that, The arrangement of the plurality of silicon interposer chips and the plurality of memory chips in a flat configuration further includes: A second temporary carrier board is provided to fix the first surfaces of the plurality of silicon interposer chips and the back side of the memory chip to the second temporary carrier board, wherein the front side of the memory chip is provided with conductive bumps; After forming the first molding compound, the method further includes: thinning the first surface of the first molding compound to expose the first surface of the silicon interposer chip and the conductive bumps on the front side of the memory chip.
5. The method according to claim 4, characterized in that, A first wiring layer, electrically connected to the silicon interposer chip and the memory chip respectively, is formed on the first surface of the first molding layer, and further includes: The first wiring layer is formed on the first surface of the thinned first molding layer, the second surface of the silicon interposer chip, and the front side of the memory chip; A second wiring layer electrically connected to the silicon interposer chip is formed on the second surface of the first molding layer, and the method further includes: Remove the second temporary carrier plate; The second wiring layer is formed on the second surface of the first molding layer and the first surface of the silicon interposer chip.
6. The method according to claim 1, characterized in that, In two adjacent memory chip modules, the memory chips in the upper memory chip module correspond one-to-one with the memory chips in the lower memory chip module; The silicon adapter chips in the upper-layer memory chip module are distributed in a one-to-one correspondence with the silicon adapter chips in the lower-layer memory chip module.
7. The method according to claim 6, characterized in that, Stacking and bonding multiple memory chip modules sequentially includes: In two adjacent memory chip modules, the front side of the memory chip in the upper memory chip module is bonded to the back side of the memory chip in the lower memory chip module; or, In two adjacent memory chip modules, the front side of the memory chip in the upper memory chip module is bonded to the front side of the memory chip in the lower memory chip module.
8. The method according to claim 1, characterized in that, In two adjacent memory chip modules, the memory chips in the upper memory chip module and the memory chips in the lower memory chip module are distributed alternately; The silicon adapter chips in the upper-layer memory chip module and the silicon adapter chips in the lower-layer memory chip module are distributed alternately.
9. The method according to claim 8, characterized in that, Stacking and bonding multiple memory chip modules sequentially includes: In two adjacent memory chip modules, the front side of the memory chip in the upper memory chip module is bonded to the back side of the memory chip in the lower memory chip module; or, In two adjacent memory chip modules, the front side of the memory chip in the upper memory chip module is bonded to the front side of the memory chip in the lower memory chip module.
10. A multi-layer stacked memory package structure, characterized in that, It is packaged using the multilayer stacked memory packaging method according to any one of claims 1 to 9.