Anti-warping packaging structure and corresponding packaging method thereof

Abstract

The invention provides an anti-warping packaging structure, which can obviously reduce packaging warping, improve process yield and product reliability, is compatible with an existing low-cost dry film material process and a large-size panel-level packaging technology, and provides possibility for manufacturing large-size and multi-layer wiring high-performance packaging. The structure comprises a chip, the active surface of which is provided with a first rewiring layer; a plastic package layer; the core board comprises a core board body, a second rewiring layer and a third rewiring layer, the second rewiring layer is arranged on the upper surface of the core board body, and the third rewiring layer is arranged on the lower surface of the core board body; the upper surface of the chip is electrically connected with the third rewiring layer through the first rewiring layer, the third rewiring layer is connected with the second rewiring layer through a copper column in the core plate body, and the periphery of the chip in the thickness direction is coated with a plastic package layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip packaging, in particular to a warpage-resistant packaging structure, and provides a packaging method of the packaging structure. BACKGROUND

[0002] The existing wafer-level packaging technology mostly uses dry film or organic dielectric material as the dielectric layer of the redistribution layer. However, the dry film and other dielectric materials are soft and have poor mechanical strength. After the multilayer metal circuit is made on the dielectric layer, due to the significant difference in the thermal expansion coefficient between the metal and the dry film material, a huge internal stress is generated in the thermal cycle of the packaging process. The stress acts on the relatively soft dielectric layer structure, which easily leads to serious warpage deformation of the entire packaging product. The warpage can cause a series of process and reliability problems such as inaccurate photoetching focusing, decreased circuit yield, and subsequent mounting and welding difficulties, which restricts the application of the technology in high-performance packaging. SUMMARY

[0003] In view of the above problems, the present application provides a warpage-resistant packaging structure which can significantly reduce packaging warpage, improve process yield and product reliability, and is compatible with the existing low-cost dry film material process and high-density packaging technology, thereby making it possible to manufacture high-density interconnection and multilayer wiring high-performance packaging.

[0004] A warpage-resistant packaging structure, characterized in that it comprises: a chip, the active surface of which is arranged with a first redistribution layer; a plastic encapsulation layer; and a core board comprising a core board body, a second redistribution layer, and a third redistribution layer, the upper surface of the core board body being provided with the second redistribution layer, and the lower surface of the core board body being provided with the third redistribution layer; the upper surface of the chip being electrically connected to the third redistribution layer through the first redistribution layer, the third redistribution layer being connected to the second redistribution layer through the copper column in the core board body, and the chip being covered with the plastic encapsulation layer in the thickness direction.

[0005] Further features are as follows: the second redistribution layer and the third redistribution layer are arranged symmetrically or asymmetrically in the number of layers, so that the thermal stress on both sides of the core board body is counteracted, thereby balancing the warpage from the root; Preferably, the second redistribution layer and the third redistribution layer are symmetrical in the number of layers and structure relative to the redistribution layer of the core board body, thereby providing strong mechanical support for the entire packaging body; the core board body is a copper-free core board or a double-sided copper-clad core board that has been etched with a circuit; The core plate body is laser drilled at the designed pad position to prepare for the conduction of the upper and lower metal layers; the core plate body is also laser drilled at the blank area without electrical connection to prepare for the auxiliary connection copper column to increase the bonding force between the core plate body and the redistribution layer.

[0006] A packaging method of a warp-resistant packaging structure, characterized in that: a single chip is arranged and attached on a temporary carrier, the temporary carrier is a wafer or a circular glass, the temporary carrier has a small area, a wafer-level package is formed, then a plastic encapsulation layer is obtained, then the temporary carrier is separated, a third redistribution layer is made on the surface of the chip, the third redistribution layer is electrically connected to the chip, then a core plate body is bonded on the third redistribution layer, then a second redistribution layer is made on the upper surface of the core plate body, then tin balls are made on the second redistribution layer, and finally the entire packaging body is cut into separate independent units.

[0007] Further characterized in that, the specific operation steps are as follows: S1: a first redistribution layer is made on the surface of the wafer; S2: the wafer is ground to a target thickness and then cut into single chips; S3: the single chips are attached on a temporary carrier with temporary bonding glue, and plastic encapsulation is performed to obtain a plastic encapsulation layer; S4: after the temporary carrier is separated, a third redistribution layer is made on the active surface of the plastic encapsulation body chip; S5: a core plate body is bonded on the third redistribution layer, laser drilling is performed at the pad position of the core plate body to prepare for the conduction of the upper and lower metal layers; the same laser drilling is performed at the blank area without electrical connection to prepare for the auxiliary connection copper column to increase the bonding force between the core plate and the redistribution layer; S6: after the drilling is metalized, a second redistribution layer is made on the upper surface of the core plate body, and tin balls are made on the second redistribution layer; S7: the entire packaging body is cut into separate independent units.

[0008] Further characterized in that: In step S5, the core plate body is a copper-free core plate or a double-sided copper-clad core plate that has been etched with lines; the bonding material between the third redistribution layer and the core plate body can use dry film, semi-cured sheet, or use a hot-press bonding process to bond the third redistribution layer and the copper-clad surface of the core plate body together; In step S6, when the second redistribution layer is made, the number of layers of the second redistribution layer and the third redistribution layer on both sides of the core plate body is the same to balance the stress, or the number of redistribution layers on both sides of the core plate is different to balance the warp of the packaging body.

[0009] By adopting the technical scheme, the core plate body is pressed and stacked in the middle of the two groups of multilayer redistribution layers, and the redistribution layers on the upper and lower sides of the core plate body are symmetrical in the number of layers and structure, so that the overall core plate provides strong mechanical support for the entire package, and the redistribution layers on the two sides of the core plate body can also be designed to be symmetrical or asymmetrical in the number of layers, so that the thermal stress is counteracted on the two sides of the core plate, thereby balancing the warping from the root; the structure can significantly reduce the packaging warping, improve the process yield and product reliability, and is compatible with the existing low-cost dry film material process and high-density packaging technology, thereby providing the possibility for manufacturing high-density interconnection, multilayer wiring and high-performance packaging. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A specific embodiment structure schematic diagram of the anti-warping packaging structure of the application; Figure 2 A specific embodiment step S1 schematic diagram of the method of the application; Figure 3 A specific embodiment step S2 schematic diagram of the method of the application; Figure 4 A specific embodiment step S3 schematic diagram of the method of the application; Figure 5 A specific embodiment step S4 schematic diagram of the method of the application; Figure 6 A specific embodiment step S5 schematic diagram of the method of the application; Figure 7 A specific embodiment step S6 schematic diagram of the method of the application; Figure 8 A specific embodiment step S7 schematic diagram of the method of the application; The names corresponding to the serial numbers in the figure are as follows: Chip 10, active surface 11, first redistribution layer 12, plastic packaging layer 20, core plate 30, core plate body 31, second redistribution layer 32, third redistribution layer 33, temporary carrier plate 40, tin ball 50, temporary bonding glue 60. DETAILED DESCRIPTION

[0011] An anti-warping packaging structure, see Figure 1 which comprises a chip 10, a plastic packaging layer 20, and a core plate 30; The active surface 11 of the chip 10 is arranged with a first redistribution layer 12; The core plate 30 comprises a core plate body 31, a second redistribution layer 32, and a third redistribution layer 33, the upper surface of the core plate body 31 is provided with the second redistribution layer 32, and the lower surface of the core plate body 31 is provided with the third redistribution layer 33; The upper surface of the chip 10 is electrically connected to the third redistribution layer 33 through the first redistribution layer 12, the third redistribution layer 33 is connected to the second redistribution layer 32 through the copper column in the core plate body 10, and the chip 10 is covered with the plastic sealing layer 20 in the thickness direction.

[0012] In specific implementation, the entire packaging structure can be arranged reversely for subsequent use.

[0013] In specific implementation, the bottom of the chip 10 is directly covered with the plastic sealing layer 20 if there is no electrical connection structure, and if there is an electrical connection structure, the plastic sealing layer is ground to expose the electrical connection structure, and then additional electrical connection operation is performed with the external structure, which is not described here.

[0014] In specific implementation, the second redistribution layer 32 and the third redistribution layer 33 are arranged symmetrically or asymmetrically in the number of layers, so that the thermal stress is counteracted on both sides of the core plate body, thereby balancing the warping from the root.

[0015] In specific implementation, the second redistribution layer 32 and the third redistribution layer 33 are arranged symmetrically in the number of layers and structure relative to the redistribution layer of the core plate body 10, thereby providing strong mechanical support for the entire packaging body.

[0016] In specific implementation, the core plate body 31 is a copper-free core plate or a double-sided copper-clad core plate that has been etched with lines. The core plate body 31 is laser-drilled at the designed pad position to prepare for the conduction of the upper and lower layers of metal, and the core plate body 31 is laser-drilled in the blank area without electrical connection to prepare for the production of auxiliary connection copper columns, thereby increasing the bonding force of the core plate body 31 and the redistribution layer.

[0017] A packaging method of a warping-resistant packaging structure is provided in Figures 2-8 The single chip 10 is arranged and attached on a temporary carrier 40, the temporary carrier 40 is a wafer or a circular glass, the temporary carrier 40 has a small area, and a wafer-level packaging is formed, then the packaging obtains the plastic sealing layer 20, then the temporary carrier 40 is separated, the third redistribution layer 33 is made on the surface of the chip 10, the third redistribution layer 33 is electrically connected to the chip 10, then the core plate body 31 is bonded on the third redistribution layer 33, then the second redistribution layer 32 is made on the upper surface of the core plate body 31, then the tin balls 50 are made on the second redistribution layer 32, and finally the entire packaging body is cut into separate independent units.

[0018] In specific implementation, the specific operation steps are as follows: S1 make the first redistribution layer 12 on the wafer surface, which is made by photolithography and electroplating process, rearranging the connection points of the internal circuit of the chip, the first redistribution layer is composed of metal lines and dielectric layer, the dielectric layer material includes but is not limited to dry film, organic polymer dielectric material, the thickness of the dielectric layer is 15-45 microns; S2 cut the wafer into single chip 10 after grinding to the target thickness; S3 paste the single chip 10 on the temporary carrier 40 with temporary bonding glue 60, and perform plastic packaging to obtain the plastic packaging layer 20, the thickness of the plastic packaging layer 20 is equal to the thickness of the chip 10, or exceeds the thickness of the chip 10 by 70-200 microns, in a specific embodiment, the thickness of the plastic packaging layer 20 is 100 microns greater than the thickness of the chip 10; S4 make the third redistribution layer 33 on the active surface 11 of the chip 10 after removing the temporary carrier 40; S5 bond the core plate body 31 above the third redistribution layer 33, and perform laser drilling at the pad position of the core plate body 31 to prepare for the conduction of the upper and lower layers of metal; perform the same laser drilling in the blank area without electrical connection to prepare for the manufacture of auxiliary connection copper columns, so as to increase the bonding force of the core plate and the redistribution layer; The core plate body 31 is a copper-free core plate or a double-sided copper-clad core plate that has been etched with lines; the bonding material between the third redistribution layer 33 and the core plate body 31 can use dry film, semi-cured sheet, or use a hot-press bonding process to bond the third redistribution layer and the copper-clad surface of the core plate body together; S6 after the hole metallization of the drilled hole, make the second redistribution layer 32 on the upper surface of the core plate body 31, and make the tin ball 50 above the second redistribution layer 32; When making the second redistribution layer 32, the number of layers of the second redistribution layer 32 and the third redistribution layer 33 on both sides of the core plate body 31 is the same to balance the stress, or the number of layers of the redistribution layers on both sides of the core plate is different to balance the warping of the package; S7 cut the entire package into separate independent units.

[0019] The core plate body is pressed between the two groups of multilayer redistribution layers, and the redistribution layers on the upper and lower sides of the core plate body are kept symmetrical in number of layers and structure, so that the overall core plate provides strong mechanical support for the entire package, while the redistribution layers on both sides of the core plate body can also be designed by symmetrical or asymmetrical number of layers to make the thermal stress on both sides of the core plate counteract each other, thereby balancing the warping from the root; this structure can significantly reduce the package warping, improve the process yield and product reliability, and is compatible with the existing low-cost dry film material process and large-size panel-level packaging technology, which makes it possible to manufacture large-size, multi-layer wiring high-performance packages.

[0020] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0021] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. An anti-warpage packaging structure, characterized in that, It includes: The chip has a first redistribution layer arranged on its active surface; Plastic sealant; And a core board, which includes a core board body, a second redistribution layer, and a third redistribution layer, wherein the upper surface of the core board body is provided with the second redistribution layer and the lower surface of the core board body is provided with the third redistribution layer. The upper surface of the chip is electrically connected to the third redistribution layer through the first redistribution layer, and the third redistribution layer is connected to the second redistribution layer through copper pillars in the core board body. The outer periphery of the chip in the thickness direction is covered with a plastic encapsulation layer.

2. The anti-warping packaging structure according to claim 1, characterized in that: The second and third rewiring layers, through the arrangement of symmetrical or asymmetrical layers, allow thermal stress to cancel each other out on both sides of the core board body.

3. The anti-warping packaging structure according to claim 2, characterized in that: The second and third wiring layers are symmetrical in number and structure relative to the rewiring layers of the core board body.

4. The anti-warping packaging structure according to claim 1, characterized in that: The core board body is either a copper-free core board or a double-sided copper-clad core board that has already undergone circuit etching.

5. The anti-warping packaging structure according to claim 1, characterized in that: The core board body has laser-drilled holes at the designed solder pad positions to prepare for the conduction of the upper and lower metal layers; the core board body also has the same laser-drilled holes in the blank areas without electrical connections to prepare for the fabrication of auxiliary connecting copper pillars.

6. A packaging method for an anti-warpage packaging structure, used to fabricate an anti-warpage packaging structure as described in any one of claims 1-5, characterized in that: Individual chips are arranged and mounted on a temporary carrier board, which can be a wafer carrier board or a circular glass carrier board. The temporary carrier board has a small area to form a wafer-level package. After encapsulation, a molding layer is obtained. After being removed from the temporary carrier board, a third redistribution layer is made on the surface of the chip so that the third redistribution layer is electrically connected to the chip. Then, the core board body is bonded on the third redistribution layer. Next, a second redistribution layer is made on the upper surface of the core board body. Then, solder balls are made on the second redistribution layer. Finally, the entire package is cut into individual independent units.

7. The method for manufacturing an anti-warping packaging structure according to claim 6, characterized in that, The specific operating steps are as follows: S1 fabricates the first redistribution layer on the wafer surface; After the S2 wafer is ground to the target thickness, it is cut into individual chips; S3 mounts a single chip onto a temporary carrier board with temporary bonding adhesive and then encapsulates it to obtain an encapsulation layer; After S4 debonds and removes the temporary carrier board, a third redistribution layer is fabricated on the active side of the molded chip. S5 bonds the core board body above the third redistribution layer and performs laser drilling at the pad positions of the core board body to prepare for the conduction of the upper and lower metal layers; the same laser drilling is made in the blank areas without electrical connections to prepare for the creation of auxiliary connection copper pillars to increase the bonding force between the core board and the redistribution layer. After S6 performs in-hole metallization on the drilled hole, a second redistribution layer is made on the upper surface of the core board body, and solder balls are made above the second redistribution layer. S7 cuts the entire package into individual, independent units.

8. The method for manufacturing an anti-warping packaging structure according to claim 7, characterized in that: In step S5, the core board body is a copper-free core board or a double-sided copper-clad core board that has undergone circuit etching; the bonding material between the third redistribution layer and the core board body can be dry film, prepreg, or the third redistribution layer can be bonded to the copper-clad surface of the core board body using a hot-press bonding process.

9. The method for manufacturing an anti-warping packaging structure according to claim 7, characterized in that: In step S6, when the second rewiring layer is fabricated, the number of the second and third rewiring layers on both sides of the core board body is the same to balance the stress, or the different number of rewiring layers on both sides of the core board is used to balance the warpage of the package.

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