Copackaged optical device and method of manufacturing

Abstract

A method of manufacturing a co-packaged optical device includes bonding at least one redistribution interposer substrate to a package substrate, bonding a package component and a memory component to an upper surface of the redistribution interposer substrate; and bonding a photonic chip to the upper surface of the redistribution interposer substrate.

Description

TECHNICAL FIELD

[0001] The present invention relates to a co-packaged optical device and manufacturing method. BACKGROUND

[0002] Electronic signaling and processing is a technology used for signal transmission and processing. In recent years, optical signaling and processing has been used for an increasing number of applications, particularly for signal transmission using fiber optic related applications.

[0003] Optical signaling and processing is often combined with electronic signaling and processing to provide fully mature applications. For example, fiber optics can be used for long distance signal transmission, and electrical signals can be used for short distance signal transmission as well as processing and control. Thus, devices that integrate long distance optical components and short distance electronic components are formed for conversion between optical signals and electrical signals, as well as processing of optical signals and electrical signals. The package can thus include both an optical (photonic) die containing optical devices and an electronic die containing electronic devices. SUMMARY

[0004] In one embodiment, a method of manufacturing a co-packaged optical device includes bonding at least one package component and a memory component to an upper surface of a redistribution interposer substrate, bonding the redistribution interposer substrate to a package substrate, removing molding from the upper surface of the redistribution interposer substrate to expose interconnect structures connected to the redistribution interposer substrate, and bonding a photonic chip to the upper surface of the redistribution interposer substrate.

[0005] In another embodiment, a co-packaged optical device includes a redistribution interposer substrate bonded to a package substrate, a die component bonded to an upper surface of the redistribution interposer substrate, and a photonic chip bonded to the upper surface of the redistribution interposer substrate, wherein a portion of a molding layer is between the photonic chip and the redistribution interposer substrate.

[0006] In yet another embodiment, a co-packaged optical device includes a redistribution interposer substrate bonded to a package substrate, a top die component bonded to an upper surface of the redistribution interposer substrate, a photonic chip bonded to the upper surface of the redistribution interposer substrate, and a molding wall defining a hollow structure around the top die component and the photonic chip. BRIEF DESCRIPTION OF DRAWINGS

[0007] When read in conjunction with the accompanying Figure One The various aspects of the present disclosure can be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the sake of clarity. It is to be understood that other specific arrangements can be utilized and that the generic description set forth in this disclosure is explained only for a clear understanding and will not be used to limit the scope of the disclosure.

[0008] Figure 1An optical device incorporating an interposer is illustrated in accordance with some embodiments.

[0009] Figures 2-6 An intermediate stage view of forming an optical device using a wafer-on-substrate (WoS) architecture is illustrated in accordance with some embodiments.

[0010] Figures 7A-7D A view of bonding a photonic chip to a redistribution layer substrate using a solder bonding method is illustrated in accordance with some embodiments.

[0011] Figures 8A-8C A view of bonding a photonic chip to a redistribution layer substrate by forming a solder bump through an opening in the molding in a under-fill layer / over-molding process is illustrated in accordance with some embodiments.

[0012] Figures 9A-9C A view of bonding a photonic chip to a redistribution layer substrate by forming a solder bump on a dielectric via is illustrated in accordance with some embodiments.

[0013] Figures 10A-10B A view of bonding a photonic chip to a redistribution layer substrate using a solder bonding method in which the molding has been etched to provide a hollow trim is illustrated in accordance with some embodiments.

[0014] Figures 11A-11B A view of bonding a photonic chip to a redistribution layer substrate by forming a solder bump through an opening in the molding in a under-fill layer / over-molding process in which the molding has been etched to provide a hollow trim is illustrated in accordance with some embodiments.

[0015] Figures 12A-12B A view of bonding a photonic chip to a redistribution layer substrate by forming a solder bump on a dielectric via in which the molding has been etched to provide a hollow trim is illustrated in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first feature is formed directly on the second feature, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features are not directly in contact. In addition, the present disclosure can refer to reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, for ease of explanation, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for the purpose of illustrating one component or feature's relationship to another component or feature, as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Embodiments will now be discussed with reference to certain embodiments in which optical interposers are present on interposers that also include compact photonic engine chips to provide optical interconnections between optical devices. In some embodiments, the photonic engine chips can use system on integrated chip (SoIC) packaging technology to combine electronic integrated circuits (EICs) with photonic integrated circuits (PICs). System on integrated chip (SoIC) includes 3D inter-chip (3D IC) stacking technology for integrating chiplets that are partitioned from a system on chip (SoC).

[0019] The embodiments presented herein are intended to be illustrative and not limiting of the embodiments discussed. Rather, the embodiments discussed can be incorporated into a variety of broad implementations, such as general silicon photonics, or 3D integrated circuits with photonic applications, and all such implementations are fully intended to be encompassed within the scope of the embodiments.

[0020] Reference will now be made to Figure 1wherein a Chip-on-Wafer-on-Substrate (CoWoS) substrate 100 architecture including a redistribution interposer substrate 110 is shown. In an embodiment, the Chip-on-Wafer-on-Substrate (CoWoS) architecture can be a CoWoS-R or CoWoS-L substrate architecture. CoWoS-R is a package type that can employ an Integrated FanOut (InFO) fan-out wafer level package, featuring at least one redistribution layer and through insulator via (TIV) (also known as InFO via) to provide interconnects between small chips. For example, in Figure 1 In an embodiment, the redistribution interposer substrate 110 includes at least one redistribution layer. CoWoS-L includes local silicon interconnect (LSI) chips 111 for die-to-die interconnects and redistribution layers for power and signal delivery.

[0021] In an embodiment, the redistribution interposer substrate 110 can include local silicon interconnect (LSI) chips 111, a front side redistribution layer (FSRDL) 112, and a back side redistribution layer (BSRDL) 113, which can be collectively referred to as the circuitry of the redistribution interposer substrate 110. The circuitry of the redistribution interposer substrate 110 can provide top electrical communication of the top die assembly 120 connected to the top surface of the redistribution interposer substrate 110 to the top of the substrate 137 (e.g., a printed circuit board (PCB) substrate). The circuitry of the redistribution interposer substrate 110 can also provide intra-connectivity between the chips of the top die assembly 120. In some embodiments, the redistribution interposer substrate 110 is a molding-based interposer with wide-pitch redistribution layers on both the front side and back side, and with through insulator vias (TIV) for signal and power delivery, providing low loss for high-speed transmission of mid-high frequency signals.

[0022] The redistribution interposer substrate 110 can be connected to a substrate 137 (e.g., a printed circuit board substrate) by solder joints 131 (e.g., C4 solder joints). The opposite side of the substrate 137 (e.g., a printed circuit board substrate) can also include solder bumps 123, such as a ball grid array (BGA) solder. In some embodiments, the substrate 137 can also include a ring structure 140 and one or more surface mount device (SMD) chips 145 connected directly thereto.

[0023] In an embodiment, the top die assembly 120 includes a package assembly 125, a memory assembly 130, and at least one photonic chip 135, which can be a small photonic engine chip. For example, the package assembly 125 can include a device die, a package including the device die encapsulated therein, a system on chip (SoC) or integrated chip system (SoIC) die including multiple integrated circuits (or device dies) as system integration, or the like. The device die in the package assembly 125 can be or include a logic die, a memory die, an input / output die, an integrated passive device (IPD), or the like, or a combination thereof. For example, the logic device die in the package assembly can be a central processing unit (CPU) die, a graphic processing unit (GPU) die, a mobile application die, a micro control unit (MCU) die, a baseband (BB) die, an application processor (AP) die, or the like. The memory die in the package assembly 125 can include a static random-access memory (SRAM) die, a dynamic random-access memory (DRAM) die, or the like. The device die in the package assembly 125 can include a semiconductor substrate and an interconnect structure.

[0024] In some embodiments, the memory assembly 130 can include a memory stack, such as a high bandwidth memory (HBM) stack. In some other embodiments, the memory assembly 130 can include memory dies forming a die stack, and an encapsulation (e.g., a molding compound) region encapsulating the memory dies therein.

[0025] In some embodiments, the package assembly 125 and the memory assembly 130 can be bonded to the underlying redistribution interposer substrate 110 through bond 150. According to some embodiments, the bonding is performed through a Chip-on-Wafer (CoW) bonding process, in which the package assembly 125 and the memory assembly 130 (as separate chips / packages) are bonded to the redistribution interposer substrate 110.

[0026] In some embodiments, the top die assembly 120 further includes a photonics chip 135, which can be a small form factor photonics engine chip. In some embodiments, the small form factor photonics engine chip can use a System on Integrated Chip (SoIC) packaging technology (e.g., dielectric-to-dielectric and metal-to-metal bonding processes) to combine electronic integrated circuits with photonic integrated circuits. Photonic integrated circuits are designed to take advantage of the unique properties of light, offering advantages such as high bandwidth, low power consumption, and faster data transmission speeds compared to their electronic counterparts. These circuits typically include components such as waveguides, couplers, lasers, light-emitting diodes (or other coherent light sources), modulators, detectors, and other optical components (e.g., mirrors and reflectors). However, any suitable components can be used.

[0027] A Wafer-on-Substrate (CoWoS) architecture including the redistribution interposer substrate 110 can be formed using the methods described with reference to Figures 2-6 The bonding of the photonics chip 135 to the redistribution interposer substrate 110 can be performed after the top die assembly 120 and include molding 117 that trims the molding that accompanies the underfill layer / overmolding process of the solder bonding of the package assembly 125 and the memory assembly 130 to the redistribution interposer substrate 110. Some method embodiments for bonding a photonics chip 135 (e.g., a small form factor photonics engine chip) to a redistribution interposer substrate 110 are described with reference to Figures 7A-12B .

[0028] Figure 2 is a side cross-sectional view of a local silicon interconnect (LSI) layer 109 formed. The local silicon interconnect layer 109 includes a local silicon interconnect chip 111 formed in an insulating layer 98 having metal lines / interconnects 99 formed therein. In some embodiments, the metal lines / interconnects 99 can be through insulator vias. In the depicted embodiment, the local silicon interconnect chip 111 includes two local silicon interconnect dies. In some embodiments, the methods and structures described herein integrate the local silicon interconnect chip 111 (e.g., local silicon interconnect dies) for communication between the two components of the subsequently formed top die assembly 120 as Figure 2 depicted. Figure 4

[0029] Refer to Figure 2 ​The local silicon interconnect (LSI) chip 111 acts as an intermediary silicon die to connect the top die assembly 120, such as the subsequently connected package assembly 125, memory assembly 130, and / or photonic chip 135. In some embodiments, the local silicon interconnect chip 111 can be integrated into a local silicon interconnect layer 109 that includes metal lines / interconnects 99 and insulating layers 98 arranged to provide re-distributed I / O connections. Both the local silicon interconnect chip 111 and the metal lines / interconnects 99 can include vertical vias for the metal lines / interconnects. The vertical vias enable inter-layer signal transfer, which is critical for proper signal routing.

[0030] In one embodiment, the vias (e.g., metal lines / interconnects 99) of the local silicon interconnect (LSI) layer 109 are formed first. Then, the local silicon interconnect chip 111 is placed, and both the vias and the local silicon interconnect chip 111 are encapsulated in the insulating layers 98. The structure including the local silicon interconnect chip 111 encapsulated in the insulating layers 98 can then be planarized. A first carrier wafer 95 can be placed underneath the local silicon interconnect layer 109 including the local silicon interconnect chip 111 to provide mechanical support. In some embodiments, a release film (possibly a Light-to-Heat Conversion (LTHC) layer) can adhere the local silicon interconnect (LSI) layer 109 including the local silicon interconnect chip 111 to the first carrier wafer 95. The first carrier wafer 95 can be composed of a semiconductor material (e.g., silicon (Si)) or glass.

[0031] Figure 3 is a side cross-sectional view illustrating the formation of a front side redistribution layer 112 on the local silicon interconnect layer 109 including the local silicon interconnect chip 111. The front side redistribution layer 112 includes a metal interconnect layer 114 that electrically connects different top die assemblies 120, such as the subsequently connected package assembly 125, memory assembly 130, and / or photonic chip 135, for signal and / or power routing purposes. The front side redistribution layer 112 redistributes the electrical connections, allowing the bond pads on the chip to be connected to the package leads or solder balls. The bond pads of the top die assembly 120 can be formed on the interconnect vias 115. The metal interconnect layer 114 and the interconnect vias 115 can exist in one or more layers of insulating material.

[0032] The front side redistribution layer 112, including the metal interconnect layer 114 and the interconnect via 115, can be formed using deposition processes, such as chemical vapor deposition and / or spin-on deposition to form the insulating material. The openings and trenches for the metal lines and / or traces can be formed using photolithography and etching processes. Further, the metal material for the metal lines and / or traces, such as copper and / or aluminum, can be formed using deposition processes, such as sputtering and / or electroplating. In some embodiments, the upper surface of the front side redistribution layer 112 can be planarized using a planarization process, such as chemical mechanical planarization (CMP).

[0033] Figure 4 FIG. 7 is a side cross-sectional view illustrating the joining of the top die assembly 120 (e.g., package assembly 125 and memory assembly 130) to the front side redistribution layer 112. The top die assembly 120 can be joined to the contacts on the front side redistribution layer 112 using a solder joining / flip chip type process. The joining 150 provides a connection between the contact pads of the interconnect via 115 and the contact pads of the top die assembly 120. In some embodiments, the solder joining process can include micro-bumps, which can have a bump size of 25 microns or less. In some embodiments, the micro-bumps can be provided by copper micro-bumps. In some embodiments, the micro-bumps can also be composed of lead-free materials, such as SnAg, SnCu, SnAgCu. In some other cases, the micro-bumps can be PbAg. The joining 150 can be formed using indirect joining, batch reflow, thermocompression joining, direct joining, copper-to-copper diffusion joining, stud bump joining, and combinations thereof. It is noted that the above micro-bump methods are for illustrative purposes only. Examples of other solder application methods can include printed solder paste, engraved mask posts, photosensitive organic mask and doctor blade, electroplated solder, evaporation, pin dispensing, solder paste printing, electroplated solder bumps, electroplated copper pillars, and micro-bumps, and combinations thereof.

[0034] After the solder is applied to the contacts of the top die assembly 120, the solder can be brought into contact with the contacts on the contact pads of the interconnect via 115 under elevated temperature and pressure to effect the joining. After the joining, the underfill layer 116 can be applied. The underfill layer 116 can be a thermoset epoxy or polymer applied over the joining 150 to protect them and to strengthen the solder joint.

[0035] In some embodiments, the underfill layer 116 can be applied after the solder bumps have passed through a reflow oven and can be dispensed using an automated syringe. In some embodiments, the syringe is positioned to introduce the underfill layer 116 into a structure including at least the top die assembly 120 (e.g., package assembly 125 and memory assembly 130) that are joined to the front side redistribution layer 112. The underfill layer 116 can then flow under the top die assembly 120 (e.g., package assembly 125 and memory assembly 130) using capillary action.

[0036] In some embodiments, after the application of the underfill layer 116, the structure including at least the underfilled top die assembly 120 (e.g., the package assembly 125 and the memory assembly 130) is placed into a mold. After being positioned in the mold, a molding material is then applied to fill the mold. In some embodiments, portions of the molding material can extend from under the top die assembly 120 (e.g., the package assembly 125 and the memory assembly 130) onto the upper surface of the front side redistribution layer 112 exposed. The portions of the underfill layer and / or the molding material extending from under the top assembly 120 are hereinafter referred to as the molding 117.

[0037] Figure 5 FIG. 6 is a side cross-sectional view illustrating the bonding of a structure including the top die assembly 120 to a second carrier wafer 96. In some embodiments, a release film (which can be a light-to-thermal conversion (LTHC) layer) can adhere the top die assembly 120 (e.g., the package assembly 125 and the memory assembly 130) to the second carrier wafer 96. The second carrier wafer 96 can be composed of a semiconductor material (e.g., silicon (Si)) or glass. After the second carrier wafer 96 is bonded to the top die assembly 120 (e.g., the package assembly 125 and the memory assembly 130), the first carrier wafer 95 can be removed. For example, the first carrier wafer 95 can be debonded by projecting a laser beam on the release film to decompose the release film. After the first carrier wafer 95 is removed, the backside surface of the partial silicon interconnect layer 109 including the partial silicon interconnect chip 111 is exposed.

[0038] Figure 5 FIG. 7 further depicts the formation of a backside redistribution layer (BSRDL) 113 on the backside surface of the partial silicon interconnect layer 109. The backside redistribution layer 113 includes a metal interconnect layer 108, which can be present in one or more layers of insulating material. The backside redistribution layer 113 also includes interconnect vias 104 extending to the contacts 103 present on the backside surface of the backside redistribution layer 113.

[0039] The backside redistribution layer 113 including the metal interconnect layer 108 and the interconnect vias 104 can be formed using deposition processes, such as chemical vapor deposition and / or spin-on deposition to form the insulating material. The openings and recesses for the metal lines and / or traces can be formed using photolithography and etching processes. In addition, the metal material (e.g., copper and / or aluminum) for the metal lines and / or traces can be formed using deposition processes, such as sputtering and / or electroplating. In some embodiments, the backside surface of the backside redistribution layer 113 can be planarized using a planarization process, such as chemical mechanical planarization.

[0040] Figure 5Further description of forming solder bumps 129 on contacts 103. In some embodiments, solder bumps 129 can be controlled collapse chip connection bumps (C4 bumps). C4 bumps can be used to join chip 200 to a chip carrier (e.g., substrate 137 as shown in FIG. 1). The term "solder" as used herein refers to any metal or metal compound or alloy that is melted and then cooled to join two or more metal surfaces together. Generally, the melting point of solder ranges from 150 to 250 degrees Celsius. Solder bumps can be small solder balls (solder balls) that are joined to semiconductor device contact areas, interconnects, or contact pads. In some embodiments, solder bumps can be made from a lead-free solder mixture or a leaded tin solder. Figure 6

[0041] In some embodiments, the solder bumping process to form solder joints can include in-situ sputter cleaning to remove oxides or photoresist prior to depositing metal on contacts 103. Cleaning can also be used to roughen the surface of contacts 103 (also referred to as bond pads) to promote better adhesion of the under bump metal layer (UBM). A metal mask can be used to pattern the structure for UBM and bump deposition. In one embodiment, a chromium layer, a phase change chromium / copper layer, a copper layer, and a gold layer are sequentially evaporated to form a thin film under bump metal layer (UBM) on contacts 103. In one example, a lead tin solder is then evaporated on top of the under bump metal layer to form a thick layer. The height of the bump is determined by the volume of the evaporated material deposited. It is also a function of the distance between the metal mask and the wafer and the size of the mask opening. The deposited solder is conical in shape due to the way the solder forms in the opening of the solder mask. The solder can be reflowed to form a sphere.

[0042] In some embodiments, the flip chip process for joining chip 200 to substrate 137 involves forming C4 bumps that range in diameter from 200 microns to 75 microns. Note that the C4 solder method described above is for illustration purposes only. Other solder methods can be equally applicable, such as printing solder paste bumps and electroplating solder bumps.

[0043] Figure 6 Description of side cross-sectional view depicting joining surface mount device (SMD) chip 145 to substrate 137 (e.g., printed circuit board substrate). In some embodiments, surface mount device (SMD) chip 145 can be a passive component, such as a resistor and a capacitor. In some embodiments, surface mount device (SMD) chip 145 can be joined to substrate 137 (e.g., printed circuit board substrate) by solder joining (e.g., C4 solder bump joining).

[0044] Figure 6 ​It is also illustrated that the ring structure 140 is bonded to the substrate 137. The ring structure 140 can be used for heat dissipation of the device.

[0045] Figure 6 It is further illustrated that a ball grid array (BGA) is formed on the backside of the substrate 137. In some embodiments, the ball grid array can include the solder bumps 123. In some embodiments, the solder bumps 123 of the ball grid array can be C4 solder bump bonds.

[0046] Figure 6 It is further illustrated that the second carrier wafer 96 is removed. For example, the second carrier wafer 96 can be delaminated, for example, by projecting a laser beam on the release film, thereby decomposing the release film. After the second carrier wafer 96 is removed, the upper surface of the top die assembly 120 is exposed, for example, the top surface of the package assembly 125 and the memory assembly 130 are exposed.

[0047] Figures 2-6 It is illustrated that an intermediate stage view of forming an optical device using a wafer-on-substrate (WoS) architecture that can be processed to accept a photonics chip 135 as well as the top die assembly 120. The methods and structures of the present disclosure bond the photonics chip 135 (e.g., compact photonics engine chip) to the upper surface of the redistribution interposer substrate 110. In some embodiments, by bonding the photonics chip 135 (e.g., compact photonics engine chip) to the upper surface of the redistribution interposer substrate 110, the electrical circuit path between the photonics chip 135 (e.g., compact photonics engine chip) and the package assembly 125 (e.g., system on chip (SoC) and / or system on integrated chip (SoIC) chip) is minimized, which can improve device performance. Furthermore, mounting the photonics chip 135 (e.g., compact photonics engine chip) to the upper surface of the redistribution interposer substrate 110, instead of elsewhere (e.g., mounting to the substrate 137), can also advantageously reduce the risk of the photonics chip 135 (e.g., compact photonics engine chip) that can be caused by warpage. Further, by positioning the photonics chip 135 (e.g., compact photonics engine chip) on the upper surface of the redistribution interposer substrate 110, the methods and structures described herein allow for adjusting the height of the upper surface of the photonics chip 135 to be approximately equal to the height of the ring structure 140, which can facilitate the attachment of a fiber array unit (FAU) to the photonics chip 135. The methods and structures described herein can allow the height of the photonics chip 135 and the ring structure 140 to be independent of other top assembly 120 coplanar, which can be taller or lower than the photonics chip 135.

[0048] Some method embodiments for bonding a photonic chip 135 (e.g., compact photonic engine chip) to a redistribution interposer substrate 110 are described with reference to Figures 7A-12B In each of the following process flows, bonding a photonic chip 135 can begin with removing at least a portion of molding 117 covering a portion of the redistribution interposer substrate 110. For example, a portion of the molding 117 is removed from the redistribution interposer substrate 110 to expose electrical connections of interconnect metal within the redistribution interposer substrate 110 to which a photonic chip 135 (e.g., compact photonic engine chip) is to be bonded. The molding 117 is removed from a portion of the redistribution interposer substrate 110 adjacent to a portion of a memory component 130 (e.g., high bandwidth memory module). In some embodiments described herein, there can be one memory component 130 (e.g., high bandwidth memory module) per side of a package component 125 (e.g., system on a chip (SoC) and / or system on integrated chip (SoIC) chip). In accordance with these embodiments, a photonic chip 135 (e.g., compact photonic engine chip) can then be bonded to an adjacent location of each memory component 130.

[0049] Figures 7A-7D A view of bonding a photonic chip 135 (e.g., compact photonic engine chip) to a redistribution interposer substrate 110 using a solder bonding method is illustrated in accordance with some embodiments. Figure 7A A view of applying solder balls 165 (e.g., microballs) to contacts 160 of a photonic chip 135 (e.g., compact photonic engine chip) prior to bonding the photonic chip 135 to interconnect vias 115 of a front side redistribution layer 112 is illustrated in accordance with some embodiments.

[0050] In some embodiments, the solder balls 165 can comprise microbumps, which can have a bump size of 25 microns or less. In some embodiments, the microbumps can be provided by copper microbumps. In some embodiments, the microbumps can also be composed of lead-free materials such as SnAg, SnCu, SnAgCu, or combinations thereof. In some other cases, the microbumps can be PbAg.

[0051] It is noted that the above-described microbumps are for illustration purposes only. Examples of other bonding and joining methods can include printed solder paste, engraved mask pips, phototool organic mask and squeegee, electroplated solder, evaporation, pin dispensing, solder paste printing, electroplated solder bumps, electroplated copper pillars with microbumps, and combinations thereof. In Figure 7A In some embodiments, the upper surface of the interconnect via 115 is covered by the molding 117.

[0052] Figure 7BThe molding 117 is removed to expose the upper surface of the interconnect via 115. In some embodiments, the portion of the molding 117 extending to the upper surface of the front side redistribution layer 112 is adjacent to the top die assembly 120. In some examples, the portion of the molding 117 covering the interconnect via 115 to which the photonic chip 135 is to be bonded can be removed using an etching process. In some embodiments, an etch mask (e.g., a photoresist mask) can be formed, exposing the portion of the device including the molding 117 to be removed, and protecting other portions of the device from being damaged by the etching process used to remove the molding 117.

[0053] In some embodiments, a layer of photoresist material can be deposited over the entire surface, and then patterned and developed to provide openings through which an etchant can remove the portion of the molding 117 covering the interconnect via 115 to which the photonic chip 135 (e.g., compact photonic engine chip) is to be bonded, thereby forming a photoresist mask (not shown). The layer of photoresist material can be patterned using photolithography. The etching process used to remove the exposed portion of the molding 117 can be a non-isotropic etching process. For example, the non-isotropic etching process used to remove the molding 117 can include reactive ion etching (RIE). In some embodiments, the etching process used to remove the molding 117 can selectively remove the molding material without affecting the insulating material of the front side redistribution layer 112, while also being selective to the interconnect via 115. In some embodiments, if the insulating material of the front side redistribution layer 112 is present on the interconnect via 115, it can also be removed using the etching process.

[0054] It is noted that etching is not the only method to remove the molding 117. Physical removal processes such as sawing can also be used to remove the molding 117 to expose the upper surface of the interconnect via 115 in the front side redistribution layer 112.

[0055] Referring to Figure 7C After the molding 117 is removed, solder is applied to the contacts 160 of the photonic chip 135 (e.g., compact photonic engine), and then brought into contact with the interconnect via 115 under elevated temperature and pressure to effect bonding. Figure 7C is Figure 7D Enlarged view of the window identified by reference number 301 in FIG. 15. After bonding, an underfill layer 161 can be applied. The underfill layer 161 can be a thermoset epoxy or polymer applied to the solder balls 165 to protect them and enhance the strength of the solder joints. In some embodiments, the underfill layer 161 can be applied after the solder bumps have passed through a reflow oven, and can be dispensed using an automated syringe. The underfill layer 161 flows under the photonic chip 135 (e.g., compact photonic engine chip) using capillary action, and can be heat cured.

[0056] Figure 7DThis is a side cross-sectional view depicting the bonding between the photonic chip 135 (e.g., a compact photonic engine chip) and the redistributed interposer substrate 110. Figure 7D As shown, the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is coplanar with the upper surface of the annular structure 140. The upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is coplanar with the upper surface of the top die assembly 120, such as the upper surface of the package assembly 125 (e.g., a system-on-a-chip (SoC) and / or a system-on-a-chip (SoIC)), and / or with the upper surface of the memory assembly 130 (e.g., a high-bandwidth memory (HBM) module). By increasing the height of the upper surface of the photonic chip (e.g., the compact photonic engine chip) to make it coplanar with the upper surface of the annular structure 140, these methods and structures provide a more accessible location for mounting fiber array units (FAUs) onto the photonic chip 135 (e.g., the compact photonic engine chip).

[0057] Figures 8A-8C The following is a view illustrating, according to some embodiments, bonding a photonic chip 135 (e.g., a compact photonic engine chip) to a redistributed interposer substrate 110 by forming solder balls 165 from a bottom fill layer / overlay molding process through forming openings in molding 117.

[0058] Figure 8A The trimming molding 117 is described as providing an opening 118 to the contact of the interconnecting through-hole 115. (With) Figure 7A In the depicted embodiment, a portion of the molding 117 is retained after the opening 118 leading to the interconnect via 115 contact is formed. The remaining portion of the molding 117 is retained in the final device structure and, after the photonic chip 135 (e.g., a compact photonic engine chip) is bonded to the front redistribution layer 112, its total height of its upper surface is greater than the height of the upper surface of the package assembly 125 (e.g., a system-on-a-chip (SoC) and / or a system-on-a-chip (SoIC)) and / or higher than the upper surface of the memory assembly 130 (e.g., a high-bandwidth memory module).

[0059] In some embodiments, the mold 117 can be patterned and etched to provide openings 118 in the mold 117 that expose the upper surfaces of the interconnect vias 115. In some embodiments, an etch mask, such as a photoresist mask, can be formed that exposes portions of the mold 117 that are to be etched to form the openings 118 to the upper surfaces of the interconnect vias 115 to which the photonic chips 135 (e.g., compact photonic engine chips) are to be bonded. In some embodiments, the etch mask also protects other portions of the device from being damaged by the etching process that removes portions of the mold 117. In some embodiments, the photoresist mask can be formed by depositing a layer of photoresist material and then patterning and developing the mask to provide openings through which an etchant can remove portions of the mold 117 to form the openings 118 in the mold 117 to the interconnect vias 115 to which the photonic chips 135 (e.g., compact photonic engine chips) are to be bonded. The layer of photoresist material can be patterned using photolithography techniques. The etching process that forms the openings 118 in the mold 117 can be a non-isotropic etching process. For example, the non-isotropic etching process that forms the openings 118 in the mold 117 can include reactive ion etching. In some embodiments, the etching process that forms the openings 118 in the mold 117 can selectively remove material of the mold 117 without affecting the insulating material of the front side redistribution layer 112, while also being selective to the interconnect vias 115. In some embodiments, the etching process can also be used to remove the insulating material of the front side redistribution layer 112 if it is present on the interconnect vias 115.

[0060] In some embodiments, prior to solder bonding the photonic chips 135 (e.g., compact photonic engine chips), additional conductive material can be deposited in the openings 118, which can increase the height of the interconnect vias 115. The conductive material can include copper. In some other embodiments, the conductive material can include aluminum. In some other embodiments, the conductive material can be deposited using an electroplating and / or a physical vapor deposition (PVD) process.

[0061] Figure 8A It is also illustrated that solder balls 165 (e.g., micro-balls) are applied to the contacts 160 of the photonic chips 135 (e.g., compact photonic engine chips). In some embodiments, the solder balls 165 can include micro-bumps that can have a bump size of 25 microns or less. More details regarding the formation of the solder balls 165 (e.g., micro-bumps) have been described above with reference to Figure 7A It is also illustrated that solder balls 165 (e.g., micro-bumps) are applied to the contacts 160 of the photonic chips 135 (e.g., compact photonic engine chips). In some embodiments, the solder balls 165 can include micro-bumps that can have a bump size of 25 microns or less. More details regarding the formation of the solder balls 165 (e.g., micro-bumps) have been described above with reference to

[0062] After the solder is applied to the contacts 160 of the photonic chips 135 (e.g., compact photonic engine chips), the solder can be brought into contact with the contacts on the interconnect via 115 contact pads at elevated temperature and pressure to achieve bonding, as Figure 8B illustrated.Figure 8B yes Figure 8C An enlarged view of the window identified by reference number 302. After bonding, an underfill layer 161 may be applied. The underfill layer 161 may be a thermosetting epoxy resin or polymer, applied to the solder balls 165 to protect them and enhance the strength of the solder joint. In some embodiments, the underfill layer 161 may be applied after the solder bumps have passed through a reflow oven and may be dispensed using an auto-injector. The underfill layer 161 may flow under the photonic chip 135 (e.g., a compact photonic engine chip) via capillary action and may be heat-cured.

[0063] Figure 8C This is a side cross-sectional view depicting the bonding between the photonic chip 135 (e.g., a compact photonic engine chip) and the redistributed interposer substrate 110. (See image.) Figure 8C As shown, the upper surface of the compact photonic engine chip 135 (e.g., a coupe chip) is higher than the upper surface of the top die assembly 120 (e.g., the upper surface of the package assembly 125, such as a system-on-a-chip (SoC) and / or a system-on-a-chip (SoIC) chip), and / or higher than the upper surface of the memory assembly 130 (e.g., a high-bandwidth memory module). However, the upper surface of the package assembly 12 (e.g., the upper surface of the photonic chip 135, such as the compact photonic engine chip) is coplanar with the upper surface of the annular structure 140. The increase in the height of the photonic chip 135 is due to the remaining molding 117 portion between the photonic chip 135 (e.g., the compact photonic engine chip) and the redistributed interposer substrate 110. By increasing the height of the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) to be equal to the height of the annular structure 140, these methods and structures provide a more accessible location for mounting fiber array units (FAUs) onto the photonic chip 135 (e.g., the compact photonic engine chip). The height of the photonic chip 135 can be adjusted independently of the height of the upper surface of the top die assembly 120.

[0064] Figures 9A-9C In some embodiments, a photonic chip 135 (e.g., a compact photonic engine chip) is bonded to a redistributed interposer substrate 110 (e.g., ...). Figure 9C The view shown is an example of a method in which a photonic chip 135 is bonded to an insulator through-hole (TIV) 99 (also known as a metal line / interconnect) in a local silicon interconnect (LSI) layer 109.

[0065] Figure 9A This describes applying solder balls 165 (e.g., microspheres) to contacts 160 of the photonic chip 135 before bonding the photonic chip 135 (e.g., a compact photonic engine chip) to a through-insulator (TIV) 99 present in a local silicon interconnect (LSI) layer 109. Similar to the reference... Figures 7A-7CThe described embodiments first remove portions of the molding 117 to expose underlying portions of the front side redistribution layer 112 adjacent to the top die assembly 120. After removing the molding 117, the exposed portions of the front side redistribution layer 112 are removed to expose contact surfaces of the insulator vias 99 within the local silicon interconnect layer 109.

[0066] For example, portions of the molding 117 and the front side redistribution layer 112 that cover the insulator vias (TIVs) 99 to which the photonic chip 135 (e.g., compact photonic engine chip) is to be bonded can be removed using an etching process. In some embodiments, an etch mask, such as a photoresist mask, can be formed to expose portions of the device, including the portions of the molding 117 and the front side redistribution layer 112 to be removed. In some embodiments, the photoresist mask can also protect other portions of the device that are not to be etched from damage by the etching process used to remove the portions of the molding 117 and the front side redistribution layer 112. In some embodiments, the photoresist mask can be formed by depositing a layer of photoresist material across the device, and then patterning and developing the mask to provide openings through which an etchant can remove the portions of the molding 117 and the front side redistribution layer 112 that cover the insulator vias 170 to which the photonic chip 135 (e.g., compact photonic engine chip) is to be bonded. The layer of photoresist material can be patterned using photolithography techniques.

[0067] The etching process used to remove the exposed portions of the molding 117 and the exposed portions of the front side redistribution layer 112 can be a non-isotropic etching process. For example, the non-isotropic etching process used to remove the molding 117 and the front side redistribution layer 112 can include reactive ion etching. In some embodiments, the etching process used to remove the molding 117 can selectively remove the material of the molding 117 without etching the insulating material of the front side redistribution layer 112. In some embodiments, the etching process used to remove the front side redistribution layer 112 can be selective to the insulator vias 99 while also being selective to the insulating layer 98 of the local silicon interconnect layer 109.

[0068] Figure 9A It is also described that solder balls 165 (e.g., micro-bumps) are applied to the contacts 160 of the photonic chip 135 (e.g., compact photonic engine chip). Further details regarding the formation of the solder balls 165 (e.g., micro-bumps) have been provided in the description of Figure 7A .

[0069] After the solder is applied to the contacts 160 of the photonic chip 135 (e.g., compact photonic engine chip), the solder can be brought into contact with the contacts of the insulator vias (TIVs) 99 at elevated temperature and pressure to effect bonding, as shown in Figure 9B . Figure 9B is Figure 9CAn enlarged view of the window identified by reference numeral 303. After bonding, an underfill layer 161 may be applied. The underfill layer 161 may be a thermosetting epoxy resin or a polymer, applied to the solder balls 165 to protect them and strengthen the solder joint. In some embodiments, the underfill layer 161 may be applied after the solder bumps have passed through a reflow oven and may be dispensed using an auto-injector. The underfill layer 161 may flow under the photonic chip 135 (e.g., a compact photonic engine chip) using capillary action and may be heat-cured.

[0070] Figure 9C This is a side cross-sectional view depicting the bonding between the photonic chip 135 (e.g., a compact photonic engine chip) and the insulator via 99 of the local silicon interconnect layer 109, which includes the local silicon interconnect chip 111. Figure 9C As shown, the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is lower than the upper surface of the top die assembly 120, for example, lower than the upper surface of the package assembly 125 (e.g., a system-on-a-chip (SoC) and / or a system-on-a-chip (SoIC) chip), and / or lower than the upper surface of the memory assembly 130 (e.g., a high-bandwidth memory module). However, the upper surface of the photonic chip 135 (e.g., the compact photonic engine chip) is coplanar with the upper surface of the annular structure 140. Figures 9A-9C Another embodiment is described, in which the height of the photonic chip 135 can be adjusted independently of the height of the upper surface of the top die assembly 120. In this example, the height of the top die assembly 120 is greater than the height of the annular structure 140. To reduce the height of the photonic chip 135, portions of the molding 117 and the front redistribution layer 112 are removed from the mounting point of the photonic chip 135. By reducing the height of the upper surface of the photonic chip (e.g., a compact photonic engine chip) to be coplanar with the upper surface of the annular structure 140, these methods and structures provide a more accessible location for mounting fiber array units (FAUs) onto the photonic chip 135 (e.g., a compact photonic engine chip).

[0071] Figures 10A-12B Some embodiments are described, in which molding 117 can be trimmed to provide a hollow structure in which the remaining portion of molding 117 serves as a molding wall 401 at the die edge. This hollow structure surrounds the package assembly 125, the memory assembly 130, and the photonic chip 135 (e.g., a compact photonic engine chip). Figures 10A-12BIn each of the depicted embodiments, the hollow structure can be formed from the molding 117 using deposition, lithography, and / or etching processes to remove the molding 117 to expose the interconnects (e.g., the insulator vias 99 and / or the interconnect vias 115) for bonding with the photonic chip 135 (e.g., compact photonic engine chip). Sawing can be an alternative method to etching the molding 117. For example, the hollow structure can be formed using a photoresist mask that protects portions of the molding 117 that provide the molding walls 401. The etching process used to define the hollow structure molding walls 401 geometry can be a non-isotropic etch, such as a reactive ion etch (RIE). The molding walls 401 can be separated from the sidewalls of the photonic chip 135 (e.g., compact photonic engine chip) by the voids 400 (e.g., spaces filled with air). In some embodiments, the molding walls 401 can be formed by lithography and etching processes to expose the interconnects (e.g., the insulator vias (TIV) 170 and / or the interconnect vias 115).

[0072] Figures 10A-10B A view illustrating the use of a solder bonding method to bond the photonic chip 135 (e.g., compact photonic engine chip) to the redistribution interposer substrate 110 is depicted, in accordance with some embodiments, where the molding 117 has been etched to provide a hollow finish. Figures 10A-10B The solder bonding method depicted is similar to the method described above with reference to Figures 7A-7D The described method. For example, Figures 10A-10B The method depicted includes removing a portion of the molding 117 from the upper surface of the front side redistribution layer 112 adjacent to the top die portion including the memory component 130. Removing the molding 117 exposes the upper surface of the interconnect vias 115. Further details of etching the molding 117 are provided above with reference to Figures 7A-7D The described method, where in Figure 9A and Figure 9B Components having the same reference numbers in Figures 7A-7D The described method can be described by the descriptions provided above with reference to Figures 10A-10B In accordance with embodiments, etching the molding 117 also includes a masking and etching process to form the hollow structure (e.g., the molding walls 401). Still referring to Figures 10A-10B After the etching process exposes the interconnect vias 115, the photonic chip 135 (e.g., compact photonic engine chip) can be bonded to the interconnect vias 115 using a solder bonding technique. For example, the photonic chip 135 can be bonded to the interconnect vias 115 using solder balls 165, and a bottom fill layer 161 can also be applied.

[0073] Figure 10A is Figure 10B A close-up view of the window identified by reference number 304 in Figure 10BAs shown, the upper surface of the photonic chip 135 (e.g., compact photonic engine chip) is coplanar with the upper surface of the top die assembly 120, e.g., the upper surface of the package assembly 125 (e.g., system on a chip (SoC) and / or system on integrated chip (SoIC) chip), and / or coplanar with the upper surface of the memory assembly 130, e.g., high bandwidth memory module. As Figure 10B As shown, the upper surface of the photonic chip 135 (e.g., compact photonic engine chip) is coplanar with the upper surface of the ring structure 140.

[0074] Figures 11A-11B A view of the photonic chip 135 (e.g., compact photonic engine chip) bonded to the redistribution interposer substrate 110 is illustrated by forming solder balls 165 from a bottom fill / overmolding process with openings formed in the molding 117 to provide a hollow trim, in accordance with some embodiments. Figures 11A-11B The solder bonding method depicted in Figures 8A-8C is similar to the method described above with reference to Figures 11A-11B For example, Figures 8A-8C The method depicted in Figure 11A includes forming openings in the portion of the molding 117 adjacent to the top die portion including the memory assembly 130. Forming the openings in the molding 117 exposes the upper surface of the interconnect via 115. Further details of etching the molding 117 are provided above with reference to Figure 11B where components having the same reference numbers in Figures 8A-8C and Figures 11A-11B may be described by the descriptions provided above for these components. However, in accordance with embodiments consistent with Figures 11A-11B After the etching process exposes the interconnect via 115, the photonic chip 135 (e.g., compact photonic engine chip) can be bonded to the interconnect via 115 using a solder bonding technique. For example, the photonic chip 135 can be bonded to the interconnect via 115 using solder balls 165 and a bottom fill layer 161 can also be applied.

[0075] Figure 11A is Figure 11B a zoomed in view of the window identified by reference number 305 in Figure 11B As shown, the upper surface of the photonic chip 135 (e.g., compact photonic engine chip) is higher than the upper surface of the top die assembly 120, e.g., the upper surface of the package assembly 125 (e.g., system on a chip (SoC) and / or system on integrated chip (SoIC) chip), and / or higher than the upper surface of the memory assembly 130, e.g., high bandwidth memory module. As Figure 11BAs shown, the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is coplanar with the upper surface of the annular structure 140.

[0076] Figures 12A-12B The illustration shows a view of bonding a photonic chip 135 (e.g., a compact photonic engine chip) to a redistribution interposer substrate 110 by forming solder balls 165 on an insulator via 170, wherein molding 117 has been etched to provide a hollow trim, according to some embodiments.

[0077] Figures 12A-12B The solder bonding method described is similar to the one mentioned above. Figures 9A-9C The described method. For example, Figures 12A-12B The described method involves removing a portion of molding 117 and front redistribution layer 112 adjacent to the top die portion including memory assembly 130. Removing a portion of molding 117 and front redistribution layer 112 exposes the upper surface of insulator via 99. Further details of etching molding 117 and front redistribution layer 112 are referenced above. Figures 9A-9C Provided by China, among which Figure 12A and Figure 12B Components with the same reference number can be found in the above reference. Figures 9A-9C The descriptions provided for these components are used to describe them. However, with Figures 12A-12B In a consistent embodiment, etching molding 117 also includes masking and etching processes for forming a hollow structure (e.g., molded wall 401). Still referring to... Figures 12A-12B After the etching process exposes the insulator via 170, the photonic chip 135 (e.g., a compact photonic engine chip) can be bonded to the insulator via 99 using solder bonding techniques. For example, the photonic chip 135 can be bonded to the insulator via 99 using solder balls 165, and an underfill layer 161 can also be applied.

[0078] Figure 12A yes Figure 12B A magnified view of the window identified by reference number 306. (See also...) Figure 12B As shown, the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is lower than the upper surface of the top die assembly 120, for example, lower than the upper surface of the package assembly 125 (e.g., a system-on-a-chip (SoC) and / or a system-on-a-chip (SoIC) chip), and / or lower than the upper surface of the memory assembly 130, for example, a high-bandwidth memory module. Figure 12B As shown, the upper surface of the photonic chip 135 (e.g., a compact photonic engine chip) is coplanar with the upper surface of the annular structure 140.

[0079] In some embodiments, by bonding the photonic chip 135 (e.g., compact photonic engine chip) to the upper surface of the redistribution interposer substrate 110, the electrical path between the photonic chip 135 (e.g., compact photonic engine chip) and the package assembly 125 (e.g., system on a chip (SoC) and / or system on integrated chip (SoIC) chip) is minimized, which can improve device performance. Further, mounting the photonic chip 135 (e.g., compact photonic engine chip) to the upper surface of the redistribution interposer substrate 110, rather than elsewhere (e.g., to the substrate 137), can also advantageously reduce the risk of the photonic chip 135 (e.g., compact photonic engine chip) that can be caused by warpage. Still further, by positioning the photonic chip 135 (e.g., compact photonic engine chip) on the upper surface of the redistribution interposer substrate 110, the methods and structures described herein allow for adjusting the height of the upper surface of the photonic chip 135 to be approximately equal to the height of the ring structure 140, which can facilitate the attachment of a fiber array unit (FAU) to the photonic chip 135. Further, by mounting the photonic chip 135 (e.g., compact photonic engine chip) to the upper surface of the redistribution interposer substrate 110, the methods and structures described herein can make it easier for the package to employ local silicon interconnect (LSI), surface mount device (SMD) chips, ring structures (oscillator ring structures), capped ring structures, and combinations thereof.

[0080] In an embodiment, a method of manufacturing a co-packaged optical device includes: bonding at least one package component and a memory component to an upper surface of a redistribution interposer substrate; bonding the redistribution interposer substrate to a package substrate; removing a mold from the upper surface of the redistribution interposer substrate to expose interconnect structures connected to the redistribution interposer substrate; and bonding a photonic chip to the upper surface of the redistribution interposer substrate. In an embodiment, the package component includes a system on chip (SoC) component. In an embodiment, the package component includes a system on integrated chip (SoIC) component. In an embodiment, the upper surface of the redistribution interposer substrate is present a ring structure, an upper surface of the ring structure is coplanar with an upper surface of the photonic chip. In an embodiment, the upper surface of the photonic chip is higher than an upper surface of the at least one package component and the memory component. In an embodiment, the upper surface of the photonic chip is coplanar with the upper surface of the at least one package component and the memory component. In an embodiment, the upper surface of the photonic chip is lower than the upper surface of the at least one package component and the memory component. In an embodiment, the method further includes removing the mold to expose the interconnect structures, including exposing interconnect vias in the redistribution interposer substrate. In an embodiment, removing the mold includes etching openings in the mold to expose interconnect posts in the redistribution interposer substrate. In an embodiment, the redistribution interposer substrate includes a local silicon interconnect layer with insulator vias, a front side redistribution layer on a first side of the local silicon interconnect layer, and a back side redistribution layer on a second side of the local silicon interconnect layer. In an embodiment, bonding the photonic chip to the upper surface of the redistribution interposer substrate includes removing the mold and a portion of the front side redistribution layer to expose the insulator vias. In an embodiment, removing the mold from the upper surface of the redistribution interposer substrate includes forming a mold wall of a hollow structure around the package component, the memory component, and the photonic chip.

[0081] In another embodiment, a co-packaged optical device includes: a redistribution interposer substrate bonded to a package substrate; a die component bonded to an upper surface of the redistribution interposer substrate; and a photonic chip bonded to the upper surface of the redistribution interposer substrate, wherein a portion of a mold layer is between the photonic chip and the redistribution interposer substrate. In an embodiment, the die component includes a package component. In an embodiment, the die component includes a memory component. In an embodiment, the upper surface of the redistribution interposer substrate is present a ring structure, an upper surface of the ring structure is coplanar with an upper surface of the photonic chip. In an embodiment, the upper surface of the photonic chip is higher than an upper surface of the at least one die component. In an embodiment, the upper surface of the photonic chip is coplanar with the upper surface of the at least one die component. In an embodiment, the upper surface of the photonic chip is lower than the upper surface of the at least one die component.

[0082] In yet another embodiment, a co-packaged optical device includes a redistribution interposer substrate bonded to a package substrate; a top die assembly bonded to an upper surface of the redistribution interposer substrate; a photonic chip bonded to an upper surface of the redistribution interposer substrate; and a molded wall defining a hollow structure around the top die assembly and the photonic chip.

[0083] The features of the above-described embodiments can be beneficial to an understanding of the application. While the application has been described in terms of particular variations, and while those variations have been shown and described as separate alternatives, it will be apparent that combinations of these alternatives can be made and still be within the scope of the application. Changes in form and substitution of equivalents are contemplated as circumstances can suggest or render expedient. It is intended that the application not be limited by the foregoing description, but encompass any and all adaptations thereof.

Claims

1. A method for manufacturing a co-packaged optical device, characterized in that, include: At least one of the packaging components and the memory components is bonded to the upper surface of the redistribution interposer substrate; The redistributed intermediate layer substrate is bonded to the packaging substrate; Remove the molding from the upper surface of the redistributed interposer substrate to expose the interconnect structure to the redistributed interposer substrate; as well as The photonic chip is bonded to the upper surface of the redistributed interposer substrate.

2. The method according to claim 1, characterized in that, The packaging component includes a system-on-a-chip (SoC) component.

3. The method according to claim 1, characterized in that, The packaging component includes an integrated chip system component.

4. The method according to claim 1, characterized in that, The redistribution interposer substrate includes a local silicon interconnect layer, the local silicon interconnect layer including an insulator via, a front redistribution layer on a first side of the local silicon interconnect layer, and a back redistribution layer on a second side of the local silicon interconnect layer.

5. A co-packaged optical device, characterized in that, include: The redistributed interlayer substrate is bonded to the packaging substrate; The die assembly is bonded to the upper surface of the redistributed interposer substrate; as well as A photonic chip is bonded to the upper surface of the redistribution interposer substrate, wherein a portion of the molding layer is located between the photonic chip and the redistribution interposer substrate.

6. The co-packaged optical device according to claim 5, characterized in that, The annular structure is present on the upper surface of the redistributed interposer substrate, and the annular structure has an upper surface that is coplanar with the upper surface of the photonic chip.

7. The co-packaged optical device according to claim 5, characterized in that, The upper surface of the photonic chip is above the upper surface of at least one of the die assembly.

8. The co-packaged optical device according to claim 5, characterized in that, The upper surface of the photonic chip is coplanar with the upper surface of at least one of the die assembly.

9. The co-packaged optical device according to claim 5, characterized in that, The upper surface of the photonic chip is below the upper surface of at least one of the die assembly.

10. A co-packaged optical device, characterized in that, include: The redistributed interlayer substrate is bonded to the packaging substrate; The top die assembly is bonded to the upper surface of the redistributed interposer substrate; A photonic chip is bonded to the upper surface of the redistributed interposer substrate; as well as A molded wall defines a hollow structure around the top die assembly and the photonic chip.

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