Fan-out panel level packaging method and corresponding packaging structure thereof

Abstract

The invention provides a fan-out panel-level packaging method which can remarkably reduce packaging warping, improve process yield and product reliability, is compatible with an existing low-cost dry film material process and a large-size panel-level packaging technology, and provides possibility for manufacturing large-size and multi-layer wiring high-performance packaging. Single chips are arranged and attached to a temporary carrier plate, then a plastic package layer is obtained through packaging, after the plastic package layer is separated from the temporary carrier plate, a third rewiring layer is manufactured on the surfaces of the chips so that the third rewiring layer can be electrically connected with the chips, then a core plate body is bonded on the third rewiring layer, and then a second rewiring layer is manufactured on the upper surface of the core plate body. And then solder balls are manufactured on the second rewiring layer, and finally the whole packaging body is cut into independent units.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip packaging, in particular to a fan-out panel level packaging method, and further provides a fan-out panel level packaging structure. BACKGROUND

[0002] The existing fan-out panel level packaging technology mostly uses dry film or organic dielectric material as the dielectric layer of the redistribution layer. However, the dry film and other dielectric materials are soft and have poor mechanical strength. After the multilayer metal circuit is made on the dry film, due to the significant difference in the thermal expansion coefficient between the metal and the dry film material, a huge internal stress is generated in the thermal cycle of the packaging process. This stress acts on the relatively soft dielectric layer structure, which can easily cause serious warping deformation of the entire packaging product. The warping can cause a series of process and reliability problems such as inaccurate photoetching focusing, decreased circuit yield, and subsequent difficulty in mounting and welding, which restricts the application of the technology in high-performance packaging. SUMMARY

[0003] In view of the above problems, the present application provides a fan-out panel level packaging method which can significantly reduce packaging warping, improve process yield and product reliability, and is compatible with the existing low-cost dry film material process and large-size panel level packaging technology, thereby providing the possibility for manufacturing large-size, multilayer wiring high-performance packaging.

[0004] A fan-out panel level packaging method, characterized in that: a single chip is arranged and mounted on a temporary carrier, and then a plastic encapsulation layer is obtained by packaging, and then the temporary carrier is detached, and a third redistribution layer is made on the surface of the chip, so that the third redistribution layer is electrically connected to the chip, and then a chip body is bonded on the third redistribution layer, and then a second redistribution layer is made on the upper surface of the chip body, and then tin balls are made on the second redistribution layer, and finally the entire packaging body is cut into individual independent units.

[0005] Further characterized in that: the temporary carrier is a large-area rectangular steel plate.

[0006] Still further characterized in that, the specific operation steps are as follows: S1: a first redistribution layer is made on the wafer surface; S2: the wafer is ground to a target thickness and then cut into single chips; S3: the single chips are mounted on the temporary carrier with temporary bonding glue, and then plastic encapsulation is performed to obtain a plastic encapsulation layer; S4: after the temporary carrier is detached by debonding, a third redistribution layer is made on the active surface of the plastic encapsulation body chip; S5 bonds the core board body above the third redistribution layer and performs laser drilling at the pad positions of the core board body to prepare for the conduction of the upper and lower metal layers; the same laser drilling is made in the blank areas without electrical connections to prepare for the creation of auxiliary connection copper pillars to increase the bonding force between the core board and the redistribution layer. After S6 performs in-hole metallization on the drilled hole, a second redistribution layer is made on the upper surface of the core board body, and solder balls are made above the second redistribution layer. S7 cuts the entire package into individual, independent units.

[0007] Its further characteristic is: In step S5, the core board body is a copper-free core board or a double-sided copper-clad core board that has undergone circuit etching; the bonding material between the third redistribution layer and the core board body can be dry film, prepreg, or the third redistribution layer can be bonded to the copper-clad surface of the core board body using a hot-press bonding process. In step S6, when the second rewiring layer is fabricated, the number of the second and third rewiring layers on both sides of the core board body is the same to balance the stress, or the different number of rewiring layers on both sides of the core board is used to balance the warpage of the package.

[0008] A fan-out panel-level packaging structure, characterized in that it comprises: The chip has a first redistribution layer arranged on its active surface; Molding layer; And a core board, which includes a core board body, a second redistribution layer, and a third redistribution layer, wherein the upper surface of the core board body is provided with the second redistribution layer and the lower surface of the core board body is provided with the third redistribution layer. The upper surface of the chip is electrically connected to the third redistribution layer through the first redistribution layer, and the third redistribution layer is connected to the second redistribution layer through copper pillars in the core board body. The outer periphery of the chip in the thickness direction is covered with a plastic encapsulation layer.

[0009] Its further features are: The second and third rewiring layers, through the arrangement of symmetrical or asymmetrical layers, allow thermal stress to cancel each other out on both sides of the core board body, thereby balancing warping from the root. Preferably, the second wiring layer and the third wiring layer are symmetrical in number and structure with respect to the rewiring layer of the core board body, so that the core board provides strong mechanical support for the entire package. The core board body is either a copper-free core board or a double-sided copper-clad core board that has undergone circuit etching. The core plate body is laser drilled at the designed pad position to prepare for the conduction of the upper and lower metal layers; the core plate body is also laser drilled at the blank area without electrical connection to prepare for the auxiliary connection copper column to increase the bonding force between the core plate body and the redistribution layer.

[0010] After the above technical scheme, the core plate body is pressed and stacked between the two groups of multilayer redistribution layers, and the upper and lower redistribution layers of the core plate body are symmetrical in the number of layers and structure, so that the overall core plate provides strong mechanical support for the entire package, and the redistribution layers on both sides of the core plate body can also be designed by symmetrical or asymmetrical layers to offset the thermal stress on both sides of the core plate, thereby balancing the warping from the root cause. This structure can significantly reduce the packaging warping, improve the process yield and product reliability, and is compatible with the existing low-cost dry film material process and large-size panel-level packaging technology, which provides the possibility for manufacturing large-size, multi-layer wiring high-performance packaging. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 The step flow chart of the method of the application; Figure 2 The specific embodiment structure diagram of the fan-out panel-level packaging structure of the application; The names corresponding to the serial numbers in the figure are as follows: Chip 10, active surface 11, first redistribution layer 12, plastic encapsulation layer 20, core plate 30, core plate body 31, second redistribution layer 32, third redistribution layer 33, temporary carrier plate 40, tin ball 50, temporary bonding glue 60. DETAILED DESCRIPTION

[0012] A packaging method of a fan-out panel-level packaging structure, see Figure 1 : a single chip 10 is arranged and attached on a temporary carrier plate 40, the temporary carrier plate 40 is specifically a large-area rectangular steel plate, then a plastic encapsulation layer 20 is obtained, then the temporary carrier plate 40 is separated, a third redistribution layer 33 is made on the surface of the chip 10, so that the third redistribution layer 33 is electrically connected to the chip 10, then the core plate body 31 is bonded on the third redistribution layer 33, then a second redistribution layer 32 is made on the upper surface of the core plate body 31, then a tin ball 50 is made on the second redistribution layer 32, and finally the entire packaging body is cut into separate independent units.

[0013] In a specific embodiment, the specific operation steps are as follows: S1: a first redistribution layer 12 is made on the wafer surface, which is made on the wafer by a photolithography and electroplating process to rearrange the connection points of the internal circuit of the chip, the first redistribution layer is composed of metal lines and dielectric layers, the dielectric layer material includes but is not limited to dry film, organic polymer dielectric material, and the dielectric layer thickness is 15-45 microns; S2 grinding the wafer S2 to the target thickness and cutting it into single chips 10; S3 mounting the single chips 10 on the temporary carrier 40 with temporary bonding glue 60 and plastic packaging to obtain a plastic packaging layer 20, the thickness of the plastic packaging layer 20 being equal to the thickness of the chip 10 or 70-200 microns more than the thickness of the chip 10, in a specific embodiment, the thickness of the plastic packaging layer 20 being 100 microns more than the thickness of the chip 10; S4 making a third redistribution layer 33 on the active surface 11 of the chip 10 after removing the temporary carrier 40; S5 bonding the core board body 31 on the third redistribution layer 33 and laser drilling on the pad positions of the core board body 31 to prepare for the conduction between the upper and lower layers of metal and making the same laser drilling on the blank area without electrical connection to prepare for the making of auxiliary connecting copper columns to increase the bonding force between the core board and the redistribution layer; The core board body 31 is a copper-free core board or a double-sided copper-clad core board that has been etched; the bonding material between the third redistribution layer 33 and the core board body 31 can use dry film, semi-cured sheet, or use the hot-press bonding process to bond the third redistribution layer and the copper-clad surface of the core board body together; S6 making the second redistribution layer 32 on the upper surface of the core board body 31 after the hole metallization of the drilling and making the solder balls 50 on the upper surface of the second redistribution layer 32; When making the second redistribution layer 32, the number of layers of the second redistribution layer 32 and the third redistribution layer 33 on both sides of the core board body 31 is the same to balance the stress, or the different number of redistribution layers on both sides of the core board is used to balance the warping of the package; S7 cutting the entire package into separate independent units.

[0014] A fan-out panel-level package structure, see Figure 2 which comprises a chip 10, a plastic packaging layer 20, and a core board 30; The active surface 11 of the chip 10 is arranged with a first redistribution layer 12; The core board 30 comprises a core board body 31, a second redistribution layer 32, and a third redistribution layer 33, the upper surface of the core board body 31 being provided with the second redistribution layer 32, and the lower surface of the core board body 31 being provided with the third redistribution layer 33; The upper surface of the chip 10 is electrically connected to the third redistribution layer 33 through the first redistribution layer 12, the third redistribution layer 33 is connected to the second redistribution layer 32 through the copper column in the core board body 10, and the thickness direction of the chip 10 is covered with the plastic packaging layer 20.

[0015] In a specific implementation, the entire package structure can be arranged in reverse for subsequent use.

[0016] In a specific implementation, the bottom of the chip 10 is directly covered by the plastic sealing layer 20 if there is no electrical connection structure on the bottom of the chip 10. If there is an electrical connection structure on the bottom of the chip 10, the plastic sealing layer is ground to expose the electrical connection structure, and then additional electrical connection operation is performed with the external structure. This will not be described here.

[0017] In a specific implementation, the second redistribution layer 32 and the third redistribution layer 33 are designed to be symmetrical or asymmetrical in the number of layers, so that the thermal stress on both sides of the core plate body is counteracted, thereby balancing the warping from the root.

[0018] In a specific embodiment, the second redistribution layer 32 and the third redistribution layer 33 are symmetrical in the number of layers and structure with respect to the redistribution layer of the core plate body 10, thereby providing strong mechanical support for the entire package by the core plate 30.

[0019] In a specific implementation, the core plate body 31 is a copper-free core plate or a double-sided copper-clad core plate that has been etched with lines. The core plate body 31 is laser-drilled at the designed pad positions to prepare for the conduction of the upper and lower metal layers. The core plate body 31 is laser-drilled at the blank areas without electrical connection to prepare for the manufacture of auxiliary connection copper columns, thereby increasing the bonding force between the core plate body 31 and the redistribution layer.

[0020] The core plate body is pressed and stacked between the two groups of multilayer redistribution layers, and the redistribution layers on the upper and lower sides of the core plate body are symmetrical in the number of layers and structure, thereby providing strong mechanical support for the entire package by the core plate. Meanwhile, the redistribution layers on both sides of the core plate body can be designed to be symmetrical or asymmetrical in the number of layers, so that the thermal stress on both sides of the core plate is counteracted, thereby balancing the warping from the root. This structure can significantly reduce the package warping, improve the process yield and product reliability, and is compatible with the existing low-cost dry film material process and large-size panel-level packaging technology, thereby making it possible to manufacture large-size, multilayer, and high-performance packages.

[0021] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0022] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes every feature described. The specification can include implicit combinations of explicitly mentioned features and / or explicit combinations of implicitely mentioned features. Each embodiment depends on the explicit combinations of features and / or the implicit combinations of features made specifically within that embodiment, and each such embodiment can be combined with every other such embodiment to create further embodiments.

Claims

1. A fan-out panel-level packaging method, characterized in that: The process involves arranging individual chips on a temporary carrier board, then encapsulating them to obtain a molding compound. After detaching from the temporary carrier board, a third redistribution layer is fabricated on the surface of the chip, allowing the third redistribution layer to electrically connect to the chip. The core board body is then bonded to the third redistribution layer. A second redistribution layer is then fabricated on the upper surface of the core board body, followed by the fabrication of solder balls on the second redistribution layer. Finally, the entire package is cut into individual independent units.

2. The fan-out panel-level packaging method according to claim 1, characterized in that: The temporary carrier plate is specifically a large rectangular steel plate.

3. The fan-out panel-level packaging method according to claim 1, characterized in that, The specific operating steps are as follows: S1 fabricates the first redistribution layer on the wafer surface; After the S2 wafer is ground to the target thickness, it is cut into individual chips; S3 mounts a single chip onto a temporary carrier board with temporary bonding adhesive and then encapsulates it to obtain an encapsulation layer; After S4 debonds and removes the temporary carrier board, a third redistribution layer is fabricated on the active side of the molded chip. S5 bonds the core board body above the third redistribution layer and performs laser drilling at the pad positions of the core board body to prepare for the conduction of the upper and lower metal layers; the same laser drilling is made in the blank areas without electrical connections to prepare for the creation of auxiliary connection copper pillars to increase the bonding force between the core board and the redistribution layer. After S6 performs in-hole metallization on the drilled hole, a second redistribution layer is made on the upper surface of the core board body, and solder balls are made above the second redistribution layer. S7 cuts the entire package into individual, independent units.

4. The fan-out panel-level packaging method according to claim 3, characterized in that: In step S5, the core board body is a copper-free core board or a double-sided copper-clad core board that has undergone circuit etching; the bonding material between the third redistribution layer and the core board body can be dry film, prepreg, or the third redistribution layer can be bonded to the copper-clad surface of the core board body using a hot-press bonding process.

5. A fan-out panel-level packaging method according to claim 3, characterized in that: In step S6, when the second rewiring layer is fabricated, the number of the second and third rewiring layers on both sides of the core board body is the same to balance the stress, or the different number of rewiring layers on both sides of the core board is used to balance the warpage of the package.

6. A fan-out panel-level packaging structure, which is obtained by the fan-out panel-level packaging method according to any one of claims 1-5, characterized in that, It includes: The chip has a first redistribution layer arranged on its active surface; Molding layer; And a core board, which includes a core board body, a second redistribution layer, and a third redistribution layer, wherein the upper surface of the core board body is provided with the second redistribution layer and the lower surface of the core board body is provided with the third redistribution layer. The upper surface of the chip is electrically connected to the third redistribution layer through the first redistribution layer, and the third redistribution layer is connected to the second redistribution layer through copper pillars in the core board body. The outer periphery of the chip in the thickness direction is covered with a plastic encapsulation layer.

7. A fan-out panel-level packaging structure according to claim 6, characterized in that: The second and third redistribution layers are configured with symmetrical or asymmetrical number of layers.

8. A fan-out panel-level packaging structure according to claim 6, characterized in that: The second and third wiring layers are symmetrical in number and structure relative to the rewiring layers of the core board body.

9. A fan-out panel-level packaging structure according to claim 6, characterized in that: The core board body is either a copper-free core board or a double-sided copper-clad core board that has already undergone circuit etching.

10. A fan-out panel-level packaging structure according to claim 6, characterized in that: The core board body has laser-drilled holes at the designed pad positions to prepare for the conduction of the upper and lower metal layers; the core board body also has the same laser-drilled holes in the blank areas without electrical connections to prepare for the fabrication of auxiliary connecting copper pillars, thereby increasing the bonding force between the core board body and the redistribution layer.

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